en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_msc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
50:a417edff4437 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32gg_msc.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32GG_MSC register and bit field definitions
mbed_official 50:a417edff4437 4 * @version 4.2.0
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32 /**************************************************************************//**
mbed_official 50:a417edff4437 33 * @addtogroup Parts
mbed_official 50:a417edff4437 34 * @{
mbed_official 50:a417edff4437 35 ******************************************************************************/
mbed_official 50:a417edff4437 36 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 37 * @defgroup EFM32GG_MSC
bogdanm 0:9b334a45a8ff 38 * @{
bogdanm 0:9b334a45a8ff 39 * @brief EFM32GG_MSC Register Declaration
bogdanm 0:9b334a45a8ff 40 *****************************************************************************/
bogdanm 0:9b334a45a8ff 41 typedef struct
bogdanm 0:9b334a45a8ff 42 {
bogdanm 0:9b334a45a8ff 43 __IO uint32_t CTRL; /**< Memory System Control Register */
bogdanm 0:9b334a45a8ff 44 __IO uint32_t READCTRL; /**< Read Control Register */
bogdanm 0:9b334a45a8ff 45 __IO uint32_t WRITECTRL; /**< Write Control Register */
bogdanm 0:9b334a45a8ff 46 __IO uint32_t WRITECMD; /**< Write Command Register */
bogdanm 0:9b334a45a8ff 47 __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 50 __IO uint32_t WDATA; /**< Write Data Register */
bogdanm 0:9b334a45a8ff 51 __I uint32_t STATUS; /**< Status Register */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 54 __I uint32_t IF; /**< Interrupt Flag Register */
bogdanm 0:9b334a45a8ff 55 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
bogdanm 0:9b334a45a8ff 56 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
bogdanm 0:9b334a45a8ff 57 __IO uint32_t IEN; /**< Interrupt Enable Register */
bogdanm 0:9b334a45a8ff 58 __IO uint32_t LOCK; /**< Configuration Lock Register */
bogdanm 0:9b334a45a8ff 59 __IO uint32_t CMD; /**< Command Register */
bogdanm 0:9b334a45a8ff 60 __I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
bogdanm 0:9b334a45a8ff 61 __I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
bogdanm 0:9b334a45a8ff 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 63 __IO uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
bogdanm 0:9b334a45a8ff 64 __IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */
bogdanm 0:9b334a45a8ff 65 } MSC_TypeDef; /** @} */
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 68 * @defgroup EFM32GG_MSC_BitFields
bogdanm 0:9b334a45a8ff 69 * @{
bogdanm 0:9b334a45a8ff 70 *****************************************************************************/
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /* Bit fields for MSC CTRL */
bogdanm 0:9b334a45a8ff 73 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
bogdanm 0:9b334a45a8ff 74 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
bogdanm 0:9b334a45a8ff 75 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
bogdanm 0:9b334a45a8ff 76 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
bogdanm 0:9b334a45a8ff 77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
bogdanm 0:9b334a45a8ff 78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
bogdanm 0:9b334a45a8ff 79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
bogdanm 0:9b334a45a8ff 80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
bogdanm 0:9b334a45a8ff 81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
bogdanm 0:9b334a45a8ff 82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
bogdanm 0:9b334a45a8ff 83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Bit fields for MSC READCTRL */
bogdanm 0:9b334a45a8ff 86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 87 #define _MSC_READCTRL_MASK 0x000301FFUL /**< Mask for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 88 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
bogdanm 0:9b334a45a8ff 89 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
bogdanm 0:9b334a45a8ff 90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 104 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
bogdanm 0:9b334a45a8ff 105 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
bogdanm 0:9b334a45a8ff 106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
bogdanm 0:9b334a45a8ff 107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 109 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
bogdanm 0:9b334a45a8ff 110 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
bogdanm 0:9b334a45a8ff 111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
bogdanm 0:9b334a45a8ff 112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 114 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
bogdanm 0:9b334a45a8ff 115 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
bogdanm 0:9b334a45a8ff 116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
bogdanm 0:9b334a45a8ff 117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 119 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
bogdanm 0:9b334a45a8ff 120 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
bogdanm 0:9b334a45a8ff 121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
bogdanm 0:9b334a45a8ff 122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 124 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */
bogdanm 0:9b334a45a8ff 125 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */
bogdanm 0:9b334a45a8ff 126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */
bogdanm 0:9b334a45a8ff 127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 129 #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
bogdanm 0:9b334a45a8ff 130 #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
bogdanm 0:9b334a45a8ff 131 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
bogdanm 0:9b334a45a8ff 132 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 133 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 134 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */
bogdanm 0:9b334a45a8ff 135 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */
bogdanm 0:9b334a45a8ff 136 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 137 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 138 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 139 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 140 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 141 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 142 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 143 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 144 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 145 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* Bit fields for MSC WRITECTRL */
bogdanm 0:9b334a45a8ff 148 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 149 #define _MSC_WRITECTRL_MASK 0x0000003FUL /**< Mask for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 150 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
bogdanm 0:9b334a45a8ff 151 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
bogdanm 0:9b334a45a8ff 152 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
bogdanm 0:9b334a45a8ff 153 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 154 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 155 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
bogdanm 0:9b334a45a8ff 156 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
bogdanm 0:9b334a45a8ff 157 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
bogdanm 0:9b334a45a8ff 158 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 159 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 160 #define MSC_WRITECTRL_WDOUBLE (0x1UL << 2) /**< Write two words at a time */
bogdanm 0:9b334a45a8ff 161 #define _MSC_WRITECTRL_WDOUBLE_SHIFT 2 /**< Shift value for MSC_WDOUBLE */
bogdanm 0:9b334a45a8ff 162 #define _MSC_WRITECTRL_WDOUBLE_MASK 0x4UL /**< Bit mask for MSC_WDOUBLE */
bogdanm 0:9b334a45a8ff 163 #define _MSC_WRITECTRL_WDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 164 #define MSC_WRITECTRL_WDOUBLE_DEFAULT (_MSC_WRITECTRL_WDOUBLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 165 #define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Erase */
bogdanm 0:9b334a45a8ff 166 #define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */
bogdanm 0:9b334a45a8ff 167 #define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */
bogdanm 0:9b334a45a8ff 168 #define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 169 #define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 170 #define MSC_WRITECTRL_LPERASE (0x1UL << 4) /**< Low-Power Erase */
bogdanm 0:9b334a45a8ff 171 #define _MSC_WRITECTRL_LPERASE_SHIFT 4 /**< Shift value for MSC_LPERASE */
bogdanm 0:9b334a45a8ff 172 #define _MSC_WRITECTRL_LPERASE_MASK 0x10UL /**< Bit mask for MSC_LPERASE */
bogdanm 0:9b334a45a8ff 173 #define _MSC_WRITECTRL_LPERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 174 #define MSC_WRITECTRL_LPERASE_DEFAULT (_MSC_WRITECTRL_LPERASE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 175 #define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */
bogdanm 0:9b334a45a8ff 176 #define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */
bogdanm 0:9b334a45a8ff 177 #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */
bogdanm 0:9b334a45a8ff 178 #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 179 #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /* Bit fields for MSC WRITECMD */
bogdanm 0:9b334a45a8ff 182 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 183 #define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 184 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
bogdanm 0:9b334a45a8ff 185 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
bogdanm 0:9b334a45a8ff 186 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
bogdanm 0:9b334a45a8ff 187 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 188 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 189 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
bogdanm 0:9b334a45a8ff 190 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
bogdanm 0:9b334a45a8ff 191 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
bogdanm 0:9b334a45a8ff 192 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 193 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 194 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
bogdanm 0:9b334a45a8ff 195 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
bogdanm 0:9b334a45a8ff 196 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
bogdanm 0:9b334a45a8ff 197 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 198 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 199 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
bogdanm 0:9b334a45a8ff 200 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
bogdanm 0:9b334a45a8ff 201 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
bogdanm 0:9b334a45a8ff 202 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 203 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 204 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
bogdanm 0:9b334a45a8ff 205 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
bogdanm 0:9b334a45a8ff 206 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
bogdanm 0:9b334a45a8ff 207 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 208 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 209 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
bogdanm 0:9b334a45a8ff 210 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
bogdanm 0:9b334a45a8ff 211 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
bogdanm 0:9b334a45a8ff 212 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 213 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 214 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
bogdanm 0:9b334a45a8ff 215 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
bogdanm 0:9b334a45a8ff 216 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
bogdanm 0:9b334a45a8ff 217 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 218 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 219 #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */
bogdanm 0:9b334a45a8ff 220 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */
bogdanm 0:9b334a45a8ff 221 #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */
bogdanm 0:9b334a45a8ff 222 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 223 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 224 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
bogdanm 0:9b334a45a8ff 225 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
bogdanm 0:9b334a45a8ff 226 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
bogdanm 0:9b334a45a8ff 227 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 228 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Bit fields for MSC ADDRB */
bogdanm 0:9b334a45a8ff 231 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 232 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 233 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 234 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 235 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 236 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Bit fields for MSC WDATA */
bogdanm 0:9b334a45a8ff 239 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
bogdanm 0:9b334a45a8ff 240 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
bogdanm 0:9b334a45a8ff 241 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
bogdanm 0:9b334a45a8ff 242 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
bogdanm 0:9b334a45a8ff 243 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
bogdanm 0:9b334a45a8ff 244 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /* Bit fields for MSC STATUS */
bogdanm 0:9b334a45a8ff 247 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
bogdanm 0:9b334a45a8ff 248 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
bogdanm 0:9b334a45a8ff 249 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
bogdanm 0:9b334a45a8ff 250 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
bogdanm 0:9b334a45a8ff 251 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
bogdanm 0:9b334a45a8ff 252 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 253 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 254 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
bogdanm 0:9b334a45a8ff 255 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
bogdanm 0:9b334a45a8ff 256 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
bogdanm 0:9b334a45a8ff 257 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 258 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 259 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
bogdanm 0:9b334a45a8ff 260 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
bogdanm 0:9b334a45a8ff 261 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
bogdanm 0:9b334a45a8ff 262 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 263 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 264 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
bogdanm 0:9b334a45a8ff 265 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
bogdanm 0:9b334a45a8ff 266 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
bogdanm 0:9b334a45a8ff 267 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 268 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 269 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
bogdanm 0:9b334a45a8ff 270 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
bogdanm 0:9b334a45a8ff 271 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
bogdanm 0:9b334a45a8ff 272 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 273 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 274 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
bogdanm 0:9b334a45a8ff 275 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
bogdanm 0:9b334a45a8ff 276 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
bogdanm 0:9b334a45a8ff 277 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 278 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 279 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
bogdanm 0:9b334a45a8ff 280 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
bogdanm 0:9b334a45a8ff 281 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
bogdanm 0:9b334a45a8ff 282 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 283 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* Bit fields for MSC IF */
bogdanm 0:9b334a45a8ff 286 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
bogdanm 0:9b334a45a8ff 287 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */
bogdanm 0:9b334a45a8ff 288 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
bogdanm 0:9b334a45a8ff 289 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
bogdanm 0:9b334a45a8ff 290 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
bogdanm 0:9b334a45a8ff 291 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 292 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 293 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
bogdanm 0:9b334a45a8ff 294 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
bogdanm 0:9b334a45a8ff 295 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
bogdanm 0:9b334a45a8ff 296 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 297 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 298 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 299 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
bogdanm 0:9b334a45a8ff 300 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
bogdanm 0:9b334a45a8ff 301 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 302 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 303 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 304 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
bogdanm 0:9b334a45a8ff 305 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
bogdanm 0:9b334a45a8ff 306 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 307 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Bit fields for MSC IFS */
bogdanm 0:9b334a45a8ff 310 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
bogdanm 0:9b334a45a8ff 311 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */
bogdanm 0:9b334a45a8ff 312 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
bogdanm 0:9b334a45a8ff 313 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
bogdanm 0:9b334a45a8ff 314 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
bogdanm 0:9b334a45a8ff 315 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 316 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 317 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
bogdanm 0:9b334a45a8ff 318 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
bogdanm 0:9b334a45a8ff 319 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
bogdanm 0:9b334a45a8ff 320 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 321 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 322 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */
bogdanm 0:9b334a45a8ff 323 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
bogdanm 0:9b334a45a8ff 324 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
bogdanm 0:9b334a45a8ff 325 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 326 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 327 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */
bogdanm 0:9b334a45a8ff 328 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
bogdanm 0:9b334a45a8ff 329 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
bogdanm 0:9b334a45a8ff 330 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 331 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /* Bit fields for MSC IFC */
bogdanm 0:9b334a45a8ff 334 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
bogdanm 0:9b334a45a8ff 335 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */
bogdanm 0:9b334a45a8ff 336 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
bogdanm 0:9b334a45a8ff 337 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
bogdanm 0:9b334a45a8ff 338 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
bogdanm 0:9b334a45a8ff 339 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 340 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 341 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
bogdanm 0:9b334a45a8ff 342 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
bogdanm 0:9b334a45a8ff 343 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
bogdanm 0:9b334a45a8ff 344 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 345 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 346 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */
bogdanm 0:9b334a45a8ff 347 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
bogdanm 0:9b334a45a8ff 348 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
bogdanm 0:9b334a45a8ff 349 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 350 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 351 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */
bogdanm 0:9b334a45a8ff 352 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
bogdanm 0:9b334a45a8ff 353 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
bogdanm 0:9b334a45a8ff 354 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 355 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* Bit fields for MSC IEN */
bogdanm 0:9b334a45a8ff 358 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
bogdanm 0:9b334a45a8ff 359 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */
bogdanm 0:9b334a45a8ff 360 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
bogdanm 0:9b334a45a8ff 361 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
bogdanm 0:9b334a45a8ff 362 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
bogdanm 0:9b334a45a8ff 363 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 364 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 365 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
bogdanm 0:9b334a45a8ff 366 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
bogdanm 0:9b334a45a8ff 367 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
bogdanm 0:9b334a45a8ff 368 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 369 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 370 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 371 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
bogdanm 0:9b334a45a8ff 372 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
bogdanm 0:9b334a45a8ff 373 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 374 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 375 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 376 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
bogdanm 0:9b334a45a8ff 377 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
bogdanm 0:9b334a45a8ff 378 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 379 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /* Bit fields for MSC LOCK */
bogdanm 0:9b334a45a8ff 382 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
bogdanm 0:9b334a45a8ff 383 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
bogdanm 0:9b334a45a8ff 384 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
bogdanm 0:9b334a45a8ff 385 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
bogdanm 0:9b334a45a8ff 386 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
bogdanm 0:9b334a45a8ff 387 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
bogdanm 0:9b334a45a8ff 388 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
bogdanm 0:9b334a45a8ff 389 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
bogdanm 0:9b334a45a8ff 390 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
bogdanm 0:9b334a45a8ff 391 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
bogdanm 0:9b334a45a8ff 392 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
bogdanm 0:9b334a45a8ff 393 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
bogdanm 0:9b334a45a8ff 394 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
bogdanm 0:9b334a45a8ff 395 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* Bit fields for MSC CMD */
bogdanm 0:9b334a45a8ff 398 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
bogdanm 0:9b334a45a8ff 399 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */
bogdanm 0:9b334a45a8ff 400 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
bogdanm 0:9b334a45a8ff 401 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
bogdanm 0:9b334a45a8ff 402 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
bogdanm 0:9b334a45a8ff 403 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 404 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 405 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
bogdanm 0:9b334a45a8ff 406 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
bogdanm 0:9b334a45a8ff 407 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
bogdanm 0:9b334a45a8ff 408 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 409 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 410 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
bogdanm 0:9b334a45a8ff 411 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
bogdanm 0:9b334a45a8ff 412 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
bogdanm 0:9b334a45a8ff 413 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 414 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Bit fields for MSC CACHEHITS */
bogdanm 0:9b334a45a8ff 417 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 418 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 419 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 420 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 421 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 422 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Bit fields for MSC CACHEMISSES */
bogdanm 0:9b334a45a8ff 425 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 426 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 427 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 428 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 429 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 430 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Bit fields for MSC TIMEBASE */
bogdanm 0:9b334a45a8ff 433 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 434 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 435 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */
bogdanm 0:9b334a45a8ff 436 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */
bogdanm 0:9b334a45a8ff 437 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 438 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 439 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */
bogdanm 0:9b334a45a8ff 440 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */
bogdanm 0:9b334a45a8ff 441 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */
bogdanm 0:9b334a45a8ff 442 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 443 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 444 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 445 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 446 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 447 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Bit fields for MSC MASSLOCK */
bogdanm 0:9b334a45a8ff 450 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 451 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 452 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
bogdanm 0:9b334a45a8ff 453 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
bogdanm 0:9b334a45a8ff 454 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 455 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 456 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 457 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 458 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 459 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 460 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 461 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 462 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 463 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /** @} End of group EFM32GG_MSC */
mbed_official 50:a417edff4437 466 /** @} End of group Parts */
bogdanm 0:9b334a45a8ff 467