mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_usb.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_ll_usb.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief USB Low Layer HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the USB Peripheral Controller:
bogdanm	0:9b334a45a8ff	11	* + Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + I/O operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	*
bogdanm	0:9b334a45a8ff	16	@verbatim
bogdanm	0:9b334a45a8ff	17	==============================================================================
bogdanm	0:9b334a45a8ff	18	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	19	==============================================================================
bogdanm	0:9b334a45a8ff	20	[..]
bogdanm	0:9b334a45a8ff	21	(#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
bogdanm	0:9b334a45a8ff	22
bogdanm	0:9b334a45a8ff	23	(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
bogdanm	0:9b334a45a8ff	26
bogdanm	0:9b334a45a8ff	27	@endverbatim
bogdanm	0:9b334a45a8ff	28	******************************************************************************
bogdanm	0:9b334a45a8ff	29	* @attention
bogdanm	0:9b334a45a8ff	30	*
bogdanm	0:9b334a45a8ff	31	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	32	*
bogdanm	0:9b334a45a8ff	33	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	34	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	35	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	36	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	37	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	38	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	39	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	40	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	41	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	42	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	43	*
bogdanm	0:9b334a45a8ff	44	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	45	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	46	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	47	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	48	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	49	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	50	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	51	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	52	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	53	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	54	*
bogdanm	0:9b334a45a8ff	55	******************************************************************************
bogdanm	0:9b334a45a8ff	56	*/
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	59	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	/** @addtogroup STM32L4xx_LL_USB_DRIVER
bogdanm	0:9b334a45a8ff	64	* @{
bogdanm	0:9b334a45a8ff	65	*/
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	#if defined (HAL_PCD_MODULE_ENABLED) \|\| defined (HAL_HCD_MODULE_ENABLED)
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	70	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	71	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	72	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	73	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	74	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	75	static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
bogdanm	0:9b334a45a8ff	80	* @{
bogdanm	0:9b334a45a8ff	81	*/
bogdanm	0:9b334a45a8ff	82
bogdanm	0:9b334a45a8ff	83	/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	84	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	85	*
bogdanm	0:9b334a45a8ff	86	@verbatim
bogdanm	0:9b334a45a8ff	87	===============================================================================
bogdanm	0:9b334a45a8ff	88	##### Initialization/de-initialization functions #####
bogdanm	0:9b334a45a8ff	89	===============================================================================
bogdanm	0:9b334a45a8ff	90	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	@endverbatim
bogdanm	0:9b334a45a8ff	93	* @{
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	/**
bogdanm	0:9b334a45a8ff	97	* @brief Initializes the USB Core
bogdanm	0:9b334a45a8ff	98	* @param USBx: USB Instance
bogdanm	0:9b334a45a8ff	99	* @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
bogdanm	0:9b334a45a8ff	100	* the configuration information for the specified USBx peripheral.
bogdanm	0:9b334a45a8ff	101	* @retval HAL status
bogdanm	0:9b334a45a8ff	102	*/
bogdanm	0:9b334a45a8ff	103	HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
bogdanm	0:9b334a45a8ff	104	{
bogdanm	0:9b334a45a8ff	105	/* Select FS Embedded PHY */
bogdanm	0:9b334a45a8ff	106	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_PHYSEL;
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	/* Reset after a PHY select and set Host mode */
bogdanm	0:9b334a45a8ff	109	USB_CoreReset(USBx);
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/* Deactivate the power down*/
bogdanm	0:9b334a45a8ff	112	USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	/* Enable srpcap*/
bogdanm	0:9b334a45a8ff	115	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_SRPCAP;
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	return HAL_OK;
bogdanm	0:9b334a45a8ff	118	}
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	/**
bogdanm	0:9b334a45a8ff	121	* @brief USB_EnableGlobalInt
bogdanm	0:9b334a45a8ff	122	* Enables the controller's Global Int in the AHB Config reg
bogdanm	0:9b334a45a8ff	123	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	124	* @retval HAL status
bogdanm	0:9b334a45a8ff	125	*/
bogdanm	0:9b334a45a8ff	126	HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	127	{
bogdanm	0:9b334a45a8ff	128	USBx->GAHBCFG \|= USB_OTG_GAHBCFG_GINT;
bogdanm	0:9b334a45a8ff	129	return HAL_OK;
bogdanm	0:9b334a45a8ff	130	}
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	/**
bogdanm	0:9b334a45a8ff	134	* @brief USB_DisableGlobalInt
bogdanm	0:9b334a45a8ff	135	* Disable the controller's Global Int in the AHB Config reg
bogdanm	0:9b334a45a8ff	136	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	137	* @retval HAL status
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139	HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	140	{
bogdanm	0:9b334a45a8ff	141	USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
bogdanm	0:9b334a45a8ff	142	return HAL_OK;
bogdanm	0:9b334a45a8ff	143	}
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	/**
bogdanm	0:9b334a45a8ff	146	* @brief USB_SetCurrentMode : Set functional mode
bogdanm	0:9b334a45a8ff	147	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	148	* @param mode: current core mode
bogdanm	0:9b334a45a8ff	149	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	150	* @arg USB_OTG_DEVICE_MODE: Peripheral mode
bogdanm	0:9b334a45a8ff	151	* @arg USB_OTG_HOST_MODE: Host mode
bogdanm	0:9b334a45a8ff	152	* @arg USB_OTG_DRD_MODE: Dual Role Device mode
bogdanm	0:9b334a45a8ff	153	* @retval HAL status
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155	HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
bogdanm	0:9b334a45a8ff	156	{
bogdanm	0:9b334a45a8ff	157	USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD \| USB_OTG_GUSBCFG_FDMOD);
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	if ( mode == USB_OTG_HOST_MODE)
bogdanm	0:9b334a45a8ff	160	{
bogdanm	0:9b334a45a8ff	161	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_FHMOD;
bogdanm	0:9b334a45a8ff	162	}
bogdanm	0:9b334a45a8ff	163	else if ( mode == USB_OTG_DEVICE_MODE)
bogdanm	0:9b334a45a8ff	164	{
bogdanm	0:9b334a45a8ff	165	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_FDMOD;
bogdanm	0:9b334a45a8ff	166	}
bogdanm	0:9b334a45a8ff	167	HAL_Delay(50);
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	return HAL_OK;
bogdanm	0:9b334a45a8ff	170	}
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/**
bogdanm	0:9b334a45a8ff	173	* @brief USB_DevInit : Initializes the USB_OTG controller registers
bogdanm	0:9b334a45a8ff	174	* for device mode
bogdanm	0:9b334a45a8ff	175	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	176	* @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
bogdanm	0:9b334a45a8ff	177	* the configuration information for the specified USBx peripheral.
bogdanm	0:9b334a45a8ff	178	* @retval HAL status
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180	HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
bogdanm	0:9b334a45a8ff	181	{
bogdanm	0:9b334a45a8ff	182	uint32_t i = 0;
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/Activate VBUS Sensing B /
bogdanm	0:9b334a45a8ff	185	USBx->GCCFG \|= USB_OTG_GCCFG_VBDEN;
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	if (cfg.vbus_sensing_enable == 0)
bogdanm	0:9b334a45a8ff	188	{
bogdanm	0:9b334a45a8ff	189	/* Deactivate VBUS Sensing B */
bogdanm	0:9b334a45a8ff	190	USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	/* B-peripheral session valid override enable*/
bogdanm	0:9b334a45a8ff	193	USBx->GOTGCTL \|= USB_OTG_GOTGCTL_BVALOEN;
bogdanm	0:9b334a45a8ff	194	USBx->GOTGCTL \|= USB_OTG_GOTGCTL_BVALOVAL;
bogdanm	0:9b334a45a8ff	195	}
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	/* Restart the Phy Clock */
bogdanm	0:9b334a45a8ff	198	USBx_PCGCCTL = 0;
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/* Device mode configuration */
bogdanm	0:9b334a45a8ff	201	USBx_DEVICE->DCFG \|= DCFG_FRAME_INTERVAL_80;
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/* Set Full speed phy */
bogdanm	0:9b334a45a8ff	204	USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/* Flush the FIFOs */
bogdanm	0:9b334a45a8ff	207	USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
bogdanm	0:9b334a45a8ff	208	USB_FlushRxFifo(USBx);
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Clear all pending Device Interrupts */
bogdanm	0:9b334a45a8ff	211	USBx_DEVICE->DIEPMSK = 0;
bogdanm	0:9b334a45a8ff	212	USBx_DEVICE->DOEPMSK = 0;
bogdanm	0:9b334a45a8ff	213	USBx_DEVICE->DAINT = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	214	USBx_DEVICE->DAINTMSK = 0;
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	for (i = 0; i < cfg.dev_endpoints; i++)
bogdanm	0:9b334a45a8ff	217	{
bogdanm	0:9b334a45a8ff	218	if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
bogdanm	0:9b334a45a8ff	219	{
bogdanm	0:9b334a45a8ff	220	USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS \| USB_OTG_DIEPCTL_SNAK);
bogdanm	0:9b334a45a8ff	221	}
bogdanm	0:9b334a45a8ff	222	else
bogdanm	0:9b334a45a8ff	223	{
bogdanm	0:9b334a45a8ff	224	USBx_INEP(i)->DIEPCTL = 0;
bogdanm	0:9b334a45a8ff	225	}
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	USBx_INEP(i)->DIEPTSIZ = 0;
bogdanm	0:9b334a45a8ff	228	USBx_INEP(i)->DIEPINT = 0xFF;
bogdanm	0:9b334a45a8ff	229	}
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	for (i = 0; i < cfg.dev_endpoints; i++)
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
bogdanm	0:9b334a45a8ff	234	{
bogdanm	0:9b334a45a8ff	235	USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS \| USB_OTG_DOEPCTL_SNAK);
bogdanm	0:9b334a45a8ff	236	}
bogdanm	0:9b334a45a8ff	237	else
bogdanm	0:9b334a45a8ff	238	{
bogdanm	0:9b334a45a8ff	239	USBx_OUTEP(i)->DOEPCTL = 0;
bogdanm	0:9b334a45a8ff	240	}
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	USBx_OUTEP(i)->DOEPTSIZ = 0;
bogdanm	0:9b334a45a8ff	243	USBx_OUTEP(i)->DOEPINT = 0xFF;
bogdanm	0:9b334a45a8ff	244	}
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	if (cfg.dma_enable == 1)
bogdanm	0:9b334a45a8ff	249	{
bogdanm	0:9b334a45a8ff	250	/Set threshold parameters /
bogdanm	0:9b334a45a8ff	251	USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 \| USB_OTG_DTHRCTL_RXTHRLEN_6);
bogdanm	0:9b334a45a8ff	252	USBx_DEVICE->DTHRCTL \|= (USB_OTG_DTHRCTL_RXTHREN \| USB_OTG_DTHRCTL_ISOTHREN \| USB_OTG_DTHRCTL_NONISOTHREN);
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	i= USBx_DEVICE->DTHRCTL;
bogdanm	0:9b334a45a8ff	255	}
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	/* Disable all interrupts. */
bogdanm	0:9b334a45a8ff	258	USBx->GINTMSK = 0;
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/* Clear any pending interrupts */
bogdanm	0:9b334a45a8ff	261	USBx->GINTSTS = 0xBFFFFFFF;
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Enable the common interrupts */
bogdanm	0:9b334a45a8ff	264	if (cfg.dma_enable == DISABLE)
bogdanm	0:9b334a45a8ff	265	{
bogdanm	0:9b334a45a8ff	266	USBx->GINTMSK \|= USB_OTG_GINTMSK_RXFLVLM;
bogdanm	0:9b334a45a8ff	267	}
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/* Enable interrupts matching to the Device mode ONLY */
bogdanm	0:9b334a45a8ff	270	USBx->GINTMSK \|= (USB_OTG_GINTMSK_USBSUSPM \| USB_OTG_GINTMSK_USBRST \|\
bogdanm	0:9b334a45a8ff	271	USB_OTG_GINTMSK_ENUMDNEM \| USB_OTG_GINTMSK_IEPINT \|\
bogdanm	0:9b334a45a8ff	272	USB_OTG_GINTMSK_OEPINT \| USB_OTG_GINTMSK_IISOIXFRM\|\
bogdanm	0:9b334a45a8ff	273	USB_OTG_GINTMSK_PXFRM_IISOOXFRM \| USB_OTG_GINTMSK_WUIM);
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	if(cfg.Sof_enable)
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	USBx->GINTMSK \|= USB_OTG_GINTMSK_SOFM;
bogdanm	0:9b334a45a8ff	278	}
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	if (cfg.vbus_sensing_enable == ENABLE)
bogdanm	0:9b334a45a8ff	281	{
bogdanm	0:9b334a45a8ff	282	USBx->GINTMSK \|= (USB_OTG_GINTMSK_SRQIM \| USB_OTG_GINTMSK_OTGINT);
bogdanm	0:9b334a45a8ff	283	}
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	return HAL_OK;
bogdanm	0:9b334a45a8ff	286	}
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/**
bogdanm	0:9b334a45a8ff	290	* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
bogdanm	0:9b334a45a8ff	291	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	292	* @param num: FIFO number
bogdanm	0:9b334a45a8ff	293	* This parameter can be a value from 1 to 15
bogdanm	0:9b334a45a8ff	294	15 means Flush all Tx FIFOs
bogdanm	0:9b334a45a8ff	295	* @retval HAL status
bogdanm	0:9b334a45a8ff	296	*/
bogdanm	0:9b334a45a8ff	297	HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
bogdanm	0:9b334a45a8ff	298	{
bogdanm	0:9b334a45a8ff	299	uint32_t count = 0;
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH \|(uint32_t)( num << 6));
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	do
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	if (++count > 200000)
bogdanm	0:9b334a45a8ff	306	{
bogdanm	0:9b334a45a8ff	307	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	308	}
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	return HAL_OK;
bogdanm	0:9b334a45a8ff	313	}
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @brief USB_FlushRxFifo : Flush Rx FIFO
bogdanm	0:9b334a45a8ff	318	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	319	* @retval HAL status
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321	HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	322	{
bogdanm	0:9b334a45a8ff	323	uint32_t count = 0;
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	do
bogdanm	0:9b334a45a8ff	328	{
bogdanm	0:9b334a45a8ff	329	if (++count > 200000)
bogdanm	0:9b334a45a8ff	330	{
bogdanm	0:9b334a45a8ff	331	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	332	}
bogdanm	0:9b334a45a8ff	333	}
bogdanm	0:9b334a45a8ff	334	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	return HAL_OK;
bogdanm	0:9b334a45a8ff	337	}
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	/**
bogdanm	0:9b334a45a8ff	340	* @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
bogdanm	0:9b334a45a8ff	341	* depending the PHY type and the enumeration speed of the device.
bogdanm	0:9b334a45a8ff	342	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	343	* @param speed: device speed
bogdanm	0:9b334a45a8ff	344	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	345	* @arg USB_OTG_SPEED_HIGH: High speed mode
bogdanm	0:9b334a45a8ff	346	* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
bogdanm	0:9b334a45a8ff	347	* @arg USB_OTG_SPEED_FULL: Full speed mode
bogdanm	0:9b334a45a8ff	348	* @arg USB_OTG_SPEED_LOW: Low speed mode
bogdanm	0:9b334a45a8ff	349	* @retval Hal status
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351	HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
bogdanm	0:9b334a45a8ff	352	{
bogdanm	0:9b334a45a8ff	353	USBx_DEVICE->DCFG \|= speed;
bogdanm	0:9b334a45a8ff	354	return HAL_OK;
bogdanm	0:9b334a45a8ff	355	}
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/**
bogdanm	0:9b334a45a8ff	358	* @brief USB_GetDevSpeed :Return the Dev Speed
bogdanm	0:9b334a45a8ff	359	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	360	* @retval speed : device speed
bogdanm	0:9b334a45a8ff	361	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	362	* @arg USB_OTG_SPEED_HIGH: High speed mode
bogdanm	0:9b334a45a8ff	363	* @arg USB_OTG_SPEED_FULL: Full speed mode
bogdanm	0:9b334a45a8ff	364	* @arg USB_OTG_SPEED_LOW: Low speed mode
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366	uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	367	{
bogdanm	0:9b334a45a8ff	368	uint8_t speed = 0;
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
bogdanm	0:9b334a45a8ff	371	{
bogdanm	0:9b334a45a8ff	372	speed = USB_OTG_SPEED_HIGH;
bogdanm	0:9b334a45a8ff	373	}
bogdanm	0:9b334a45a8ff	374	else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)\|\|
bogdanm	0:9b334a45a8ff	375	((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
bogdanm	0:9b334a45a8ff	376	{
bogdanm	0:9b334a45a8ff	377	speed = USB_OTG_SPEED_FULL;
bogdanm	0:9b334a45a8ff	378	}
bogdanm	0:9b334a45a8ff	379	else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
bogdanm	0:9b334a45a8ff	380	{
bogdanm	0:9b334a45a8ff	381	speed = USB_OTG_SPEED_LOW;
bogdanm	0:9b334a45a8ff	382	}
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	return speed;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @brief Activate and configure an endpoint
bogdanm	0:9b334a45a8ff	389	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	390	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	391	* @retval HAL status
bogdanm	0:9b334a45a8ff	392	*/
bogdanm	0:9b334a45a8ff	393	HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	394	{
bogdanm	0:9b334a45a8ff	395	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	396	{
bogdanm	0:9b334a45a8ff	397	USBx_DEVICE->DAINTMSK \|= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
bogdanm	0:9b334a45a8ff	400	{
bogdanm	0:9b334a45a8ff	401	USBx_INEP(ep->num)->DIEPCTL \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	402	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	403	}
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	}
bogdanm	0:9b334a45a8ff	406	else
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	USBx_DEVICE->DAINTMSK \|= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
bogdanm	0:9b334a45a8ff	411	{
bogdanm	0:9b334a45a8ff	412	USBx_OUTEP(ep->num)->DOEPCTL \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	413	(USB_OTG_DIEPCTL_SD0PID_SEVNFRM)\| (USB_OTG_DOEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	414	}
bogdanm	0:9b334a45a8ff	415	}
bogdanm	0:9b334a45a8ff	416	return HAL_OK;
bogdanm	0:9b334a45a8ff	417	}
bogdanm	0:9b334a45a8ff	418	/**
bogdanm	0:9b334a45a8ff	419	* @brief Activate and configure a dedicated endpoint
bogdanm	0:9b334a45a8ff	420	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	421	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	422	* @retval HAL status
bogdanm	0:9b334a45a8ff	423	*/
bogdanm	0:9b334a45a8ff	424	HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	425	{
bogdanm	0:9b334a45a8ff	426	static __IO uint32_t debug = 0;
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/* Read DEPCTLn register */
bogdanm	0:9b334a45a8ff	429	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	430	{
bogdanm	0:9b334a45a8ff	431	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
bogdanm	0:9b334a45a8ff	432	{
bogdanm	0:9b334a45a8ff	433	USBx_INEP(ep->num)->DIEPCTL \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	434	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	435	}
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	debug \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	439	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	USBx_DEVICE->DEACHMSK \|= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
bogdanm	0:9b334a45a8ff	442	}
bogdanm	0:9b334a45a8ff	443	else
bogdanm	0:9b334a45a8ff	444	{
bogdanm	0:9b334a45a8ff	445	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
bogdanm	0:9b334a45a8ff	446	{
bogdanm	0:9b334a45a8ff	447	USBx_OUTEP(ep->num)->DOEPCTL \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	448	((ep->num) << 22 ) \| (USB_OTG_DOEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
bogdanm	0:9b334a45a8ff	451	debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
bogdanm	0:9b334a45a8ff	452	debug \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
bogdanm	0:9b334a45a8ff	453	((ep->num) << 22 ) \| (USB_OTG_DOEPCTL_USBAEP));
bogdanm	0:9b334a45a8ff	454	}
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	USBx_DEVICE->DEACHMSK \|= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
bogdanm	0:9b334a45a8ff	457	}
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	return HAL_OK;
bogdanm	0:9b334a45a8ff	460	}
bogdanm	0:9b334a45a8ff	461	/**
bogdanm	0:9b334a45a8ff	462	* @brief De-activate and de-initialize an endpoint
bogdanm	0:9b334a45a8ff	463	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	464	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	465	* @retval HAL status
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467	HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	/* Read DEPCTLn register */
bogdanm	0:9b334a45a8ff	470	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	471	{
bogdanm	0:9b334a45a8ff	472	USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
bogdanm	0:9b334a45a8ff	473	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
bogdanm	0:9b334a45a8ff	474	USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
bogdanm	0:9b334a45a8ff	475	}
bogdanm	0:9b334a45a8ff	476	else
bogdanm	0:9b334a45a8ff	477	{
bogdanm	0:9b334a45a8ff	478	USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
bogdanm	0:9b334a45a8ff	479	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
bogdanm	0:9b334a45a8ff	480	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
bogdanm	0:9b334a45a8ff	481	}
bogdanm	0:9b334a45a8ff	482	return HAL_OK;
bogdanm	0:9b334a45a8ff	483	}
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/**
bogdanm	0:9b334a45a8ff	486	* @brief De-activate and de-initialize a dedicated endpoint
bogdanm	0:9b334a45a8ff	487	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	488	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	489	* @retval HAL status
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491	HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	492	{
bogdanm	0:9b334a45a8ff	493	/* Read DEPCTLn register */
bogdanm	0:9b334a45a8ff	494	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	495	{
bogdanm	0:9b334a45a8ff	496	USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
bogdanm	0:9b334a45a8ff	497	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
bogdanm	0:9b334a45a8ff	498	}
bogdanm	0:9b334a45a8ff	499	else
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
bogdanm	0:9b334a45a8ff	502	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504	return HAL_OK;
bogdanm	0:9b334a45a8ff	505	}
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @brief USB_EPStartXfer : setup and starts a transfer over an EP
bogdanm	0:9b334a45a8ff	509	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	510	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	511	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	512	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	513	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	514	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	515	* @retval HAL status
bogdanm	0:9b334a45a8ff	516	*/
bogdanm	0:9b334a45a8ff	517	HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep, uint8_t dma)
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	uint16_t pktcnt = 0;
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* IN endpoint */
bogdanm	0:9b334a45a8ff	522	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	523	{
bogdanm	0:9b334a45a8ff	524	/* Zero Length Packet? */
bogdanm	0:9b334a45a8ff	525	if (ep->xfer_len == 0)
bogdanm	0:9b334a45a8ff	526	{
bogdanm	0:9b334a45a8ff	527	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	528	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
bogdanm	0:9b334a45a8ff	529	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	530	}
bogdanm	0:9b334a45a8ff	531	else
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	/* Program the transfer size and packet count
bogdanm	0:9b334a45a8ff	534	* as follows: xfersize = N * maxpacket +
bogdanm	0:9b334a45a8ff	535	* short_packet pktcnt = N + (short_packet
bogdanm	0:9b334a45a8ff	536	* exist ? 1 : 0)
bogdanm	0:9b334a45a8ff	537	*/
bogdanm	0:9b334a45a8ff	538	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	539	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	540	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
bogdanm	0:9b334a45a8ff	541	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	if (ep->type == EP_TYPE_ISOC)
bogdanm	0:9b334a45a8ff	544	{
bogdanm	0:9b334a45a8ff	545	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
bogdanm	0:9b334a45a8ff	546	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
bogdanm	0:9b334a45a8ff	547	}
bogdanm	0:9b334a45a8ff	548	}
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	if (dma == 1)
bogdanm	0:9b334a45a8ff	551	{
bogdanm	0:9b334a45a8ff	552	USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
bogdanm	0:9b334a45a8ff	553	}
bogdanm	0:9b334a45a8ff	554	else
bogdanm	0:9b334a45a8ff	555	{
bogdanm	0:9b334a45a8ff	556	if (ep->type != EP_TYPE_ISOC)
bogdanm	0:9b334a45a8ff	557	{
bogdanm	0:9b334a45a8ff	558	/* Enable the Tx FIFO Empty Interrupt for this EP */
bogdanm	0:9b334a45a8ff	559	if (ep->xfer_len > 0)
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	USBx_DEVICE->DIEPEMPMSK \|= 1 << ep->num;
bogdanm	0:9b334a45a8ff	562	}
bogdanm	0:9b334a45a8ff	563	}
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	if (ep->type == EP_TYPE_ISOC)
bogdanm	0:9b334a45a8ff	567	{
bogdanm	0:9b334a45a8ff	568	if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
bogdanm	0:9b334a45a8ff	569	{
bogdanm	0:9b334a45a8ff	570	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SODDFRM;
bogdanm	0:9b334a45a8ff	571	}
bogdanm	0:9b334a45a8ff	572	else
bogdanm	0:9b334a45a8ff	573	{
bogdanm	0:9b334a45a8ff	574	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576	}
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* EP enable, IN data in FIFO */
bogdanm	0:9b334a45a8ff	579	USBx_INEP(ep->num)->DIEPCTL \|= (USB_OTG_DIEPCTL_CNAK \| USB_OTG_DIEPCTL_EPENA);
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	if (ep->type == EP_TYPE_ISOC)
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
bogdanm	0:9b334a45a8ff	584	}
bogdanm	0:9b334a45a8ff	585	}
bogdanm	0:9b334a45a8ff	586	else /* OUT endpoint */
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	/* Program the transfer size and packet count as follows:
bogdanm	0:9b334a45a8ff	589	* pktcnt = N
bogdanm	0:9b334a45a8ff	590	* xfersize = N * maxpacket
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	593	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	if (ep->xfer_len == 0)
bogdanm	0:9b334a45a8ff	596	{
bogdanm	0:9b334a45a8ff	597	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
bogdanm	0:9b334a45a8ff	598	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
bogdanm	0:9b334a45a8ff	599	}
bogdanm	0:9b334a45a8ff	600	else
bogdanm	0:9b334a45a8ff	601	{
bogdanm	0:9b334a45a8ff	602	pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
bogdanm	0:9b334a45a8ff	603	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
bogdanm	0:9b334a45a8ff	604	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	if (dma == 1)
bogdanm	0:9b334a45a8ff	608	{
bogdanm	0:9b334a45a8ff	609	USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
bogdanm	0:9b334a45a8ff	610	}
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	if (ep->type == EP_TYPE_ISOC)
bogdanm	0:9b334a45a8ff	613	{
bogdanm	0:9b334a45a8ff	614	if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
bogdanm	0:9b334a45a8ff	615	{
bogdanm	0:9b334a45a8ff	616	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SODDFRM;
bogdanm	0:9b334a45a8ff	617	}
bogdanm	0:9b334a45a8ff	618	else
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
bogdanm	0:9b334a45a8ff	621	}
bogdanm	0:9b334a45a8ff	622	}
bogdanm	0:9b334a45a8ff	623	/* EP enable */
bogdanm	0:9b334a45a8ff	624	USBx_OUTEP(ep->num)->DOEPCTL \|= (USB_OTG_DOEPCTL_CNAK \| USB_OTG_DOEPCTL_EPENA);
bogdanm	0:9b334a45a8ff	625	}
bogdanm	0:9b334a45a8ff	626	return HAL_OK;
bogdanm	0:9b334a45a8ff	627	}
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/**
bogdanm	0:9b334a45a8ff	630	* @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
bogdanm	0:9b334a45a8ff	631	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	632	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	633	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	634	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	635	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	636	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	637	* @retval HAL status
bogdanm	0:9b334a45a8ff	638	*/
bogdanm	0:9b334a45a8ff	639	HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep, uint8_t dma)
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	/* IN endpoint */
bogdanm	0:9b334a45a8ff	642	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	643	{
bogdanm	0:9b334a45a8ff	644	/* Zero Length Packet? */
bogdanm	0:9b334a45a8ff	645	if (ep->xfer_len == 0)
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	648	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
bogdanm	0:9b334a45a8ff	649	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651	else
bogdanm	0:9b334a45a8ff	652	{
bogdanm	0:9b334a45a8ff	653	/* Program the transfer size and packet count
bogdanm	0:9b334a45a8ff	654	* as follows: xfersize = N * maxpacket +
bogdanm	0:9b334a45a8ff	655	* short_packet pktcnt = N + (short_packet
bogdanm	0:9b334a45a8ff	656	* exist ? 1 : 0)
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	659	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	if(ep->xfer_len > ep->maxpacket)
bogdanm	0:9b334a45a8ff	662	{
bogdanm	0:9b334a45a8ff	663	ep->xfer_len = ep->maxpacket;
bogdanm	0:9b334a45a8ff	664	}
bogdanm	0:9b334a45a8ff	665	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
bogdanm	0:9b334a45a8ff	666	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	if (dma == 1)
bogdanm	0:9b334a45a8ff	671	{
bogdanm	0:9b334a45a8ff	672	USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674	else
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	/* Enable the Tx FIFO Empty Interrupt for this EP */
bogdanm	0:9b334a45a8ff	677	if (ep->xfer_len > 0)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	USBx_DEVICE->DIEPEMPMSK \|= 1 << (ep->num);
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681	}
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/* EP enable, IN data in FIFO */
bogdanm	0:9b334a45a8ff	684	USBx_INEP(ep->num)->DIEPCTL \|= (USB_OTG_DIEPCTL_CNAK \| USB_OTG_DIEPCTL_EPENA);
bogdanm	0:9b334a45a8ff	685	}
bogdanm	0:9b334a45a8ff	686	else /* OUT endpoint */
bogdanm	0:9b334a45a8ff	687	{
bogdanm	0:9b334a45a8ff	688	/* Program the transfer size and packet count as follows:
bogdanm	0:9b334a45a8ff	689	* pktcnt = N
bogdanm	0:9b334a45a8ff	690	* xfersize = N * maxpacket
bogdanm	0:9b334a45a8ff	691	*/
bogdanm	0:9b334a45a8ff	692	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
bogdanm	0:9b334a45a8ff	693	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695	if (ep->xfer_len > 0)
bogdanm	0:9b334a45a8ff	696	{
bogdanm	0:9b334a45a8ff	697	ep->xfer_len = ep->maxpacket;
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
bogdanm	0:9b334a45a8ff	701	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	if (dma == 1)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
bogdanm	0:9b334a45a8ff	707	}
bogdanm	0:9b334a45a8ff	708
bogdanm	0:9b334a45a8ff	709	/* EP enable */
bogdanm	0:9b334a45a8ff	710	USBx_OUTEP(ep->num)->DOEPCTL \|= (USB_OTG_DOEPCTL_CNAK \| USB_OTG_DOEPCTL_EPENA);
bogdanm	0:9b334a45a8ff	711	}
bogdanm	0:9b334a45a8ff	712	return HAL_OK;
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/**
bogdanm	0:9b334a45a8ff	716	* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
bogdanm	0:9b334a45a8ff	717	* with the EP/channel
bogdanm	0:9b334a45a8ff	718	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	719	* @param src: pointer to source buffer
bogdanm	0:9b334a45a8ff	720	* @param ch_ep_num: endpoint or host channel number
bogdanm	0:9b334a45a8ff	721	* @param len: Number of bytes to write
bogdanm	0:9b334a45a8ff	722	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	723	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	724	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	725	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	726	* @retval HAL status
bogdanm	0:9b334a45a8ff	727	*/
bogdanm	0:9b334a45a8ff	728	HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef USBx, uint8_t src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
bogdanm	0:9b334a45a8ff	729	{
bogdanm	0:9b334a45a8ff	730	uint32_t count32b= 0 , i= 0;
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	if (dma == 0)
bogdanm	0:9b334a45a8ff	733	{
bogdanm	0:9b334a45a8ff	734	count32b = (len + 3) / 4;
bogdanm	0:9b334a45a8ff	735	for (i = 0; i < count32b; i++, src += 4)
bogdanm	0:9b334a45a8ff	736	{
bogdanm	0:9b334a45a8ff	737	USBx_DFIFO(ch_ep_num) = ((__packed uint32_t )src);
bogdanm	0:9b334a45a8ff	738	}
bogdanm	0:9b334a45a8ff	739	}
bogdanm	0:9b334a45a8ff	740	return HAL_OK;
bogdanm	0:9b334a45a8ff	741	}
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/**
bogdanm	0:9b334a45a8ff	744	* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
bogdanm	0:9b334a45a8ff	745	* with the EP/channel
bogdanm	0:9b334a45a8ff	746	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	747	* @param src: source pointer
bogdanm	0:9b334a45a8ff	748	* @param ch_ep_num: endpoint or host channel number
bogdanm	0:9b334a45a8ff	749	* @param len: Number of bytes to read
bogdanm	0:9b334a45a8ff	750	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	751	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	752	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	753	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	754	* @retval pointer to destination buffer
bogdanm	0:9b334a45a8ff	755	*/
bogdanm	0:9b334a45a8ff	756	void USB_ReadPacket(USB_OTG_GlobalTypeDef USBx, uint8_t *dest, uint16_t len)
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	uint32_t i=0;
bogdanm	0:9b334a45a8ff	759	uint32_t count32b = (len + 3) / 4;
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	for ( i = 0; i < count32b; i++, dest += 4 )
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	(__packed uint32_t )dest = USBx_DFIFO(0);
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	}
bogdanm	0:9b334a45a8ff	766	return ((void *)dest);
bogdanm	0:9b334a45a8ff	767	}
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/**
bogdanm	0:9b334a45a8ff	770	* @brief USB_EPSetStall : set a stall condition over an EP
bogdanm	0:9b334a45a8ff	771	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	772	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	773	* @retval HAL status
bogdanm	0:9b334a45a8ff	774	*/
bogdanm	0:9b334a45a8ff	775	HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	776	{
bogdanm	0:9b334a45a8ff	777	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	778	{
bogdanm	0:9b334a45a8ff	779	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_STALL;
bogdanm	0:9b334a45a8ff	784	}
bogdanm	0:9b334a45a8ff	785	else
bogdanm	0:9b334a45a8ff	786	{
bogdanm	0:9b334a45a8ff	787	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_STALL;
bogdanm	0:9b334a45a8ff	792	}
bogdanm	0:9b334a45a8ff	793	return HAL_OK;
bogdanm	0:9b334a45a8ff	794	}
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/**
bogdanm	0:9b334a45a8ff	798	* @brief USB_EPClearStall : Clear a stall condition over an EP
bogdanm	0:9b334a45a8ff	799	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	800	* @param ep: pointer to endpoint structure
bogdanm	0:9b334a45a8ff	801	* @retval HAL status
bogdanm	0:9b334a45a8ff	802	*/
bogdanm	0:9b334a45a8ff	803	HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	if (ep->is_in == 1)
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
bogdanm	0:9b334a45a8ff	808	if (ep->type == EP_TYPE_INTR \|\| ep->type == EP_TYPE_BULK)
bogdanm	0:9b334a45a8ff	809	{
bogdanm	0:9b334a45a8ff	810	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	}
bogdanm	0:9b334a45a8ff	813	else
bogdanm	0:9b334a45a8ff	814	{
bogdanm	0:9b334a45a8ff	815	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
bogdanm	0:9b334a45a8ff	816	if (ep->type == EP_TYPE_INTR \|\| ep->type == EP_TYPE_BULK)
bogdanm	0:9b334a45a8ff	817	{
bogdanm	0:9b334a45a8ff	818	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
bogdanm	0:9b334a45a8ff	819	}
bogdanm	0:9b334a45a8ff	820	}
bogdanm	0:9b334a45a8ff	821	return HAL_OK;
bogdanm	0:9b334a45a8ff	822	}
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/**
bogdanm	0:9b334a45a8ff	825	* @brief USB_StopDevice : Stop the USB device mode
bogdanm	0:9b334a45a8ff	826	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	827	* @retval HAL status
bogdanm	0:9b334a45a8ff	828	*/
bogdanm	0:9b334a45a8ff	829	HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	830	{
bogdanm	0:9b334a45a8ff	831	uint32_t i;
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/* Clear Pending interrupt */
bogdanm	0:9b334a45a8ff	834	for (i = 0; i < 15 ; i++)
bogdanm	0:9b334a45a8ff	835	{
bogdanm	0:9b334a45a8ff	836	USBx_INEP(i)->DIEPINT = 0xFF;
bogdanm	0:9b334a45a8ff	837	USBx_OUTEP(i)->DOEPINT = 0xFF;
bogdanm	0:9b334a45a8ff	838	}
bogdanm	0:9b334a45a8ff	839	USBx_DEVICE->DAINT = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Clear interrupt masks */
bogdanm	0:9b334a45a8ff	842	USBx_DEVICE->DIEPMSK = 0;
bogdanm	0:9b334a45a8ff	843	USBx_DEVICE->DOEPMSK = 0;
bogdanm	0:9b334a45a8ff	844	USBx_DEVICE->DAINTMSK = 0;
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Flush the FIFO */
bogdanm	0:9b334a45a8ff	847	USB_FlushRxFifo(USBx);
bogdanm	0:9b334a45a8ff	848	USB_FlushTxFifo(USBx , 0x10 );
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	return HAL_OK;
bogdanm	0:9b334a45a8ff	851	}
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	/**
bogdanm	0:9b334a45a8ff	854	* @brief USB_SetDevAddress : Stop the USB device mode
bogdanm	0:9b334a45a8ff	855	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	856	* @param address: new device address to be assigned
bogdanm	0:9b334a45a8ff	857	* This parameter can be a value from 0 to 255
bogdanm	0:9b334a45a8ff	858	* @retval HAL status
bogdanm	0:9b334a45a8ff	859	*/
bogdanm	0:9b334a45a8ff	860	HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
bogdanm	0:9b334a45a8ff	863	USBx_DEVICE->DCFG \|= (address << 4) & USB_OTG_DCFG_DAD ;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	return HAL_OK;
bogdanm	0:9b334a45a8ff	866	}
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/**
bogdanm	0:9b334a45a8ff	869	* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
bogdanm	0:9b334a45a8ff	870	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	871	* @retval HAL status
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	874	{
bogdanm	0:9b334a45a8ff	875	USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
bogdanm	0:9b334a45a8ff	876	HAL_Delay(3);
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	return HAL_OK;
bogdanm	0:9b334a45a8ff	879	}
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/**
bogdanm	0:9b334a45a8ff	882	* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
bogdanm	0:9b334a45a8ff	883	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	884	* @retval HAL status
bogdanm	0:9b334a45a8ff	885	*/
bogdanm	0:9b334a45a8ff	886	HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	USBx_DEVICE->DCTL \|= USB_OTG_DCTL_SDIS ;
bogdanm	0:9b334a45a8ff	889	HAL_Delay(3);
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	return HAL_OK;
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @brief USB_ReadInterrupts: return the global USB interrupt status
bogdanm	0:9b334a45a8ff	896	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	897	* @retval HAL status
bogdanm	0:9b334a45a8ff	898	*/
bogdanm	0:9b334a45a8ff	899	uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	uint32_t v = 0;
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	v = USBx->GINTSTS;
bogdanm	0:9b334a45a8ff	904	v &= USBx->GINTMSK;
bogdanm	0:9b334a45a8ff	905	return v;
bogdanm	0:9b334a45a8ff	906	}
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	/**
bogdanm	0:9b334a45a8ff	909	* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
bogdanm	0:9b334a45a8ff	910	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	911	* @retval HAL status
bogdanm	0:9b334a45a8ff	912	*/
bogdanm	0:9b334a45a8ff	913	uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	914	{
bogdanm	0:9b334a45a8ff	915	uint32_t v;
bogdanm	0:9b334a45a8ff	916	v = USBx_DEVICE->DAINT;
bogdanm	0:9b334a45a8ff	917	v &= USBx_DEVICE->DAINTMSK;
bogdanm	0:9b334a45a8ff	918	return ((v & 0xffff0000) >> 16);
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/**
bogdanm	0:9b334a45a8ff	922	* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
bogdanm	0:9b334a45a8ff	923	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	924	* @retval HAL status
bogdanm	0:9b334a45a8ff	925	*/
bogdanm	0:9b334a45a8ff	926	uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	927	{
bogdanm	0:9b334a45a8ff	928	uint32_t v;
bogdanm	0:9b334a45a8ff	929	v = USBx_DEVICE->DAINT;
bogdanm	0:9b334a45a8ff	930	v &= USBx_DEVICE->DAINTMSK;
bogdanm	0:9b334a45a8ff	931	return ((v & 0xFFFF));
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/**
bogdanm	0:9b334a45a8ff	935	* @brief Returns Device OUT EP Interrupt register
bogdanm	0:9b334a45a8ff	936	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	937	* @param epnum: endpoint number
bogdanm	0:9b334a45a8ff	938	* This parameter can be a value from 0 to 15
bogdanm	0:9b334a45a8ff	939	* @retval Device OUT EP Interrupt register
bogdanm	0:9b334a45a8ff	940	*/
bogdanm	0:9b334a45a8ff	941	uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
bogdanm	0:9b334a45a8ff	942	{
bogdanm	0:9b334a45a8ff	943	uint32_t v;
bogdanm	0:9b334a45a8ff	944	v = USBx_OUTEP(epnum)->DOEPINT;
bogdanm	0:9b334a45a8ff	945	v &= USBx_DEVICE->DOEPMSK;
bogdanm	0:9b334a45a8ff	946	return v;
bogdanm	0:9b334a45a8ff	947	}
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	/**
bogdanm	0:9b334a45a8ff	950	* @brief Returns Device IN EP Interrupt register
bogdanm	0:9b334a45a8ff	951	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	952	* @param epnum: endpoint number
bogdanm	0:9b334a45a8ff	953	* This parameter can be a value from 0 to 15
bogdanm	0:9b334a45a8ff	954	* @retval Device IN EP Interrupt register
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956	uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
bogdanm	0:9b334a45a8ff	957	{
bogdanm	0:9b334a45a8ff	958	uint32_t v, msk, emp;
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	msk = USBx_DEVICE->DIEPMSK;
bogdanm	0:9b334a45a8ff	961	emp = USBx_DEVICE->DIEPEMPMSK;
bogdanm	0:9b334a45a8ff	962	msk \|= ((emp >> epnum) & 0x1) << 7;
bogdanm	0:9b334a45a8ff	963	v = USBx_INEP(epnum)->DIEPINT & msk;
bogdanm	0:9b334a45a8ff	964	return v;
bogdanm	0:9b334a45a8ff	965	}
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	/**
bogdanm	0:9b334a45a8ff	968	* @brief USB_ClearInterrupts: clear a USB interrupt
bogdanm	0:9b334a45a8ff	969	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	970	* @param interrupt: interrupt flag
bogdanm	0:9b334a45a8ff	971	* @retval None
bogdanm	0:9b334a45a8ff	972	*/
bogdanm	0:9b334a45a8ff	973	void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
bogdanm	0:9b334a45a8ff	974	{
bogdanm	0:9b334a45a8ff	975	USBx->GINTSTS \|= interrupt;
bogdanm	0:9b334a45a8ff	976	}
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/**
bogdanm	0:9b334a45a8ff	979	* @brief Returns USB core mode
bogdanm	0:9b334a45a8ff	980	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	981	* @retval return core mode : Host or Device
bogdanm	0:9b334a45a8ff	982	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	983	* 0 : Host
bogdanm	0:9b334a45a8ff	984	* 1 : Device
bogdanm	0:9b334a45a8ff	985	*/
bogdanm	0:9b334a45a8ff	986	uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	987	{
bogdanm	0:9b334a45a8ff	988	return ((USBx->GINTSTS ) & 0x1);
bogdanm	0:9b334a45a8ff	989	}
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @brief Activate EP0 for Setup transactions
bogdanm	0:9b334a45a8ff	994	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	995	* @retval HAL status
bogdanm	0:9b334a45a8ff	996	*/
bogdanm	0:9b334a45a8ff	997	HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	/* Set the MPS of the IN EP based on the enumeration speed */
bogdanm	0:9b334a45a8ff	1000	USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
bogdanm	0:9b334a45a8ff	1003	{
bogdanm	0:9b334a45a8ff	1004	USBx_INEP(0)->DIEPCTL \|= 3;
bogdanm	0:9b334a45a8ff	1005	}
bogdanm	0:9b334a45a8ff	1006	USBx_DEVICE->DCTL \|= USB_OTG_DCTL_CGINAK;
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	return HAL_OK;
bogdanm	0:9b334a45a8ff	1009	}
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/**
bogdanm	0:9b334a45a8ff	1013	* @brief Prepare the EP0 to start the first control setup
bogdanm	0:9b334a45a8ff	1014	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1015	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	1016	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1017	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	1018	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	1019	* @param psetup: pointer to setup packet
bogdanm	0:9b334a45a8ff	1020	* @retval HAL status
bogdanm	0:9b334a45a8ff	1021	*/
bogdanm	0:9b334a45a8ff	1022	HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef USBx, uint8_t dma, uint8_t psetup)
bogdanm	0:9b334a45a8ff	1023	{
bogdanm	0:9b334a45a8ff	1024	USBx_OUTEP(0)->DOEPTSIZ = 0;
bogdanm	0:9b334a45a8ff	1025	USBx_OUTEP(0)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
bogdanm	0:9b334a45a8ff	1026	USBx_OUTEP(0)->DOEPTSIZ \|= (3 * 8);
bogdanm	0:9b334a45a8ff	1027	USBx_OUTEP(0)->DOEPTSIZ \|= USB_OTG_DOEPTSIZ_STUPCNT;
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	if (dma == 1)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
bogdanm	0:9b334a45a8ff	1032	/* EP enable */
bogdanm	0:9b334a45a8ff	1033	USBx_OUTEP(0)->DOEPCTL = 0x80008000;
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	return HAL_OK;
bogdanm	0:9b334a45a8ff	1037	}
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/**
bogdanm	0:9b334a45a8ff	1041	* @brief Reset the USB Core (needed after USB clock settings change)
bogdanm	0:9b334a45a8ff	1042	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1043	* @retval HAL status
bogdanm	0:9b334a45a8ff	1044	*/
bogdanm	0:9b334a45a8ff	1045	static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1046	{
bogdanm	0:9b334a45a8ff	1047	uint32_t count = 0;
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/* Wait for AHB master IDLE state. */
bogdanm	0:9b334a45a8ff	1050	do
bogdanm	0:9b334a45a8ff	1051	{
bogdanm	0:9b334a45a8ff	1052	if (++count > 200000)
bogdanm	0:9b334a45a8ff	1053	{
bogdanm	0:9b334a45a8ff	1054	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1055	}
bogdanm	0:9b334a45a8ff	1056	}
bogdanm	0:9b334a45a8ff	1057	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/* Core Soft Reset */
bogdanm	0:9b334a45a8ff	1060	count = 0;
bogdanm	0:9b334a45a8ff	1061	USBx->GRSTCTL \|= USB_OTG_GRSTCTL_CSRST;
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	do
bogdanm	0:9b334a45a8ff	1064	{
bogdanm	0:9b334a45a8ff	1065	if (++count > 200000)
bogdanm	0:9b334a45a8ff	1066	{
bogdanm	0:9b334a45a8ff	1067	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1068	}
bogdanm	0:9b334a45a8ff	1069	}
bogdanm	0:9b334a45a8ff	1070	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	return HAL_OK;
bogdanm	0:9b334a45a8ff	1073	}
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/**
bogdanm	0:9b334a45a8ff	1077	* @brief USB_HostInit : Initializes the USB OTG controller registers
bogdanm	0:9b334a45a8ff	1078	* for Host mode
bogdanm	0:9b334a45a8ff	1079	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1080	* @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1081	* the configuration information for the specified USBx peripheral.
bogdanm	0:9b334a45a8ff	1082	* @retval HAL status
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084	HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
bogdanm	0:9b334a45a8ff	1085	{
bogdanm	0:9b334a45a8ff	1086	uint32_t i;
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/* Restart the Phy Clock */
bogdanm	0:9b334a45a8ff	1089	USBx_PCGCCTL = 0;
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/Activate VBUS Sensing B /
bogdanm	0:9b334a45a8ff	1092	USBx->GCCFG \|= USB_OTG_GCCFG_VBDEN;
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	/* Disable the FS/LS support mode only */
bogdanm	0:9b334a45a8ff	1095	if((cfg.speed == USB_OTG_SPEED_FULL)&&
bogdanm	0:9b334a45a8ff	1096	(USBx != USB_OTG_FS))
bogdanm	0:9b334a45a8ff	1097	{
bogdanm	0:9b334a45a8ff	1098	USBx_HOST->HCFG \|= USB_OTG_HCFG_FSLSS;
bogdanm	0:9b334a45a8ff	1099	}
bogdanm	0:9b334a45a8ff	1100	else
bogdanm	0:9b334a45a8ff	1101	{
bogdanm	0:9b334a45a8ff	1102	USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
bogdanm	0:9b334a45a8ff	1103	}
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/* Make sure the FIFOs are flushed. */
bogdanm	0:9b334a45a8ff	1106	USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
bogdanm	0:9b334a45a8ff	1107	USB_FlushRxFifo(USBx);
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Clear all pending HC Interrupts */
bogdanm	0:9b334a45a8ff	1110	for (i = 0; i < cfg.Host_channels; i++)
bogdanm	0:9b334a45a8ff	1111	{
bogdanm	0:9b334a45a8ff	1112	USBx_HC(i)->HCINT = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	1113	USBx_HC(i)->HCINTMSK = 0;
bogdanm	0:9b334a45a8ff	1114	}
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/* Enable VBUS driving */
bogdanm	0:9b334a45a8ff	1117	USB_DriveVbus(USBx, 1);
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	HAL_Delay(200);
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/* Disable all interrupts. */
bogdanm	0:9b334a45a8ff	1122	USBx->GINTMSK = 0;
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/* Clear any pending interrupts */
bogdanm	0:9b334a45a8ff	1125	USBx->GINTSTS = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/* set Rx FIFO size */
bogdanm	0:9b334a45a8ff	1128	USBx->GRXFSIZ = (uint32_t )0x80;
bogdanm	0:9b334a45a8ff	1129	USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) \| 0x80);
bogdanm	0:9b334a45a8ff	1130	USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) \| 0xE0);
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/* Enable the common interrupts */
bogdanm	0:9b334a45a8ff	1133	if (cfg.dma_enable == DISABLE)
bogdanm	0:9b334a45a8ff	1134	{
bogdanm	0:9b334a45a8ff	1135	USBx->GINTMSK \|= USB_OTG_GINTMSK_RXFLVLM;
bogdanm	0:9b334a45a8ff	1136	}
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	/* Enable interrupts matching to the Host mode ONLY */
bogdanm	0:9b334a45a8ff	1139	USBx->GINTMSK \|= (USB_OTG_GINTMSK_PRTIM \| USB_OTG_GINTMSK_HCIM \|\
bogdanm	0:9b334a45a8ff	1140	USB_OTG_GINTMSK_SOFM \|USB_OTG_GINTSTS_DISCINT\|\
bogdanm	0:9b334a45a8ff	1141	USB_OTG_GINTMSK_PXFRM_IISOOXFRM \| USB_OTG_GINTMSK_WUIM);
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	return HAL_OK;
bogdanm	0:9b334a45a8ff	1144	}
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/**
bogdanm	0:9b334a45a8ff	1147	* @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
bogdanm	0:9b334a45a8ff	1148	* HCFG register on the PHY type and set the right frame interval
bogdanm	0:9b334a45a8ff	1149	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1150	* @param freq: clock frequency
bogdanm	0:9b334a45a8ff	1151	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1152	* HCFG_48_MHZ : Full Speed 48 MHz Clock
bogdanm	0:9b334a45a8ff	1153	* HCFG_6_MHZ : Low Speed 6 MHz Clock
bogdanm	0:9b334a45a8ff	1154	* @retval HAL status
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156	HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
bogdanm	0:9b334a45a8ff	1157	{
bogdanm	0:9b334a45a8ff	1158	USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
bogdanm	0:9b334a45a8ff	1159	USBx_HOST->HCFG \|= (freq & USB_OTG_HCFG_FSLSPCS);
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	if (freq == HCFG_48_MHZ)
bogdanm	0:9b334a45a8ff	1162	{
bogdanm	0:9b334a45a8ff	1163	USBx_HOST->HFIR = (uint32_t)48000;
bogdanm	0:9b334a45a8ff	1164	}
bogdanm	0:9b334a45a8ff	1165	else if (freq == HCFG_6_MHZ)
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	USBx_HOST->HFIR = (uint32_t)6000;
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169	return HAL_OK;
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	/**
bogdanm	0:9b334a45a8ff	1173	* @brief USB_OTG_ResetPort : Reset Host Port
bogdanm	0:9b334a45a8ff	1174	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1175	* @retval HAL status
bogdanm	0:9b334a45a8ff	1176	* @note (1)The application must wait at least 10 ms
bogdanm	0:9b334a45a8ff	1177	* before clearing the reset bit.
bogdanm	0:9b334a45a8ff	1178	*/
bogdanm	0:9b334a45a8ff	1179	HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1180	{
bogdanm	0:9b334a45a8ff	1181	__IO uint32_t hprt0;
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	hprt0 = USBx_HPRT0;
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	hprt0 &= ~(USB_OTG_HPRT_PENA \| USB_OTG_HPRT_PCDET \|\
bogdanm	0:9b334a45a8ff	1186	USB_OTG_HPRT_PENCHNG \| USB_OTG_HPRT_POCCHNG );
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	USBx_HPRT0 = (USB_OTG_HPRT_PRST \| hprt0);
bogdanm	0:9b334a45a8ff	1189	HAL_Delay (10); /* See Note #1 */
bogdanm	0:9b334a45a8ff	1190	USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
bogdanm	0:9b334a45a8ff	1191	return HAL_OK;
bogdanm	0:9b334a45a8ff	1192	}
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/**
bogdanm	0:9b334a45a8ff	1195	* @brief USB_DriveVbus : activate or de-activate vbus
bogdanm	0:9b334a45a8ff	1196	* @param state: VBUS state
bogdanm	0:9b334a45a8ff	1197	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1198	* 0 : VBUS Active
bogdanm	0:9b334a45a8ff	1199	* 1 : VBUS Inactive
bogdanm	0:9b334a45a8ff	1200	* @retval HAL status
bogdanm	0:9b334a45a8ff	1201	*/
bogdanm	0:9b334a45a8ff	1202	HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
bogdanm	0:9b334a45a8ff	1203	{
bogdanm	0:9b334a45a8ff	1204	__IO uint32_t hprt0;
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	hprt0 = USBx_HPRT0;
bogdanm	0:9b334a45a8ff	1207	hprt0 &= ~(USB_OTG_HPRT_PENA \| USB_OTG_HPRT_PCDET \|\
bogdanm	0:9b334a45a8ff	1208	USB_OTG_HPRT_PENCHNG \| USB_OTG_HPRT_POCCHNG );
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
bogdanm	0:9b334a45a8ff	1211	{
bogdanm	0:9b334a45a8ff	1212	USBx_HPRT0 = (USB_OTG_HPRT_PPWR \| hprt0);
bogdanm	0:9b334a45a8ff	1213	}
bogdanm	0:9b334a45a8ff	1214	if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
bogdanm	0:9b334a45a8ff	1215	{
bogdanm	0:9b334a45a8ff	1216	USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
bogdanm	0:9b334a45a8ff	1217	}
bogdanm	0:9b334a45a8ff	1218	return HAL_OK;
bogdanm	0:9b334a45a8ff	1219	}
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/**
bogdanm	0:9b334a45a8ff	1222	* @brief Return Host Core speed
bogdanm	0:9b334a45a8ff	1223	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1224	* @retval speed : Host speed
bogdanm	0:9b334a45a8ff	1225	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1226	* @arg USB_OTG_SPEED_HIGH: High speed mode
bogdanm	0:9b334a45a8ff	1227	* @arg USB_OTG_SPEED_FULL: Full speed mode
bogdanm	0:9b334a45a8ff	1228	* @arg USB_OTG_SPEED_LOW: Low speed mode
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230	uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1231	{
bogdanm	0:9b334a45a8ff	1232	__IO uint32_t hprt0;
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	hprt0 = USBx_HPRT0;
bogdanm	0:9b334a45a8ff	1235	return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/**
bogdanm	0:9b334a45a8ff	1239	* @brief Return Host Current Frame number
bogdanm	0:9b334a45a8ff	1240	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1241	* @retval current frame number
bogdanm	0:9b334a45a8ff	1242	*/
bogdanm	0:9b334a45a8ff	1243	uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1244	{
bogdanm	0:9b334a45a8ff	1245	return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
bogdanm	0:9b334a45a8ff	1246	}
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/**
bogdanm	0:9b334a45a8ff	1249	* @brief Initialize a host channel
bogdanm	0:9b334a45a8ff	1250	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1251	* @param ch_num : Channel number
bogdanm	0:9b334a45a8ff	1252	* This parameter can be a value from 1 to 15
bogdanm	0:9b334a45a8ff	1253	* @param epnum: Endpoint number
bogdanm	0:9b334a45a8ff	1254	* This parameter can be a value from 1 to 15
bogdanm	0:9b334a45a8ff	1255	* @param dev_address: Current device address
bogdanm	0:9b334a45a8ff	1256	* This parameter can be a value from 0 to 255
bogdanm	0:9b334a45a8ff	1257	* @param speed: Current device speed
bogdanm	0:9b334a45a8ff	1258	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1259	* @arg USB_OTG_SPEED_HIGH: High speed mode
bogdanm	0:9b334a45a8ff	1260	* @arg USB_OTG_SPEED_FULL: Full speed mode
bogdanm	0:9b334a45a8ff	1261	* @arg USB_OTG_SPEED_LOW: Low speed mode
bogdanm	0:9b334a45a8ff	1262	* @param ep_type: Endpoint Type
bogdanm	0:9b334a45a8ff	1263	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1264	* @arg EP_TYPE_CTRL: Control type
bogdanm	0:9b334a45a8ff	1265	* @arg EP_TYPE_ISOC: Isochronous type
bogdanm	0:9b334a45a8ff	1266	* @arg EP_TYPE_BULK: Bulk type
bogdanm	0:9b334a45a8ff	1267	* @arg EP_TYPE_INTR: Interrupt type
bogdanm	0:9b334a45a8ff	1268	* @param mps: Max Packet Size
bogdanm	0:9b334a45a8ff	1269	* This parameter can be a value from 0 to32K
bogdanm	0:9b334a45a8ff	1270	* @retval HAL state
bogdanm	0:9b334a45a8ff	1271	*/
bogdanm	0:9b334a45a8ff	1272	HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
bogdanm	0:9b334a45a8ff	1273	uint8_t ch_num,
bogdanm	0:9b334a45a8ff	1274	uint8_t epnum,
bogdanm	0:9b334a45a8ff	1275	uint8_t dev_address,
bogdanm	0:9b334a45a8ff	1276	uint8_t speed,
bogdanm	0:9b334a45a8ff	1277	uint8_t ep_type,
bogdanm	0:9b334a45a8ff	1278	uint16_t mps)
bogdanm	0:9b334a45a8ff	1279	{
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	/* Clear old interrupt conditions for this host channel. */
bogdanm	0:9b334a45a8ff	1282	USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	/* Enable channel interrupts required for this transfer. */
bogdanm	0:9b334a45a8ff	1285	switch (ep_type)
bogdanm	0:9b334a45a8ff	1286	{
bogdanm	0:9b334a45a8ff	1287	case EP_TYPE_CTRL:
bogdanm	0:9b334a45a8ff	1288	case EP_TYPE_BULK:
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
bogdanm	0:9b334a45a8ff	1291	USB_OTG_HCINTMSK_STALLM \|\
bogdanm	0:9b334a45a8ff	1292	USB_OTG_HCINTMSK_TXERRM \|\
bogdanm	0:9b334a45a8ff	1293	USB_OTG_HCINTMSK_DTERRM \|\
bogdanm	0:9b334a45a8ff	1294	USB_OTG_HCINTMSK_AHBERR \|\
bogdanm	0:9b334a45a8ff	1295	USB_OTG_HCINTMSK_NAKM ;
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	if (epnum & 0x80)
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	USBx_HC(ch_num)->HCINTMSK \|= USB_OTG_HCINTMSK_BBERRM;
bogdanm	0:9b334a45a8ff	1300	}
bogdanm	0:9b334a45a8ff	1301	break;
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	case EP_TYPE_INTR:
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
bogdanm	0:9b334a45a8ff	1306	USB_OTG_HCINTMSK_STALLM \|\
bogdanm	0:9b334a45a8ff	1307	USB_OTG_HCINTMSK_TXERRM \|\
bogdanm	0:9b334a45a8ff	1308	USB_OTG_HCINTMSK_DTERRM \|\
bogdanm	0:9b334a45a8ff	1309	USB_OTG_HCINTMSK_NAKM \|\
bogdanm	0:9b334a45a8ff	1310	USB_OTG_HCINTMSK_AHBERR \|\
bogdanm	0:9b334a45a8ff	1311	USB_OTG_HCINTMSK_FRMORM ;
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	if (epnum & 0x80)
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	USBx_HC(ch_num)->HCINTMSK \|= USB_OTG_HCINTMSK_BBERRM;
bogdanm	0:9b334a45a8ff	1316	}
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	break;
bogdanm	0:9b334a45a8ff	1319	case EP_TYPE_ISOC:
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
bogdanm	0:9b334a45a8ff	1322	USB_OTG_HCINTMSK_ACKM \|\
bogdanm	0:9b334a45a8ff	1323	USB_OTG_HCINTMSK_AHBERR \|\
bogdanm	0:9b334a45a8ff	1324	USB_OTG_HCINTMSK_FRMORM ;
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	if (epnum & 0x80)
bogdanm	0:9b334a45a8ff	1327	{
bogdanm	0:9b334a45a8ff	1328	USBx_HC(ch_num)->HCINTMSK \|= (USB_OTG_HCINTMSK_TXERRM \| USB_OTG_HCINTMSK_BBERRM);
bogdanm	0:9b334a45a8ff	1329	}
bogdanm	0:9b334a45a8ff	1330	break;
bogdanm	0:9b334a45a8ff	1331	}
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/* Enable the top level host channel interrupt. */
bogdanm	0:9b334a45a8ff	1334	USBx_HOST->HAINTMSK \|= (1 << ch_num);
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Make sure host channel interrupts are enabled. */
bogdanm	0:9b334a45a8ff	1337	USBx->GINTMSK \|= USB_OTG_GINTMSK_HCIM;
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Program the HCCHAR register */
bogdanm	0:9b334a45a8ff	1340	USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) \|\
bogdanm	0:9b334a45a8ff	1341	(((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)\|\
bogdanm	0:9b334a45a8ff	1342	((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)\|\
bogdanm	0:9b334a45a8ff	1343	(((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)\|\
bogdanm	0:9b334a45a8ff	1344	((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)\|\
bogdanm	0:9b334a45a8ff	1345	(mps & USB_OTG_HCCHAR_MPSIZ));
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	if (ep_type == EP_TYPE_INTR)
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	USBx_HC(ch_num)->HCCHAR \|= USB_OTG_HCCHAR_ODDFRM ;
bogdanm	0:9b334a45a8ff	1350	}
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	return HAL_OK;
bogdanm	0:9b334a45a8ff	1353	}
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/**
bogdanm	0:9b334a45a8ff	1356	* @brief Start a transfer over a host channel
bogdanm	0:9b334a45a8ff	1357	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1358	* @param hc: pointer to host channel structure
bogdanm	0:9b334a45a8ff	1359	* @param dma: USB dma enabled or disabled
bogdanm	0:9b334a45a8ff	1360	* This parameter can be one of these values:
bogdanm	0:9b334a45a8ff	1361	* 0 : DMA feature not used
bogdanm	0:9b334a45a8ff	1362	* 1 : DMA feature used
bogdanm	0:9b334a45a8ff	1363	* @retval HAL state
bogdanm	0:9b334a45a8ff	1364	*/
bogdanm	0:9b334a45a8ff	1365	#if defined (__CC_ARM) /!< ARM Compiler /
bogdanm	0:9b334a45a8ff	1366	#pragma O0
bogdanm	0:9b334a45a8ff	1367	#elif defined (__GNUC__) /!< GNU Compiler /
bogdanm	0:9b334a45a8ff	1368	#pragma GCC optimize ("O0")
bogdanm	0:9b334a45a8ff	1369	#endif /* __CC_ARM */
bogdanm	0:9b334a45a8ff	1370	HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef USBx, USB_OTG_HCTypeDef hc, uint8_t dma)
bogdanm	0:9b334a45a8ff	1371	{
bogdanm	0:9b334a45a8ff	1372	uint8_t is_oddframe = 0;
bogdanm	0:9b334a45a8ff	1373	uint16_t len_words = 0;
bogdanm	0:9b334a45a8ff	1374	uint16_t num_packets = 0;
bogdanm	0:9b334a45a8ff	1375	uint16_t max_hc_pkt_count = 256;
bogdanm	0:9b334a45a8ff	1376	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	/* Compute the expected number of packets associated to the transfer */
bogdanm	0:9b334a45a8ff	1379	if (hc->xfer_len > 0)
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	if (num_packets > max_hc_pkt_count)
bogdanm	0:9b334a45a8ff	1384	{
bogdanm	0:9b334a45a8ff	1385	num_packets = max_hc_pkt_count;
bogdanm	0:9b334a45a8ff	1386	hc->xfer_len = num_packets * hc->max_packet;
bogdanm	0:9b334a45a8ff	1387	}
bogdanm	0:9b334a45a8ff	1388	}
bogdanm	0:9b334a45a8ff	1389	else
bogdanm	0:9b334a45a8ff	1390	{
bogdanm	0:9b334a45a8ff	1391	num_packets = 1;
bogdanm	0:9b334a45a8ff	1392	}
bogdanm	0:9b334a45a8ff	1393	if (hc->ep_is_in)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	hc->xfer_len = num_packets * hc->max_packet;
bogdanm	0:9b334a45a8ff	1396	}
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	/* Initialize the HCTSIZn register */
bogdanm	0:9b334a45a8ff	1399	USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) \|\
bogdanm	0:9b334a45a8ff	1400	((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) \|\
bogdanm	0:9b334a45a8ff	1401	(((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	if (dma)
bogdanm	0:9b334a45a8ff	1404	{
bogdanm	0:9b334a45a8ff	1405	/* xfer_buff MUST be 32-bits aligned */
bogdanm	0:9b334a45a8ff	1406	USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
bogdanm	0:9b334a45a8ff	1407	}
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
bogdanm	0:9b334a45a8ff	1410	USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
bogdanm	0:9b334a45a8ff	1411	USBx_HC(hc->ch_num)->HCCHAR \|= (is_oddframe << 29);
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Set host channel enable */
bogdanm	0:9b334a45a8ff	1414	tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
bogdanm	0:9b334a45a8ff	1415	tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1416	tmpreg \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1417	USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	if (dma == 0) /* Slave mode */
bogdanm	0:9b334a45a8ff	1420	{
bogdanm	0:9b334a45a8ff	1421	if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	switch(hc->ep_type)
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	/* Non periodic transfer */
bogdanm	0:9b334a45a8ff	1426	case EP_TYPE_CTRL:
bogdanm	0:9b334a45a8ff	1427	case EP_TYPE_BULK:
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	len_words = (hc->xfer_len + 3) / 4;
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	/* check if there is enough space in FIFO space */
bogdanm	0:9b334a45a8ff	1432	if(len_words > (USBx->HNPTXSTS & 0xFFFF))
bogdanm	0:9b334a45a8ff	1433	{
bogdanm	0:9b334a45a8ff	1434	/* need to process data in nptxfempty interrupt */
bogdanm	0:9b334a45a8ff	1435	USBx->GINTMSK \|= USB_OTG_GINTMSK_NPTXFEM;
bogdanm	0:9b334a45a8ff	1436	}
bogdanm	0:9b334a45a8ff	1437	break;
bogdanm	0:9b334a45a8ff	1438	/* Periodic transfer */
bogdanm	0:9b334a45a8ff	1439	case EP_TYPE_INTR:
bogdanm	0:9b334a45a8ff	1440	case EP_TYPE_ISOC:
bogdanm	0:9b334a45a8ff	1441	len_words = (hc->xfer_len + 3) / 4;
bogdanm	0:9b334a45a8ff	1442	/* check if there is enough space in FIFO space */
bogdanm	0:9b334a45a8ff	1443	if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
bogdanm	0:9b334a45a8ff	1444	{
bogdanm	0:9b334a45a8ff	1445	/* need to process data in ptxfempty interrupt */
bogdanm	0:9b334a45a8ff	1446	USBx->GINTMSK \|= USB_OTG_GINTMSK_PTXFEM;
bogdanm	0:9b334a45a8ff	1447	}
bogdanm	0:9b334a45a8ff	1448	break;
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	default:
bogdanm	0:9b334a45a8ff	1451	break;
bogdanm	0:9b334a45a8ff	1452	}
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	/* Write packet into the Tx FIFO. */
bogdanm	0:9b334a45a8ff	1455	USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457	}
bogdanm	0:9b334a45a8ff	1458
bogdanm	0:9b334a45a8ff	1459	return HAL_OK;
bogdanm	0:9b334a45a8ff	1460	}
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/**
bogdanm	0:9b334a45a8ff	1463	* @brief Read all host channel interrupts status
bogdanm	0:9b334a45a8ff	1464	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1465	* @retval HAL state
bogdanm	0:9b334a45a8ff	1466	*/
bogdanm	0:9b334a45a8ff	1467	uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	return ((USBx_HOST->HAINT) & 0xFFFF);
bogdanm	0:9b334a45a8ff	1470	}
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	/**
bogdanm	0:9b334a45a8ff	1473	* @brief Halt a host channel
bogdanm	0:9b334a45a8ff	1474	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1475	* @param hc_num: Host Channel number
bogdanm	0:9b334a45a8ff	1476	* This parameter can be a value from 1 to 15
bogdanm	0:9b334a45a8ff	1477	* @retval HAL state
bogdanm	0:9b334a45a8ff	1478	*/
bogdanm	0:9b334a45a8ff	1479	HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
bogdanm	0:9b334a45a8ff	1480	{
bogdanm	0:9b334a45a8ff	1481	uint32_t count = 0;
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	/* Check for space in the request queue to issue the halt. */
bogdanm	0:9b334a45a8ff	1484	if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) \|\| ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
bogdanm	0:9b334a45a8ff	1485	{
bogdanm	0:9b334a45a8ff	1486	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	if ((USBx->HNPTXSTS & 0xFFFF) == 0)
bogdanm	0:9b334a45a8ff	1489	{
bogdanm	0:9b334a45a8ff	1490	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1491	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1492	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
bogdanm	0:9b334a45a8ff	1493	do
bogdanm	0:9b334a45a8ff	1494	{
bogdanm	0:9b334a45a8ff	1495	if (++count > 1000)
bogdanm	0:9b334a45a8ff	1496	{
bogdanm	0:9b334a45a8ff	1497	break;
bogdanm	0:9b334a45a8ff	1498	}
bogdanm	0:9b334a45a8ff	1499	}
bogdanm	0:9b334a45a8ff	1500	while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
bogdanm	0:9b334a45a8ff	1501	}
bogdanm	0:9b334a45a8ff	1502	else
bogdanm	0:9b334a45a8ff	1503	{
bogdanm	0:9b334a45a8ff	1504	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1505	}
bogdanm	0:9b334a45a8ff	1506	}
bogdanm	0:9b334a45a8ff	1507	else
bogdanm	0:9b334a45a8ff	1508	{
bogdanm	0:9b334a45a8ff	1509	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
bogdanm	0:9b334a45a8ff	1512	{
bogdanm	0:9b334a45a8ff	1513	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1514	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1515	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
bogdanm	0:9b334a45a8ff	1516	do
bogdanm	0:9b334a45a8ff	1517	{
bogdanm	0:9b334a45a8ff	1518	if (++count > 1000)
bogdanm	0:9b334a45a8ff	1519	{
bogdanm	0:9b334a45a8ff	1520	break;
bogdanm	0:9b334a45a8ff	1521	}
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523	while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
bogdanm	0:9b334a45a8ff	1524	}
bogdanm	0:9b334a45a8ff	1525	else
bogdanm	0:9b334a45a8ff	1526	{
bogdanm	0:9b334a45a8ff	1527	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529	}
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	return HAL_OK;
bogdanm	0:9b334a45a8ff	1532	}
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	/**
bogdanm	0:9b334a45a8ff	1535	* @brief Initiate Do Ping protocol
bogdanm	0:9b334a45a8ff	1536	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1537	* @param hc_num: Host Channel number
bogdanm	0:9b334a45a8ff	1538	* This parameter can be a value from 1 to 15
bogdanm	0:9b334a45a8ff	1539	* @retval HAL state
bogdanm	0:9b334a45a8ff	1540	*/
bogdanm	0:9b334a45a8ff	1541	HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
bogdanm	0:9b334a45a8ff	1542	{
bogdanm	0:9b334a45a8ff	1543	uint8_t num_packets = 1;
bogdanm	0:9b334a45a8ff	1544	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) \|\
bogdanm	0:9b334a45a8ff	1547	USB_OTG_HCTSIZ_DOPING;
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549	/* Set host channel enable */
bogdanm	0:9b334a45a8ff	1550	tmpreg = USBx_HC(ch_num)->HCCHAR;
bogdanm	0:9b334a45a8ff	1551	tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1552	tmpreg \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1553	USBx_HC(ch_num)->HCCHAR = tmpreg;
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	return HAL_OK;
bogdanm	0:9b334a45a8ff	1556	}
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/**
bogdanm	0:9b334a45a8ff	1559	* @brief Stop Host Core
bogdanm	0:9b334a45a8ff	1560	* @param USBx: Selected device
bogdanm	0:9b334a45a8ff	1561	* @retval HAL state
bogdanm	0:9b334a45a8ff	1562	*/
bogdanm	0:9b334a45a8ff	1563	HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
bogdanm	0:9b334a45a8ff	1564	{
bogdanm	0:9b334a45a8ff	1565	uint8_t i;
bogdanm	0:9b334a45a8ff	1566	uint32_t count = 0;
bogdanm	0:9b334a45a8ff	1567	uint32_t value;
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	USB_DisableGlobalInt(USBx);
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	/* Flush FIFO */
bogdanm	0:9b334a45a8ff	1572	USB_FlushTxFifo(USBx, 0x10);
bogdanm	0:9b334a45a8ff	1573	USB_FlushRxFifo(USBx);
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	/* Flush out any leftover queued requests. */
bogdanm	0:9b334a45a8ff	1576	for (i = 0; i <= 15; i++)
bogdanm	0:9b334a45a8ff	1577	{
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	value = USBx_HC(i)->HCCHAR ;
bogdanm	0:9b334a45a8ff	1580	value \|= USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1581	value &= ~USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1582	value &= ~USB_OTG_HCCHAR_EPDIR;
bogdanm	0:9b334a45a8ff	1583	USBx_HC(i)->HCCHAR = value;
bogdanm	0:9b334a45a8ff	1584	}
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/* Halt all channels to put them into a known state. */
bogdanm	0:9b334a45a8ff	1587	for (i = 0; i <= 15; i++)
bogdanm	0:9b334a45a8ff	1588	{
bogdanm	0:9b334a45a8ff	1589	value = USBx_HC(i)->HCCHAR ;
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	value \|= USB_OTG_HCCHAR_CHDIS;
bogdanm	0:9b334a45a8ff	1592	value \|= USB_OTG_HCCHAR_CHENA;
bogdanm	0:9b334a45a8ff	1593	value &= ~USB_OTG_HCCHAR_EPDIR;
bogdanm	0:9b334a45a8ff	1594
bogdanm	0:9b334a45a8ff	1595	USBx_HC(i)->HCCHAR = value;
bogdanm	0:9b334a45a8ff	1596	do
bogdanm	0:9b334a45a8ff	1597	{
bogdanm	0:9b334a45a8ff	1598	if (++count > 1000)
bogdanm	0:9b334a45a8ff	1599	{
bogdanm	0:9b334a45a8ff	1600	break;
bogdanm	0:9b334a45a8ff	1601	}
bogdanm	0:9b334a45a8ff	1602	}
bogdanm	0:9b334a45a8ff	1603	while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
bogdanm	0:9b334a45a8ff	1604	}
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/* Clear any pending Host interrupts */
bogdanm	0:9b334a45a8ff	1607	USBx_HOST->HAINT = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	1608	USBx->GINTSTS = 0xFFFFFFFF;
bogdanm	0:9b334a45a8ff	1609	USB_EnableGlobalInt(USBx);
bogdanm	0:9b334a45a8ff	1610	return HAL_OK;
bogdanm	0:9b334a45a8ff	1611	}
bogdanm	0:9b334a45a8ff	1612	/**
bogdanm	0:9b334a45a8ff	1613	* @}
bogdanm	0:9b334a45a8ff	1614	*/
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	#endif /* defined (HAL_PCD_MODULE_ENABLED) \|\| defined (HAL_HCD_MODULE_ENABLED) */
bogdanm	0:9b334a45a8ff	1617
bogdanm	0:9b334a45a8ff	1618	/**
bogdanm	0:9b334a45a8ff	1619	* @}
bogdanm	0:9b334a45a8ff	1620	*/
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
bogdanm	0:9b334a45a8ff	1623
bogdanm	0:9b334a45a8ff	1624	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_usb.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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