en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_fmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_ll_fmc.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief FMC Low Layer HAL module driver. |
| bogdanm | 0:9b334a45a8ff | 8 | * This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 9 | * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
| bogdanm | 0:9b334a45a8ff | 10 | * + Initialization/de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 11 | * + Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 12 | * + Peripheral State functions |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 15 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 16 | ##### FMC peripheral features ##### |
| bogdanm | 0:9b334a45a8ff | 17 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 18 | [..] The Flexible memory controller (FMC) includes following memory controllers: |
| bogdanm | 0:9b334a45a8ff | 19 | (+) The NOR/PSRAM memory controller |
| bogdanm | 0:9b334a45a8ff | 20 | (+) The NAND memory controller |
| bogdanm | 0:9b334a45a8ff | 21 | |
| bogdanm | 0:9b334a45a8ff | 22 | [..] The FMC functional block makes the interface with synchronous and asynchronous static |
| bogdanm | 0:9b334a45a8ff | 23 | memories and 16-bit PC memory cards. Its main purposes are: |
| bogdanm | 0:9b334a45a8ff | 24 | (+) to translate AHB transactions into the appropriate external device protocol. |
| bogdanm | 0:9b334a45a8ff | 25 | (+) to meet the access time requirements of the external memory devices. |
| bogdanm | 0:9b334a45a8ff | 26 | |
| bogdanm | 0:9b334a45a8ff | 27 | [..] All external memories share the addresses, data and control signals with the controller. |
| bogdanm | 0:9b334a45a8ff | 28 | Each external device is accessed by means of a unique Chip Select. The FMC performs |
| bogdanm | 0:9b334a45a8ff | 29 | only one access at a time to an external device. |
| bogdanm | 0:9b334a45a8ff | 30 | The main features of the FMC controller are the following: |
| bogdanm | 0:9b334a45a8ff | 31 | (+) Interface with static-memory mapped devices including: |
| bogdanm | 0:9b334a45a8ff | 32 | (++) Static random access memory (SRAM). |
| bogdanm | 0:9b334a45a8ff | 33 | (++) NOR Flash memory. |
| bogdanm | 0:9b334a45a8ff | 34 | (++) PSRAM (4 memory banks). |
| bogdanm | 0:9b334a45a8ff | 35 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
| bogdanm | 0:9b334a45a8ff | 36 | data |
| bogdanm | 0:9b334a45a8ff | 37 | (+) Independent Chip Select control for each memory bank |
| bogdanm | 0:9b334a45a8ff | 38 | (+) Independent configuration for each memory bank |
| bogdanm | 0:9b334a45a8ff | 39 | |
| bogdanm | 0:9b334a45a8ff | 40 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 41 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 42 | * @attention |
| bogdanm | 0:9b334a45a8ff | 43 | * |
| bogdanm | 0:9b334a45a8ff | 44 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 45 | * |
| bogdanm | 0:9b334a45a8ff | 46 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 47 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 48 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 49 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 50 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 51 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 52 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 53 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 54 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 55 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 56 | * |
| bogdanm | 0:9b334a45a8ff | 57 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 58 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 59 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 60 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 61 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 62 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 63 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 64 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 65 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 66 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 67 | * |
| bogdanm | 0:9b334a45a8ff | 68 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 69 | */ |
| bogdanm | 0:9b334a45a8ff | 70 | |
| bogdanm | 0:9b334a45a8ff | 71 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 72 | #include "stm32l4xx_hal.h" |
| bogdanm | 0:9b334a45a8ff | 73 | |
| bogdanm | 0:9b334a45a8ff | 74 | /** @addtogroup STM32L4xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 75 | * @{ |
| bogdanm | 0:9b334a45a8ff | 76 | */ |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) |
| bogdanm | 0:9b334a45a8ff | 79 | |
| bogdanm | 0:9b334a45a8ff | 80 | /** @defgroup FMC_LL FMC Low Layer |
| bogdanm | 0:9b334a45a8ff | 81 | * @brief FMC driver modules |
| bogdanm | 0:9b334a45a8ff | 82 | * @{ |
| bogdanm | 0:9b334a45a8ff | 83 | */ |
| bogdanm | 0:9b334a45a8ff | 84 | |
| bogdanm | 0:9b334a45a8ff | 85 | /* Private typedef -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 86 | /* Private define ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 87 | /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants |
| bogdanm | 0:9b334a45a8ff | 88 | * @{ |
| bogdanm | 0:9b334a45a8ff | 89 | */ |
| bogdanm | 0:9b334a45a8ff | 90 | |
| bogdanm | 0:9b334a45a8ff | 91 | /* ----------------------- FMC registers bit mask --------------------------- */ |
| bogdanm | 0:9b334a45a8ff | 92 | /* --- BCRx Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 93 | /* BCRx register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 94 | #define BCRx_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ |
| bogdanm | 0:9b334a45a8ff | 95 | FMC_BCRx_MTYP | FMC_BCRx_MWID |\ |
| bogdanm | 0:9b334a45a8ff | 96 | FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ |
| bogdanm | 0:9b334a45a8ff | 97 | FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ |
| bogdanm | 0:9b334a45a8ff | 98 | FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ |
| bogdanm | 0:9b334a45a8ff | 99 | FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ |
| bogdanm | 0:9b334a45a8ff | 100 | FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW)) |
| bogdanm | 0:9b334a45a8ff | 101 | /* --- BTRx Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 102 | /* BTRx register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 103 | #define BTRx_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ |
| bogdanm | 0:9b334a45a8ff | 104 | FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ |
| bogdanm | 0:9b334a45a8ff | 105 | FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ |
| bogdanm | 0:9b334a45a8ff | 106 | FMC_BTRx_ACCMOD)) |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | /* --- BWTRx Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 109 | /* BWTRx register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define BWTRx_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ |
| bogdanm | 0:9b334a45a8ff | 111 | FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD)) |
| bogdanm | 0:9b334a45a8ff | 112 | |
| bogdanm | 0:9b334a45a8ff | 113 | /* --- PCR Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 114 | /* PCR register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN |\ |
| bogdanm | 0:9b334a45a8ff | 116 | FMC_PCR_PTYP | FMC_PCR_PWID |\ |
| bogdanm | 0:9b334a45a8ff | 117 | FMC_PCR_ECCEN | FMC_PCR_TCLR |\ |
| bogdanm | 0:9b334a45a8ff | 118 | FMC_PCR_TAR | FMC_PCR_ECCPS)) |
| bogdanm | 0:9b334a45a8ff | 119 | |
| bogdanm | 0:9b334a45a8ff | 120 | /* --- SR Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 121 | /* SR register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define SR_CLEAR_MASK ((uint32_t)(FMC_SR_FEMPT)) |
| bogdanm | 0:9b334a45a8ff | 123 | |
| bogdanm | 0:9b334a45a8ff | 124 | /* --- PMEM Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 125 | /* PMEM register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ |
| bogdanm | 0:9b334a45a8ff | 127 | FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) |
| bogdanm | 0:9b334a45a8ff | 128 | |
| bogdanm | 0:9b334a45a8ff | 129 | /* --- PATT Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 130 | /* PATT register clear mask */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ |
| bogdanm | 0:9b334a45a8ff | 132 | FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) |
| bogdanm | 0:9b334a45a8ff | 133 | /** |
| bogdanm | 0:9b334a45a8ff | 134 | * @} |
| bogdanm | 0:9b334a45a8ff | 135 | */ |
| bogdanm | 0:9b334a45a8ff | 136 | |
| bogdanm | 0:9b334a45a8ff | 137 | /* Private macro -------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 138 | /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros |
| bogdanm | 0:9b334a45a8ff | 139 | * @{ |
| bogdanm | 0:9b334a45a8ff | 140 | */ |
| bogdanm | 0:9b334a45a8ff | 141 | |
| bogdanm | 0:9b334a45a8ff | 142 | /** |
| bogdanm | 0:9b334a45a8ff | 143 | * @} |
| bogdanm | 0:9b334a45a8ff | 144 | */ |
| bogdanm | 0:9b334a45a8ff | 145 | |
| bogdanm | 0:9b334a45a8ff | 146 | /* Private variables ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 147 | /* Private function prototypes -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 148 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 149 | |
| bogdanm | 0:9b334a45a8ff | 150 | /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
| bogdanm | 0:9b334a45a8ff | 151 | * @{ |
| bogdanm | 0:9b334a45a8ff | 152 | */ |
| bogdanm | 0:9b334a45a8ff | 153 | |
| bogdanm | 0:9b334a45a8ff | 154 | /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions |
| bogdanm | 0:9b334a45a8ff | 155 | * @brief NORSRAM Controller functions |
| bogdanm | 0:9b334a45a8ff | 156 | * |
| bogdanm | 0:9b334a45a8ff | 157 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 158 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 159 | ##### How to use NORSRAM device driver ##### |
| bogdanm | 0:9b334a45a8ff | 160 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 161 | |
| bogdanm | 0:9b334a45a8ff | 162 | [..] |
| bogdanm | 0:9b334a45a8ff | 163 | This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
| bogdanm | 0:9b334a45a8ff | 164 | to run the NORSRAM external devices. |
| bogdanm | 0:9b334a45a8ff | 165 | |
| bogdanm | 0:9b334a45a8ff | 166 | (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
| bogdanm | 0:9b334a45a8ff | 167 | (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
| bogdanm | 0:9b334a45a8ff | 168 | (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
| bogdanm | 0:9b334a45a8ff | 169 | (+) FMC NORSRAM bank extended timing configuration using the function |
| bogdanm | 0:9b334a45a8ff | 170 | FMC_NORSRAM_Extended_Timing_Init() |
| bogdanm | 0:9b334a45a8ff | 171 | (+) FMC NORSRAM bank enable/disable write operation using the functions |
| bogdanm | 0:9b334a45a8ff | 172 | FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
| bogdanm | 0:9b334a45a8ff | 173 | |
| bogdanm | 0:9b334a45a8ff | 174 | |
| bogdanm | 0:9b334a45a8ff | 175 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 176 | * @{ |
| bogdanm | 0:9b334a45a8ff | 177 | */ |
| bogdanm | 0:9b334a45a8ff | 178 | |
| bogdanm | 0:9b334a45a8ff | 179 | /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 180 | * @brief Initialization and Configuration functions |
| bogdanm | 0:9b334a45a8ff | 181 | * |
| bogdanm | 0:9b334a45a8ff | 182 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 183 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 184 | ##### Initialization and de-initialization functions ##### |
| bogdanm | 0:9b334a45a8ff | 185 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 186 | [..] |
| bogdanm | 0:9b334a45a8ff | 187 | This section provides functions allowing to: |
| bogdanm | 0:9b334a45a8ff | 188 | (+) Initialize and configure the FMC NORSRAM interface |
| bogdanm | 0:9b334a45a8ff | 189 | (+) De-initialize the FMC NORSRAM interface |
| bogdanm | 0:9b334a45a8ff | 190 | (+) Configure the FMC clock and associated GPIOs |
| bogdanm | 0:9b334a45a8ff | 191 | |
| bogdanm | 0:9b334a45a8ff | 192 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 193 | * @{ |
| bogdanm | 0:9b334a45a8ff | 194 | */ |
| bogdanm | 0:9b334a45a8ff | 195 | |
| bogdanm | 0:9b334a45a8ff | 196 | /** |
| bogdanm | 0:9b334a45a8ff | 197 | * @brief Initialize the FMC_NORSRAM device according to the specified |
| bogdanm | 0:9b334a45a8ff | 198 | * control parameters in the FMC_NORSRAM_InitTypeDef |
| bogdanm | 0:9b334a45a8ff | 199 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 200 | * @param Init: Pointer to NORSRAM Initialization structure |
| bogdanm | 0:9b334a45a8ff | 201 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 202 | */ |
| bogdanm | 0:9b334a45a8ff | 203 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
| bogdanm | 0:9b334a45a8ff | 204 | { |
| bogdanm | 0:9b334a45a8ff | 205 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 206 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 207 | assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
| bogdanm | 0:9b334a45a8ff | 208 | assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
| bogdanm | 0:9b334a45a8ff | 209 | assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
| bogdanm | 0:9b334a45a8ff | 210 | assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| bogdanm | 0:9b334a45a8ff | 211 | assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
| bogdanm | 0:9b334a45a8ff | 212 | assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
| bogdanm | 0:9b334a45a8ff | 213 | assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
| bogdanm | 0:9b334a45a8ff | 214 | assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
| bogdanm | 0:9b334a45a8ff | 215 | assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
| bogdanm | 0:9b334a45a8ff | 216 | assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
| bogdanm | 0:9b334a45a8ff | 217 | assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
| bogdanm | 0:9b334a45a8ff | 218 | assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
| bogdanm | 0:9b334a45a8ff | 219 | assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
| bogdanm | 0:9b334a45a8ff | 220 | assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
| bogdanm | 0:9b334a45a8ff | 221 | assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
| bogdanm | 0:9b334a45a8ff | 222 | |
| bogdanm | 0:9b334a45a8ff | 223 | /* Set NORSRAM device control parameters */ |
| bogdanm | 0:9b334a45a8ff | 224 | if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
| bogdanm | 0:9b334a45a8ff | 225 | { |
| bogdanm | 0:9b334a45a8ff | 226 | MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE |\ |
| bogdanm | 0:9b334a45a8ff | 227 | Init->DataAddressMux |\ |
| bogdanm | 0:9b334a45a8ff | 228 | Init->MemoryType |\ |
| bogdanm | 0:9b334a45a8ff | 229 | Init->MemoryDataWidth |\ |
| bogdanm | 0:9b334a45a8ff | 230 | Init->BurstAccessMode |\ |
| bogdanm | 0:9b334a45a8ff | 231 | Init->WaitSignalPolarity |\ |
| bogdanm | 0:9b334a45a8ff | 232 | Init->WaitSignalActive |\ |
| bogdanm | 0:9b334a45a8ff | 233 | Init->WriteOperation |\ |
| bogdanm | 0:9b334a45a8ff | 234 | Init->WaitSignal |\ |
| bogdanm | 0:9b334a45a8ff | 235 | Init->ExtendedMode |\ |
| bogdanm | 0:9b334a45a8ff | 236 | Init->AsynchronousWait |\ |
| bogdanm | 0:9b334a45a8ff | 237 | Init->WriteBurst |\ |
| bogdanm | 0:9b334a45a8ff | 238 | Init->ContinuousClock |\ |
| bogdanm | 0:9b334a45a8ff | 239 | Init->WriteFifo |\ |
| bogdanm | 0:9b334a45a8ff | 240 | Init->PageSize) |
| bogdanm | 0:9b334a45a8ff | 241 | ); |
| bogdanm | 0:9b334a45a8ff | 242 | } |
| bogdanm | 0:9b334a45a8ff | 243 | else |
| bogdanm | 0:9b334a45a8ff | 244 | { |
| bogdanm | 0:9b334a45a8ff | 245 | MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE |\ |
| bogdanm | 0:9b334a45a8ff | 246 | Init->DataAddressMux |\ |
| bogdanm | 0:9b334a45a8ff | 247 | Init->MemoryType |\ |
| bogdanm | 0:9b334a45a8ff | 248 | Init->MemoryDataWidth |\ |
| bogdanm | 0:9b334a45a8ff | 249 | Init->BurstAccessMode |\ |
| bogdanm | 0:9b334a45a8ff | 250 | Init->WaitSignalPolarity |\ |
| bogdanm | 0:9b334a45a8ff | 251 | Init->WaitSignalActive |\ |
| bogdanm | 0:9b334a45a8ff | 252 | Init->WriteOperation |\ |
| bogdanm | 0:9b334a45a8ff | 253 | Init->WaitSignal |\ |
| bogdanm | 0:9b334a45a8ff | 254 | Init->ExtendedMode |\ |
| bogdanm | 0:9b334a45a8ff | 255 | Init->AsynchronousWait |\ |
| bogdanm | 0:9b334a45a8ff | 256 | Init->WriteBurst |\ |
| bogdanm | 0:9b334a45a8ff | 257 | Init->ContinuousClock |\ |
| bogdanm | 0:9b334a45a8ff | 258 | Init->WriteFifo |\ |
| bogdanm | 0:9b334a45a8ff | 259 | Init->PageSize) |
| bogdanm | 0:9b334a45a8ff | 260 | ); |
| bogdanm | 0:9b334a45a8ff | 261 | } |
| bogdanm | 0:9b334a45a8ff | 262 | |
| bogdanm | 0:9b334a45a8ff | 263 | /* Specific bits on bank1 register for bank2..4 */ |
| bogdanm | 0:9b334a45a8ff | 264 | if(Init->NSBank != FMC_NORSRAM_BANK1) |
| bogdanm | 0:9b334a45a8ff | 265 | { |
| bogdanm | 0:9b334a45a8ff | 266 | /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ |
| bogdanm | 0:9b334a45a8ff | 267 | SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); |
| bogdanm | 0:9b334a45a8ff | 268 | |
| bogdanm | 0:9b334a45a8ff | 269 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
| bogdanm | 0:9b334a45a8ff | 270 | if(Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) |
| bogdanm | 0:9b334a45a8ff | 271 | { |
| bogdanm | 0:9b334a45a8ff | 272 | Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; |
| bogdanm | 0:9b334a45a8ff | 273 | MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCRx_BURSTEN | FMC_BCR1_CCLKEN, (uint32_t)(Init->BurstAccessMode |\ |
| bogdanm | 0:9b334a45a8ff | 274 | Init->ContinuousClock)); |
| bogdanm | 0:9b334a45a8ff | 275 | } |
| bogdanm | 0:9b334a45a8ff | 276 | } |
| bogdanm | 0:9b334a45a8ff | 277 | |
| bogdanm | 0:9b334a45a8ff | 278 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 279 | } |
| bogdanm | 0:9b334a45a8ff | 280 | |
| bogdanm | 0:9b334a45a8ff | 281 | |
| bogdanm | 0:9b334a45a8ff | 282 | /** |
| bogdanm | 0:9b334a45a8ff | 283 | * @brief DeInitialize the FMC_NORSRAM peripheral |
| bogdanm | 0:9b334a45a8ff | 284 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 285 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
| bogdanm | 0:9b334a45a8ff | 286 | * @param Bank: NORSRAM bank number |
| bogdanm | 0:9b334a45a8ff | 287 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 288 | */ |
| bogdanm | 0:9b334a45a8ff | 289 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 290 | { |
| bogdanm | 0:9b334a45a8ff | 291 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 292 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 293 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
| bogdanm | 0:9b334a45a8ff | 294 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | /* Disable the FMC_NORSRAM device */ |
| bogdanm | 0:9b334a45a8ff | 297 | __FMC_NORSRAM_DISABLE(Device, Bank); |
| bogdanm | 0:9b334a45a8ff | 298 | |
| bogdanm | 0:9b334a45a8ff | 299 | /* De-initialize the FMC_NORSRAM device */ |
| bogdanm | 0:9b334a45a8ff | 300 | /* FMC_NORSRAM_BANK1 */ |
| bogdanm | 0:9b334a45a8ff | 301 | if(Bank == FMC_NORSRAM_BANK1) |
| bogdanm | 0:9b334a45a8ff | 302 | { |
| bogdanm | 0:9b334a45a8ff | 303 | Device->BTCR[Bank] = 0x000030DB; |
| bogdanm | 0:9b334a45a8ff | 304 | } |
| bogdanm | 0:9b334a45a8ff | 305 | /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
| bogdanm | 0:9b334a45a8ff | 306 | else |
| bogdanm | 0:9b334a45a8ff | 307 | { |
| bogdanm | 0:9b334a45a8ff | 308 | Device->BTCR[Bank] = 0x000030D2; |
| bogdanm | 0:9b334a45a8ff | 309 | } |
| bogdanm | 0:9b334a45a8ff | 310 | |
| bogdanm | 0:9b334a45a8ff | 311 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
| bogdanm | 0:9b334a45a8ff | 312 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 315 | } |
| bogdanm | 0:9b334a45a8ff | 316 | |
| bogdanm | 0:9b334a45a8ff | 317 | |
| bogdanm | 0:9b334a45a8ff | 318 | /** |
| bogdanm | 0:9b334a45a8ff | 319 | * @brief Initialize the FMC_NORSRAM Timing according to the specified |
| bogdanm | 0:9b334a45a8ff | 320 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| bogdanm | 0:9b334a45a8ff | 321 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 322 | * @param Timing: Pointer to NORSRAM Timing structure |
| bogdanm | 0:9b334a45a8ff | 323 | * @param Bank: NORSRAM bank number |
| bogdanm | 0:9b334a45a8ff | 324 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 325 | */ |
| bogdanm | 0:9b334a45a8ff | 326 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 327 | { |
| bogdanm | 0:9b334a45a8ff | 328 | uint32_t tmpr = 0; |
| bogdanm | 0:9b334a45a8ff | 329 | |
| bogdanm | 0:9b334a45a8ff | 330 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 331 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 332 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 333 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| bogdanm | 0:9b334a45a8ff | 334 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 335 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| bogdanm | 0:9b334a45a8ff | 336 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| bogdanm | 0:9b334a45a8ff | 337 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| bogdanm | 0:9b334a45a8ff | 338 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| bogdanm | 0:9b334a45a8ff | 339 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 340 | |
| bogdanm | 0:9b334a45a8ff | 341 | /* Set FMC_NORSRAM device timing parameters */ |
| bogdanm | 0:9b334a45a8ff | 342 | MODIFY_REG(Device->BTCR[Bank + 1], \ |
| bogdanm | 0:9b334a45a8ff | 343 | BTRx_CLEAR_MASK, \ |
| bogdanm | 0:9b334a45a8ff | 344 | (uint32_t)(Timing->AddressSetupTime |\ |
| bogdanm | 0:9b334a45a8ff | 345 | ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ |
| bogdanm | 0:9b334a45a8ff | 346 | ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\ |
| bogdanm | 0:9b334a45a8ff | 347 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) |\ |
| bogdanm | 0:9b334a45a8ff | 348 | (((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)) |\ |
| bogdanm | 0:9b334a45a8ff | 349 | (((Timing->DataLatency)-2) << POSITION_VAL(FMC_BTRx_DATLAT)) |\ |
| bogdanm | 0:9b334a45a8ff | 350 | (Timing->AccessMode))); |
| bogdanm | 0:9b334a45a8ff | 351 | |
| bogdanm | 0:9b334a45a8ff | 352 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
| bogdanm | 0:9b334a45a8ff | 353 | if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
| bogdanm | 0:9b334a45a8ff | 354 | { |
| bogdanm | 0:9b334a45a8ff | 355 | tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV))); |
| bogdanm | 0:9b334a45a8ff | 356 | tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)); |
| bogdanm | 0:9b334a45a8ff | 357 | MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); |
| bogdanm | 0:9b334a45a8ff | 358 | } |
| bogdanm | 0:9b334a45a8ff | 359 | |
| bogdanm | 0:9b334a45a8ff | 360 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 361 | } |
| bogdanm | 0:9b334a45a8ff | 362 | |
| bogdanm | 0:9b334a45a8ff | 363 | /** |
| bogdanm | 0:9b334a45a8ff | 364 | * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
| bogdanm | 0:9b334a45a8ff | 365 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| bogdanm | 0:9b334a45a8ff | 366 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 367 | * @param Timing: Pointer to NORSRAM Timing structure |
| bogdanm | 0:9b334a45a8ff | 368 | * @param Bank: NORSRAM bank number |
| bogdanm | 0:9b334a45a8ff | 369 | * @param ExtendedMode: FMC Extended Mode |
| bogdanm | 0:9b334a45a8ff | 370 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 371 | * @arg FMC_EXTENDED_MODE_DISABLE |
| bogdanm | 0:9b334a45a8ff | 372 | * @arg FMC_EXTENDED_MODE_ENABLE |
| bogdanm | 0:9b334a45a8ff | 373 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 374 | */ |
| bogdanm | 0:9b334a45a8ff | 375 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
| bogdanm | 0:9b334a45a8ff | 376 | { |
| bogdanm | 0:9b334a45a8ff | 377 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 378 | assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| bogdanm | 0:9b334a45a8ff | 381 | if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
| bogdanm | 0:9b334a45a8ff | 382 | { |
| bogdanm | 0:9b334a45a8ff | 383 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 384 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 385 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 386 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| bogdanm | 0:9b334a45a8ff | 387 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 388 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| bogdanm | 0:9b334a45a8ff | 389 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 390 | |
| bogdanm | 0:9b334a45a8ff | 391 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| bogdanm | 0:9b334a45a8ff | 392 | MODIFY_REG(Device->BWTR[Bank], \ |
| bogdanm | 0:9b334a45a8ff | 393 | BWTRx_CLEAR_MASK, \ |
| bogdanm | 0:9b334a45a8ff | 394 | (uint32_t)(Timing->AddressSetupTime |\ |
| bogdanm | 0:9b334a45a8ff | 395 | ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ |
| bogdanm | 0:9b334a45a8ff | 396 | ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\ |
| bogdanm | 0:9b334a45a8ff | 397 | (Timing->AccessMode))); |
| bogdanm | 0:9b334a45a8ff | 398 | } |
| bogdanm | 0:9b334a45a8ff | 399 | else |
| bogdanm | 0:9b334a45a8ff | 400 | { |
| bogdanm | 0:9b334a45a8ff | 401 | Device->BWTR[Bank] = 0x0FFFFFFF; |
| bogdanm | 0:9b334a45a8ff | 402 | } |
| bogdanm | 0:9b334a45a8ff | 403 | |
| bogdanm | 0:9b334a45a8ff | 404 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 405 | } |
| bogdanm | 0:9b334a45a8ff | 406 | |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | /** |
| bogdanm | 0:9b334a45a8ff | 409 | * @} |
| bogdanm | 0:9b334a45a8ff | 410 | */ |
| bogdanm | 0:9b334a45a8ff | 411 | |
| bogdanm | 0:9b334a45a8ff | 412 | |
| bogdanm | 0:9b334a45a8ff | 413 | /** @defgroup FMC_NORSRAM_Exported_Functions_Group2 Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 414 | * @brief management functions |
| bogdanm | 0:9b334a45a8ff | 415 | * |
| bogdanm | 0:9b334a45a8ff | 416 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 417 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 418 | ##### FMC_NORSRAM Control functions ##### |
| bogdanm | 0:9b334a45a8ff | 419 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 420 | [..] |
| bogdanm | 0:9b334a45a8ff | 421 | This subsection provides a set of functions allowing to control dynamically |
| bogdanm | 0:9b334a45a8ff | 422 | the FMC NORSRAM interface. |
| bogdanm | 0:9b334a45a8ff | 423 | |
| bogdanm | 0:9b334a45a8ff | 424 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 425 | * @{ |
| bogdanm | 0:9b334a45a8ff | 426 | */ |
| bogdanm | 0:9b334a45a8ff | 427 | |
| bogdanm | 0:9b334a45a8ff | 428 | /** |
| bogdanm | 0:9b334a45a8ff | 429 | * @brief Enables dynamically FMC_NORSRAM write operation. |
| bogdanm | 0:9b334a45a8ff | 430 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 431 | * @param Bank: NORSRAM bank number |
| bogdanm | 0:9b334a45a8ff | 432 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 433 | */ |
| bogdanm | 0:9b334a45a8ff | 434 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 435 | { |
| bogdanm | 0:9b334a45a8ff | 436 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 437 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 438 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 439 | |
| bogdanm | 0:9b334a45a8ff | 440 | /* Enable write operation */ |
| bogdanm | 0:9b334a45a8ff | 441 | SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
| bogdanm | 0:9b334a45a8ff | 442 | |
| bogdanm | 0:9b334a45a8ff | 443 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 444 | } |
| bogdanm | 0:9b334a45a8ff | 445 | |
| bogdanm | 0:9b334a45a8ff | 446 | /** |
| bogdanm | 0:9b334a45a8ff | 447 | * @brief Disables dynamically FMC_NORSRAM write operation. |
| bogdanm | 0:9b334a45a8ff | 448 | * @param Device: Pointer to NORSRAM device instance |
| bogdanm | 0:9b334a45a8ff | 449 | * @param Bank: NORSRAM bank number |
| bogdanm | 0:9b334a45a8ff | 450 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 451 | */ |
| bogdanm | 0:9b334a45a8ff | 452 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 453 | { |
| bogdanm | 0:9b334a45a8ff | 454 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 455 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 456 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 457 | |
| bogdanm | 0:9b334a45a8ff | 458 | /* Disable write operation */ |
| bogdanm | 0:9b334a45a8ff | 459 | CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
| bogdanm | 0:9b334a45a8ff | 460 | |
| bogdanm | 0:9b334a45a8ff | 461 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 462 | } |
| bogdanm | 0:9b334a45a8ff | 463 | |
| bogdanm | 0:9b334a45a8ff | 464 | /** |
| bogdanm | 0:9b334a45a8ff | 465 | * @} |
| bogdanm | 0:9b334a45a8ff | 466 | */ |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | /** |
| bogdanm | 0:9b334a45a8ff | 469 | * @} |
| bogdanm | 0:9b334a45a8ff | 470 | */ |
| bogdanm | 0:9b334a45a8ff | 471 | |
| bogdanm | 0:9b334a45a8ff | 472 | /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions |
| bogdanm | 0:9b334a45a8ff | 473 | * @brief NAND Controller functions |
| bogdanm | 0:9b334a45a8ff | 474 | * |
| bogdanm | 0:9b334a45a8ff | 475 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 476 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 477 | ##### How to use NAND device driver ##### |
| bogdanm | 0:9b334a45a8ff | 478 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 479 | [..] |
| bogdanm | 0:9b334a45a8ff | 480 | This driver contains a set of APIs to interface with the FMC NAND banks in order |
| bogdanm | 0:9b334a45a8ff | 481 | to run the NAND external devices. |
| bogdanm | 0:9b334a45a8ff | 482 | |
| bogdanm | 0:9b334a45a8ff | 483 | (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
| bogdanm | 0:9b334a45a8ff | 484 | (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
| bogdanm | 0:9b334a45a8ff | 485 | (+) FMC NAND bank common space timing configuration using the function |
| bogdanm | 0:9b334a45a8ff | 486 | FMC_NAND_CommonSpace_Timing_Init() |
| bogdanm | 0:9b334a45a8ff | 487 | (+) FMC NAND bank attribute space timing configuration using the function |
| bogdanm | 0:9b334a45a8ff | 488 | FMC_NAND_AttributeSpace_Timing_Init() |
| bogdanm | 0:9b334a45a8ff | 489 | (+) FMC NAND bank enable/disable ECC correction feature using the functions |
| bogdanm | 0:9b334a45a8ff | 490 | FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
| bogdanm | 0:9b334a45a8ff | 491 | (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
| bogdanm | 0:9b334a45a8ff | 492 | |
| bogdanm | 0:9b334a45a8ff | 493 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 494 | * @{ |
| bogdanm | 0:9b334a45a8ff | 495 | */ |
| bogdanm | 0:9b334a45a8ff | 496 | |
| bogdanm | 0:9b334a45a8ff | 497 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 498 | * @brief Initialization and Configuration functions |
| bogdanm | 0:9b334a45a8ff | 499 | * |
| bogdanm | 0:9b334a45a8ff | 500 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 501 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 502 | ##### Initialization and de-initialization functions ##### |
| bogdanm | 0:9b334a45a8ff | 503 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 504 | [..] |
| bogdanm | 0:9b334a45a8ff | 505 | This section provides functions allowing to: |
| bogdanm | 0:9b334a45a8ff | 506 | (+) Initialize and configure the FMC NAND interface |
| bogdanm | 0:9b334a45a8ff | 507 | (+) De-initialize the FMC NAND interface |
| bogdanm | 0:9b334a45a8ff | 508 | (+) Configure the FMC clock and associated GPIOs |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 511 | * @{ |
| bogdanm | 0:9b334a45a8ff | 512 | */ |
| bogdanm | 0:9b334a45a8ff | 513 | |
| bogdanm | 0:9b334a45a8ff | 514 | /** |
| bogdanm | 0:9b334a45a8ff | 515 | * @brief Initializes the FMC_NAND device according to the specified |
| bogdanm | 0:9b334a45a8ff | 516 | * control parameters in the FMC_NAND_HandleTypeDef |
| bogdanm | 0:9b334a45a8ff | 517 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 518 | * @param Init: Pointer to NAND Initialization structure |
| bogdanm | 0:9b334a45a8ff | 519 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 520 | */ |
| bogdanm | 0:9b334a45a8ff | 521 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
| bogdanm | 0:9b334a45a8ff | 522 | { |
| bogdanm | 0:9b334a45a8ff | 523 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 524 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 525 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
| bogdanm | 0:9b334a45a8ff | 526 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| bogdanm | 0:9b334a45a8ff | 527 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| bogdanm | 0:9b334a45a8ff | 528 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
| bogdanm | 0:9b334a45a8ff | 529 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| bogdanm | 0:9b334a45a8ff | 530 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 531 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 532 | |
| bogdanm | 0:9b334a45a8ff | 533 | /* Set NAND device control parameters */ |
| bogdanm | 0:9b334a45a8ff | 534 | /* NAND bank 3 registers configuration */ |
| bogdanm | 0:9b334a45a8ff | 535 | MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |\ |
| bogdanm | 0:9b334a45a8ff | 536 | FMC_PCR_MEMORY_TYPE_NAND |\ |
| bogdanm | 0:9b334a45a8ff | 537 | Init->MemoryDataWidth |\ |
| bogdanm | 0:9b334a45a8ff | 538 | Init->EccComputation |\ |
| bogdanm | 0:9b334a45a8ff | 539 | Init->ECCPageSize |\ |
| bogdanm | 0:9b334a45a8ff | 540 | ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) |\ |
| bogdanm | 0:9b334a45a8ff | 541 | ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR)))); |
| bogdanm | 0:9b334a45a8ff | 542 | |
| bogdanm | 0:9b334a45a8ff | 543 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 544 | |
| bogdanm | 0:9b334a45a8ff | 545 | } |
| bogdanm | 0:9b334a45a8ff | 546 | |
| bogdanm | 0:9b334a45a8ff | 547 | /** |
| bogdanm | 0:9b334a45a8ff | 548 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
| bogdanm | 0:9b334a45a8ff | 549 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| bogdanm | 0:9b334a45a8ff | 550 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 551 | * @param Timing: Pointer to NAND timing structure |
| bogdanm | 0:9b334a45a8ff | 552 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 553 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 554 | */ |
| bogdanm | 0:9b334a45a8ff | 555 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 556 | { |
| bogdanm | 0:9b334a45a8ff | 557 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 558 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 559 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| bogdanm | 0:9b334a45a8ff | 560 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 561 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 562 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 563 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 564 | |
| bogdanm | 0:9b334a45a8ff | 565 | /* Set FMC_NAND device timing parameters */ |
| bogdanm | 0:9b334a45a8ff | 566 | /* NAND bank 3 registers configuration */ |
| bogdanm | 0:9b334a45a8ff | 567 | MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |\ |
| bogdanm | 0:9b334a45a8ff | 568 | ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ |
| bogdanm | 0:9b334a45a8ff | 569 | ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ |
| bogdanm | 0:9b334a45a8ff | 570 | ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 573 | } |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | /** |
| bogdanm | 0:9b334a45a8ff | 576 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
| bogdanm | 0:9b334a45a8ff | 577 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| bogdanm | 0:9b334a45a8ff | 578 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 579 | * @param Timing: Pointer to NAND timing structure |
| bogdanm | 0:9b334a45a8ff | 580 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 581 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 582 | */ |
| bogdanm | 0:9b334a45a8ff | 583 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 584 | { |
| bogdanm | 0:9b334a45a8ff | 585 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 586 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 587 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| bogdanm | 0:9b334a45a8ff | 588 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 589 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 590 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| bogdanm | 0:9b334a45a8ff | 591 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 592 | |
| bogdanm | 0:9b334a45a8ff | 593 | /* Set FMC_NAND device timing parameters */ |
| bogdanm | 0:9b334a45a8ff | 594 | /* NAND bank 3 registers configuration */ |
| bogdanm | 0:9b334a45a8ff | 595 | MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |\ |
| bogdanm | 0:9b334a45a8ff | 596 | ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ |
| bogdanm | 0:9b334a45a8ff | 597 | ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ |
| bogdanm | 0:9b334a45a8ff | 598 | ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); |
| bogdanm | 0:9b334a45a8ff | 599 | |
| bogdanm | 0:9b334a45a8ff | 600 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 601 | } |
| bogdanm | 0:9b334a45a8ff | 602 | |
| bogdanm | 0:9b334a45a8ff | 603 | |
| bogdanm | 0:9b334a45a8ff | 604 | /** |
| bogdanm | 0:9b334a45a8ff | 605 | * @brief DeInitialize the FMC_NAND device |
| bogdanm | 0:9b334a45a8ff | 606 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 607 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 608 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 609 | */ |
| bogdanm | 0:9b334a45a8ff | 610 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 611 | { |
| bogdanm | 0:9b334a45a8ff | 612 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 613 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 614 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 615 | |
| bogdanm | 0:9b334a45a8ff | 616 | /* Disable the NAND Bank */ |
| bogdanm | 0:9b334a45a8ff | 617 | __FMC_NAND_DISABLE(Device, Bank); |
| bogdanm | 0:9b334a45a8ff | 618 | |
| bogdanm | 0:9b334a45a8ff | 619 | /* Set the FMC_NAND_BANK registers to their reset values */ |
| bogdanm | 0:9b334a45a8ff | 620 | WRITE_REG(Device->PCR, 0x00000018); |
| bogdanm | 0:9b334a45a8ff | 621 | WRITE_REG(Device->SR, 0x00000040); |
| bogdanm | 0:9b334a45a8ff | 622 | WRITE_REG(Device->PMEM, 0xFCFCFCFC); |
| bogdanm | 0:9b334a45a8ff | 623 | WRITE_REG(Device->PATT, 0xFCFCFCFC); |
| bogdanm | 0:9b334a45a8ff | 624 | |
| bogdanm | 0:9b334a45a8ff | 625 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 626 | } |
| bogdanm | 0:9b334a45a8ff | 627 | |
| bogdanm | 0:9b334a45a8ff | 628 | /** |
| bogdanm | 0:9b334a45a8ff | 629 | * @} |
| bogdanm | 0:9b334a45a8ff | 630 | */ |
| bogdanm | 0:9b334a45a8ff | 631 | |
| bogdanm | 0:9b334a45a8ff | 632 | |
| bogdanm | 0:9b334a45a8ff | 633 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 634 | * @brief management functions |
| bogdanm | 0:9b334a45a8ff | 635 | * |
| bogdanm | 0:9b334a45a8ff | 636 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 637 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 638 | ##### FMC_NAND Control functions ##### |
| bogdanm | 0:9b334a45a8ff | 639 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 640 | [..] |
| bogdanm | 0:9b334a45a8ff | 641 | This subsection provides a set of functions allowing to control dynamically |
| bogdanm | 0:9b334a45a8ff | 642 | the FMC NAND interface. |
| bogdanm | 0:9b334a45a8ff | 643 | |
| bogdanm | 0:9b334a45a8ff | 644 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 645 | * @{ |
| bogdanm | 0:9b334a45a8ff | 646 | */ |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | |
| bogdanm | 0:9b334a45a8ff | 649 | /** |
| bogdanm | 0:9b334a45a8ff | 650 | * @brief Enables dynamically FMC_NAND ECC feature. |
| bogdanm | 0:9b334a45a8ff | 651 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 652 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 653 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 654 | */ |
| bogdanm | 0:9b334a45a8ff | 655 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 656 | { |
| bogdanm | 0:9b334a45a8ff | 657 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 658 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 659 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 660 | |
| bogdanm | 0:9b334a45a8ff | 661 | /* Enable ECC feature */ |
| bogdanm | 0:9b334a45a8ff | 662 | SET_BIT(Device->PCR, FMC_PCR_ECCEN); |
| bogdanm | 0:9b334a45a8ff | 663 | |
| bogdanm | 0:9b334a45a8ff | 664 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 665 | } |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | |
| bogdanm | 0:9b334a45a8ff | 668 | /** |
| bogdanm | 0:9b334a45a8ff | 669 | * @brief Disables dynamically FMC_NAND ECC feature. |
| bogdanm | 0:9b334a45a8ff | 670 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 671 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 672 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 673 | */ |
| bogdanm | 0:9b334a45a8ff | 674 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| bogdanm | 0:9b334a45a8ff | 675 | { |
| bogdanm | 0:9b334a45a8ff | 676 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 677 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 678 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 679 | |
| bogdanm | 0:9b334a45a8ff | 680 | /* Disable ECC feature */ |
| bogdanm | 0:9b334a45a8ff | 681 | CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); |
| bogdanm | 0:9b334a45a8ff | 682 | |
| bogdanm | 0:9b334a45a8ff | 683 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 684 | } |
| bogdanm | 0:9b334a45a8ff | 685 | |
| bogdanm | 0:9b334a45a8ff | 686 | /** |
| bogdanm | 0:9b334a45a8ff | 687 | * @brief Disables dynamically FMC_NAND ECC feature. |
| bogdanm | 0:9b334a45a8ff | 688 | * @param Device: Pointer to NAND device instance |
| bogdanm | 0:9b334a45a8ff | 689 | * @param ECCval: Pointer to ECC value |
| bogdanm | 0:9b334a45a8ff | 690 | * @param Bank: NAND bank number |
| bogdanm | 0:9b334a45a8ff | 691 | * @param Timeout: Timeout wait value |
| bogdanm | 0:9b334a45a8ff | 692 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 693 | */ |
| bogdanm | 0:9b334a45a8ff | 694 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| bogdanm | 0:9b334a45a8ff | 695 | { |
| bogdanm | 0:9b334a45a8ff | 696 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 697 | |
| bogdanm | 0:9b334a45a8ff | 698 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 699 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| bogdanm | 0:9b334a45a8ff | 700 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| bogdanm | 0:9b334a45a8ff | 701 | |
| bogdanm | 0:9b334a45a8ff | 702 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 703 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 704 | |
| bogdanm | 0:9b334a45a8ff | 705 | /* Wait until FIFO is empty */ |
| bogdanm | 0:9b334a45a8ff | 706 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
| bogdanm | 0:9b334a45a8ff | 707 | { |
| bogdanm | 0:9b334a45a8ff | 708 | /* Check for the Timeout */ |
| bogdanm | 0:9b334a45a8ff | 709 | if(Timeout != HAL_MAX_DELAY) |
| bogdanm | 0:9b334a45a8ff | 710 | { |
| bogdanm | 0:9b334a45a8ff | 711 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| bogdanm | 0:9b334a45a8ff | 712 | { |
| bogdanm | 0:9b334a45a8ff | 713 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 714 | } |
| bogdanm | 0:9b334a45a8ff | 715 | } |
| bogdanm | 0:9b334a45a8ff | 716 | } |
| bogdanm | 0:9b334a45a8ff | 717 | |
| bogdanm | 0:9b334a45a8ff | 718 | /* Get the ECCR register value */ |
| bogdanm | 0:9b334a45a8ff | 719 | *ECCval = (uint32_t)Device->ECCR; |
| bogdanm | 0:9b334a45a8ff | 720 | |
| bogdanm | 0:9b334a45a8ff | 721 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 722 | } |
| bogdanm | 0:9b334a45a8ff | 723 | |
| bogdanm | 0:9b334a45a8ff | 724 | /** |
| bogdanm | 0:9b334a45a8ff | 725 | * @} |
| bogdanm | 0:9b334a45a8ff | 726 | */ |
| bogdanm | 0:9b334a45a8ff | 727 | |
| bogdanm | 0:9b334a45a8ff | 728 | /** |
| bogdanm | 0:9b334a45a8ff | 729 | * @} |
| bogdanm | 0:9b334a45a8ff | 730 | */ |
| bogdanm | 0:9b334a45a8ff | 731 | |
| bogdanm | 0:9b334a45a8ff | 732 | /** |
| bogdanm | 0:9b334a45a8ff | 733 | * @} |
| bogdanm | 0:9b334a45a8ff | 734 | */ |
| bogdanm | 0:9b334a45a8ff | 735 | |
| bogdanm | 0:9b334a45a8ff | 736 | /** |
| bogdanm | 0:9b334a45a8ff | 737 | * @} |
| bogdanm | 0:9b334a45a8ff | 738 | */ |
| bogdanm | 0:9b334a45a8ff | 739 | |
| bogdanm | 0:9b334a45a8ff | 740 | /** |
| bogdanm | 0:9b334a45a8ff | 741 | * @} |
| bogdanm | 0:9b334a45a8ff | 742 | */ |
| bogdanm | 0:9b334a45a8ff | 743 | |
| bogdanm | 0:9b334a45a8ff | 744 | #endif /* HAL_FMC_MODULE_ENABLED */ |
| bogdanm | 0:9b334a45a8ff | 745 | |
| bogdanm | 0:9b334a45a8ff | 746 | /** |
| bogdanm | 0:9b334a45a8ff | 747 | * @} |
| bogdanm | 0:9b334a45a8ff | 748 | */ |
| bogdanm | 0:9b334a45a8ff | 749 | |
| bogdanm | 0:9b334a45a8ff | 750 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |