mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L4xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L4xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	71	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	74	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	78	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	0:9b334a45a8ff	81	reaches zero, an update event is generated and counting restarts
bogdanm	0:9b334a45a8ff	82	from the RCR value (N).
bogdanm	0:9b334a45a8ff	83	This means in PWM mode that (N+1) corresponds to:
bogdanm	0:9b334a45a8ff	84	- the number of PWM periods in edge-aligned mode
bogdanm	0:9b334a45a8ff	85	- the number of half PWM period in center-aligned mode
bogdanm	0:9b334a45a8ff	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	0:9b334a45a8ff	87	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	88	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/**
bogdanm	0:9b334a45a8ff	91	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	92	*/
bogdanm	0:9b334a45a8ff	93	typedef struct
bogdanm	0:9b334a45a8ff	94	{
bogdanm	0:9b334a45a8ff	95	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	106	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	115	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	119	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	120	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	/**
bogdanm	0:9b334a45a8ff	123	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125	typedef struct
bogdanm	0:9b334a45a8ff	126	{
bogdanm	0:9b334a45a8ff	127	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	138	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	142	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	146	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	153
bogdanm	0:9b334a45a8ff	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	156	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/**
bogdanm	0:9b334a45a8ff	160	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	161	*/
bogdanm	0:9b334a45a8ff	162	typedef struct
bogdanm	0:9b334a45a8ff	163	{
bogdanm	0:9b334a45a8ff	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	175	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/**
bogdanm	0:9b334a45a8ff	178	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180	typedef struct
bogdanm	0:9b334a45a8ff	181	{
bogdanm	0:9b334a45a8ff	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	208	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/**
bogdanm	0:9b334a45a8ff	212	* @brief Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	213	*/
bogdanm	0:9b334a45a8ff	214	typedef struct
bogdanm	0:9b334a45a8ff	215	{
bogdanm	0:9b334a45a8ff	216	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	0:9b334a45a8ff	217	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	218	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	0:9b334a45a8ff	219	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	0:9b334a45a8ff	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	222	uint32_t ClockFilter; /*!< TIM clock filter
bogdanm	0:9b334a45a8ff	223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	224	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/**
bogdanm	0:9b334a45a8ff	227	* @brief Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	228	*/
bogdanm	0:9b334a45a8ff	229	typedef struct
bogdanm	0:9b334a45a8ff	230	{
bogdanm	0:9b334a45a8ff	231	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	0:9b334a45a8ff	232	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	0:9b334a45a8ff	234	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	0:9b334a45a8ff	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	0:9b334a45a8ff	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	0:9b334a45a8ff	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm	0:9b334a45a8ff	240	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	241	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @brief TIM Master configuration Structure definition
bogdanm	0:9b334a45a8ff	245	* @note Advanced timers provide TRGO2 internal line which is redirected
bogdanm	0:9b334a45a8ff	246	* to the ADC
bogdanm	0:9b334a45a8ff	247	*/
bogdanm	0:9b334a45a8ff	248	typedef struct {
bogdanm	0:9b334a45a8ff	249	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm	0:9b334a45a8ff	250	This parameter can be a value of @ref TIM_Master_Mode_Selection */
bogdanm	0:9b334a45a8ff	251	uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
bogdanm	0:9b334a45a8ff	252	This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
bogdanm	0:9b334a45a8ff	253	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm	0:9b334a45a8ff	255	}TIM_MasterConfigTypeDef;
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	/**
bogdanm	0:9b334a45a8ff	258	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	259	*/
bogdanm	0:9b334a45a8ff	260	typedef struct {
bogdanm	0:9b334a45a8ff	261	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	0:9b334a45a8ff	262	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	0:9b334a45a8ff	263	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	0:9b334a45a8ff	264	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	265	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	0:9b334a45a8ff	266	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	267	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	0:9b334a45a8ff	268	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	269	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	0:9b334a45a8ff	270	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/**
bogdanm	0:9b334a45a8ff	275	* @brief TIM Break input(s) and Dead time configuration Structure definition
bogdanm	0:9b334a45a8ff	276	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
bogdanm	0:9b334a45a8ff	277	* filter and polarity.
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	typedef struct
bogdanm	0:9b334a45a8ff	280	{
bogdanm	0:9b334a45a8ff	281	uint32_t OffStateRunMode; /*!< TIM off state in run mode
bogdanm	0:9b334a45a8ff	282	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm	0:9b334a45a8ff	283	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
bogdanm	0:9b334a45a8ff	284	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm	0:9b334a45a8ff	285	uint32_t LockLevel; /*!< TIM Lock level
bogdanm	0:9b334a45a8ff	286	This parameter can be a value of @ref TIM_Lock_level */
bogdanm	0:9b334a45a8ff	287	uint32_t DeadTime; /*!< TIM dead Time
bogdanm	0:9b334a45a8ff	288	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	289	uint32_t BreakState; /*!< TIM Break State
bogdanm	0:9b334a45a8ff	290	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm	0:9b334a45a8ff	291	uint32_t BreakPolarity; /*!< TIM Break input polarity
bogdanm	0:9b334a45a8ff	292	This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm	0:9b334a45a8ff	293	uint32_t BreakFilter; /*!< Specifies the break input filter.
bogdanm	0:9b334a45a8ff	294	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	295	uint32_t Break2State; /*!< TIM Break2 State
bogdanm	0:9b334a45a8ff	296	This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
bogdanm	0:9b334a45a8ff	297	uint32_t Break2Polarity; /*!< TIM Break2 input polarity
bogdanm	0:9b334a45a8ff	298	This parameter can be a value of @ref TIM_Break2_Polarity */
bogdanm	0:9b334a45a8ff	299	uint32_t Break2Filter; /*!< TIM break2 input filter.
bogdanm	0:9b334a45a8ff	300	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	301	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
bogdanm	0:9b334a45a8ff	302	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm	0:9b334a45a8ff	303	} TIM_BreakDeadTimeConfigTypeDef;
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/**
bogdanm	0:9b334a45a8ff	306	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	307	*/
bogdanm	0:9b334a45a8ff	308	typedef enum
bogdanm	0:9b334a45a8ff	309	{
bogdanm	0:9b334a45a8ff	310	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	311	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	312	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	313	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	314	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	315	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	/**
bogdanm	0:9b334a45a8ff	318	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	319	*/
bogdanm	0:9b334a45a8ff	320	typedef enum
bogdanm	0:9b334a45a8ff	321	{
bogdanm	0:9b334a45a8ff	322	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	323	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	324	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	325	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	326	HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /!< The active channel is 5 /
bogdanm	0:9b334a45a8ff	327	HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /!< The active channel is 6 /
bogdanm	0:9b334a45a8ff	328	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	329	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334	typedef struct
bogdanm	0:9b334a45a8ff	335	{
bogdanm	0:9b334a45a8ff	336	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	337	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	338	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	339	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	340	This array is accessed by a @ref DMA_Handle_index */
bogdanm	0:9b334a45a8ff	341	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	342	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	343	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @}
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348	/* End of exported types -----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	351	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	352	* @{
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
bogdanm	0:9b334a45a8ff	356	* @{
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	359	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
bogdanm	0:9b334a45a8ff	360	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @}
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
bogdanm	0:9b334a45a8ff	366	* @{
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	#define TIM_DMABASE_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	369	#define TIM_DMABASE_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	370	#define TIM_DMABASE_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	371	#define TIM_DMABASE_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	372	#define TIM_DMABASE_SR (0x00000004)
bogdanm	0:9b334a45a8ff	373	#define TIM_DMABASE_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	374	#define TIM_DMABASE_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	375	#define TIM_DMABASE_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	376	#define TIM_DMABASE_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	377	#define TIM_DMABASE_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	378	#define TIM_DMABASE_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	379	#define TIM_DMABASE_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	380	#define TIM_DMABASE_RCR (0x0000000C)
bogdanm	0:9b334a45a8ff	381	#define TIM_DMABASE_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	382	#define TIM_DMABASE_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	383	#define TIM_DMABASE_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	384	#define TIM_DMABASE_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	385	#define TIM_DMABASE_BDTR (0x00000011)
bogdanm	0:9b334a45a8ff	386	#define TIM_DMABASE_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	387	#define TIM_DMABASE_DMAR (0x00000013)
bogdanm	0:9b334a45a8ff	388	#define TIM_DMABASE_OR1 (0x00000014)
bogdanm	0:9b334a45a8ff	389	#define TIM_DMABASE_CCMR3 (0x00000015)
bogdanm	0:9b334a45a8ff	390	#define TIM_DMABASE_CCR5 (0x00000016)
bogdanm	0:9b334a45a8ff	391	#define TIM_DMABASE_CCR6 (0x00000017)
bogdanm	0:9b334a45a8ff	392	#define TIM_DMABASE_OR2 (0x00000018)
bogdanm	0:9b334a45a8ff	393	#define TIM_DMABASE_OR3 (0x00000019)
bogdanm	0:9b334a45a8ff	394	/**
bogdanm	0:9b334a45a8ff	395	* @}
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/** @defgroup TIM_Event_Source TIM Extended Event Source
bogdanm	0:9b334a45a8ff	399	* @{
bogdanm	0:9b334a45a8ff	400	*/
bogdanm	0:9b334a45a8ff	401	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
bogdanm	0:9b334a45a8ff	402	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
bogdanm	0:9b334a45a8ff	403	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
bogdanm	0:9b334a45a8ff	404	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
bogdanm	0:9b334a45a8ff	405	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
bogdanm	0:9b334a45a8ff	406	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
bogdanm	0:9b334a45a8ff	407	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
bogdanm	0:9b334a45a8ff	408	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
bogdanm	0:9b334a45a8ff	409	#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /!< A break 2 event is generated /
bogdanm	0:9b334a45a8ff	410	/**
bogdanm	0:9b334a45a8ff	411	* @}
bogdanm	0:9b334a45a8ff	412	*/
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
bogdanm	0:9b334a45a8ff	415	* @{
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	418	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	419	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	420	/**
bogdanm	0:9b334a45a8ff	421	* @}
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	0:9b334a45a8ff	425	* @{
bogdanm	0:9b334a45a8ff	426	*/
bogdanm	0:9b334a45a8ff	427	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	428	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	429	/**
bogdanm	0:9b334a45a8ff	430	* @}
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	0:9b334a45a8ff	434	* @{
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	437	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	438	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	439	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	440	/**
bogdanm	0:9b334a45a8ff	441	* @}
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	0:9b334a45a8ff	445	* @{
bogdanm	0:9b334a45a8ff	446	*/
bogdanm	0:9b334a45a8ff	447	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	448	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	449	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	450	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	451	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @}
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	0:9b334a45a8ff	457	* @{
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	460	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	461	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	462	/**
bogdanm	0:9b334a45a8ff	463	* @}
bogdanm	0:9b334a45a8ff	464	*/
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
bogdanm	0:9b334a45a8ff	467	* @{
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	470	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	471	/**
bogdanm	0:9b334a45a8ff	472	* @}
bogdanm	0:9b334a45a8ff	473	*/
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	0:9b334a45a8ff	476	* @{
bogdanm	0:9b334a45a8ff	477	*/
bogdanm	0:9b334a45a8ff	478	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	479	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	480	/**
bogdanm	0:9b334a45a8ff	481	* @}
bogdanm	0:9b334a45a8ff	482	*/
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
bogdanm	0:9b334a45a8ff	485	* @{
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	488	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	489	/**
bogdanm	0:9b334a45a8ff	490	* @}
bogdanm	0:9b334a45a8ff	491	*/
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	0:9b334a45a8ff	494	* @{
bogdanm	0:9b334a45a8ff	495	*/
bogdanm	0:9b334a45a8ff	496	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	497	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	498	/**
bogdanm	0:9b334a45a8ff	499	* @}
bogdanm	0:9b334a45a8ff	500	*/
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	0:9b334a45a8ff	503	* @{
bogdanm	0:9b334a45a8ff	504	*/
bogdanm	0:9b334a45a8ff	505	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	506	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @}
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	0:9b334a45a8ff	512	* @{
bogdanm	0:9b334a45a8ff	513	*/
bogdanm	0:9b334a45a8ff	514	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	0:9b334a45a8ff	515	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	516	/**
bogdanm	0:9b334a45a8ff	517	* @}
bogdanm	0:9b334a45a8ff	518	*/
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	0:9b334a45a8ff	521	* @{
bogdanm	0:9b334a45a8ff	522	*/
bogdanm	0:9b334a45a8ff	523	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	0:9b334a45a8ff	524	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	525	/**
bogdanm	0:9b334a45a8ff	526	* @}
bogdanm	0:9b334a45a8ff	527	*/
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	0:9b334a45a8ff	530	* @{
bogdanm	0:9b334a45a8ff	531	*/
bogdanm	0:9b334a45a8ff	532	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	533	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	534	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	535	/**
bogdanm	0:9b334a45a8ff	536	* @}
bogdanm	0:9b334a45a8ff	537	*/
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	0:9b334a45a8ff	540	* @{
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	543	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	544	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	545	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	546	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	547	/**
bogdanm	0:9b334a45a8ff	548	* @}
bogdanm	0:9b334a45a8ff	549	*/
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	0:9b334a45a8ff	552	* @{
bogdanm	0:9b334a45a8ff	553	*/
bogdanm	0:9b334a45a8ff	554	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	555	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	556	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	557	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	558	/**
bogdanm	0:9b334a45a8ff	559	* @}
bogdanm	0:9b334a45a8ff	560	*/
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	0:9b334a45a8ff	563	* @{
bogdanm	0:9b334a45a8ff	564	*/
bogdanm	0:9b334a45a8ff	565	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	566	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	567	/**
bogdanm	0:9b334a45a8ff	568	* @}
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	0:9b334a45a8ff	572	* @{
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	575	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	576	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @}
bogdanm	0:9b334a45a8ff	579	*/
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
bogdanm	0:9b334a45a8ff	582	* @{
bogdanm	0:9b334a45a8ff	583	*/
bogdanm	0:9b334a45a8ff	584	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	585	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	586	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	587	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	588	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	589	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	0:9b334a45a8ff	590	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	591	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	0:9b334a45a8ff	592	/**
bogdanm	0:9b334a45a8ff	593	* @}
bogdanm	0:9b334a45a8ff	594	*/
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/** @defgroup TIM_Commutation_Source TIM Commutation Source
bogdanm	0:9b334a45a8ff	597	* @{
bogdanm	0:9b334a45a8ff	598	*/
bogdanm	0:9b334a45a8ff	599	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	0:9b334a45a8ff	600	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	601	/**
bogdanm	0:9b334a45a8ff	602	* @}
bogdanm	0:9b334a45a8ff	603	*/
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	0:9b334a45a8ff	606	* @{
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	609	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	610	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	611	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	612	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	613	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	0:9b334a45a8ff	614	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @}
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	0:9b334a45a8ff	620	* @{
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	623	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	624	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	625	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	626	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	627	#define TIM_FLAG_CC5 (TIM_SR_CC5IF)
bogdanm	0:9b334a45a8ff	628	#define TIM_FLAG_CC6 (TIM_SR_CC6IF)
bogdanm	0:9b334a45a8ff	629	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	0:9b334a45a8ff	630	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	631	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	0:9b334a45a8ff	632	#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
bogdanm	0:9b334a45a8ff	633	#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
bogdanm	0:9b334a45a8ff	634	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	635	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	636	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	637	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	638	/**
bogdanm	0:9b334a45a8ff	639	* @}
bogdanm	0:9b334a45a8ff	640	*/
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/** @defgroup TIM_Channel TIM Channel
bogdanm	0:9b334a45a8ff	643	* @{
bogdanm	0:9b334a45a8ff	644	*/
bogdanm	0:9b334a45a8ff	645	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	646	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	647	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	648	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	649	#define TIM_CHANNEL_5 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	650	#define TIM_CHANNEL_6 ((uint32_t)0x0014)
bogdanm	0:9b334a45a8ff	651	#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
bogdanm	0:9b334a45a8ff	652	/**
bogdanm	0:9b334a45a8ff	653	* @}
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	0:9b334a45a8ff	657	* @{
bogdanm	0:9b334a45a8ff	658	*/
bogdanm	0:9b334a45a8ff	659	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	660	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	661	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	662	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	663	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	664	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	665	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	666	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	667	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	668	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	669	/**
bogdanm	0:9b334a45a8ff	670	* @}
bogdanm	0:9b334a45a8ff	671	*/
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	0:9b334a45a8ff	674	* @{
bogdanm	0:9b334a45a8ff	675	*/
bogdanm	0:9b334a45a8ff	676	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	677	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	678	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	679	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	680	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	681	/**
bogdanm	0:9b334a45a8ff	682	* @}
bogdanm	0:9b334a45a8ff	683	*/
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	0:9b334a45a8ff	686	* @{
bogdanm	0:9b334a45a8ff	687	*/
bogdanm	0:9b334a45a8ff	688	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	689	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	690	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	691	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	692	/**
bogdanm	0:9b334a45a8ff	693	* @}
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	0:9b334a45a8ff	697	* @{
bogdanm	0:9b334a45a8ff	698	*/
bogdanm	0:9b334a45a8ff	699	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	700	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	701	/**
bogdanm	0:9b334a45a8ff	702	* @}
bogdanm	0:9b334a45a8ff	703	*/
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	0:9b334a45a8ff	706	* @{
bogdanm	0:9b334a45a8ff	707	*/
bogdanm	0:9b334a45a8ff	708	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	709	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	710	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	711	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	712	/**
bogdanm	0:9b334a45a8ff	713	* @}
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
bogdanm	0:9b334a45a8ff	717	* @{
bogdanm	0:9b334a45a8ff	718	*/
bogdanm	0:9b334a45a8ff	719	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	0:9b334a45a8ff	720	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	721	/**
bogdanm	0:9b334a45a8ff	722	* @}
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
bogdanm	0:9b334a45a8ff	726	* @{
bogdanm	0:9b334a45a8ff	727	*/
bogdanm	0:9b334a45a8ff	728	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	0:9b334a45a8ff	729	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	730	/**
bogdanm	0:9b334a45a8ff	731	* @}
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733	/** @defgroup TIM_Lock_level TIM Lock level
bogdanm	0:9b334a45a8ff	734	* @{
bogdanm	0:9b334a45a8ff	735	*/
bogdanm	0:9b334a45a8ff	736	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	737	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	0:9b334a45a8ff	738	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	0:9b334a45a8ff	739	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	0:9b334a45a8ff	740	/**
bogdanm	0:9b334a45a8ff	741	* @}
bogdanm	0:9b334a45a8ff	742	*/
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
bogdanm	0:9b334a45a8ff	745	* @{
bogdanm	0:9b334a45a8ff	746	*/
bogdanm	0:9b334a45a8ff	747	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	0:9b334a45a8ff	748	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	749	/**
bogdanm	0:9b334a45a8ff	750	* @}
bogdanm	0:9b334a45a8ff	751	*/
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	0:9b334a45a8ff	754	* @{
bogdanm	0:9b334a45a8ff	755	*/
bogdanm	0:9b334a45a8ff	756	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	757	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	0:9b334a45a8ff	758	/**
bogdanm	0:9b334a45a8ff	759	* @}
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
bogdanm	0:9b334a45a8ff	763	* @{
bogdanm	0:9b334a45a8ff	764	*/
bogdanm	0:9b334a45a8ff	765	#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	766	#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
bogdanm	0:9b334a45a8ff	767	/**
bogdanm	0:9b334a45a8ff	768	* @}
bogdanm	0:9b334a45a8ff	769	*/
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
bogdanm	0:9b334a45a8ff	772	* @{
bogdanm	0:9b334a45a8ff	773	*/
bogdanm	0:9b334a45a8ff	774	#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	775	#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
bogdanm	0:9b334a45a8ff	776	/**
bogdanm	0:9b334a45a8ff	777	* @}
bogdanm	0:9b334a45a8ff	778	*/
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	0:9b334a45a8ff	781	* @{
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	0:9b334a45a8ff	784	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	785	/**
bogdanm	0:9b334a45a8ff	786	* @}
bogdanm	0:9b334a45a8ff	787	*/
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
bogdanm	0:9b334a45a8ff	790	* @{
bogdanm	0:9b334a45a8ff	791	*/
bogdanm	0:9b334a45a8ff	792	#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
bogdanm	0:9b334a45a8ff	793	#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
bogdanm	0:9b334a45a8ff	794	#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
bogdanm	0:9b334a45a8ff	795	#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
bogdanm	0:9b334a45a8ff	796	/**
bogdanm	0:9b334a45a8ff	797	* @}
bogdanm	0:9b334a45a8ff	798	*/
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	0:9b334a45a8ff	801	* @{
bogdanm	0:9b334a45a8ff	802	*/
bogdanm	0:9b334a45a8ff	803	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	804	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	805	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	806	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	807	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	808	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	809	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	810	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	811	/**
bogdanm	0:9b334a45a8ff	812	* @}
bogdanm	0:9b334a45a8ff	813	*/
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
bogdanm	0:9b334a45a8ff	816	* @{
bogdanm	0:9b334a45a8ff	817	*/
bogdanm	0:9b334a45a8ff	818	#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	819	#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	820	#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	821	#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	822	#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
bogdanm	0:9b334a45a8ff	823	#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	824	#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	825	#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	826	#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
bogdanm	0:9b334a45a8ff	827	#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	828	#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	829	#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	830	#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2))
bogdanm	0:9b334a45a8ff	831	#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	832	#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	833	#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	834	/**
bogdanm	0:9b334a45a8ff	835	* @}
bogdanm	0:9b334a45a8ff	836	*/
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
bogdanm	0:9b334a45a8ff	839	* @{
bogdanm	0:9b334a45a8ff	840	*/
bogdanm	0:9b334a45a8ff	841	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	842	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	843	/**
bogdanm	0:9b334a45a8ff	844	* @}
bogdanm	0:9b334a45a8ff	845	*/
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/** @defgroup TIM_Slave_Mode TIM Slave mode
bogdanm	0:9b334a45a8ff	848	* @{
bogdanm	0:9b334a45a8ff	849	*/
bogdanm	0:9b334a45a8ff	850	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	851	#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
bogdanm	0:9b334a45a8ff	852	#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0))
bogdanm	0:9b334a45a8ff	853	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1))
bogdanm	0:9b334a45a8ff	854	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0))
bogdanm	0:9b334a45a8ff	855	#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
bogdanm	0:9b334a45a8ff	856	/**
bogdanm	0:9b334a45a8ff	857	* @}
bogdanm	0:9b334a45a8ff	858	*/
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
bogdanm	0:9b334a45a8ff	861	* @{
bogdanm	0:9b334a45a8ff	862	*/
bogdanm	0:9b334a45a8ff	863	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	864	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	865	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	866	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	867	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	868	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	869	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	870	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
bogdanm	0:9b334a45a8ff	873	#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	874	#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	875	#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	876	#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	877	#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	878	/**
bogdanm	0:9b334a45a8ff	879	* @}
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881
bogdanm	0:9b334a45a8ff	882	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	0:9b334a45a8ff	883	* @{
bogdanm	0:9b334a45a8ff	884	*/
bogdanm	0:9b334a45a8ff	885	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	886	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	887	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	888	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	889	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	890	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	891	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	892	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	893	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @}
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	0:9b334a45a8ff	899	* @{
bogdanm	0:9b334a45a8ff	900	*/
bogdanm	0:9b334a45a8ff	901	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	902	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	903	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	904	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	905	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	906	/**
bogdanm	0:9b334a45a8ff	907	* @}
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	0:9b334a45a8ff	911	* @{
bogdanm	0:9b334a45a8ff	912	*/
bogdanm	0:9b334a45a8ff	913	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	914	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	915	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	916	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	917	/**
bogdanm	0:9b334a45a8ff	918	* @}
bogdanm	0:9b334a45a8ff	919	*/
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	0:9b334a45a8ff	922	* @{
bogdanm	0:9b334a45a8ff	923	*/
bogdanm	0:9b334a45a8ff	924	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	925	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	926	/**
bogdanm	0:9b334a45a8ff	927	* @}
bogdanm	0:9b334a45a8ff	928	*/
bogdanm	0:9b334a45a8ff	929
bogdanm	0:9b334a45a8ff	930	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	0:9b334a45a8ff	931	* @{
bogdanm	0:9b334a45a8ff	932	*/
bogdanm	0:9b334a45a8ff	933	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
bogdanm	0:9b334a45a8ff	934	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
bogdanm	0:9b334a45a8ff	935	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
bogdanm	0:9b334a45a8ff	936	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
bogdanm	0:9b334a45a8ff	937	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
bogdanm	0:9b334a45a8ff	938	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
bogdanm	0:9b334a45a8ff	939	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
bogdanm	0:9b334a45a8ff	940	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
bogdanm	0:9b334a45a8ff	941	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
bogdanm	0:9b334a45a8ff	942	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
bogdanm	0:9b334a45a8ff	943	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
bogdanm	0:9b334a45a8ff	944	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
bogdanm	0:9b334a45a8ff	945	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
bogdanm	0:9b334a45a8ff	946	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
bogdanm	0:9b334a45a8ff	947	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
bogdanm	0:9b334a45a8ff	948	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
bogdanm	0:9b334a45a8ff	949	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
bogdanm	0:9b334a45a8ff	950	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm	0:9b334a45a8ff	951	/**
bogdanm	0:9b334a45a8ff	952	* @}
bogdanm	0:9b334a45a8ff	953	*/
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/** @defgroup DMA_Handle_index TIM DMA Handle Index
bogdanm	0:9b334a45a8ff	956	* @{
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	959	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	960	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	961	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	962	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	963	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	0:9b334a45a8ff	964	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	965	/**
bogdanm	0:9b334a45a8ff	966	* @}
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
bogdanm	0:9b334a45a8ff	970	* @{
bogdanm	0:9b334a45a8ff	971	*/
bogdanm	0:9b334a45a8ff	972	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	973	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	974	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	975	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	976	/**
bogdanm	0:9b334a45a8ff	977	* @}
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/** @defgroup TIM_Break_System
bogdanm	0:9b334a45a8ff	981	* @{
bogdanm	0:9b334a45a8ff	982	*/
bogdanm	0:9b334a45a8ff	983	#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 /
bogdanm	0:9b334a45a8ff	984	#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface /
bogdanm	0:9b334a45a8ff	985	#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 /
bogdanm	0:9b334a45a8ff	986	#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 /
bogdanm	0:9b334a45a8ff	987	/**
bogdanm	0:9b334a45a8ff	988	* @}
bogdanm	0:9b334a45a8ff	989	*/
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/**
bogdanm	0:9b334a45a8ff	992	* @}
bogdanm	0:9b334a45a8ff	993	*/
bogdanm	0:9b334a45a8ff	994	/* End of exported constants -------------------------------------------------*/
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	997	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	0:9b334a45a8ff	998	* @{
bogdanm	0:9b334a45a8ff	999	*/
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/** @brief Reset TIM handle state.
bogdanm	0:9b334a45a8ff	1002	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1003	* @retval None
bogdanm	0:9b334a45a8ff	1004	*/
bogdanm	0:9b334a45a8ff	1005	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	/**
bogdanm	0:9b334a45a8ff	1008	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1009	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1010	* @retval None
bogdanm	0:9b334a45a8ff	1011	*/
bogdanm	0:9b334a45a8ff	1012	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Enable the TIM main Output.
bogdanm	0:9b334a45a8ff	1016	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1017	* @retval None
bogdanm	0:9b334a45a8ff	1018	*/
bogdanm	0:9b334a45a8ff	1019	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	/**
bogdanm	0:9b334a45a8ff	1022	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1023	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1024	* @retval None
bogdanm	0:9b334a45a8ff	1025	*/
bogdanm	0:9b334a45a8ff	1026	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1027	do { \
bogdanm	0:9b334a45a8ff	1028	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1029	{ \
bogdanm	0:9b334a45a8ff	1030	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1031	{ \
bogdanm	0:9b334a45a8ff	1032	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	1033	} \
bogdanm	0:9b334a45a8ff	1034	} \
bogdanm	0:9b334a45a8ff	1035	} while(0)
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/**
bogdanm	0:9b334a45a8ff	1038	* @brief Disable the TIM main Output.
bogdanm	0:9b334a45a8ff	1039	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1040	* @retval None
bogdanm	0:9b334a45a8ff	1041	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
bogdanm	0:9b334a45a8ff	1042	*/
bogdanm	0:9b334a45a8ff	1043	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1044	do { \
bogdanm	0:9b334a45a8ff	1045	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1046	{ \
bogdanm	0:9b334a45a8ff	1047	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1048	{ \
bogdanm	0:9b334a45a8ff	1049	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	0:9b334a45a8ff	1050	} \
bogdanm	0:9b334a45a8ff	1051	} \
bogdanm	0:9b334a45a8ff	1052	} while(0)
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/** @brief Enable the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1055	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1056	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
bogdanm	0:9b334a45a8ff	1057	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1058	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1059	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1060	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1061	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1062	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1063	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1064	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1065	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1066	* @retval None
bogdanm	0:9b334a45a8ff	1067	*/
bogdanm	0:9b334a45a8ff	1068	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/** @brief Disable the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1072	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1073	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
bogdanm	0:9b334a45a8ff	1074	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1075	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1076	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1077	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1078	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1079	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1080	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1081	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1082	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1083	* @retval None
bogdanm	0:9b334a45a8ff	1084	*/
bogdanm	0:9b334a45a8ff	1085	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/** @brief Enable the specified DMA request.
bogdanm	0:9b334a45a8ff	1088	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1089	* @param __DMA__: specifies the TIM DMA request to enable.
bogdanm	0:9b334a45a8ff	1090	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1091	* @arg TIM_DMA_UPDATE: Update DMA request
bogdanm	0:9b334a45a8ff	1092	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
bogdanm	0:9b334a45a8ff	1093	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
bogdanm	0:9b334a45a8ff	1094	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
bogdanm	0:9b334a45a8ff	1095	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
bogdanm	0:9b334a45a8ff	1096	* @arg TIM_DMA_COM: Commutation DMA request
bogdanm	0:9b334a45a8ff	1097	* @arg TIM_DMA_TRIGGER: Trigger DMA request
bogdanm	0:9b334a45a8ff	1098	* @arg TIM_DMA_BREAK: Break DMA request
bogdanm	0:9b334a45a8ff	1099	* @retval None
bogdanm	0:9b334a45a8ff	1100	*/
bogdanm	0:9b334a45a8ff	1101	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/** @brief Disable the specified DMA request.
bogdanm	0:9b334a45a8ff	1104	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1105	* @param __DMA__: specifies the TIM DMA request to disable.
bogdanm	0:9b334a45a8ff	1106	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1107	* @arg TIM_DMA_UPDATE: Update DMA request
bogdanm	0:9b334a45a8ff	1108	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
bogdanm	0:9b334a45a8ff	1109	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
bogdanm	0:9b334a45a8ff	1110	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
bogdanm	0:9b334a45a8ff	1111	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
bogdanm	0:9b334a45a8ff	1112	* @arg TIM_DMA_COM: Commutation DMA request
bogdanm	0:9b334a45a8ff	1113	* @arg TIM_DMA_TRIGGER: Trigger DMA request
bogdanm	0:9b334a45a8ff	1114	* @arg TIM_DMA_BREAK: Break DMA request
bogdanm	0:9b334a45a8ff	1115	* @retval None
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/** @brief Check whether the specified TIM interrupt flag is set or not.
bogdanm	0:9b334a45a8ff	1120	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1121	* @param __FLAG__: specifies the TIM interrupt flag to check.
bogdanm	0:9b334a45a8ff	1122	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1123	* @arg TIM_FLAG_UPDATE: Update interrupt flag
bogdanm	0:9b334a45a8ff	1124	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
bogdanm	0:9b334a45a8ff	1125	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
bogdanm	0:9b334a45a8ff	1126	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
bogdanm	0:9b334a45a8ff	1127	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
bogdanm	0:9b334a45a8ff	1128	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
bogdanm	0:9b334a45a8ff	1129	* @arg TIM_FLAG_CC6: Compare 5 interrupt flag
bogdanm	0:9b334a45a8ff	1130	* @arg TIM_FLAG_COM: Commutation interrupt flag
bogdanm	0:9b334a45a8ff	1131	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
bogdanm	0:9b334a45a8ff	1132	* @arg TIM_FLAG_BREAK: Break interrupt flag
bogdanm	0:9b334a45a8ff	1133	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
bogdanm	0:9b334a45a8ff	1134	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
bogdanm	0:9b334a45a8ff	1135	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
bogdanm	0:9b334a45a8ff	1136	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
bogdanm	0:9b334a45a8ff	1137	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
bogdanm	0:9b334a45a8ff	1138	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
bogdanm	0:9b334a45a8ff	1139	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1140	*/
bogdanm	0:9b334a45a8ff	1141	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	/** @brief Clear the specified TIM interrupt flag.
bogdanm	0:9b334a45a8ff	1144	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1145	* @param __FLAG__: specifies the TIM interrupt flag to clear.
bogdanm	0:9b334a45a8ff	1146	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1147	* @arg TIM_FLAG_UPDATE: Update interrupt flag
bogdanm	0:9b334a45a8ff	1148	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
bogdanm	0:9b334a45a8ff	1149	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
bogdanm	0:9b334a45a8ff	1150	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
bogdanm	0:9b334a45a8ff	1151	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
bogdanm	0:9b334a45a8ff	1152	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
bogdanm	0:9b334a45a8ff	1153	* @arg TIM_FLAG_CC6: Compare 5 interrupt flag
bogdanm	0:9b334a45a8ff	1154	* @arg TIM_FLAG_COM: Commutation interrupt flag
bogdanm	0:9b334a45a8ff	1155	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
bogdanm	0:9b334a45a8ff	1156	* @arg TIM_FLAG_BREAK: Break interrupt flag
bogdanm	0:9b334a45a8ff	1157	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
bogdanm	0:9b334a45a8ff	1158	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
bogdanm	0:9b334a45a8ff	1159	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
bogdanm	0:9b334a45a8ff	1160	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
bogdanm	0:9b334a45a8ff	1161	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
bogdanm	0:9b334a45a8ff	1162	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
bogdanm	0:9b334a45a8ff	1163	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	/**
bogdanm	0:9b334a45a8ff	1168	* @brief Check whether the specified TIM interrupt source is enabled or not.
bogdanm	0:9b334a45a8ff	1169	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1170	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
bogdanm	0:9b334a45a8ff	1171	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1172	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1173	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1174	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1175	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1176	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1177	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1178	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1179	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1180	* @retval The state of TIM_IT (SET or RESET).
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	/** @brief Clear the TIM interrupt pending bits.
bogdanm	0:9b334a45a8ff	1185	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1186	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1187	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1188	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1189	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1190	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1191	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1192	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1193	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1194	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1195	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1196	* @retval None
bogdanm	0:9b334a45a8ff	1197	*/
bogdanm	0:9b334a45a8ff	1198	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/**
bogdanm	0:9b334a45a8ff	1201	* @brief Indicates whether or not the TIM Counter is used as downcounter.
bogdanm	0:9b334a45a8ff	1202	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1203	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
bogdanm	0:9b334a45a8ff	1204	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
bogdanm	0:9b334a45a8ff	1205	mode.
bogdanm	0:9b334a45a8ff	1206	*/
bogdanm	0:9b334a45a8ff	1207	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/**
bogdanm	0:9b334a45a8ff	1211	* @brief Set the TIM Prescaler on runtime.
bogdanm	0:9b334a45a8ff	1212	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1213	* @param __PRESC__: specifies the Prescaler new value.
bogdanm	0:9b334a45a8ff	1214	* @retval None
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/**
bogdanm	0:9b334a45a8ff	1219	* @brief Set the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1220	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1221	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1222	* @retval None
bogdanm	0:9b334a45a8ff	1223	*/
bogdanm	0:9b334a45a8ff	1224	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/**
bogdanm	0:9b334a45a8ff	1227	* @brief Get the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1228	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1229	* @retval None
bogdanm	0:9b334a45a8ff	1230	*/
bogdanm	0:9b334a45a8ff	1231	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1232	((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/**
bogdanm	0:9b334a45a8ff	1235	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
bogdanm	0:9b334a45a8ff	1236	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1237	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1238	* @retval None
bogdanm	0:9b334a45a8ff	1239	*/
bogdanm	0:9b334a45a8ff	1240	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1241	do{ \
bogdanm	0:9b334a45a8ff	1242	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1243	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1244	} while(0)
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/**
bogdanm	0:9b334a45a8ff	1247	* @brief Get the TIM Autoreload Register value on runtime.
bogdanm	0:9b334a45a8ff	1248	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1249	* @retval None
bogdanm	0:9b334a45a8ff	1250	*/
bogdanm	0:9b334a45a8ff	1251	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1252	((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	/**
bogdanm	0:9b334a45a8ff	1255	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
bogdanm	0:9b334a45a8ff	1256	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1257	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1258	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1259	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1260	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1261	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1262	* @retval None
bogdanm	0:9b334a45a8ff	1263	*/
bogdanm	0:9b334a45a8ff	1264	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1265	do{ \
bogdanm	0:9b334a45a8ff	1266	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1267	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1268	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1269	} while(0)
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/**
bogdanm	0:9b334a45a8ff	1272	* @brief Get the TIM Clock Division value on runtime.
bogdanm	0:9b334a45a8ff	1273	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1274	* @retval None
bogdanm	0:9b334a45a8ff	1275	*/
bogdanm	0:9b334a45a8ff	1276	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1277	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/**
bogdanm	0:9b334a45a8ff	1280	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1281	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1282	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1283	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1284	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1285	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1286	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1287	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1288	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1289	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1290	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1291	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1292	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1293	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1294	* @retval None
bogdanm	0:9b334a45a8ff	1295	*/
bogdanm	0:9b334a45a8ff	1296	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1297	do{ \
bogdanm	0:9b334a45a8ff	1298	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1299	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1300	} while(0)
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/**
bogdanm	0:9b334a45a8ff	1303	* @brief Get the TIM Input Capture prescaler on runtime.
bogdanm	0:9b334a45a8ff	1304	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1305	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1306	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1307	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1308	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1309	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1310	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1311	* @retval None
bogdanm	0:9b334a45a8ff	1312	*/
bogdanm	0:9b334a45a8ff	1313	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1314	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1315	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1316	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1317	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/**
bogdanm	0:9b334a45a8ff	1320	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	1321	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1322	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1323	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1324	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1325	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1326	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1327	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1328	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	1329	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	1330	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	1331	* @retval None
bogdanm	0:9b334a45a8ff	1332	*/
bogdanm	0:9b334a45a8ff	1333	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	1334	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	1335	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	1336	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	1337	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	1338	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	1339	((__HANDLE__)->Instance->CCR6 \|= (__COMPARE__)))
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/**
bogdanm	0:9b334a45a8ff	1342	* @brief Get the TIM Capture Compare Register value on runtime.
bogdanm	0:9b334a45a8ff	1343	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1344	* @param __CHANNEL__: TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	1345	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1346	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	1347	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	1348	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	1349	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	1350	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
bogdanm	0:9b334a45a8ff	1351	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
bogdanm	0:9b334a45a8ff	1352	* @retval None
bogdanm	0:9b334a45a8ff	1353	*/
bogdanm	0:9b334a45a8ff	1354	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1355	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
bogdanm	0:9b334a45a8ff	1356	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
bogdanm	0:9b334a45a8ff	1357	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
bogdanm	0:9b334a45a8ff	1358	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
bogdanm	0:9b334a45a8ff	1359	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
bogdanm	0:9b334a45a8ff	1360	((__HANDLE__)->Instance->CCR6))
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	/**
bogdanm	0:9b334a45a8ff	1363	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
bogdanm	0:9b334a45a8ff	1364	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1365	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	0:9b334a45a8ff	1366	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1367	* enabled)
bogdanm	0:9b334a45a8ff	1368	* @retval None
bogdanm	0:9b334a45a8ff	1369	*/
bogdanm	0:9b334a45a8ff	1370	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1371	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	/**
bogdanm	0:9b334a45a8ff	1374	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
bogdanm	0:9b334a45a8ff	1375	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1376	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	0:9b334a45a8ff	1377	* following events generate an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1378	* enabled):
bogdanm	0:9b334a45a8ff	1379	* _ Counter overflow underflow
bogdanm	0:9b334a45a8ff	1380	* _ Setting the UG bit
bogdanm	0:9b334a45a8ff	1381	* _ Update generation through the slave mode controller
bogdanm	0:9b334a45a8ff	1382	* @retval None
bogdanm	0:9b334a45a8ff	1383	*/
bogdanm	0:9b334a45a8ff	1384	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1385	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/**
bogdanm	0:9b334a45a8ff	1388	* @brief Set the TIM Capture x input polarity on runtime.
bogdanm	0:9b334a45a8ff	1389	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1390	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1391	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1392	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1393	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1394	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1395	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1396	* @param __POLARITY__: Polarity for TIx source
bogdanm	0:9b334a45a8ff	1397	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
bogdanm	0:9b334a45a8ff	1398	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
bogdanm	0:9b334a45a8ff	1399	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
bogdanm	0:9b334a45a8ff	1400	* @retval None
bogdanm	0:9b334a45a8ff	1401	*/
bogdanm	0:9b334a45a8ff	1402	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1403	do{ \
bogdanm	0:9b334a45a8ff	1404	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1405	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
bogdanm	0:9b334a45a8ff	1406	}while(0)
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	/**
bogdanm	0:9b334a45a8ff	1409	* @}
bogdanm	0:9b334a45a8ff	1410	*/
bogdanm	0:9b334a45a8ff	1411	/* End of exported macros ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Private constants ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1414	/** @defgroup TIM_Private_Constants TIM Private Constants
bogdanm	0:9b334a45a8ff	1415	* @{
bogdanm	0:9b334a45a8ff	1416	*/
bogdanm	0:9b334a45a8ff	1417	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	1418	channels have been disabled */
bogdanm	0:9b334a45a8ff	1419	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	1420	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	0:9b334a45a8ff	1421	/**
bogdanm	0:9b334a45a8ff	1422	* @}
bogdanm	0:9b334a45a8ff	1423	*/
bogdanm	0:9b334a45a8ff	1424	/* End of private constants --------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1427	/** @defgroup TIM_Private_Macros TIM Private Macros
bogdanm	0:9b334a45a8ff	1428	* @{
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
bogdanm	0:9b334a45a8ff	1432	((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
bogdanm	0:9b334a45a8ff	1433	((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
bogdanm	0:9b334a45a8ff	1436	((__BASE__) == TIM_DMABASE_CR2) \|\| \
bogdanm	0:9b334a45a8ff	1437	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	1438	((__BASE__) == TIM_DMABASE_DIER) \|\| \
bogdanm	0:9b334a45a8ff	1439	((__BASE__) == TIM_DMABASE_SR) \|\| \
bogdanm	0:9b334a45a8ff	1440	((__BASE__) == TIM_DMABASE_EGR) \|\| \
bogdanm	0:9b334a45a8ff	1441	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	1442	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	1443	((__BASE__) == TIM_DMABASE_CCER) \|\| \
bogdanm	0:9b334a45a8ff	1444	((__BASE__) == TIM_DMABASE_CNT) \|\| \
bogdanm	0:9b334a45a8ff	1445	((__BASE__) == TIM_DMABASE_PSC) \|\| \
bogdanm	0:9b334a45a8ff	1446	((__BASE__) == TIM_DMABASE_ARR) \|\| \
bogdanm	0:9b334a45a8ff	1447	((__BASE__) == TIM_DMABASE_RCR) \|\| \
bogdanm	0:9b334a45a8ff	1448	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	1449	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	1450	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	1451	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	1452	((__BASE__) == TIM_DMABASE_BDTR) \|\| \
bogdanm	0:9b334a45a8ff	1453	((__BASE__) == TIM_DMABASE_CCMR3) \|\| \
bogdanm	0:9b334a45a8ff	1454	((__BASE__) == TIM_DMABASE_CCR5) \|\| \
bogdanm	0:9b334a45a8ff	1455	((__BASE__) == TIM_DMABASE_CCR6) \|\| \
bogdanm	0:9b334a45a8ff	1456	((__BASE__) == TIM_DMABASE_OR1) \|\| \
bogdanm	0:9b334a45a8ff	1457	((__BASE__) == TIM_DMABASE_OR2) \|\| \
bogdanm	0:9b334a45a8ff	1458	((__BASE__) == TIM_DMABASE_OR3))
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	1465	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	1466	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	1467	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	1468	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1471	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1472	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	1473
bogdanm	0:9b334a45a8ff	1474	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1475	((__STATE__) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1478	((__POLARITY__) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1481	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	1484	((__STATE__) == TIM_OCIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	1487	((__STATE__) == TIM_OCNIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1490	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1491	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	1492
bogdanm	0:9b334a45a8ff	1493	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	1494	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	1495	((__SELECTION__) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1498	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1499	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1500	((__PRESCALER__) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	1503	((__MODE__) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	1506	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	1507	((__MODE__) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1512	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1513	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	1514	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	1515	((__CHANNEL__) == TIM_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	1516	((__CHANNEL__) == TIM_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	1517	((__CHANNEL__) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1520	((__CHANNEL__) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1523	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1524	((__CHANNEL__) == TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	1527	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	1528	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1529	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1530	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1531	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1532	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	1533	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	1534	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	1535	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1538	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1539	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1540	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1541	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1544	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1545	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1546	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1551	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1554	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1555	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1556	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1562	((__STATE__) == TIM_OSSR_DISABLE))
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1565	((__STATE__) == TIM_OSSI_DISABLE))
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	1568	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1569	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1570	((__LEVEL__) == TIM_LOCKLEVEL_3))
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1576	((__STATE__) == TIM_BREAK_DISABLE))
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1579	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1582	((__STATE__) == TIM_BREAK2_DISABLE))
bogdanm	0:9b334a45a8ff	1583
bogdanm	0:9b334a45a8ff	1584	#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1585	((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1588	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
bogdanm	0:9b334a45a8ff	1591
bogdanm	0:9b334a45a8ff	1592	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1593	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1594	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	1595	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	1596	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	1597	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	1598	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	1599	((__SOURCE__) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	1600
bogdanm	0:9b334a45a8ff	1601	#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1602	((__SOURCE__) == TIM_TRGO2_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1603	((__SOURCE__) == TIM_TRGO2_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	1604	((__SOURCE__) == TIM_TRGO2_OC1) \|\| \
bogdanm	0:9b334a45a8ff	1605	((__SOURCE__) == TIM_TRGO2_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	1606	((__SOURCE__) == TIM_TRGO2_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	1607	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	1608	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	1609	((__SOURCE__) == TIM_TRGO2_OC4REF) \|\| \
bogdanm	0:9b334a45a8ff	1610	((__SOURCE__) == TIM_TRGO2_OC5REF) \|\| \
bogdanm	0:9b334a45a8ff	1611	((__SOURCE__) == TIM_TRGO2_OC6REF) \|\| \
bogdanm	0:9b334a45a8ff	1612	((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) \|\| \
bogdanm	0:9b334a45a8ff	1613	((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) \|\| \
bogdanm	0:9b334a45a8ff	1614	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1615	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1616	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1617	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1620	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1623	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1624	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	1625	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	1626	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) \|\| \
bogdanm	0:9b334a45a8ff	1627	((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	1630	((__MODE__) == TIM_OCMODE_PWM2) \|\| \
bogdanm	0:9b334a45a8ff	1631	((__MODE__) == TIM_OCMODE_COMBINED_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	1632	((__MODE__) == TIM_OCMODE_COMBINED_PWM2) \|\| \
bogdanm	0:9b334a45a8ff	1633	((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	1634	((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	1637	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1638	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1639	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	1640	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1641	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1642	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) \|\| \
bogdanm	0:9b334a45a8ff	1643	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1646	((__SELECTION__) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1647	((__SELECTION__) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1648	((__SELECTION__) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1649	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	1650	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	1651	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	1652	((__SELECTION__) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1655	((__SELECTION__) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1656	((__SELECTION__) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1657	((__SELECTION__) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1658	((__SELECTION__) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	1662	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1663	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	1664	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	1665	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1668	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1669	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1670	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	1675	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
bogdanm	0:9b334a45a8ff	1678	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1679	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1680	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1681	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1682	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1683	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1684	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1685	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1686	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1687	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1688	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1689	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1690	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1691	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1692	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1693	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1694	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) \|\| \
bogdanm	0:9b334a45a8ff	1701	((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) \|\| \
bogdanm	0:9b334a45a8ff	1702	((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) \|\| \
bogdanm	0:9b334a45a8ff	1703	((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1706	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1707	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	1708	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1709	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1712	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1713	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	1714	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1715	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1718	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
bogdanm	0:9b334a45a8ff	1719	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
bogdanm	0:9b334a45a8ff	1720	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
bogdanm	0:9b334a45a8ff	1721	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12))))
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1724	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
bogdanm	0:9b334a45a8ff	1725	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
bogdanm	0:9b334a45a8ff	1726	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
bogdanm	0:9b334a45a8ff	1727	((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729	/**
bogdanm	0:9b334a45a8ff	1730	* @}
bogdanm	0:9b334a45a8ff	1731	*/
bogdanm	0:9b334a45a8ff	1732	/* End of private macros -----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	/* Include TIM HAL Extended module */
bogdanm	0:9b334a45a8ff	1735	#include "stm32l4xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1738	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	1739	* @{
bogdanm	0:9b334a45a8ff	1740	*/
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	1743	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	1744	* @{
bogdanm	0:9b334a45a8ff	1745	*/
bogdanm	0:9b334a45a8ff	1746	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1747	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1748	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1749	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1750	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1751	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1752	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1753	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1754	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1755	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1756	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1757	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1758	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1759	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1760	/**
bogdanm	0:9b334a45a8ff	1761	* @}
bogdanm	0:9b334a45a8ff	1762	*/
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	1765	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	1766	* @{
bogdanm	0:9b334a45a8ff	1767	*/
bogdanm	0:9b334a45a8ff	1768	/* Timer Output Compare functions *********************************************/
bogdanm	0:9b334a45a8ff	1769	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1770	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1771	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1772	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1773	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1774	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1775	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1776	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1777	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1778	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1779	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1780	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1781	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1782	/**
bogdanm	0:9b334a45a8ff	1783	* @}
bogdanm	0:9b334a45a8ff	1784	*/
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	1787	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	1788	* @{
bogdanm	0:9b334a45a8ff	1789	*/
bogdanm	0:9b334a45a8ff	1790	/* Timer PWM functions ********************************************************/
bogdanm	0:9b334a45a8ff	1791	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1792	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1793	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1794	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1795	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1796	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1797	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1798	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1799	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1800	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1801	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1802	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1803	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1804	/**
bogdanm	0:9b334a45a8ff	1805	* @}
bogdanm	0:9b334a45a8ff	1806	*/
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1809	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1810	* @{
bogdanm	0:9b334a45a8ff	1811	*/
bogdanm	0:9b334a45a8ff	1812	/* Timer Input Capture functions **********************************************/
bogdanm	0:9b334a45a8ff	1813	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1814	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1815	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1816	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1817	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1818	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1819	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1820	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1821	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1822	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1823	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1824	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1825	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1826	/**
bogdanm	0:9b334a45a8ff	1827	* @}
bogdanm	0:9b334a45a8ff	1828	*/
bogdanm	0:9b334a45a8ff	1829
bogdanm	0:9b334a45a8ff	1830	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1831	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1832	* @{
bogdanm	0:9b334a45a8ff	1833	*/
bogdanm	0:9b334a45a8ff	1834	/* Timer One Pulse functions **************************************************/
bogdanm	0:9b334a45a8ff	1835	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1836	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1837	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1838	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1839	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1840	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1841	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1842	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1843	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1844	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1845	/**
bogdanm	0:9b334a45a8ff	1846	* @}
bogdanm	0:9b334a45a8ff	1847	*/
bogdanm	0:9b334a45a8ff	1848
bogdanm	0:9b334a45a8ff	1849	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	1850	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	1851	* @{
bogdanm	0:9b334a45a8ff	1852	*/
bogdanm	0:9b334a45a8ff	1853	/* Timer Encoder functions ****************************************************/
bogdanm	0:9b334a45a8ff	1854	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1855	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1856	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1857	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1858	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1859	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1860	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1861	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1862	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1863	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1864	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1865	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1866	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @}
bogdanm	0:9b334a45a8ff	1869	*/
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	1872	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	1873	* @{
bogdanm	0:9b334a45a8ff	1874	*/
bogdanm	0:9b334a45a8ff	1875	/* Interrupt Handler functions ***********************************************/
bogdanm	0:9b334a45a8ff	1876	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1877	/**
bogdanm	0:9b334a45a8ff	1878	* @}
bogdanm	0:9b334a45a8ff	1879	*/
bogdanm	0:9b334a45a8ff	1880
bogdanm	0:9b334a45a8ff	1881	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1882	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1883	* @{
bogdanm	0:9b334a45a8ff	1884	*/
bogdanm	0:9b334a45a8ff	1885	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1886	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1887	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1888	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1889	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1890	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1891	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1892	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1893	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1894	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1895	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1896	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1897	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1898	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1899	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1900	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1901	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1902	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1903	/**
bogdanm	0:9b334a45a8ff	1904	* @}
bogdanm	0:9b334a45a8ff	1905	*/
bogdanm	0:9b334a45a8ff	1906
bogdanm	0:9b334a45a8ff	1907	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	1908	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	1909	* @{
bogdanm	0:9b334a45a8ff	1910	*/
bogdanm	0:9b334a45a8ff	1911	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1912	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1913	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1914	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1915	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1916	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1917	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1918	/**
bogdanm	0:9b334a45a8ff	1919	* @}
bogdanm	0:9b334a45a8ff	1920	*/
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	1923	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1924	* @{
bogdanm	0:9b334a45a8ff	1925	*/
bogdanm	0:9b334a45a8ff	1926	/* Peripheral State functions ************************************************/
bogdanm	0:9b334a45a8ff	1927	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1928	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1929	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1930	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1931	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1932	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1933	/**
bogdanm	0:9b334a45a8ff	1934	* @}
bogdanm	0:9b334a45a8ff	1935	*/
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	/**
bogdanm	0:9b334a45a8ff	1938	* @}
bogdanm	0:9b334a45a8ff	1939	*/
bogdanm	0:9b334a45a8ff	1940	/* End of exported functions -------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/* Private functions----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1943	/** @defgroup TIM_Private_Functions TIM Private Functions
bogdanm	0:9b334a45a8ff	1944	* @{
bogdanm	0:9b334a45a8ff	1945	*/
bogdanm	0:9b334a45a8ff	1946	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	0:9b334a45a8ff	1947	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	1948	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1949	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1950	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1951	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1952	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	1953	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm	0:9b334a45a8ff	1954
bogdanm	0:9b334a45a8ff	1955	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1956	void TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1957	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1958	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	0:9b334a45a8ff	1959	/**
bogdanm	0:9b334a45a8ff	1960	* @}
bogdanm	0:9b334a45a8ff	1961	*/
bogdanm	0:9b334a45a8ff	1962	/* End of private functions --------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1963
bogdanm	0:9b334a45a8ff	1964	/**
bogdanm	0:9b334a45a8ff	1965	* @}
bogdanm	0:9b334a45a8ff	1966	*/
bogdanm	0:9b334a45a8ff	1967
bogdanm	0:9b334a45a8ff	1968	/**
bogdanm	0:9b334a45a8ff	1969	* @}
bogdanm	0:9b334a45a8ff	1970	*/
bogdanm	0:9b334a45a8ff	1971
bogdanm	0:9b334a45a8ff	1972	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1973	}
bogdanm	0:9b334a45a8ff	1974	#endif
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	#endif /* __STM32L4xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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