mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Base Start
bogdanm	0:9b334a45a8ff	12	* + Time Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Time Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Time Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Time Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Time Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Time Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Time Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Time Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Time Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Time Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Time Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Time One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Time One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Time One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Time Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Time Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Time Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Time Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Commutation Event configuration with Interruption and DMA
bogdanm	0:9b334a45a8ff	32	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	33	* + Time External Clock configuration
bogdanm	0:9b334a45a8ff	34	@verbatim
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	37	==============================================================================
bogdanm	0:9b334a45a8ff	38	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	39	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm	0:9b334a45a8ff	41	counter clock frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	42	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	43	(++) Input Capture
bogdanm	0:9b334a45a8ff	44	(++) Output Compare
bogdanm	0:9b334a45a8ff	45	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	46	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	49	==============================================================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	52	depending on the selected feature:
bogdanm	0:9b334a45a8ff	53	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	54	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	55	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	61	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	62	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	63	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	64	__HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	68	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	70	any start function.
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	73	Initialization function of this driver:
bogdanm	0:9b334a45a8ff	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	76	Output Compare signal.
bogdanm	0:9b334a45a8ff	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	78	PWM signal.
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	80	external signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm	0:9b334a45a8ff	82	in One Pulse Mode.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm	0:9b334a45a8ff	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm	0:9b334a45a8ff	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm	0:9b334a45a8ff	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm	0:9b334a45a8ff	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm	0:9b334a45a8ff	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm	0:9b334a45a8ff	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	94	HAL_TIM_DMABurst_WriteStart()
bogdanm	0:9b334a45a8ff	95	HAL_TIM_DMABurst_ReadStart()
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
bogdanm	0:9b334a45a8ff	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIM TIM
bogdanm	0:9b334a45a8ff	136	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	145	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	147	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	148	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	149	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	150	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	151	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	152	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	153	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	154	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	155	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
bogdanm	0:9b334a45a8ff	156	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	157	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	158	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	159	TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm	0:9b334a45a8ff	160	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	163	* @{
bogdanm	0:9b334a45a8ff	164	*/
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	167	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	168	*
bogdanm	0:9b334a45a8ff	169	@verbatim
bogdanm	0:9b334a45a8ff	170	==============================================================================
bogdanm	0:9b334a45a8ff	171	##### Time Base functions #####
bogdanm	0:9b334a45a8ff	172	==============================================================================
bogdanm	0:9b334a45a8ff	173	[..]
bogdanm	0:9b334a45a8ff	174	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	175	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	176	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	177	(+) Start the Time Base.
bogdanm	0:9b334a45a8ff	178	(+) Stop the Time Base.
bogdanm	0:9b334a45a8ff	179	(+) Start the Time Base and enable interrupt.
bogdanm	0:9b334a45a8ff	180	(+) Stop the Time Base and disable interrupt.
bogdanm	0:9b334a45a8ff	181	(+) Start the Time Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	182	(+) Stop the Time Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	@endverbatim
bogdanm	0:9b334a45a8ff	185	* @{
bogdanm	0:9b334a45a8ff	186	*/
bogdanm	0:9b334a45a8ff	187	/**
bogdanm	0:9b334a45a8ff	188	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	189	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	190	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	191	* @retval HAL status
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	194	{
bogdanm	0:9b334a45a8ff	195	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	196	if(htim == NULL)
bogdanm	0:9b334a45a8ff	197	{
bogdanm	0:9b334a45a8ff	198	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	199	}
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/* Check the parameters */
bogdanm	0:9b334a45a8ff	202	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	203	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	204	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	207	{
bogdanm	0:9b334a45a8ff	208	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	209	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	212	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	213	}
bogdanm	0:9b334a45a8ff	214
bogdanm	0:9b334a45a8ff	215	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	216	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	219	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	222	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	return HAL_OK;
bogdanm	0:9b334a45a8ff	225	}
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/**
bogdanm	0:9b334a45a8ff	228	* @brief DeInitialize the TIM Base peripheral
bogdanm	0:9b334a45a8ff	229	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	230	* @retval HAL status
bogdanm	0:9b334a45a8ff	231	*/
bogdanm	0:9b334a45a8ff	232	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	233	{
bogdanm	0:9b334a45a8ff	234	/* Check the parameters */
bogdanm	0:9b334a45a8ff	235	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	240	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	243	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/* Change TIM state */
bogdanm	0:9b334a45a8ff	246	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/* Release Lock */
bogdanm	0:9b334a45a8ff	249	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	return HAL_OK;
bogdanm	0:9b334a45a8ff	252	}
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/**
bogdanm	0:9b334a45a8ff	255	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	256	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	257	* @retval None
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	260	{
bogdanm	0:9b334a45a8ff	261	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	262	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264	}
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	/**
bogdanm	0:9b334a45a8ff	267	* @brief DeInitialize TIM Base MSP.
bogdanm	0:9b334a45a8ff	268	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	269	* @retval None
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	272	{
bogdanm	0:9b334a45a8ff	273	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	274	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276	}
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/**
bogdanm	0:9b334a45a8ff	280	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	281	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	282	* @retval HAL status
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	285	{
bogdanm	0:9b334a45a8ff	286	/* Check the parameters */
bogdanm	0:9b334a45a8ff	287	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	290	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	293	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	296	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/* Return function status */
bogdanm	0:9b334a45a8ff	299	return HAL_OK;
bogdanm	0:9b334a45a8ff	300	}
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	304	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	305	* @retval HAL status
bogdanm	0:9b334a45a8ff	306	*/
bogdanm	0:9b334a45a8ff	307	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	308	{
bogdanm	0:9b334a45a8ff	309	/* Check the parameters */
bogdanm	0:9b334a45a8ff	310	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	313	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	316	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	319	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Return function status */
bogdanm	0:9b334a45a8ff	322	return HAL_OK;
bogdanm	0:9b334a45a8ff	323	}
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	327	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	328	* @retval HAL status
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	331	{
bogdanm	0:9b334a45a8ff	332	/* Check the parameters */
bogdanm	0:9b334a45a8ff	333	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	336	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	339	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	/* Return function status */
bogdanm	0:9b334a45a8ff	342	return HAL_OK;
bogdanm	0:9b334a45a8ff	343	}
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	347	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	348	* @retval HAL status
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	/* Check the parameters */
bogdanm	0:9b334a45a8ff	353	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	354	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	355	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	358	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/* Return function status */
bogdanm	0:9b334a45a8ff	361	return HAL_OK;
bogdanm	0:9b334a45a8ff	362	}
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	366	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	367	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	368	* @param Length: The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	369	* @retval HAL status
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	/* Check the parameters */
bogdanm	0:9b334a45a8ff	374	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	377	{
bogdanm	0:9b334a45a8ff	378	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	379	}
bogdanm	0:9b334a45a8ff	380	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	381	{
bogdanm	0:9b334a45a8ff	382	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	383	{
bogdanm	0:9b334a45a8ff	384	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386	else
bogdanm	0:9b334a45a8ff	387	{
bogdanm	0:9b334a45a8ff	388	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	389	}
bogdanm	0:9b334a45a8ff	390	}
bogdanm	0:9b334a45a8ff	391	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	392	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	395	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	398	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	401	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	404	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/* Return function status */
bogdanm	0:9b334a45a8ff	407	return HAL_OK;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/**
bogdanm	0:9b334a45a8ff	411	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	412	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	413	* @retval HAL status
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	416	{
bogdanm	0:9b334a45a8ff	417	/* Check the parameters */
bogdanm	0:9b334a45a8ff	418	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	421	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	424	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/* Change the htim state */
bogdanm	0:9b334a45a8ff	427	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/* Return function status */
bogdanm	0:9b334a45a8ff	430	return HAL_OK;
bogdanm	0:9b334a45a8ff	431	}
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/**
bogdanm	0:9b334a45a8ff	434	* @}
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	438	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	439	*
bogdanm	0:9b334a45a8ff	440	@verbatim
bogdanm	0:9b334a45a8ff	441	==============================================================================
bogdanm	0:9b334a45a8ff	442	##### Time Output Compare functions #####
bogdanm	0:9b334a45a8ff	443	==============================================================================
bogdanm	0:9b334a45a8ff	444	[..]
bogdanm	0:9b334a45a8ff	445	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	446	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	447	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	448	(+) Start the Time Output Compare.
bogdanm	0:9b334a45a8ff	449	(+) Stop the Time Output Compare.
bogdanm	0:9b334a45a8ff	450	(+) Start the Time Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	451	(+) Stop the Time Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	452	(+) Start the Time Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	453	(+) Stop the Time Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	@endverbatim
bogdanm	0:9b334a45a8ff	456	* @{
bogdanm	0:9b334a45a8ff	457	*/
bogdanm	0:9b334a45a8ff	458	/**
bogdanm	0:9b334a45a8ff	459	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	460	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	461	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	462	* @retval HAL status
bogdanm	0:9b334a45a8ff	463	*/
bogdanm	0:9b334a45a8ff	464	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	467	if(htim == NULL)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	470	}
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/* Check the parameters */
bogdanm	0:9b334a45a8ff	473	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	474	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	475	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	478	{
bogdanm	0:9b334a45a8ff	479	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	480	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	481
bogdanm	0:9b334a45a8ff	482	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	483	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	487	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	490	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	493	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	return HAL_OK;
bogdanm	0:9b334a45a8ff	496	}
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	/**
bogdanm	0:9b334a45a8ff	499	* @brief DeInitialize the TIM peripheral
bogdanm	0:9b334a45a8ff	500	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	501	* @retval HAL status
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	504	{
bogdanm	0:9b334a45a8ff	505	/* Check the parameters */
bogdanm	0:9b334a45a8ff	506	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	511	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	514	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/* Change TIM state */
bogdanm	0:9b334a45a8ff	517	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/* Release Lock */
bogdanm	0:9b334a45a8ff	520	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	return HAL_OK;
bogdanm	0:9b334a45a8ff	523	}
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/**
bogdanm	0:9b334a45a8ff	526	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	527	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	528	* @retval None
bogdanm	0:9b334a45a8ff	529	*/
bogdanm	0:9b334a45a8ff	530	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	533	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	534	*/
bogdanm	0:9b334a45a8ff	535	}
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/**
bogdanm	0:9b334a45a8ff	538	* @brief DeInitialize TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	539	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	540	* @retval None
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	543	{
bogdanm	0:9b334a45a8ff	544	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	545	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	546	*/
bogdanm	0:9b334a45a8ff	547	}
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	/**
bogdanm	0:9b334a45a8ff	550	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	551	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	552	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	553	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	554	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	555	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	556	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	557	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	558	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	559	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	560	* @retval HAL status
bogdanm	0:9b334a45a8ff	561	*/
bogdanm	0:9b334a45a8ff	562	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	563	{
bogdanm	0:9b334a45a8ff	564	/* Check the parameters */
bogdanm	0:9b334a45a8ff	565	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	568	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	571	{
bogdanm	0:9b334a45a8ff	572	/* Enable the main output */
bogdanm	0:9b334a45a8ff	573	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	574	}
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	577	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/* Return function status */
bogdanm	0:9b334a45a8ff	580	return HAL_OK;
bogdanm	0:9b334a45a8ff	581	}
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/**
bogdanm	0:9b334a45a8ff	584	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	585	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	586	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	587	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	588	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	589	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	590	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	591	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	592	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	593	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	594	* @retval HAL status
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	597	{
bogdanm	0:9b334a45a8ff	598	/* Check the parameters */
bogdanm	0:9b334a45a8ff	599	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	602	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	605	{
bogdanm	0:9b334a45a8ff	606	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	607	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	608	}
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	611	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	/* Return function status */
bogdanm	0:9b334a45a8ff	614	return HAL_OK;
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/**
bogdanm	0:9b334a45a8ff	618	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	619	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	620	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	621	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	622	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	623	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	624	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	625	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	626	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	627	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	628	* @retval HAL status
bogdanm	0:9b334a45a8ff	629	*/
bogdanm	0:9b334a45a8ff	630	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	/* Check the parameters */
bogdanm	0:9b334a45a8ff	633	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	switch (Channel)
bogdanm	0:9b334a45a8ff	636	{
bogdanm	0:9b334a45a8ff	637	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	640	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	break;
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	645	{
bogdanm	0:9b334a45a8ff	646	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	647	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649	break;
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	652	{
bogdanm	0:9b334a45a8ff	653	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	654	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	655	}
bogdanm	0:9b334a45a8ff	656	break;
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	659	{
bogdanm	0:9b334a45a8ff	660	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	661	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663	break;
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	default:
bogdanm	0:9b334a45a8ff	666	break;
bogdanm	0:9b334a45a8ff	667	}
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	670	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	/* Enable the main output */
bogdanm	0:9b334a45a8ff	675	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	679	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/* Return function status */
bogdanm	0:9b334a45a8ff	682	return HAL_OK;
bogdanm	0:9b334a45a8ff	683	}
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	/**
bogdanm	0:9b334a45a8ff	686	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	687	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	688	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	689	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	690	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	691	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	692	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	693	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	694	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	695	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	696	* @retval HAL status
bogdanm	0:9b334a45a8ff	697	*/
bogdanm	0:9b334a45a8ff	698	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	699	{
bogdanm	0:9b334a45a8ff	700	/* Check the parameters */
bogdanm	0:9b334a45a8ff	701	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	switch (Channel)
bogdanm	0:9b334a45a8ff	704	{
bogdanm	0:9b334a45a8ff	705	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	706	{
bogdanm	0:9b334a45a8ff	707	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	708	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	709	}
bogdanm	0:9b334a45a8ff	710	break;
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	713	{
bogdanm	0:9b334a45a8ff	714	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717	break;
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	720	{
bogdanm	0:9b334a45a8ff	721	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724	break;
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	727	{
bogdanm	0:9b334a45a8ff	728	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	730	}
bogdanm	0:9b334a45a8ff	731	break;
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	default:
bogdanm	0:9b334a45a8ff	734	break;
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	738	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	743	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	744	}
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	747	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/* Return function status */
bogdanm	0:9b334a45a8ff	750	return HAL_OK;
bogdanm	0:9b334a45a8ff	751	}
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/**
bogdanm	0:9b334a45a8ff	754	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	755	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	756	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	757	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	758	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	759	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	760	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	761	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	762	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	763	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	764	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	765	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	766	* @retval HAL status
bogdanm	0:9b334a45a8ff	767	*/
bogdanm	0:9b334a45a8ff	768	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	769	{
bogdanm	0:9b334a45a8ff	770	/* Check the parameters */
bogdanm	0:9b334a45a8ff	771	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	774	{
bogdanm	0:9b334a45a8ff	775	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	776	}
bogdanm	0:9b334a45a8ff	777	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	778	{
bogdanm	0:9b334a45a8ff	779	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783	else
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	switch (Channel)
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	791	{
bogdanm	0:9b334a45a8ff	792	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	793	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	796	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	799	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	800
bogdanm	0:9b334a45a8ff	801	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	802	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	803	}
bogdanm	0:9b334a45a8ff	804	break;
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	809	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	812	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	815	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	818	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	819	}
bogdanm	0:9b334a45a8ff	820	break;
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	823	{
bogdanm	0:9b334a45a8ff	824	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	825	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	828	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	831	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	834	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836	break;
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	839	{
bogdanm	0:9b334a45a8ff	840	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	841	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	844	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	847	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	850	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	851	}
bogdanm	0:9b334a45a8ff	852	break;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	default:
bogdanm	0:9b334a45a8ff	855	break;
bogdanm	0:9b334a45a8ff	856	}
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	859	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	862	{
bogdanm	0:9b334a45a8ff	863	/* Enable the main output */
bogdanm	0:9b334a45a8ff	864	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	865	}
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	868	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/* Return function status */
bogdanm	0:9b334a45a8ff	871	return HAL_OK;
bogdanm	0:9b334a45a8ff	872	}
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/**
bogdanm	0:9b334a45a8ff	875	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	876	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	877	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	878	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	879	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	880	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	881	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	882	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	883	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	884	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	885	* @retval HAL status
bogdanm	0:9b334a45a8ff	886	*/
bogdanm	0:9b334a45a8ff	887	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	888	{
bogdanm	0:9b334a45a8ff	889	/* Check the parameters */
bogdanm	0:9b334a45a8ff	890	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	switch (Channel)
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	895	{
bogdanm	0:9b334a45a8ff	896	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	897	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899	break;
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	902	{
bogdanm	0:9b334a45a8ff	903	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	904	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	905	}
bogdanm	0:9b334a45a8ff	906	break;
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	909	{
bogdanm	0:9b334a45a8ff	910	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	911	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	912	}
bogdanm	0:9b334a45a8ff	913	break;
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	916	{
bogdanm	0:9b334a45a8ff	917	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	918	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920	break;
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	default:
bogdanm	0:9b334a45a8ff	923	break;
bogdanm	0:9b334a45a8ff	924	}
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	927	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	932	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	936	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Change the htim state */
bogdanm	0:9b334a45a8ff	939	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	/* Return function status */
bogdanm	0:9b334a45a8ff	942	return HAL_OK;
bogdanm	0:9b334a45a8ff	943	}
bogdanm	0:9b334a45a8ff	944
bogdanm	0:9b334a45a8ff	945	/**
bogdanm	0:9b334a45a8ff	946	* @}
bogdanm	0:9b334a45a8ff	947	*/
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	950	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	951	*
bogdanm	0:9b334a45a8ff	952	@verbatim
bogdanm	0:9b334a45a8ff	953	==============================================================================
bogdanm	0:9b334a45a8ff	954	##### Time PWM functions #####
bogdanm	0:9b334a45a8ff	955	==============================================================================
bogdanm	0:9b334a45a8ff	956	[..]
bogdanm	0:9b334a45a8ff	957	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	958	(+) Initialize and configure the TIM OPWM.
bogdanm	0:9b334a45a8ff	959	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	960	(+) Start the Time PWM.
bogdanm	0:9b334a45a8ff	961	(+) Stop the Time PWM.
bogdanm	0:9b334a45a8ff	962	(+) Start the Time PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	963	(+) Stop the Time PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	964	(+) Start the Time PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	965	(+) Stop the Time PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	@endverbatim
bogdanm	0:9b334a45a8ff	968	* @{
bogdanm	0:9b334a45a8ff	969	*/
bogdanm	0:9b334a45a8ff	970	/**
bogdanm	0:9b334a45a8ff	971	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	972	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	973	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	974	* @retval HAL status
bogdanm	0:9b334a45a8ff	975	*/
bogdanm	0:9b334a45a8ff	976	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	977	{
bogdanm	0:9b334a45a8ff	978	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	979	if(htim == NULL)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	982	}
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	/* Check the parameters */
bogdanm	0:9b334a45a8ff	985	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	986	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	987	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	990	{
bogdanm	0:9b334a45a8ff	991	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	992	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	995	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	996	}
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	999	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	1002	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1005	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	return HAL_OK;
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/**
bogdanm	0:9b334a45a8ff	1011	* @brief DeInitialize the TIM peripheral
bogdanm	0:9b334a45a8ff	1012	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1013	* @retval HAL status
bogdanm	0:9b334a45a8ff	1014	*/
bogdanm	0:9b334a45a8ff	1015	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1016	{
bogdanm	0:9b334a45a8ff	1017	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1018	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1023	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1026	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1029	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/* Release Lock */
bogdanm	0:9b334a45a8ff	1032	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	return HAL_OK;
bogdanm	0:9b334a45a8ff	1035	}
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/**
bogdanm	0:9b334a45a8ff	1038	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1039	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1040	* @retval None
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1045	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1046	*/
bogdanm	0:9b334a45a8ff	1047	}
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/**
bogdanm	0:9b334a45a8ff	1050	* @brief DeInitialize TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1051	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1052	* @retval None
bogdanm	0:9b334a45a8ff	1053	*/
bogdanm	0:9b334a45a8ff	1054	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1055	{
bogdanm	0:9b334a45a8ff	1056	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1057	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	}
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/**
bogdanm	0:9b334a45a8ff	1062	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1063	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1064	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1065	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1066	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1067	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1068	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1069	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1070	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	1071	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	1072	* @retval HAL status
bogdanm	0:9b334a45a8ff	1073	*/
bogdanm	0:9b334a45a8ff	1074	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1075	{
bogdanm	0:9b334a45a8ff	1076	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1077	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1080	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1083	{
bogdanm	0:9b334a45a8ff	1084	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1085	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1086	}
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1089	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Return function status */
bogdanm	0:9b334a45a8ff	1092	return HAL_OK;
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/**
bogdanm	0:9b334a45a8ff	1096	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1097	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1098	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1099	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1100	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1101	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1102	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1103	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1104	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	1105	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	1106	* @retval HAL status
bogdanm	0:9b334a45a8ff	1107	*/
bogdanm	0:9b334a45a8ff	1108	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1109	{
bogdanm	0:9b334a45a8ff	1110	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1111	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1114	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1117	{
bogdanm	0:9b334a45a8ff	1118	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1119	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1120	}
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1123	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1126	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/* Return function status */
bogdanm	0:9b334a45a8ff	1129	return HAL_OK;
bogdanm	0:9b334a45a8ff	1130	}
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/**
bogdanm	0:9b334a45a8ff	1133	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1134	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1135	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1136	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1137	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1138	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1139	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1140	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1141	* @retval HAL status
bogdanm	0:9b334a45a8ff	1142	*/
bogdanm	0:9b334a45a8ff	1143	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1144	{
bogdanm	0:9b334a45a8ff	1145	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1146	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	switch (Channel)
bogdanm	0:9b334a45a8ff	1149	{
bogdanm	0:9b334a45a8ff	1150	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1153	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1154	}
bogdanm	0:9b334a45a8ff	1155	break;
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1158	{
bogdanm	0:9b334a45a8ff	1159	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1161	}
bogdanm	0:9b334a45a8ff	1162	break;
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1165	{
bogdanm	0:9b334a45a8ff	1166	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1167	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169	break;
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1172	{
bogdanm	0:9b334a45a8ff	1173	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1174	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1175	}
bogdanm	0:9b334a45a8ff	1176	break;
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	default:
bogdanm	0:9b334a45a8ff	1179	break;
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1183	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1186	{
bogdanm	0:9b334a45a8ff	1187	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1188	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1189	}
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1192	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/* Return function status */
bogdanm	0:9b334a45a8ff	1195	return HAL_OK;
bogdanm	0:9b334a45a8ff	1196	}
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/**
bogdanm	0:9b334a45a8ff	1199	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1200	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1201	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1202	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1203	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1204	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1205	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1206	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1207	* @retval HAL status
bogdanm	0:9b334a45a8ff	1208	*/
bogdanm	0:9b334a45a8ff	1209	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1210	{
bogdanm	0:9b334a45a8ff	1211	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1212	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	switch (Channel)
bogdanm	0:9b334a45a8ff	1215	{
bogdanm	0:9b334a45a8ff	1216	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1217	{
bogdanm	0:9b334a45a8ff	1218	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1219	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221	break;
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1224	{
bogdanm	0:9b334a45a8ff	1225	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1226	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1227	}
bogdanm	0:9b334a45a8ff	1228	break;
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1231	{
bogdanm	0:9b334a45a8ff	1232	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1233	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1234	}
bogdanm	0:9b334a45a8ff	1235	break;
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1238	{
bogdanm	0:9b334a45a8ff	1239	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1240	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1241	}
bogdanm	0:9b334a45a8ff	1242	break;
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	default:
bogdanm	0:9b334a45a8ff	1245	break;
bogdanm	0:9b334a45a8ff	1246	}
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1249	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1252	{
bogdanm	0:9b334a45a8ff	1253	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1254	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1255	}
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1258	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/* Return function status */
bogdanm	0:9b334a45a8ff	1261	return HAL_OK;
bogdanm	0:9b334a45a8ff	1262	}
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/**
bogdanm	0:9b334a45a8ff	1265	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1266	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1267	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1268	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1269	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1270	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1271	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1272	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1273	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	1274	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1275	* @retval HAL status
bogdanm	0:9b334a45a8ff	1276	*/
bogdanm	0:9b334a45a8ff	1277	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1278	{
bogdanm	0:9b334a45a8ff	1279	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1280	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1289	{
bogdanm	0:9b334a45a8ff	1290	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1291	}
bogdanm	0:9b334a45a8ff	1292	else
bogdanm	0:9b334a45a8ff	1293	{
bogdanm	0:9b334a45a8ff	1294	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1295	}
bogdanm	0:9b334a45a8ff	1296	}
bogdanm	0:9b334a45a8ff	1297	switch (Channel)
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1300	{
bogdanm	0:9b334a45a8ff	1301	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1302	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1305	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1308	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1311	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1312	}
bogdanm	0:9b334a45a8ff	1313	break;
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1316	{
bogdanm	0:9b334a45a8ff	1317	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1318	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1321	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1324	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1327	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1328	}
bogdanm	0:9b334a45a8ff	1329	break;
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1332	{
bogdanm	0:9b334a45a8ff	1333	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1334	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1337	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1340	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1343	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1344	}
bogdanm	0:9b334a45a8ff	1345	break;
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1350	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1353	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1356	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1359	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1360	}
bogdanm	0:9b334a45a8ff	1361	break;
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	default:
bogdanm	0:9b334a45a8ff	1364	break;
bogdanm	0:9b334a45a8ff	1365	}
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1368	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1371	{
bogdanm	0:9b334a45a8ff	1372	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1373	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1377	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	/* Return function status */
bogdanm	0:9b334a45a8ff	1380	return HAL_OK;
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/**
bogdanm	0:9b334a45a8ff	1384	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1385	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1386	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1387	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1388	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1389	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1390	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1391	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1392	* @retval HAL status
bogdanm	0:9b334a45a8ff	1393	*/
bogdanm	0:9b334a45a8ff	1394	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1395	{
bogdanm	0:9b334a45a8ff	1396	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1397	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	switch (Channel)
bogdanm	0:9b334a45a8ff	1400	{
bogdanm	0:9b334a45a8ff	1401	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1402	{
bogdanm	0:9b334a45a8ff	1403	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1404	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1405	}
bogdanm	0:9b334a45a8ff	1406	break;
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1409	{
bogdanm	0:9b334a45a8ff	1410	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1411	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1412	}
bogdanm	0:9b334a45a8ff	1413	break;
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1416	{
bogdanm	0:9b334a45a8ff	1417	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1418	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420	break;
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1423	{
bogdanm	0:9b334a45a8ff	1424	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1425	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1426	}
bogdanm	0:9b334a45a8ff	1427	break;
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	default:
bogdanm	0:9b334a45a8ff	1430	break;
bogdanm	0:9b334a45a8ff	1431	}
bogdanm	0:9b334a45a8ff	1432
bogdanm	0:9b334a45a8ff	1433	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1434	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1437	{
bogdanm	0:9b334a45a8ff	1438	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1439	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1440	}
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1443	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1446	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	/* Return function status */
bogdanm	0:9b334a45a8ff	1449	return HAL_OK;
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/**
bogdanm	0:9b334a45a8ff	1453	* @}
bogdanm	0:9b334a45a8ff	1454	*/
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1457	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1458	*
bogdanm	0:9b334a45a8ff	1459	@verbatim
bogdanm	0:9b334a45a8ff	1460	==============================================================================
bogdanm	0:9b334a45a8ff	1461	##### Time Input Capture functions #####
bogdanm	0:9b334a45a8ff	1462	==============================================================================
bogdanm	0:9b334a45a8ff	1463	[..]
bogdanm	0:9b334a45a8ff	1464	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1465	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1466	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1467	(+) Start the Time Input Capture.
bogdanm	0:9b334a45a8ff	1468	(+) Stop the Time Input Capture.
bogdanm	0:9b334a45a8ff	1469	(+) Start the Time Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1470	(+) Stop the Time Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1471	(+) Start the Time Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1472	(+) Stop the Time Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1473
bogdanm	0:9b334a45a8ff	1474	@endverbatim
bogdanm	0:9b334a45a8ff	1475	* @{
bogdanm	0:9b334a45a8ff	1476	*/
bogdanm	0:9b334a45a8ff	1477	/**
bogdanm	0:9b334a45a8ff	1478	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1479	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	1480	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1481	* @retval HAL status
bogdanm	0:9b334a45a8ff	1482	*/
bogdanm	0:9b334a45a8ff	1483	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1484	{
bogdanm	0:9b334a45a8ff	1485	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1486	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1487	{
bogdanm	0:9b334a45a8ff	1488	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1489	}
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1492	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1493	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1494	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1499	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1502	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1503	}
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1506	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1509	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1512	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	return HAL_OK;
bogdanm	0:9b334a45a8ff	1515	}
bogdanm	0:9b334a45a8ff	1516
bogdanm	0:9b334a45a8ff	1517	/**
bogdanm	0:9b334a45a8ff	1518	* @brief DeInitialize the TIM peripheral
bogdanm	0:9b334a45a8ff	1519	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1520	* @retval HAL status
bogdanm	0:9b334a45a8ff	1521	*/
bogdanm	0:9b334a45a8ff	1522	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1523	{
bogdanm	0:9b334a45a8ff	1524	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1525	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1530	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1533	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1536	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Release Lock */
bogdanm	0:9b334a45a8ff	1539	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	return HAL_OK;
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/**
bogdanm	0:9b334a45a8ff	1545	* @brief Initializes the TIM INput Capture MSP.
bogdanm	0:9b334a45a8ff	1546	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1547	* @retval None
bogdanm	0:9b334a45a8ff	1548	*/
bogdanm	0:9b334a45a8ff	1549	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1550	{
bogdanm	0:9b334a45a8ff	1551	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1552	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1553	*/
bogdanm	0:9b334a45a8ff	1554	}
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/**
bogdanm	0:9b334a45a8ff	1557	* @brief DeInitialize TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1558	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1559	* @retval None
bogdanm	0:9b334a45a8ff	1560	*/
bogdanm	0:9b334a45a8ff	1561	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1562	{
bogdanm	0:9b334a45a8ff	1563	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1564	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1565	*/
bogdanm	0:9b334a45a8ff	1566	}
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	/**
bogdanm	0:9b334a45a8ff	1569	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1570	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1571	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1572	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1573	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1574	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1575	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1576	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1577	* @retval HAL status
bogdanm	0:9b334a45a8ff	1578	*/
bogdanm	0:9b334a45a8ff	1579	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1580	{
bogdanm	0:9b334a45a8ff	1581	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1582	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1583
bogdanm	0:9b334a45a8ff	1584	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1585	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1588	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/* Return function status */
bogdanm	0:9b334a45a8ff	1591	return HAL_OK;
bogdanm	0:9b334a45a8ff	1592	}
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/**
bogdanm	0:9b334a45a8ff	1595	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1596	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1597	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1598	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1599	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1600	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1601	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1602	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1603	* @retval HAL status
bogdanm	0:9b334a45a8ff	1604	*/
bogdanm	0:9b334a45a8ff	1605	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1606	{
bogdanm	0:9b334a45a8ff	1607	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1608	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1611	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1614	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/* Return function status */
bogdanm	0:9b334a45a8ff	1617	return HAL_OK;
bogdanm	0:9b334a45a8ff	1618	}
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	/**
bogdanm	0:9b334a45a8ff	1621	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1622	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1623	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1624	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1625	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1626	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1627	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1628	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1629	* @retval HAL status
bogdanm	0:9b334a45a8ff	1630	*/
bogdanm	0:9b334a45a8ff	1631	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1632	{
bogdanm	0:9b334a45a8ff	1633	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1634	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	switch (Channel)
bogdanm	0:9b334a45a8ff	1637	{
bogdanm	0:9b334a45a8ff	1638	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1639	{
bogdanm	0:9b334a45a8ff	1640	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1641	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1642	}
bogdanm	0:9b334a45a8ff	1643	break;
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1646	{
bogdanm	0:9b334a45a8ff	1647	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1648	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1649	}
bogdanm	0:9b334a45a8ff	1650	break;
bogdanm	0:9b334a45a8ff	1651
bogdanm	0:9b334a45a8ff	1652	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1653	{
bogdanm	0:9b334a45a8ff	1654	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1656	}
bogdanm	0:9b334a45a8ff	1657	break;
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1660	{
bogdanm	0:9b334a45a8ff	1661	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1663	}
bogdanm	0:9b334a45a8ff	1664	break;
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	default:
bogdanm	0:9b334a45a8ff	1667	break;
bogdanm	0:9b334a45a8ff	1668	}
bogdanm	0:9b334a45a8ff	1669	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1670	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1673	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	/* Return function status */
bogdanm	0:9b334a45a8ff	1676	return HAL_OK;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	/**
bogdanm	0:9b334a45a8ff	1680	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1681	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1682	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1683	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1684	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1685	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1686	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1687	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1688	* @retval HAL status
bogdanm	0:9b334a45a8ff	1689	*/
bogdanm	0:9b334a45a8ff	1690	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1691	{
bogdanm	0:9b334a45a8ff	1692	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1693	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1694
bogdanm	0:9b334a45a8ff	1695	switch (Channel)
bogdanm	0:9b334a45a8ff	1696	{
bogdanm	0:9b334a45a8ff	1697	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1698	{
bogdanm	0:9b334a45a8ff	1699	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1700	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702	break;
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1707	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709	break;
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1712	{
bogdanm	0:9b334a45a8ff	1713	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1714	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1715	}
bogdanm	0:9b334a45a8ff	1716	break;
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1719	{
bogdanm	0:9b334a45a8ff	1720	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1721	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1722	}
bogdanm	0:9b334a45a8ff	1723	break;
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	default:
bogdanm	0:9b334a45a8ff	1726	break;
bogdanm	0:9b334a45a8ff	1727	}
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1730	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1731
bogdanm	0:9b334a45a8ff	1732	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1733	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	/* Return function status */
bogdanm	0:9b334a45a8ff	1736	return HAL_OK;
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738
bogdanm	0:9b334a45a8ff	1739	/**
bogdanm	0:9b334a45a8ff	1740	* @brief Starts the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1741	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1742	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1743	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1744	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1745	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1746	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1747	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1748	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1749	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1750	* @retval HAL status
bogdanm	0:9b334a45a8ff	1751	*/
bogdanm	0:9b334a45a8ff	1752	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1753	{
bogdanm	0:9b334a45a8ff	1754	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1755	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1756	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1757
bogdanm	0:9b334a45a8ff	1758	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1759	{
bogdanm	0:9b334a45a8ff	1760	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1761	}
bogdanm	0:9b334a45a8ff	1762	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1763	{
bogdanm	0:9b334a45a8ff	1764	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1767	}
bogdanm	0:9b334a45a8ff	1768	else
bogdanm	0:9b334a45a8ff	1769	{
bogdanm	0:9b334a45a8ff	1770	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1771	}
bogdanm	0:9b334a45a8ff	1772	}
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	switch (Channel)
bogdanm	0:9b334a45a8ff	1775	{
bogdanm	0:9b334a45a8ff	1776	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1779	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1782	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1783
bogdanm	0:9b334a45a8ff	1784	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1785	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1788	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1789	}
bogdanm	0:9b334a45a8ff	1790	break;
bogdanm	0:9b334a45a8ff	1791
bogdanm	0:9b334a45a8ff	1792	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1795	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1798	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1799
bogdanm	0:9b334a45a8ff	1800	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1801	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1804	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1805	}
bogdanm	0:9b334a45a8ff	1806	break;
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1809	{
bogdanm	0:9b334a45a8ff	1810	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1811	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1814	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1817	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1818
bogdanm	0:9b334a45a8ff	1819	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1820	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1821	}
bogdanm	0:9b334a45a8ff	1822	break;
bogdanm	0:9b334a45a8ff	1823
bogdanm	0:9b334a45a8ff	1824	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1825	{
bogdanm	0:9b334a45a8ff	1826	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1827	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1828
bogdanm	0:9b334a45a8ff	1829	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1830	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1833	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1836	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1837	}
bogdanm	0:9b334a45a8ff	1838	break;
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	default:
bogdanm	0:9b334a45a8ff	1841	break;
bogdanm	0:9b334a45a8ff	1842	}
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1845	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1848	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	/* Return function status */
bogdanm	0:9b334a45a8ff	1851	return HAL_OK;
bogdanm	0:9b334a45a8ff	1852	}
bogdanm	0:9b334a45a8ff	1853
bogdanm	0:9b334a45a8ff	1854	/**
bogdanm	0:9b334a45a8ff	1855	* @brief Stops the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1856	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1857	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1858	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1859	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1860	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1861	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1862	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1863	* @retval HAL status
bogdanm	0:9b334a45a8ff	1864	*/
bogdanm	0:9b334a45a8ff	1865	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1866	{
bogdanm	0:9b334a45a8ff	1867	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1868	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1869	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	switch (Channel)
bogdanm	0:9b334a45a8ff	1872	{
bogdanm	0:9b334a45a8ff	1873	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1874	{
bogdanm	0:9b334a45a8ff	1875	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1876	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1877	}
bogdanm	0:9b334a45a8ff	1878	break;
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1881	{
bogdanm	0:9b334a45a8ff	1882	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1883	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1884	}
bogdanm	0:9b334a45a8ff	1885	break;
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1888	{
bogdanm	0:9b334a45a8ff	1889	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1890	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1891	}
bogdanm	0:9b334a45a8ff	1892	break;
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1895	{
bogdanm	0:9b334a45a8ff	1896	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1897	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1898	}
bogdanm	0:9b334a45a8ff	1899	break;
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	default:
bogdanm	0:9b334a45a8ff	1902	break;
bogdanm	0:9b334a45a8ff	1903	}
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1906	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1909	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1912	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* Return function status */
bogdanm	0:9b334a45a8ff	1915	return HAL_OK;
bogdanm	0:9b334a45a8ff	1916	}
bogdanm	0:9b334a45a8ff	1917	/**
bogdanm	0:9b334a45a8ff	1918	* @}
bogdanm	0:9b334a45a8ff	1919	*/
bogdanm	0:9b334a45a8ff	1920
bogdanm	0:9b334a45a8ff	1921	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1922	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1923	*
bogdanm	0:9b334a45a8ff	1924	@verbatim
bogdanm	0:9b334a45a8ff	1925	==============================================================================
bogdanm	0:9b334a45a8ff	1926	##### Time One Pulse functions #####
bogdanm	0:9b334a45a8ff	1927	==============================================================================
bogdanm	0:9b334a45a8ff	1928	[..]
bogdanm	0:9b334a45a8ff	1929	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1930	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1931	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1932	(+) Start the Time One Pulse.
bogdanm	0:9b334a45a8ff	1933	(+) Stop the Time One Pulse.
bogdanm	0:9b334a45a8ff	1934	(+) Start the Time One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1935	(+) Stop the Time One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1936	(+) Start the Time One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1937	(+) Stop the Time One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1938
bogdanm	0:9b334a45a8ff	1939	@endverbatim
bogdanm	0:9b334a45a8ff	1940	* @{
bogdanm	0:9b334a45a8ff	1941	*/
bogdanm	0:9b334a45a8ff	1942	/**
bogdanm	0:9b334a45a8ff	1943	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1944	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	1945	* @param htim: TIM OnePulse handle
bogdanm	0:9b334a45a8ff	1946	* @param OnePulseMode: Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1947	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1948	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1949	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
bogdanm	0:9b334a45a8ff	1950	* @retval HAL status
bogdanm	0:9b334a45a8ff	1951	*/
bogdanm	0:9b334a45a8ff	1952	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	1953	{
bogdanm	0:9b334a45a8ff	1954	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1955	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1956	{
bogdanm	0:9b334a45a8ff	1957	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1958	}
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1961	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1962	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1963	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1964	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1967	{
bogdanm	0:9b334a45a8ff	1968	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1969	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1970
bogdanm	0:9b334a45a8ff	1971	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1972	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	1973	}
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1976	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	1979	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	1982	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	1985	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1988	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1989
bogdanm	0:9b334a45a8ff	1990	return HAL_OK;
bogdanm	0:9b334a45a8ff	1991	}
bogdanm	0:9b334a45a8ff	1992
bogdanm	0:9b334a45a8ff	1993	/**
bogdanm	0:9b334a45a8ff	1994	* @brief DeInitialize the TIM One Pulse
bogdanm	0:9b334a45a8ff	1995	* @param htim: TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1996	* @retval HAL status
bogdanm	0:9b334a45a8ff	1997	*/
bogdanm	0:9b334a45a8ff	1998	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1999	{
bogdanm	0:9b334a45a8ff	2000	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2001	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2002
bogdanm	0:9b334a45a8ff	2003	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2004
bogdanm	0:9b334a45a8ff	2005	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2006	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2007
bogdanm	0:9b334a45a8ff	2008	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2009	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2012	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	/* Release Lock */
bogdanm	0:9b334a45a8ff	2015	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2016
bogdanm	0:9b334a45a8ff	2017	return HAL_OK;
bogdanm	0:9b334a45a8ff	2018	}
bogdanm	0:9b334a45a8ff	2019
bogdanm	0:9b334a45a8ff	2020	/**
bogdanm	0:9b334a45a8ff	2021	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2022	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2023	* @retval None
bogdanm	0:9b334a45a8ff	2024	*/
bogdanm	0:9b334a45a8ff	2025	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2026	{
bogdanm	0:9b334a45a8ff	2027	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2028	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2029	*/
bogdanm	0:9b334a45a8ff	2030	}
bogdanm	0:9b334a45a8ff	2031
bogdanm	0:9b334a45a8ff	2032	/**
bogdanm	0:9b334a45a8ff	2033	* @brief DeInitialize TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2034	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2035	* @retval None
bogdanm	0:9b334a45a8ff	2036	*/
bogdanm	0:9b334a45a8ff	2037	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2038	{
bogdanm	0:9b334a45a8ff	2039	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2040	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2041	*/
bogdanm	0:9b334a45a8ff	2042	}
bogdanm	0:9b334a45a8ff	2043
bogdanm	0:9b334a45a8ff	2044	/**
bogdanm	0:9b334a45a8ff	2045	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2046	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2047	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2048	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2049	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2050	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2051	* @retval HAL status
bogdanm	0:9b334a45a8ff	2052	*/
bogdanm	0:9b334a45a8ff	2053	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2054	{
bogdanm	0:9b334a45a8ff	2055	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2056	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2057	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2058	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2059	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2062	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2063
bogdanm	0:9b334a45a8ff	2064	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2065	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2066
bogdanm	0:9b334a45a8ff	2067	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2068	{
bogdanm	0:9b334a45a8ff	2069	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2070	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2071	}
bogdanm	0:9b334a45a8ff	2072
bogdanm	0:9b334a45a8ff	2073	/* Return function status */
bogdanm	0:9b334a45a8ff	2074	return HAL_OK;
bogdanm	0:9b334a45a8ff	2075	}
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	/**
bogdanm	0:9b334a45a8ff	2078	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2079	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2080	* @param OutputChannel : TIM Channels to be disable
bogdanm	0:9b334a45a8ff	2081	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2082	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2083	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2084	* @retval HAL status
bogdanm	0:9b334a45a8ff	2085	*/
bogdanm	0:9b334a45a8ff	2086	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2087	{
bogdanm	0:9b334a45a8ff	2088	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2089	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2090	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2091	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2092	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2095	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2096
bogdanm	0:9b334a45a8ff	2097	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2098	{
bogdanm	0:9b334a45a8ff	2099	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2100	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2101	}
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2104	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	/* Return function status */
bogdanm	0:9b334a45a8ff	2107	return HAL_OK;
bogdanm	0:9b334a45a8ff	2108	}
bogdanm	0:9b334a45a8ff	2109
bogdanm	0:9b334a45a8ff	2110	/**
bogdanm	0:9b334a45a8ff	2111	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2112	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2113	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2114	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2115	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2116	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2117	* @retval HAL status
bogdanm	0:9b334a45a8ff	2118	*/
bogdanm	0:9b334a45a8ff	2119	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2120	{
bogdanm	0:9b334a45a8ff	2121	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2122	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2123	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2124	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2125	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2126
bogdanm	0:9b334a45a8ff	2127	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2128	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2131	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2134	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2137	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2138
bogdanm	0:9b334a45a8ff	2139	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2140	{
bogdanm	0:9b334a45a8ff	2141	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2142	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2143	}
bogdanm	0:9b334a45a8ff	2144
bogdanm	0:9b334a45a8ff	2145	/* Return function status */
bogdanm	0:9b334a45a8ff	2146	return HAL_OK;
bogdanm	0:9b334a45a8ff	2147	}
bogdanm	0:9b334a45a8ff	2148
bogdanm	0:9b334a45a8ff	2149	/**
bogdanm	0:9b334a45a8ff	2150	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2151	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2152	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2153	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2154	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2155	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2156	* @retval HAL status
bogdanm	0:9b334a45a8ff	2157	*/
bogdanm	0:9b334a45a8ff	2158	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2159	{
bogdanm	0:9b334a45a8ff	2160	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2161	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2162
bogdanm	0:9b334a45a8ff	2163	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2164	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2167	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2168	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2169	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2170	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2171	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2172	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2173
bogdanm	0:9b334a45a8ff	2174	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2175	{
bogdanm	0:9b334a45a8ff	2176	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2177	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2178	}
bogdanm	0:9b334a45a8ff	2179
bogdanm	0:9b334a45a8ff	2180	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2181	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	/* Return function status */
bogdanm	0:9b334a45a8ff	2184	return HAL_OK;
bogdanm	0:9b334a45a8ff	2185	}
bogdanm	0:9b334a45a8ff	2186
bogdanm	0:9b334a45a8ff	2187	/**
bogdanm	0:9b334a45a8ff	2188	* @}
bogdanm	0:9b334a45a8ff	2189	*/
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	2192	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2193	*
bogdanm	0:9b334a45a8ff	2194	@verbatim
bogdanm	0:9b334a45a8ff	2195	==============================================================================
bogdanm	0:9b334a45a8ff	2196	##### Time Encoder functions #####
bogdanm	0:9b334a45a8ff	2197	==============================================================================
bogdanm	0:9b334a45a8ff	2198	[..]
bogdanm	0:9b334a45a8ff	2199	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2200	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2201	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2202	(+) Start the Time Encoder.
bogdanm	0:9b334a45a8ff	2203	(+) Stop the Time Encoder.
bogdanm	0:9b334a45a8ff	2204	(+) Start the Time Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2205	(+) Stop the Time Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2206	(+) Start the Time Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2207	(+) Stop the Time Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	@endverbatim
bogdanm	0:9b334a45a8ff	2210	* @{
bogdanm	0:9b334a45a8ff	2211	*/
bogdanm	0:9b334a45a8ff	2212	/**
bogdanm	0:9b334a45a8ff	2213	* @brief Initializes the TIM Encoder Interface and initialize the associated handle.
bogdanm	0:9b334a45a8ff	2214	* @param htim: TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2215	* @param sConfig: TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2216	* @retval HAL status
bogdanm	0:9b334a45a8ff	2217	*/
bogdanm	0:9b334a45a8ff	2218	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2219	{
bogdanm	0:9b334a45a8ff	2220	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2221	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2222	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2225	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2226	{
bogdanm	0:9b334a45a8ff	2227	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2228	}
bogdanm	0:9b334a45a8ff	2229
bogdanm	0:9b334a45a8ff	2230	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2231	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2232	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2233	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2234	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2235	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2236	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2237	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2238	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2239	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2240	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2241
bogdanm	0:9b334a45a8ff	2242	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2243	{
bogdanm	0:9b334a45a8ff	2244	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	2245	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2248	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2249	}
bogdanm	0:9b334a45a8ff	2250
bogdanm	0:9b334a45a8ff	2251	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2252	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2253
bogdanm	0:9b334a45a8ff	2254	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2255	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2256
bogdanm	0:9b334a45a8ff	2257	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2258	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2259
bogdanm	0:9b334a45a8ff	2260	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2261	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2262
bogdanm	0:9b334a45a8ff	2263	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2264	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2265
bogdanm	0:9b334a45a8ff	2266	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2267	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2268
bogdanm	0:9b334a45a8ff	2269	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2270	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2271
bogdanm	0:9b334a45a8ff	2272	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2273	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2274	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2275
bogdanm	0:9b334a45a8ff	2276	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2277	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2278	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2279	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2280	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2281
bogdanm	0:9b334a45a8ff	2282	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2283	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2284	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2285	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2286
bogdanm	0:9b334a45a8ff	2287	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2288	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2289
bogdanm	0:9b334a45a8ff	2290	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2291	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2294	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2295
bogdanm	0:9b334a45a8ff	2296	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2297	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299	return HAL_OK;
bogdanm	0:9b334a45a8ff	2300	}
bogdanm	0:9b334a45a8ff	2301
bogdanm	0:9b334a45a8ff	2302
bogdanm	0:9b334a45a8ff	2303	/**
bogdanm	0:9b334a45a8ff	2304	* @brief DeInitialize the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2305	* @param htim: TIM Encoder handle
bogdanm	0:9b334a45a8ff	2306	* @retval HAL status
bogdanm	0:9b334a45a8ff	2307	*/
bogdanm	0:9b334a45a8ff	2308	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2309	{
bogdanm	0:9b334a45a8ff	2310	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2311	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2312
bogdanm	0:9b334a45a8ff	2313	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2314
bogdanm	0:9b334a45a8ff	2315	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2316	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2319	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2322	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	/* Release Lock */
bogdanm	0:9b334a45a8ff	2325	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	return HAL_OK;
bogdanm	0:9b334a45a8ff	2328	}
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	/**
bogdanm	0:9b334a45a8ff	2331	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2332	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2333	* @retval None
bogdanm	0:9b334a45a8ff	2334	*/
bogdanm	0:9b334a45a8ff	2335	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2336	{
bogdanm	0:9b334a45a8ff	2337	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2338	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2339	*/
bogdanm	0:9b334a45a8ff	2340	}
bogdanm	0:9b334a45a8ff	2341
bogdanm	0:9b334a45a8ff	2342	/**
bogdanm	0:9b334a45a8ff	2343	* @brief DeInitialize TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2344	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2345	* @retval None
bogdanm	0:9b334a45a8ff	2346	*/
bogdanm	0:9b334a45a8ff	2347	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2348	{
bogdanm	0:9b334a45a8ff	2349	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2350	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2351	*/
bogdanm	0:9b334a45a8ff	2352	}
bogdanm	0:9b334a45a8ff	2353
bogdanm	0:9b334a45a8ff	2354	/**
bogdanm	0:9b334a45a8ff	2355	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2356	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2357	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2358	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2359	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2360	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2361	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2362	* @retval HAL status
bogdanm	0:9b334a45a8ff	2363	*/
bogdanm	0:9b334a45a8ff	2364	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2365	{
bogdanm	0:9b334a45a8ff	2366	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2367	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2368
bogdanm	0:9b334a45a8ff	2369	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2370	switch (Channel)
bogdanm	0:9b334a45a8ff	2371	{
bogdanm	0:9b334a45a8ff	2372	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2373	{
bogdanm	0:9b334a45a8ff	2374	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2375	break;
bogdanm	0:9b334a45a8ff	2376	}
bogdanm	0:9b334a45a8ff	2377	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2378	{
bogdanm	0:9b334a45a8ff	2379	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2380	break;
bogdanm	0:9b334a45a8ff	2381	}
bogdanm	0:9b334a45a8ff	2382	default :
bogdanm	0:9b334a45a8ff	2383	{
bogdanm	0:9b334a45a8ff	2384	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2385	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2386	break;
bogdanm	0:9b334a45a8ff	2387	}
bogdanm	0:9b334a45a8ff	2388	}
bogdanm	0:9b334a45a8ff	2389	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2390	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2391
bogdanm	0:9b334a45a8ff	2392	/* Return function status */
bogdanm	0:9b334a45a8ff	2393	return HAL_OK;
bogdanm	0:9b334a45a8ff	2394	}
bogdanm	0:9b334a45a8ff	2395
bogdanm	0:9b334a45a8ff	2396	/**
bogdanm	0:9b334a45a8ff	2397	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2398	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2399	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2400	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2401	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2402	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2403	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2404	* @retval HAL status
bogdanm	0:9b334a45a8ff	2405	*/
bogdanm	0:9b334a45a8ff	2406	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2407	{
bogdanm	0:9b334a45a8ff	2408	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2409	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2410
bogdanm	0:9b334a45a8ff	2411	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2412	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2413	switch (Channel)
bogdanm	0:9b334a45a8ff	2414	{
bogdanm	0:9b334a45a8ff	2415	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2416	{
bogdanm	0:9b334a45a8ff	2417	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2418	break;
bogdanm	0:9b334a45a8ff	2419	}
bogdanm	0:9b334a45a8ff	2420	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2421	{
bogdanm	0:9b334a45a8ff	2422	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2423	break;
bogdanm	0:9b334a45a8ff	2424	}
bogdanm	0:9b334a45a8ff	2425	default :
bogdanm	0:9b334a45a8ff	2426	{
bogdanm	0:9b334a45a8ff	2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2428	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2429	break;
bogdanm	0:9b334a45a8ff	2430	}
bogdanm	0:9b334a45a8ff	2431	}
bogdanm	0:9b334a45a8ff	2432
bogdanm	0:9b334a45a8ff	2433	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2434	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	/* Return function status */
bogdanm	0:9b334a45a8ff	2437	return HAL_OK;
bogdanm	0:9b334a45a8ff	2438	}
bogdanm	0:9b334a45a8ff	2439
bogdanm	0:9b334a45a8ff	2440	/**
bogdanm	0:9b334a45a8ff	2441	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2442	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2443	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2444	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2445	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2446	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2447	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2448	* @retval HAL status
bogdanm	0:9b334a45a8ff	2449	*/
bogdanm	0:9b334a45a8ff	2450	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2451	{
bogdanm	0:9b334a45a8ff	2452	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2453	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2454
bogdanm	0:9b334a45a8ff	2455	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2456	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2457	switch (Channel)
bogdanm	0:9b334a45a8ff	2458	{
bogdanm	0:9b334a45a8ff	2459	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2460	{
bogdanm	0:9b334a45a8ff	2461	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2462	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2463	break;
bogdanm	0:9b334a45a8ff	2464	}
bogdanm	0:9b334a45a8ff	2465	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2466	{
bogdanm	0:9b334a45a8ff	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2468	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2469	break;
bogdanm	0:9b334a45a8ff	2470	}
bogdanm	0:9b334a45a8ff	2471	default :
bogdanm	0:9b334a45a8ff	2472	{
bogdanm	0:9b334a45a8ff	2473	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2474	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2475	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2476	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2477	break;
bogdanm	0:9b334a45a8ff	2478	}
bogdanm	0:9b334a45a8ff	2479	}
bogdanm	0:9b334a45a8ff	2480
bogdanm	0:9b334a45a8ff	2481	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2482	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2483
bogdanm	0:9b334a45a8ff	2484	/* Return function status */
bogdanm	0:9b334a45a8ff	2485	return HAL_OK;
bogdanm	0:9b334a45a8ff	2486	}
bogdanm	0:9b334a45a8ff	2487
bogdanm	0:9b334a45a8ff	2488	/**
bogdanm	0:9b334a45a8ff	2489	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2490	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2491	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2492	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2493	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2494	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2495	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2496	* @retval HAL status
bogdanm	0:9b334a45a8ff	2497	*/
bogdanm	0:9b334a45a8ff	2498	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2499	{
bogdanm	0:9b334a45a8ff	2500	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2501	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2502
bogdanm	0:9b334a45a8ff	2503	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2504	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2505	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2506	{
bogdanm	0:9b334a45a8ff	2507	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2508
bogdanm	0:9b334a45a8ff	2509	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2510	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2511	}
bogdanm	0:9b334a45a8ff	2512	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2513	{
bogdanm	0:9b334a45a8ff	2514	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2515
bogdanm	0:9b334a45a8ff	2516	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2517	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2518	}
bogdanm	0:9b334a45a8ff	2519	else
bogdanm	0:9b334a45a8ff	2520	{
bogdanm	0:9b334a45a8ff	2521	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2522	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2523
bogdanm	0:9b334a45a8ff	2524	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2525	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2526	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2527	}
bogdanm	0:9b334a45a8ff	2528
bogdanm	0:9b334a45a8ff	2529	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2530	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2531
bogdanm	0:9b334a45a8ff	2532	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2533	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2534
bogdanm	0:9b334a45a8ff	2535	/* Return function status */
bogdanm	0:9b334a45a8ff	2536	return HAL_OK;
bogdanm	0:9b334a45a8ff	2537	}
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	/**
bogdanm	0:9b334a45a8ff	2540	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2541	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2542	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2543	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2544	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2545	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2546	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2547	* @param pData1: The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2548	* @param pData2: The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2549	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2550	* @retval HAL status
bogdanm	0:9b334a45a8ff	2551	*/
bogdanm	0:9b334a45a8ff	2552	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2553	{
bogdanm	0:9b334a45a8ff	2554	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2555	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2556
bogdanm	0:9b334a45a8ff	2557	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2558	{
bogdanm	0:9b334a45a8ff	2559	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2560	}
bogdanm	0:9b334a45a8ff	2561	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2562	{
bogdanm	0:9b334a45a8ff	2563	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2564	{
bogdanm	0:9b334a45a8ff	2565	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2566	}
bogdanm	0:9b334a45a8ff	2567	else
bogdanm	0:9b334a45a8ff	2568	{
bogdanm	0:9b334a45a8ff	2569	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2570	}
bogdanm	0:9b334a45a8ff	2571	}
bogdanm	0:9b334a45a8ff	2572
bogdanm	0:9b334a45a8ff	2573	switch (Channel)
bogdanm	0:9b334a45a8ff	2574	{
bogdanm	0:9b334a45a8ff	2575	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2576	{
bogdanm	0:9b334a45a8ff	2577	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2578	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2579
bogdanm	0:9b334a45a8ff	2580	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2581	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2582
bogdanm	0:9b334a45a8ff	2583	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2584	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2585
bogdanm	0:9b334a45a8ff	2586	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2587	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2588
bogdanm	0:9b334a45a8ff	2589	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2590	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2591
bogdanm	0:9b334a45a8ff	2592	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2593	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2594	}
bogdanm	0:9b334a45a8ff	2595	break;
bogdanm	0:9b334a45a8ff	2596
bogdanm	0:9b334a45a8ff	2597	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2598	{
bogdanm	0:9b334a45a8ff	2599	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2600	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2601
bogdanm	0:9b334a45a8ff	2602	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2603	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
bogdanm	0:9b334a45a8ff	2604	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2605	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2609
bogdanm	0:9b334a45a8ff	2610	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2611	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2612
bogdanm	0:9b334a45a8ff	2613	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2614	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2615	}
bogdanm	0:9b334a45a8ff	2616	break;
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2619	{
bogdanm	0:9b334a45a8ff	2620	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2621	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2622
bogdanm	0:9b334a45a8ff	2623	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2624	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2625
bogdanm	0:9b334a45a8ff	2626	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2627	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2630	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2631
bogdanm	0:9b334a45a8ff	2632	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2633	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2634
bogdanm	0:9b334a45a8ff	2635	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2636	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2637
bogdanm	0:9b334a45a8ff	2638	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2639	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2640
bogdanm	0:9b334a45a8ff	2641	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2642	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2643	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2646	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2647	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2648	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2649	}
bogdanm	0:9b334a45a8ff	2650	break;
bogdanm	0:9b334a45a8ff	2651
bogdanm	0:9b334a45a8ff	2652	default:
bogdanm	0:9b334a45a8ff	2653	break;
bogdanm	0:9b334a45a8ff	2654	}
bogdanm	0:9b334a45a8ff	2655	/* Return function status */
bogdanm	0:9b334a45a8ff	2656	return HAL_OK;
bogdanm	0:9b334a45a8ff	2657	}
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	/**
bogdanm	0:9b334a45a8ff	2660	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2661	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2662	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2663	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2664	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2665	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2666	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2667	* @retval HAL status
bogdanm	0:9b334a45a8ff	2668	*/
bogdanm	0:9b334a45a8ff	2669	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2670	{
bogdanm	0:9b334a45a8ff	2671	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2672	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2673
bogdanm	0:9b334a45a8ff	2674	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2675	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2676	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2677	{
bogdanm	0:9b334a45a8ff	2678	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2679
bogdanm	0:9b334a45a8ff	2680	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2681	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2682	}
bogdanm	0:9b334a45a8ff	2683	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2684	{
bogdanm	0:9b334a45a8ff	2685	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2686
bogdanm	0:9b334a45a8ff	2687	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2688	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2689	}
bogdanm	0:9b334a45a8ff	2690	else
bogdanm	0:9b334a45a8ff	2691	{
bogdanm	0:9b334a45a8ff	2692	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2693	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2694
bogdanm	0:9b334a45a8ff	2695	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2696	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2697	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2698	}
bogdanm	0:9b334a45a8ff	2699
bogdanm	0:9b334a45a8ff	2700	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2701	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2702
bogdanm	0:9b334a45a8ff	2703	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2704	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2705
bogdanm	0:9b334a45a8ff	2706	/* Return function status */
bogdanm	0:9b334a45a8ff	2707	return HAL_OK;
bogdanm	0:9b334a45a8ff	2708	}
bogdanm	0:9b334a45a8ff	2709
bogdanm	0:9b334a45a8ff	2710	/**
bogdanm	0:9b334a45a8ff	2711	* @}
bogdanm	0:9b334a45a8ff	2712	*/
bogdanm	0:9b334a45a8ff	2713	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	2714	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2715	*
bogdanm	0:9b334a45a8ff	2716	@verbatim
bogdanm	0:9b334a45a8ff	2717	==============================================================================
bogdanm	0:9b334a45a8ff	2718	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2719	==============================================================================
bogdanm	0:9b334a45a8ff	2720	[..]
bogdanm	0:9b334a45a8ff	2721	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2722
bogdanm	0:9b334a45a8ff	2723	@endverbatim
bogdanm	0:9b334a45a8ff	2724	* @{
bogdanm	0:9b334a45a8ff	2725	*/
bogdanm	0:9b334a45a8ff	2726	/**
bogdanm	0:9b334a45a8ff	2727	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2728	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2729	* @retval None
bogdanm	0:9b334a45a8ff	2730	*/
bogdanm	0:9b334a45a8ff	2731	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2732	{
bogdanm	0:9b334a45a8ff	2733	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2734	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2735	{
bogdanm	0:9b334a45a8ff	2736	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2737	{
bogdanm	0:9b334a45a8ff	2738	{
bogdanm	0:9b334a45a8ff	2739	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2740	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2741
bogdanm	0:9b334a45a8ff	2742	/* Input capture event */
bogdanm	0:9b334a45a8ff	2743	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2744	{
bogdanm	0:9b334a45a8ff	2745	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2746	}
bogdanm	0:9b334a45a8ff	2747	/* Output compare event */
bogdanm	0:9b334a45a8ff	2748	else
bogdanm	0:9b334a45a8ff	2749	{
bogdanm	0:9b334a45a8ff	2750	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2751	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2752	}
bogdanm	0:9b334a45a8ff	2753	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2754	}
bogdanm	0:9b334a45a8ff	2755	}
bogdanm	0:9b334a45a8ff	2756	}
bogdanm	0:9b334a45a8ff	2757	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2758	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2759	{
bogdanm	0:9b334a45a8ff	2760	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2761	{
bogdanm	0:9b334a45a8ff	2762	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2763	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2764	/* Input capture event */
bogdanm	0:9b334a45a8ff	2765	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2766	{
bogdanm	0:9b334a45a8ff	2767	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2768	}
bogdanm	0:9b334a45a8ff	2769	/* Output compare event */
bogdanm	0:9b334a45a8ff	2770	else
bogdanm	0:9b334a45a8ff	2771	{
bogdanm	0:9b334a45a8ff	2772	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2773	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2774	}
bogdanm	0:9b334a45a8ff	2775	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2776	}
bogdanm	0:9b334a45a8ff	2777	}
bogdanm	0:9b334a45a8ff	2778	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2779	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2780	{
bogdanm	0:9b334a45a8ff	2781	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2782	{
bogdanm	0:9b334a45a8ff	2783	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2784	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2785	/* Input capture event */
bogdanm	0:9b334a45a8ff	2786	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2787	{
bogdanm	0:9b334a45a8ff	2788	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2789	}
bogdanm	0:9b334a45a8ff	2790	/* Output compare event */
bogdanm	0:9b334a45a8ff	2791	else
bogdanm	0:9b334a45a8ff	2792	{
bogdanm	0:9b334a45a8ff	2793	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2794	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2795	}
bogdanm	0:9b334a45a8ff	2796	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2797	}
bogdanm	0:9b334a45a8ff	2798	}
bogdanm	0:9b334a45a8ff	2799	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2800	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2801	{
bogdanm	0:9b334a45a8ff	2802	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2803	{
bogdanm	0:9b334a45a8ff	2804	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2805	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2806	/* Input capture event */
bogdanm	0:9b334a45a8ff	2807	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2808	{
bogdanm	0:9b334a45a8ff	2809	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2810	}
bogdanm	0:9b334a45a8ff	2811	/* Output compare event */
bogdanm	0:9b334a45a8ff	2812	else
bogdanm	0:9b334a45a8ff	2813	{
bogdanm	0:9b334a45a8ff	2814	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2815	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2816	}
bogdanm	0:9b334a45a8ff	2817	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2818	}
bogdanm	0:9b334a45a8ff	2819	}
bogdanm	0:9b334a45a8ff	2820	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2821	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2822	{
bogdanm	0:9b334a45a8ff	2823	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2824	{
bogdanm	0:9b334a45a8ff	2825	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2826	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2827	}
bogdanm	0:9b334a45a8ff	2828	}
bogdanm	0:9b334a45a8ff	2829	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2830	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm	0:9b334a45a8ff	2831	{
bogdanm	0:9b334a45a8ff	2832	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2833	{
bogdanm	0:9b334a45a8ff	2834	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2835	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2836	}
bogdanm	0:9b334a45a8ff	2837	}
bogdanm	0:9b334a45a8ff	2838	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2839	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2840	{
bogdanm	0:9b334a45a8ff	2841	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2842	{
bogdanm	0:9b334a45a8ff	2843	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2844	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2845	}
bogdanm	0:9b334a45a8ff	2846	}
bogdanm	0:9b334a45a8ff	2847	/* TIM commutation event */
bogdanm	0:9b334a45a8ff	2848	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm	0:9b334a45a8ff	2849	{
bogdanm	0:9b334a45a8ff	2850	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
bogdanm	0:9b334a45a8ff	2851	{
bogdanm	0:9b334a45a8ff	2852	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm	0:9b334a45a8ff	2853	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2854	}
bogdanm	0:9b334a45a8ff	2855	}
bogdanm	0:9b334a45a8ff	2856	}
bogdanm	0:9b334a45a8ff	2857
bogdanm	0:9b334a45a8ff	2858	/**
bogdanm	0:9b334a45a8ff	2859	* @}
bogdanm	0:9b334a45a8ff	2860	*/
bogdanm	0:9b334a45a8ff	2861
bogdanm	0:9b334a45a8ff	2862	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2863	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2864	*
bogdanm	0:9b334a45a8ff	2865	@verbatim
bogdanm	0:9b334a45a8ff	2866	==============================================================================
bogdanm	0:9b334a45a8ff	2867	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2868	==============================================================================
bogdanm	0:9b334a45a8ff	2869	[..]
bogdanm	0:9b334a45a8ff	2870	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2871	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2872	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2873	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	2874	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2875	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2876
bogdanm	0:9b334a45a8ff	2877	@endverbatim
bogdanm	0:9b334a45a8ff	2878	* @{
bogdanm	0:9b334a45a8ff	2879	*/
bogdanm	0:9b334a45a8ff	2880
bogdanm	0:9b334a45a8ff	2881	/**
bogdanm	0:9b334a45a8ff	2882	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2883	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2884	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	2885	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2886	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2887	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2888	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2889	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2890	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2891	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2892	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	2893	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	2894	* @retval HAL status
bogdanm	0:9b334a45a8ff	2895	*/
bogdanm	0:9b334a45a8ff	2896	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2897	{
bogdanm	0:9b334a45a8ff	2898	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2899	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2900	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2901	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2902	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	2903	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	2904	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	2905
bogdanm	0:9b334a45a8ff	2906	/* Check input state */
bogdanm	0:9b334a45a8ff	2907	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2908
bogdanm	0:9b334a45a8ff	2909	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2910
bogdanm	0:9b334a45a8ff	2911	switch (Channel)
bogdanm	0:9b334a45a8ff	2912	{
bogdanm	0:9b334a45a8ff	2913	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2914	{
bogdanm	0:9b334a45a8ff	2915	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2916	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2917	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2918	}
bogdanm	0:9b334a45a8ff	2919	break;
bogdanm	0:9b334a45a8ff	2920
bogdanm	0:9b334a45a8ff	2921	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2922	{
bogdanm	0:9b334a45a8ff	2923	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2924	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	2925	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2926	}
bogdanm	0:9b334a45a8ff	2927	break;
bogdanm	0:9b334a45a8ff	2928
bogdanm	0:9b334a45a8ff	2929	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2930	{
bogdanm	0:9b334a45a8ff	2931	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2932	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	2933	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2934	}
bogdanm	0:9b334a45a8ff	2935	break;
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2938	{
bogdanm	0:9b334a45a8ff	2939	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2940	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	2941	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2942	}
bogdanm	0:9b334a45a8ff	2943	break;
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	default:
bogdanm	0:9b334a45a8ff	2946	break;
bogdanm	0:9b334a45a8ff	2947	}
bogdanm	0:9b334a45a8ff	2948	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2949
bogdanm	0:9b334a45a8ff	2950	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2951
bogdanm	0:9b334a45a8ff	2952	return HAL_OK;
bogdanm	0:9b334a45a8ff	2953	}
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	/**
bogdanm	0:9b334a45a8ff	2956	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	2957	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2958	* @param htim: TIM IC handle
bogdanm	0:9b334a45a8ff	2959	* @param sConfig: TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	2960	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2961	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2962	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2963	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2964	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2965	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2966	* @retval HAL status
bogdanm	0:9b334a45a8ff	2967	*/
bogdanm	0:9b334a45a8ff	2968	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2969	{
bogdanm	0:9b334a45a8ff	2970	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2971	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2972	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	2973	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	2974	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	2975	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2978
bogdanm	0:9b334a45a8ff	2979	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2980
bogdanm	0:9b334a45a8ff	2981	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2982	{
bogdanm	0:9b334a45a8ff	2983	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	2984	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2985	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2986	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2987	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2988
bogdanm	0:9b334a45a8ff	2989	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	2990	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	2991
bogdanm	0:9b334a45a8ff	2992	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	2993	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	2994	}
bogdanm	0:9b334a45a8ff	2995	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2996	{
bogdanm	0:9b334a45a8ff	2997	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	2998	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2999
bogdanm	0:9b334a45a8ff	3000	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3001	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3002	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3003	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3004
bogdanm	0:9b334a45a8ff	3005	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3006	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3007
bogdanm	0:9b334a45a8ff	3008	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	3009	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3010	}
bogdanm	0:9b334a45a8ff	3011	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	3012	{
bogdanm	0:9b334a45a8ff	3013	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	3014	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3015
bogdanm	0:9b334a45a8ff	3016	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3017	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3018	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3019	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3020
bogdanm	0:9b334a45a8ff	3021	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	3022	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	3023
bogdanm	0:9b334a45a8ff	3024	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	3025	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3026	}
bogdanm	0:9b334a45a8ff	3027	else
bogdanm	0:9b334a45a8ff	3028	{
bogdanm	0:9b334a45a8ff	3029	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	3030	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3031
bogdanm	0:9b334a45a8ff	3032	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3033	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3034	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3035	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3036
bogdanm	0:9b334a45a8ff	3037	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	3038	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	3039
bogdanm	0:9b334a45a8ff	3040	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	3041	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3042	}
bogdanm	0:9b334a45a8ff	3043
bogdanm	0:9b334a45a8ff	3044	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3045
bogdanm	0:9b334a45a8ff	3046	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3047
bogdanm	0:9b334a45a8ff	3048	return HAL_OK;
bogdanm	0:9b334a45a8ff	3049	}
bogdanm	0:9b334a45a8ff	3050
bogdanm	0:9b334a45a8ff	3051	/**
bogdanm	0:9b334a45a8ff	3052	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	3053	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3054	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3055	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	3056	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3057	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3058	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3059	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3060	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3061	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3062	* @retval HAL status
bogdanm	0:9b334a45a8ff	3063	*/
bogdanm	0:9b334a45a8ff	3064	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3065	{
bogdanm	0:9b334a45a8ff	3066	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3067
bogdanm	0:9b334a45a8ff	3068	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3069	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3070	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3071	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3072	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	3073	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3074	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	3075	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	3076
bogdanm	0:9b334a45a8ff	3077	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3078
bogdanm	0:9b334a45a8ff	3079	switch (Channel)
bogdanm	0:9b334a45a8ff	3080	{
bogdanm	0:9b334a45a8ff	3081	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3082	{
bogdanm	0:9b334a45a8ff	3083	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3084	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3085	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3086
bogdanm	0:9b334a45a8ff	3087	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3088	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3089
bogdanm	0:9b334a45a8ff	3090	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3091	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3092	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3093	}
bogdanm	0:9b334a45a8ff	3094	break;
bogdanm	0:9b334a45a8ff	3095
bogdanm	0:9b334a45a8ff	3096	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3097	{
bogdanm	0:9b334a45a8ff	3098	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3099	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3100	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3101
bogdanm	0:9b334a45a8ff	3102	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3103	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3104
bogdanm	0:9b334a45a8ff	3105	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3106	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3107	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3108	}
bogdanm	0:9b334a45a8ff	3109	break;
bogdanm	0:9b334a45a8ff	3110
bogdanm	0:9b334a45a8ff	3111	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3112	{
bogdanm	0:9b334a45a8ff	3113	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3114	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3115	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3116
bogdanm	0:9b334a45a8ff	3117	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3118	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3119
bogdanm	0:9b334a45a8ff	3120	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3121	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3122	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3123	}
bogdanm	0:9b334a45a8ff	3124	break;
bogdanm	0:9b334a45a8ff	3125
bogdanm	0:9b334a45a8ff	3126	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3127	{
bogdanm	0:9b334a45a8ff	3128	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3129	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3130	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3131
bogdanm	0:9b334a45a8ff	3132	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3133	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3134
bogdanm	0:9b334a45a8ff	3135	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3136	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3137	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3138	}
bogdanm	0:9b334a45a8ff	3139	break;
bogdanm	0:9b334a45a8ff	3140
bogdanm	0:9b334a45a8ff	3141	default:
bogdanm	0:9b334a45a8ff	3142	break;
bogdanm	0:9b334a45a8ff	3143	}
bogdanm	0:9b334a45a8ff	3144
bogdanm	0:9b334a45a8ff	3145	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3146
bogdanm	0:9b334a45a8ff	3147	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3148
bogdanm	0:9b334a45a8ff	3149	return HAL_OK;
bogdanm	0:9b334a45a8ff	3150	}
bogdanm	0:9b334a45a8ff	3151
bogdanm	0:9b334a45a8ff	3152	/**
bogdanm	0:9b334a45a8ff	3153	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3154	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3155	* @param htim: TIM One Pulse handle
bogdanm	0:9b334a45a8ff	3156	* @param sConfig: TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3157	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3158	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3159	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3160	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3161	* @param InputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3162	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3163	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3164	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3165	* @retval HAL status
bogdanm	0:9b334a45a8ff	3166	*/
bogdanm	0:9b334a45a8ff	3167	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3168	{
bogdanm	0:9b334a45a8ff	3169	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3170
bogdanm	0:9b334a45a8ff	3171	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3172	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3173	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3174
bogdanm	0:9b334a45a8ff	3175	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3176	{
bogdanm	0:9b334a45a8ff	3177	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3178
bogdanm	0:9b334a45a8ff	3179	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3180
bogdanm	0:9b334a45a8ff	3181	/* Extract the Ouput compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3182	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3183	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3184	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3185	temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm	0:9b334a45a8ff	3186	temp1.OCIdleState = sConfig->OCIdleState;
bogdanm	0:9b334a45a8ff	3187	temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm	0:9b334a45a8ff	3188
bogdanm	0:9b334a45a8ff	3189	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3190	{
bogdanm	0:9b334a45a8ff	3191	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3192	{
bogdanm	0:9b334a45a8ff	3193	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3194
bogdanm	0:9b334a45a8ff	3195	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3196	}
bogdanm	0:9b334a45a8ff	3197	break;
bogdanm	0:9b334a45a8ff	3198	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3199	{
bogdanm	0:9b334a45a8ff	3200	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3201
bogdanm	0:9b334a45a8ff	3202	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3203	}
bogdanm	0:9b334a45a8ff	3204	break;
bogdanm	0:9b334a45a8ff	3205	default:
bogdanm	0:9b334a45a8ff	3206	break;
bogdanm	0:9b334a45a8ff	3207	}
bogdanm	0:9b334a45a8ff	3208	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3209	{
bogdanm	0:9b334a45a8ff	3210	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3211	{
bogdanm	0:9b334a45a8ff	3212	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3213
bogdanm	0:9b334a45a8ff	3214	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3215	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3216
bogdanm	0:9b334a45a8ff	3217	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3218	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3219
bogdanm	0:9b334a45a8ff	3220	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3221	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3222	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3223
bogdanm	0:9b334a45a8ff	3224	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3225	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3226	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3227	}
bogdanm	0:9b334a45a8ff	3228	break;
bogdanm	0:9b334a45a8ff	3229	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3230	{
bogdanm	0:9b334a45a8ff	3231	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3234	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3235
bogdanm	0:9b334a45a8ff	3236	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3237	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3238
bogdanm	0:9b334a45a8ff	3239	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3240	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3241	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3242
bogdanm	0:9b334a45a8ff	3243	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3244	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3245	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3246	}
bogdanm	0:9b334a45a8ff	3247	break;
bogdanm	0:9b334a45a8ff	3248
bogdanm	0:9b334a45a8ff	3249	default:
bogdanm	0:9b334a45a8ff	3250	break;
bogdanm	0:9b334a45a8ff	3251	}
bogdanm	0:9b334a45a8ff	3252
bogdanm	0:9b334a45a8ff	3253	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3254
bogdanm	0:9b334a45a8ff	3255	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3256
bogdanm	0:9b334a45a8ff	3257	return HAL_OK;
bogdanm	0:9b334a45a8ff	3258	}
bogdanm	0:9b334a45a8ff	3259	else
bogdanm	0:9b334a45a8ff	3260	{
bogdanm	0:9b334a45a8ff	3261	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3262	}
bogdanm	0:9b334a45a8ff	3263	}
bogdanm	0:9b334a45a8ff	3264
bogdanm	0:9b334a45a8ff	3265	/**
bogdanm	0:9b334a45a8ff	3266	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3267	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3268	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
bogdanm	0:9b334a45a8ff	3269	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3270	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3271	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3272	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3273	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3274	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3275	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3276	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3277	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3278	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3279	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3280	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3281	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3282	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3283	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3284	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3285	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3286	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3287	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3288	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3289	* @param BurstRequestSrc: TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3290	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3291	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3292	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3293	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3294	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3295	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3296	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3297	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3298	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3299	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3300	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
bogdanm	0:9b334a45a8ff	3301	* @retval HAL status
bogdanm	0:9b334a45a8ff	3302	*/
bogdanm	0:9b334a45a8ff	3303	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3304	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3305	{
bogdanm	0:9b334a45a8ff	3306	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3307	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3308	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3309	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3310	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3311
bogdanm	0:9b334a45a8ff	3312	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3313	{
bogdanm	0:9b334a45a8ff	3314	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3315	}
bogdanm	0:9b334a45a8ff	3316	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3317	{
bogdanm	0:9b334a45a8ff	3318	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3319	{
bogdanm	0:9b334a45a8ff	3320	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3321	}
bogdanm	0:9b334a45a8ff	3322	else
bogdanm	0:9b334a45a8ff	3323	{
bogdanm	0:9b334a45a8ff	3324	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3325	}
bogdanm	0:9b334a45a8ff	3326	}
bogdanm	0:9b334a45a8ff	3327	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3328	{
bogdanm	0:9b334a45a8ff	3329	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3330	{
bogdanm	0:9b334a45a8ff	3331	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3332	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3333
bogdanm	0:9b334a45a8ff	3334	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3335	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3336
bogdanm	0:9b334a45a8ff	3337	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3338	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3339	}
bogdanm	0:9b334a45a8ff	3340	break;
bogdanm	0:9b334a45a8ff	3341	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3342	{
bogdanm	0:9b334a45a8ff	3343	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3344	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3345
bogdanm	0:9b334a45a8ff	3346	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3347	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3348
bogdanm	0:9b334a45a8ff	3349	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3350	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3351	}
bogdanm	0:9b334a45a8ff	3352	break;
bogdanm	0:9b334a45a8ff	3353	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3354	{
bogdanm	0:9b334a45a8ff	3355	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3356	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3357
bogdanm	0:9b334a45a8ff	3358	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3359	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3360
bogdanm	0:9b334a45a8ff	3361	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3362	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3363	}
bogdanm	0:9b334a45a8ff	3364	break;
bogdanm	0:9b334a45a8ff	3365	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3366	{
bogdanm	0:9b334a45a8ff	3367	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3368	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3369
bogdanm	0:9b334a45a8ff	3370	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3371	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3372
bogdanm	0:9b334a45a8ff	3373	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3374	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3375	}
bogdanm	0:9b334a45a8ff	3376	break;
bogdanm	0:9b334a45a8ff	3377	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3378	{
bogdanm	0:9b334a45a8ff	3379	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3380	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3381
bogdanm	0:9b334a45a8ff	3382	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3383	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3384
bogdanm	0:9b334a45a8ff	3385	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3386	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3387	}
bogdanm	0:9b334a45a8ff	3388	break;
bogdanm	0:9b334a45a8ff	3389	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3390	{
bogdanm	0:9b334a45a8ff	3391	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3392	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3393
bogdanm	0:9b334a45a8ff	3394	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3395	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3396
bogdanm	0:9b334a45a8ff	3397	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3398	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3399	}
bogdanm	0:9b334a45a8ff	3400	break;
bogdanm	0:9b334a45a8ff	3401	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3402	{
bogdanm	0:9b334a45a8ff	3403	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3404	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3405
bogdanm	0:9b334a45a8ff	3406	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3407	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3408
bogdanm	0:9b334a45a8ff	3409	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3410	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3411	}
bogdanm	0:9b334a45a8ff	3412	break;
bogdanm	0:9b334a45a8ff	3413	default:
bogdanm	0:9b334a45a8ff	3414	break;
bogdanm	0:9b334a45a8ff	3415	}
bogdanm	0:9b334a45a8ff	3416	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3417	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3418
bogdanm	0:9b334a45a8ff	3419	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3420	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3421
bogdanm	0:9b334a45a8ff	3422	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3423
bogdanm	0:9b334a45a8ff	3424	/* Return function status */
bogdanm	0:9b334a45a8ff	3425	return HAL_OK;
bogdanm	0:9b334a45a8ff	3426	}
bogdanm	0:9b334a45a8ff	3427
bogdanm	0:9b334a45a8ff	3428	/**
bogdanm	0:9b334a45a8ff	3429	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3430	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3431	* @param BurstRequestSrc: TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3432	* @retval HAL status
bogdanm	0:9b334a45a8ff	3433	*/
bogdanm	0:9b334a45a8ff	3434	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3435	{
bogdanm	0:9b334a45a8ff	3436	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3437	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3438
bogdanm	0:9b334a45a8ff	3439	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3440	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3441	{
bogdanm	0:9b334a45a8ff	3442	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3443	{
bogdanm	0:9b334a45a8ff	3444	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3445	}
bogdanm	0:9b334a45a8ff	3446	break;
bogdanm	0:9b334a45a8ff	3447	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3448	{
bogdanm	0:9b334a45a8ff	3449	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3450	}
bogdanm	0:9b334a45a8ff	3451	break;
bogdanm	0:9b334a45a8ff	3452	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3453	{
bogdanm	0:9b334a45a8ff	3454	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3455	}
bogdanm	0:9b334a45a8ff	3456	break;
bogdanm	0:9b334a45a8ff	3457	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3458	{
bogdanm	0:9b334a45a8ff	3459	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3460	}
bogdanm	0:9b334a45a8ff	3461	break;
bogdanm	0:9b334a45a8ff	3462	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3463	{
bogdanm	0:9b334a45a8ff	3464	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3465	}
bogdanm	0:9b334a45a8ff	3466	break;
bogdanm	0:9b334a45a8ff	3467	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3468	{
bogdanm	0:9b334a45a8ff	3469	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3470	}
bogdanm	0:9b334a45a8ff	3471	break;
bogdanm	0:9b334a45a8ff	3472	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3473	{
bogdanm	0:9b334a45a8ff	3474	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3475	}
bogdanm	0:9b334a45a8ff	3476	break;
bogdanm	0:9b334a45a8ff	3477	default:
bogdanm	0:9b334a45a8ff	3478	break;
bogdanm	0:9b334a45a8ff	3479	}
bogdanm	0:9b334a45a8ff	3480
bogdanm	0:9b334a45a8ff	3481	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3482	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3483
bogdanm	0:9b334a45a8ff	3484	/* Return function status */
bogdanm	0:9b334a45a8ff	3485	return HAL_OK;
bogdanm	0:9b334a45a8ff	3486	}
bogdanm	0:9b334a45a8ff	3487
bogdanm	0:9b334a45a8ff	3488	/**
bogdanm	0:9b334a45a8ff	3489	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3490	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3491	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
bogdanm	0:9b334a45a8ff	3492	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3493	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3494	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3495	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3496	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3497	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3498	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3499	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3500	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3501	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3502	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3503	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3504	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3505	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3506	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3507	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3508	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3509	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3510	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3511	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3512	* @param BurstRequestSrc: TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3513	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3514	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3515	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3516	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3517	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3518	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3519	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3520	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3521	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3522	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3523	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
bogdanm	0:9b334a45a8ff	3524	* @retval HAL status
bogdanm	0:9b334a45a8ff	3525	*/
bogdanm	0:9b334a45a8ff	3526	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3527	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3528	{
bogdanm	0:9b334a45a8ff	3529	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3530	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3531	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3532	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3533	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3534
bogdanm	0:9b334a45a8ff	3535	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3536	{
bogdanm	0:9b334a45a8ff	3537	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3538	}
bogdanm	0:9b334a45a8ff	3539	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3540	{
bogdanm	0:9b334a45a8ff	3541	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3542	{
bogdanm	0:9b334a45a8ff	3543	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3544	}
bogdanm	0:9b334a45a8ff	3545	else
bogdanm	0:9b334a45a8ff	3546	{
bogdanm	0:9b334a45a8ff	3547	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3548	}
bogdanm	0:9b334a45a8ff	3549	}
bogdanm	0:9b334a45a8ff	3550	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3551	{
bogdanm	0:9b334a45a8ff	3552	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3553	{
bogdanm	0:9b334a45a8ff	3554	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3555	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3556
bogdanm	0:9b334a45a8ff	3557	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3558	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3559
bogdanm	0:9b334a45a8ff	3560	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3561	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3562	}
bogdanm	0:9b334a45a8ff	3563	break;
bogdanm	0:9b334a45a8ff	3564	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3565	{
bogdanm	0:9b334a45a8ff	3566	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3567	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3568
bogdanm	0:9b334a45a8ff	3569	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3570	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3571
bogdanm	0:9b334a45a8ff	3572	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3573	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3574	}
bogdanm	0:9b334a45a8ff	3575	break;
bogdanm	0:9b334a45a8ff	3576	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3577	{
bogdanm	0:9b334a45a8ff	3578	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3579	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3580
bogdanm	0:9b334a45a8ff	3581	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3582	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3583
bogdanm	0:9b334a45a8ff	3584	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3585	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3586	}
bogdanm	0:9b334a45a8ff	3587	break;
bogdanm	0:9b334a45a8ff	3588	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3589	{
bogdanm	0:9b334a45a8ff	3590	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3591	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3592
bogdanm	0:9b334a45a8ff	3593	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3594	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3595
bogdanm	0:9b334a45a8ff	3596	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3597	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3598	}
bogdanm	0:9b334a45a8ff	3599	break;
bogdanm	0:9b334a45a8ff	3600	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3601	{
bogdanm	0:9b334a45a8ff	3602	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3603	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3604
bogdanm	0:9b334a45a8ff	3605	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3606	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3607
bogdanm	0:9b334a45a8ff	3608	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3609	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3610	}
bogdanm	0:9b334a45a8ff	3611	break;
bogdanm	0:9b334a45a8ff	3612	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3613	{
bogdanm	0:9b334a45a8ff	3614	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3615	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3616
bogdanm	0:9b334a45a8ff	3617	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3618	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3619
bogdanm	0:9b334a45a8ff	3620	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3621	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3622	}
bogdanm	0:9b334a45a8ff	3623	break;
bogdanm	0:9b334a45a8ff	3624	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3625	{
bogdanm	0:9b334a45a8ff	3626	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3627	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3628
bogdanm	0:9b334a45a8ff	3629	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3630	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3631
bogdanm	0:9b334a45a8ff	3632	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3633	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3634	}
bogdanm	0:9b334a45a8ff	3635	break;
bogdanm	0:9b334a45a8ff	3636	default:
bogdanm	0:9b334a45a8ff	3637	break;
bogdanm	0:9b334a45a8ff	3638	}
bogdanm	0:9b334a45a8ff	3639
bogdanm	0:9b334a45a8ff	3640	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3641	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3642
bogdanm	0:9b334a45a8ff	3643	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3644	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3645
bogdanm	0:9b334a45a8ff	3646	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3647
bogdanm	0:9b334a45a8ff	3648	/* Return function status */
bogdanm	0:9b334a45a8ff	3649	return HAL_OK;
bogdanm	0:9b334a45a8ff	3650	}
bogdanm	0:9b334a45a8ff	3651
bogdanm	0:9b334a45a8ff	3652	/**
bogdanm	0:9b334a45a8ff	3653	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3654	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3655	* @param BurstRequestSrc: TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3656	* @retval HAL status
bogdanm	0:9b334a45a8ff	3657	*/
bogdanm	0:9b334a45a8ff	3658	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3659	{
bogdanm	0:9b334a45a8ff	3660	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3661	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3662
bogdanm	0:9b334a45a8ff	3663	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3664	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3665	{
bogdanm	0:9b334a45a8ff	3666	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3667	{
bogdanm	0:9b334a45a8ff	3668	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3669	}
bogdanm	0:9b334a45a8ff	3670	break;
bogdanm	0:9b334a45a8ff	3671	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3672	{
bogdanm	0:9b334a45a8ff	3673	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3674	}
bogdanm	0:9b334a45a8ff	3675	break;
bogdanm	0:9b334a45a8ff	3676	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3677	{
bogdanm	0:9b334a45a8ff	3678	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3679	}
bogdanm	0:9b334a45a8ff	3680	break;
bogdanm	0:9b334a45a8ff	3681	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3682	{
bogdanm	0:9b334a45a8ff	3683	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3684	}
bogdanm	0:9b334a45a8ff	3685	break;
bogdanm	0:9b334a45a8ff	3686	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3687	{
bogdanm	0:9b334a45a8ff	3688	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3689	}
bogdanm	0:9b334a45a8ff	3690	break;
bogdanm	0:9b334a45a8ff	3691	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3692	{
bogdanm	0:9b334a45a8ff	3693	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3694	}
bogdanm	0:9b334a45a8ff	3695	break;
bogdanm	0:9b334a45a8ff	3696	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3697	{
bogdanm	0:9b334a45a8ff	3698	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3699	}
bogdanm	0:9b334a45a8ff	3700	break;
bogdanm	0:9b334a45a8ff	3701	default:
bogdanm	0:9b334a45a8ff	3702	break;
bogdanm	0:9b334a45a8ff	3703	}
bogdanm	0:9b334a45a8ff	3704
bogdanm	0:9b334a45a8ff	3705	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3706	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3707
bogdanm	0:9b334a45a8ff	3708	/* Return function status */
bogdanm	0:9b334a45a8ff	3709	return HAL_OK;
bogdanm	0:9b334a45a8ff	3710	}
bogdanm	0:9b334a45a8ff	3711
bogdanm	0:9b334a45a8ff	3712	/**
bogdanm	0:9b334a45a8ff	3713	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3714	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3715	* @param EventSource: specifies the event source.
bogdanm	0:9b334a45a8ff	3716	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3717	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
bogdanm	0:9b334a45a8ff	3718	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3719	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3720	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3721	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3722	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
bogdanm	0:9b334a45a8ff	3723	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3724	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
bogdanm	0:9b334a45a8ff	3725	* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
bogdanm	0:9b334a45a8ff	3726	* @retval None
bogdanm	0:9b334a45a8ff	3727	*/
bogdanm	0:9b334a45a8ff	3728
bogdanm	0:9b334a45a8ff	3729	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3730	{
bogdanm	0:9b334a45a8ff	3731	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3732	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3733	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3734
bogdanm	0:9b334a45a8ff	3735	/* Process Locked */
bogdanm	0:9b334a45a8ff	3736	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3737
bogdanm	0:9b334a45a8ff	3738	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3739	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3740
bogdanm	0:9b334a45a8ff	3741	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3742	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3743
bogdanm	0:9b334a45a8ff	3744	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3745	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3746
bogdanm	0:9b334a45a8ff	3747	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3748
bogdanm	0:9b334a45a8ff	3749	/* Return function status */
bogdanm	0:9b334a45a8ff	3750	return HAL_OK;
bogdanm	0:9b334a45a8ff	3751	}
bogdanm	0:9b334a45a8ff	3752
bogdanm	0:9b334a45a8ff	3753	/**
bogdanm	0:9b334a45a8ff	3754	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3755	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3756	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3757	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3758	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	3759	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3760	* @arg TIM_CHANNEL_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	3761	* @arg TIM_CHANNEL_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	3762	* @arg TIM_CHANNEL_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	3763	* @arg TIM_CHANNEL_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	3764	* @retval HAL status
bogdanm	0:9b334a45a8ff	3765	*/
bogdanm	0:9b334a45a8ff	3766	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3767	{
bogdanm	0:9b334a45a8ff	3768	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3769	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3770	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3771	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3772
bogdanm	0:9b334a45a8ff	3773	/* Process Locked */
bogdanm	0:9b334a45a8ff	3774	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3775
bogdanm	0:9b334a45a8ff	3776	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3777
bogdanm	0:9b334a45a8ff	3778	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
bogdanm	0:9b334a45a8ff	3779	{
bogdanm	0:9b334a45a8ff	3780	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3781	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3782	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3783	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3784
bogdanm	0:9b334a45a8ff	3785	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3786	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3787	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3788	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	3789	}
bogdanm	0:9b334a45a8ff	3790
bogdanm	0:9b334a45a8ff	3791	switch (Channel)
bogdanm	0:9b334a45a8ff	3792	{
bogdanm	0:9b334a45a8ff	3793	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3794	{
bogdanm	0:9b334a45a8ff	3795	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3796	{
bogdanm	0:9b334a45a8ff	3797	/* Enable the OCREF clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3798	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3799	}
bogdanm	0:9b334a45a8ff	3800	else
bogdanm	0:9b334a45a8ff	3801	{
bogdanm	0:9b334a45a8ff	3802	/* Disable the OCREF clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3803	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3804	}
bogdanm	0:9b334a45a8ff	3805	}
bogdanm	0:9b334a45a8ff	3806	break;
bogdanm	0:9b334a45a8ff	3807	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3808	{
bogdanm	0:9b334a45a8ff	3809	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3810	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3811	{
bogdanm	0:9b334a45a8ff	3812	/* Enable the OCREF clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3813	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3814	}
bogdanm	0:9b334a45a8ff	3815	else
bogdanm	0:9b334a45a8ff	3816	{
bogdanm	0:9b334a45a8ff	3817	/* Disable the OCREF clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3818	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3819	}
bogdanm	0:9b334a45a8ff	3820	}
bogdanm	0:9b334a45a8ff	3821	break;
bogdanm	0:9b334a45a8ff	3822	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3823	{
bogdanm	0:9b334a45a8ff	3824	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3825	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3826	{
bogdanm	0:9b334a45a8ff	3827	/* Enable the OCREF clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3828	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3829	}
bogdanm	0:9b334a45a8ff	3830	else
bogdanm	0:9b334a45a8ff	3831	{
bogdanm	0:9b334a45a8ff	3832	/* Disable the OCREF clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3833	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3834	}
bogdanm	0:9b334a45a8ff	3835	}
bogdanm	0:9b334a45a8ff	3836	break;
bogdanm	0:9b334a45a8ff	3837	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3838	{
bogdanm	0:9b334a45a8ff	3839	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3840	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3841	{
bogdanm	0:9b334a45a8ff	3842	/* Enable the OCREF clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3843	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3844	}
bogdanm	0:9b334a45a8ff	3845	else
bogdanm	0:9b334a45a8ff	3846	{
bogdanm	0:9b334a45a8ff	3847	/* Disable the OCREF clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3848	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3849	}
bogdanm	0:9b334a45a8ff	3850	}
bogdanm	0:9b334a45a8ff	3851	break;
bogdanm	0:9b334a45a8ff	3852	default:
bogdanm	0:9b334a45a8ff	3853	break;
bogdanm	0:9b334a45a8ff	3854	}
bogdanm	0:9b334a45a8ff	3855
bogdanm	0:9b334a45a8ff	3856	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3857
bogdanm	0:9b334a45a8ff	3858	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3859
bogdanm	0:9b334a45a8ff	3860	return HAL_OK;
bogdanm	0:9b334a45a8ff	3861	}
bogdanm	0:9b334a45a8ff	3862
bogdanm	0:9b334a45a8ff	3863	/**
bogdanm	0:9b334a45a8ff	3864	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3865	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3866	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3867	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3868	* @retval HAL status
bogdanm	0:9b334a45a8ff	3869	*/
bogdanm	0:9b334a45a8ff	3870	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3871	{
bogdanm	0:9b334a45a8ff	3872	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3873
bogdanm	0:9b334a45a8ff	3874	/* Process Locked */
bogdanm	0:9b334a45a8ff	3875	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3876
bogdanm	0:9b334a45a8ff	3877	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3878
bogdanm	0:9b334a45a8ff	3879	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3880	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3881	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
bogdanm	0:9b334a45a8ff	3882	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
bogdanm	0:9b334a45a8ff	3883	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3884
bogdanm	0:9b334a45a8ff	3885	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3886	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3887	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3888	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3889	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3890
bogdanm	0:9b334a45a8ff	3891	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3892	{
bogdanm	0:9b334a45a8ff	3893	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3894	{
bogdanm	0:9b334a45a8ff	3895	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3896	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3897	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3898	}
bogdanm	0:9b334a45a8ff	3899	break;
bogdanm	0:9b334a45a8ff	3900
bogdanm	0:9b334a45a8ff	3901	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3902	{
bogdanm	0:9b334a45a8ff	3903	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3904	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3905
bogdanm	0:9b334a45a8ff	3906	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3907	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3908	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3909	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3910	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3911	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	3912	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3913	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	3914	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3915	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	3916	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	3917	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	3918	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3919	}
bogdanm	0:9b334a45a8ff	3920	break;
bogdanm	0:9b334a45a8ff	3921
bogdanm	0:9b334a45a8ff	3922	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	3923	{
bogdanm	0:9b334a45a8ff	3924	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
bogdanm	0:9b334a45a8ff	3925	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3926
bogdanm	0:9b334a45a8ff	3927	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3928	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3929	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3930	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3931	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3932	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	3933	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	3934	}
bogdanm	0:9b334a45a8ff	3935	break;
bogdanm	0:9b334a45a8ff	3936
bogdanm	0:9b334a45a8ff	3937	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	3938	{
bogdanm	0:9b334a45a8ff	3939	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3940	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3941
bogdanm	0:9b334a45a8ff	3942	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3943	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3944	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3945	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	3946	}
bogdanm	0:9b334a45a8ff	3947	break;
bogdanm	0:9b334a45a8ff	3948
bogdanm	0:9b334a45a8ff	3949	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	3950	{
bogdanm	0:9b334a45a8ff	3951	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3952	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3953
bogdanm	0:9b334a45a8ff	3954	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3955	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3956	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3957	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	3958	}
bogdanm	0:9b334a45a8ff	3959	break;
bogdanm	0:9b334a45a8ff	3960
bogdanm	0:9b334a45a8ff	3961	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	3962	{
bogdanm	0:9b334a45a8ff	3963	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3964	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3965
bogdanm	0:9b334a45a8ff	3966	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3967	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3968	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3969	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	3970	}
bogdanm	0:9b334a45a8ff	3971	break;
bogdanm	0:9b334a45a8ff	3972
bogdanm	0:9b334a45a8ff	3973	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	3974	{
bogdanm	0:9b334a45a8ff	3975	/* Check whether or not the timer instance supports internal trigger input */
bogdanm	0:9b334a45a8ff	3976	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3977
bogdanm	0:9b334a45a8ff	3978	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	3979	}
bogdanm	0:9b334a45a8ff	3980	break;
bogdanm	0:9b334a45a8ff	3981
bogdanm	0:9b334a45a8ff	3982	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	3983	{
bogdanm	0:9b334a45a8ff	3984	/* Check whether or not the timer instance supports internal trigger input */
bogdanm	0:9b334a45a8ff	3985	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3986
bogdanm	0:9b334a45a8ff	3987	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	3988	}
bogdanm	0:9b334a45a8ff	3989	break;
bogdanm	0:9b334a45a8ff	3990
bogdanm	0:9b334a45a8ff	3991	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	3992	{
bogdanm	0:9b334a45a8ff	3993	/* Check whether or not the timer instance supports internal trigger input */
bogdanm	0:9b334a45a8ff	3994	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3995
bogdanm	0:9b334a45a8ff	3996	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	3997	}
bogdanm	0:9b334a45a8ff	3998	break;
bogdanm	0:9b334a45a8ff	3999
bogdanm	0:9b334a45a8ff	4000	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	4001	{
bogdanm	0:9b334a45a8ff	4002	/* Check whether or not the timer instance supports internal trigger input */
bogdanm	0:9b334a45a8ff	4003	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4004
bogdanm	0:9b334a45a8ff	4005	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	4006	}
bogdanm	0:9b334a45a8ff	4007	break;
bogdanm	0:9b334a45a8ff	4008
bogdanm	0:9b334a45a8ff	4009	default:
bogdanm	0:9b334a45a8ff	4010	break;
bogdanm	0:9b334a45a8ff	4011	}
bogdanm	0:9b334a45a8ff	4012	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4013
bogdanm	0:9b334a45a8ff	4014	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4015
bogdanm	0:9b334a45a8ff	4016	return HAL_OK;
bogdanm	0:9b334a45a8ff	4017	}
bogdanm	0:9b334a45a8ff	4018
bogdanm	0:9b334a45a8ff	4019	/**
bogdanm	0:9b334a45a8ff	4020	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	4021	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	4022	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4023	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	4024	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	4025	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4026	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	4027	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	4028	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	4029	* @retval HAL status
bogdanm	0:9b334a45a8ff	4030	*/
bogdanm	0:9b334a45a8ff	4031	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	4032	{
bogdanm	0:9b334a45a8ff	4033	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4034
bogdanm	0:9b334a45a8ff	4035	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4036	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4037	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	4038
bogdanm	0:9b334a45a8ff	4039	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4040	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	4041
bogdanm	0:9b334a45a8ff	4042	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	4043	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	4044
bogdanm	0:9b334a45a8ff	4045	/* Set the TI1 selection */
bogdanm	0:9b334a45a8ff	4046	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	4047
bogdanm	0:9b334a45a8ff	4048	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	4049	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4050
bogdanm	0:9b334a45a8ff	4051	return HAL_OK;
bogdanm	0:9b334a45a8ff	4052	}
bogdanm	0:9b334a45a8ff	4053
bogdanm	0:9b334a45a8ff	4054	/**
bogdanm	0:9b334a45a8ff	4055	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	4056	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4057	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4058	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4059	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4060	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4061	* @retval HAL status
bogdanm	0:9b334a45a8ff	4062	*/
bogdanm	0:9b334a45a8ff	4063	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	4064	{
bogdanm	0:9b334a45a8ff	4065	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4066	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4067	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4068	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4069
bogdanm	0:9b334a45a8ff	4070	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4071
bogdanm	0:9b334a45a8ff	4072	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4073
bogdanm	0:9b334a45a8ff	4074	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4075
bogdanm	0:9b334a45a8ff	4076	/* Disable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4077	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4078
bogdanm	0:9b334a45a8ff	4079	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4080	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4081
bogdanm	0:9b334a45a8ff	4082	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4083
bogdanm	0:9b334a45a8ff	4084	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4085
bogdanm	0:9b334a45a8ff	4086	return HAL_OK;
bogdanm	0:9b334a45a8ff	4087	}
bogdanm	0:9b334a45a8ff	4088
bogdanm	0:9b334a45a8ff	4089	/**
bogdanm	0:9b334a45a8ff	4090	* @brief Configures the TIM in Slave mode in interrupt mode
bogdanm	0:9b334a45a8ff	4091	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4092	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4093	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4094	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4095	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4096	* @retval HAL status
bogdanm	0:9b334a45a8ff	4097	*/
bogdanm	0:9b334a45a8ff	4098	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4099	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4100	{
bogdanm	0:9b334a45a8ff	4101	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4102	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4103	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4104	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4105
bogdanm	0:9b334a45a8ff	4106	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4107
bogdanm	0:9b334a45a8ff	4108	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4109
bogdanm	0:9b334a45a8ff	4110	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4111
bogdanm	0:9b334a45a8ff	4112	/* Enable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4113	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4114
bogdanm	0:9b334a45a8ff	4115	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4116	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4117
bogdanm	0:9b334a45a8ff	4118	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4119
bogdanm	0:9b334a45a8ff	4120	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4121
bogdanm	0:9b334a45a8ff	4122	return HAL_OK;
bogdanm	0:9b334a45a8ff	4123	}
bogdanm	0:9b334a45a8ff	4124
bogdanm	0:9b334a45a8ff	4125	/**
bogdanm	0:9b334a45a8ff	4126	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	4127	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4128	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	4129	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4130	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	4131	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4132	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4133	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4134	* @retval Captured value
bogdanm	0:9b334a45a8ff	4135	*/
bogdanm	0:9b334a45a8ff	4136	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4137	{
bogdanm	0:9b334a45a8ff	4138	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4139
bogdanm	0:9b334a45a8ff	4140	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4141
bogdanm	0:9b334a45a8ff	4142	switch (Channel)
bogdanm	0:9b334a45a8ff	4143	{
bogdanm	0:9b334a45a8ff	4144	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4145	{
bogdanm	0:9b334a45a8ff	4146	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4147	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4148
bogdanm	0:9b334a45a8ff	4149	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4150	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4151
bogdanm	0:9b334a45a8ff	4152	break;
bogdanm	0:9b334a45a8ff	4153	}
bogdanm	0:9b334a45a8ff	4154	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4155	{
bogdanm	0:9b334a45a8ff	4156	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4157	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4158
bogdanm	0:9b334a45a8ff	4159	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4160	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4161
bogdanm	0:9b334a45a8ff	4162	break;
bogdanm	0:9b334a45a8ff	4163	}
bogdanm	0:9b334a45a8ff	4164
bogdanm	0:9b334a45a8ff	4165	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4166	{
bogdanm	0:9b334a45a8ff	4167	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4168	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4169
bogdanm	0:9b334a45a8ff	4170	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4171	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4172
bogdanm	0:9b334a45a8ff	4173	break;
bogdanm	0:9b334a45a8ff	4174	}
bogdanm	0:9b334a45a8ff	4175
bogdanm	0:9b334a45a8ff	4176	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4177	{
bogdanm	0:9b334a45a8ff	4178	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4179	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4180
bogdanm	0:9b334a45a8ff	4181	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4182	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4183
bogdanm	0:9b334a45a8ff	4184	break;
bogdanm	0:9b334a45a8ff	4185	}
bogdanm	0:9b334a45a8ff	4186
bogdanm	0:9b334a45a8ff	4187	default:
bogdanm	0:9b334a45a8ff	4188	break;
bogdanm	0:9b334a45a8ff	4189	}
bogdanm	0:9b334a45a8ff	4190
bogdanm	0:9b334a45a8ff	4191	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4192	return tmpreg;
bogdanm	0:9b334a45a8ff	4193	}
bogdanm	0:9b334a45a8ff	4194
bogdanm	0:9b334a45a8ff	4195	/**
bogdanm	0:9b334a45a8ff	4196	* @}
bogdanm	0:9b334a45a8ff	4197	*/
bogdanm	0:9b334a45a8ff	4198
bogdanm	0:9b334a45a8ff	4199	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4200	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4201	*
bogdanm	0:9b334a45a8ff	4202	@verbatim
bogdanm	0:9b334a45a8ff	4203	==============================================================================
bogdanm	0:9b334a45a8ff	4204	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4205	==============================================================================
bogdanm	0:9b334a45a8ff	4206	[..]
bogdanm	0:9b334a45a8ff	4207	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4208	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4209	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4210	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4211	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4212	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4213
bogdanm	0:9b334a45a8ff	4214	@endverbatim
bogdanm	0:9b334a45a8ff	4215	* @{
bogdanm	0:9b334a45a8ff	4216	*/
bogdanm	0:9b334a45a8ff	4217
bogdanm	0:9b334a45a8ff	4218	/**
bogdanm	0:9b334a45a8ff	4219	* @brief Period elapsed callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4220	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4221	* @retval None
bogdanm	0:9b334a45a8ff	4222	*/
bogdanm	0:9b334a45a8ff	4223	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4224	{
bogdanm	0:9b334a45a8ff	4225	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4226	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4227	*/
bogdanm	0:9b334a45a8ff	4228
bogdanm	0:9b334a45a8ff	4229	}
bogdanm	0:9b334a45a8ff	4230	/**
bogdanm	0:9b334a45a8ff	4231	* @brief Output Compare callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4232	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	4233	* @retval None
bogdanm	0:9b334a45a8ff	4234	*/
bogdanm	0:9b334a45a8ff	4235	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4236	{
bogdanm	0:9b334a45a8ff	4237	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4238	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4239	*/
bogdanm	0:9b334a45a8ff	4240	}
bogdanm	0:9b334a45a8ff	4241	/**
bogdanm	0:9b334a45a8ff	4242	* @brief Input Capture callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4243	* @param htim : TIM IC handle
bogdanm	0:9b334a45a8ff	4244	* @retval None
bogdanm	0:9b334a45a8ff	4245	*/
bogdanm	0:9b334a45a8ff	4246	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4247	{
bogdanm	0:9b334a45a8ff	4248	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4249	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4250	*/
bogdanm	0:9b334a45a8ff	4251	}
bogdanm	0:9b334a45a8ff	4252
bogdanm	0:9b334a45a8ff	4253	/**
bogdanm	0:9b334a45a8ff	4254	* @brief PWM Pulse finished callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4255	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4256	* @retval None
bogdanm	0:9b334a45a8ff	4257	*/
bogdanm	0:9b334a45a8ff	4258	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4259	{
bogdanm	0:9b334a45a8ff	4260	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4261	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4262	*/
bogdanm	0:9b334a45a8ff	4263	}
bogdanm	0:9b334a45a8ff	4264
bogdanm	0:9b334a45a8ff	4265	/**
bogdanm	0:9b334a45a8ff	4266	* @brief Hall Trigger detection callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4267	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4268	* @retval None
bogdanm	0:9b334a45a8ff	4269	*/
bogdanm	0:9b334a45a8ff	4270	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4271	{
bogdanm	0:9b334a45a8ff	4272	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4273	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4274	*/
bogdanm	0:9b334a45a8ff	4275	}
bogdanm	0:9b334a45a8ff	4276
bogdanm	0:9b334a45a8ff	4277	/**
bogdanm	0:9b334a45a8ff	4278	* @brief Timer error callback in non-blocking mode
bogdanm	0:9b334a45a8ff	4279	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4280	* @retval None
bogdanm	0:9b334a45a8ff	4281	*/
bogdanm	0:9b334a45a8ff	4282	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4283	{
bogdanm	0:9b334a45a8ff	4284	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4285	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4286	*/
bogdanm	0:9b334a45a8ff	4287	}
bogdanm	0:9b334a45a8ff	4288
bogdanm	0:9b334a45a8ff	4289	/**
bogdanm	0:9b334a45a8ff	4290	* @}
bogdanm	0:9b334a45a8ff	4291	*/
bogdanm	0:9b334a45a8ff	4292
bogdanm	0:9b334a45a8ff	4293	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	4294	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4295	*
bogdanm	0:9b334a45a8ff	4296	@verbatim
bogdanm	0:9b334a45a8ff	4297	==============================================================================
bogdanm	0:9b334a45a8ff	4298	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4299	==============================================================================
bogdanm	0:9b334a45a8ff	4300	[..]
bogdanm	0:9b334a45a8ff	4301	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4302	and the data flow.
bogdanm	0:9b334a45a8ff	4303
bogdanm	0:9b334a45a8ff	4304	@endverbatim
bogdanm	0:9b334a45a8ff	4305	* @{
bogdanm	0:9b334a45a8ff	4306	*/
bogdanm	0:9b334a45a8ff	4307
bogdanm	0:9b334a45a8ff	4308	/**
bogdanm	0:9b334a45a8ff	4309	* @brief Return the TIM Base handle state.
bogdanm	0:9b334a45a8ff	4310	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	4311	* @retval HAL state
bogdanm	0:9b334a45a8ff	4312	*/
bogdanm	0:9b334a45a8ff	4313	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4314	{
bogdanm	0:9b334a45a8ff	4315	return htim->State;
bogdanm	0:9b334a45a8ff	4316	}
bogdanm	0:9b334a45a8ff	4317
bogdanm	0:9b334a45a8ff	4318	/**
bogdanm	0:9b334a45a8ff	4319	* @brief Return the TIM OC handle state.
bogdanm	0:9b334a45a8ff	4320	* @param htim: TIM Ouput Compare handle
bogdanm	0:9b334a45a8ff	4321	* @retval HAL state
bogdanm	0:9b334a45a8ff	4322	*/
bogdanm	0:9b334a45a8ff	4323	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4324	{
bogdanm	0:9b334a45a8ff	4325	return htim->State;
bogdanm	0:9b334a45a8ff	4326	}
bogdanm	0:9b334a45a8ff	4327
bogdanm	0:9b334a45a8ff	4328	/**
bogdanm	0:9b334a45a8ff	4329	* @brief Return the TIM PWM handle state.
bogdanm	0:9b334a45a8ff	4330	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	4331	* @retval HAL state
bogdanm	0:9b334a45a8ff	4332	*/
bogdanm	0:9b334a45a8ff	4333	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4334	{
bogdanm	0:9b334a45a8ff	4335	return htim->State;
bogdanm	0:9b334a45a8ff	4336	}
bogdanm	0:9b334a45a8ff	4337
bogdanm	0:9b334a45a8ff	4338	/**
bogdanm	0:9b334a45a8ff	4339	* @brief Return the TIM Input Capture handle state.
bogdanm	0:9b334a45a8ff	4340	* @param htim: TIM IC handle
bogdanm	0:9b334a45a8ff	4341	* @retval HAL state
bogdanm	0:9b334a45a8ff	4342	*/
bogdanm	0:9b334a45a8ff	4343	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4344	{
bogdanm	0:9b334a45a8ff	4345	return htim->State;
bogdanm	0:9b334a45a8ff	4346	}
bogdanm	0:9b334a45a8ff	4347
bogdanm	0:9b334a45a8ff	4348	/**
bogdanm	0:9b334a45a8ff	4349	* @brief Return the TIM One Pulse Mode handle state.
bogdanm	0:9b334a45a8ff	4350	* @param htim: TIM OPM handle
bogdanm	0:9b334a45a8ff	4351	* @retval HAL state
bogdanm	0:9b334a45a8ff	4352	*/
bogdanm	0:9b334a45a8ff	4353	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4354	{
bogdanm	0:9b334a45a8ff	4355	return htim->State;
bogdanm	0:9b334a45a8ff	4356	}
bogdanm	0:9b334a45a8ff	4357
bogdanm	0:9b334a45a8ff	4358	/**
bogdanm	0:9b334a45a8ff	4359	* @brief Return the TIM Encoder Mode handle state.
bogdanm	0:9b334a45a8ff	4360	* @param htim: TIM Encoder handle
bogdanm	0:9b334a45a8ff	4361	* @retval HAL state
bogdanm	0:9b334a45a8ff	4362	*/
bogdanm	0:9b334a45a8ff	4363	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4364	{
bogdanm	0:9b334a45a8ff	4365	return htim->State;
bogdanm	0:9b334a45a8ff	4366	}
bogdanm	0:9b334a45a8ff	4367
bogdanm	0:9b334a45a8ff	4368	/**
bogdanm	0:9b334a45a8ff	4369	* @}
bogdanm	0:9b334a45a8ff	4370	*/
bogdanm	0:9b334a45a8ff	4371
bogdanm	0:9b334a45a8ff	4372	/**
bogdanm	0:9b334a45a8ff	4373	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4374	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4375	* @retval None
bogdanm	0:9b334a45a8ff	4376	*/
bogdanm	0:9b334a45a8ff	4377	void TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4378	{
bogdanm	0:9b334a45a8ff	4379	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4380
bogdanm	0:9b334a45a8ff	4381	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4382
bogdanm	0:9b334a45a8ff	4383	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4384	}
bogdanm	0:9b334a45a8ff	4385
bogdanm	0:9b334a45a8ff	4386	/**
bogdanm	0:9b334a45a8ff	4387	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4388	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4389	* @retval None
bogdanm	0:9b334a45a8ff	4390	*/
bogdanm	0:9b334a45a8ff	4391	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4392	{
bogdanm	0:9b334a45a8ff	4393	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4394
bogdanm	0:9b334a45a8ff	4395	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4396
bogdanm	0:9b334a45a8ff	4397	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4398	{
bogdanm	0:9b334a45a8ff	4399	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4400	}
bogdanm	0:9b334a45a8ff	4401	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4402	{
bogdanm	0:9b334a45a8ff	4403	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4404	}
bogdanm	0:9b334a45a8ff	4405	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4406	{
bogdanm	0:9b334a45a8ff	4407	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4408	}
bogdanm	0:9b334a45a8ff	4409	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4410	{
bogdanm	0:9b334a45a8ff	4411	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4412	}
bogdanm	0:9b334a45a8ff	4413
bogdanm	0:9b334a45a8ff	4414	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4415
bogdanm	0:9b334a45a8ff	4416	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4417	}
bogdanm	0:9b334a45a8ff	4418	/**
bogdanm	0:9b334a45a8ff	4419	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4420	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4421	* @retval None
bogdanm	0:9b334a45a8ff	4422	*/
bogdanm	0:9b334a45a8ff	4423	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4424	{
bogdanm	0:9b334a45a8ff	4425	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4426
bogdanm	0:9b334a45a8ff	4427	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4428
bogdanm	0:9b334a45a8ff	4429	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4430	{
bogdanm	0:9b334a45a8ff	4431	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4432	}
bogdanm	0:9b334a45a8ff	4433	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4434	{
bogdanm	0:9b334a45a8ff	4435	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4436	}
bogdanm	0:9b334a45a8ff	4437	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4438	{
bogdanm	0:9b334a45a8ff	4439	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4440	}
bogdanm	0:9b334a45a8ff	4441	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4442	{
bogdanm	0:9b334a45a8ff	4443	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4444	}
bogdanm	0:9b334a45a8ff	4445
bogdanm	0:9b334a45a8ff	4446	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4447
bogdanm	0:9b334a45a8ff	4448	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4449	}
bogdanm	0:9b334a45a8ff	4450
bogdanm	0:9b334a45a8ff	4451	/**
bogdanm	0:9b334a45a8ff	4452	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4453	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4454	* @retval None
bogdanm	0:9b334a45a8ff	4455	*/
bogdanm	0:9b334a45a8ff	4456	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4457	{
bogdanm	0:9b334a45a8ff	4458	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4459
bogdanm	0:9b334a45a8ff	4460	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4461
bogdanm	0:9b334a45a8ff	4462	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4463	}
bogdanm	0:9b334a45a8ff	4464
bogdanm	0:9b334a45a8ff	4465	/**
bogdanm	0:9b334a45a8ff	4466	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4467	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4468	* @retval None
bogdanm	0:9b334a45a8ff	4469	*/
bogdanm	0:9b334a45a8ff	4470	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4471	{
bogdanm	0:9b334a45a8ff	4472	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4473
bogdanm	0:9b334a45a8ff	4474	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4475
bogdanm	0:9b334a45a8ff	4476	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4477	}
bogdanm	0:9b334a45a8ff	4478
bogdanm	0:9b334a45a8ff	4479	/**
bogdanm	0:9b334a45a8ff	4480	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4481	* @param TIMx: TIM peripheral
bogdanm	0:9b334a45a8ff	4482	* @param Structure: TIM Base configuration structure
bogdanm	0:9b334a45a8ff	4483	* @retval None
bogdanm	0:9b334a45a8ff	4484	*/
bogdanm	0:9b334a45a8ff	4485	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4486	{
bogdanm	0:9b334a45a8ff	4487	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4488	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4489
bogdanm	0:9b334a45a8ff	4490	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4491	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4492	{
bogdanm	0:9b334a45a8ff	4493	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4494	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4495	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4496	}
bogdanm	0:9b334a45a8ff	4497
bogdanm	0:9b334a45a8ff	4498	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4499	{
bogdanm	0:9b334a45a8ff	4500	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4501	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4502	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4503	}
bogdanm	0:9b334a45a8ff	4504
bogdanm	0:9b334a45a8ff	4505	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4506
bogdanm	0:9b334a45a8ff	4507	/* Set the Autoreload value */
bogdanm	0:9b334a45a8ff	4508	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4509
bogdanm	0:9b334a45a8ff	4510	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4511	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4512
bogdanm	0:9b334a45a8ff	4513	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4514	{
bogdanm	0:9b334a45a8ff	4515	/* Set the Repetition Counter value */
bogdanm	0:9b334a45a8ff	4516	TIMx->RCR = Structure->RepetitionCounter;
bogdanm	0:9b334a45a8ff	4517	}
bogdanm	0:9b334a45a8ff	4518
bogdanm	0:9b334a45a8ff	4519	/* Generate an update event to reload the Prescaler
bogdanm	0:9b334a45a8ff	4520	and the repetition counter(only for TIM1 and TIM8) value immediately */
bogdanm	0:9b334a45a8ff	4521	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4522	}
bogdanm	0:9b334a45a8ff	4523
bogdanm	0:9b334a45a8ff	4524	/**
bogdanm	0:9b334a45a8ff	4525	* @brief Time Ouput Compare 1 configuration
bogdanm	0:9b334a45a8ff	4526	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4527	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4528	* @retval None
bogdanm	0:9b334a45a8ff	4529	*/
bogdanm	0:9b334a45a8ff	4530	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4531	{
bogdanm	0:9b334a45a8ff	4532	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4533	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4534	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4535
bogdanm	0:9b334a45a8ff	4536	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4537	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4538
bogdanm	0:9b334a45a8ff	4539	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4540	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4541	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4542	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4543
bogdanm	0:9b334a45a8ff	4544	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4545	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4546
bogdanm	0:9b334a45a8ff	4547	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4548	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4549	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4550	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4551	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4552
bogdanm	0:9b334a45a8ff	4553	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4554	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4555	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4556	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4557
bogdanm	0:9b334a45a8ff	4558	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
bogdanm	0:9b334a45a8ff	4559	{
bogdanm	0:9b334a45a8ff	4560	/* Check parameters */
bogdanm	0:9b334a45a8ff	4561	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4562
bogdanm	0:9b334a45a8ff	4563	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4564	tmpccer &= ~TIM_CCER_CC1NP;
bogdanm	0:9b334a45a8ff	4565	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4566	tmpccer \|= OC_Config->OCNPolarity;
bogdanm	0:9b334a45a8ff	4567	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4568	tmpccer &= ~TIM_CCER_CC1NE;
bogdanm	0:9b334a45a8ff	4569	}
bogdanm	0:9b334a45a8ff	4570
bogdanm	0:9b334a45a8ff	4571	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4572	{
bogdanm	0:9b334a45a8ff	4573	/* Check parameters */
bogdanm	0:9b334a45a8ff	4574	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4575	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4576
bogdanm	0:9b334a45a8ff	4577	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4578	tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm	0:9b334a45a8ff	4579	tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm	0:9b334a45a8ff	4580	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4581	tmpcr2 \|= OC_Config->OCIdleState;
bogdanm	0:9b334a45a8ff	4582	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4583	tmpcr2 \|= OC_Config->OCNIdleState;
bogdanm	0:9b334a45a8ff	4584	}
bogdanm	0:9b334a45a8ff	4585	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4586	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4587
bogdanm	0:9b334a45a8ff	4588	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4589	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4590
bogdanm	0:9b334a45a8ff	4591	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4592	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4593
bogdanm	0:9b334a45a8ff	4594	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4595	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4596	}
bogdanm	0:9b334a45a8ff	4597
bogdanm	0:9b334a45a8ff	4598	/**
bogdanm	0:9b334a45a8ff	4599	* @brief Time Ouput Compare 2 configuration
bogdanm	0:9b334a45a8ff	4600	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4601	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4602	* @retval None
bogdanm	0:9b334a45a8ff	4603	*/
bogdanm	0:9b334a45a8ff	4604	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4605	{
bogdanm	0:9b334a45a8ff	4606	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4607	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4608	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4609
bogdanm	0:9b334a45a8ff	4610	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4611	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4612
bogdanm	0:9b334a45a8ff	4613	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4614	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4615	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4616	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4617
bogdanm	0:9b334a45a8ff	4618	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4619	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4620
bogdanm	0:9b334a45a8ff	4621	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4622	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4623	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4624
bogdanm	0:9b334a45a8ff	4625	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4626	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4627
bogdanm	0:9b334a45a8ff	4628	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4629	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4630	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4631	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4632
bogdanm	0:9b334a45a8ff	4633	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	4634	{
bogdanm	0:9b334a45a8ff	4635	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4636	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4637	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4638
bogdanm	0:9b334a45a8ff	4639	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4640	tmpccer &= ~TIM_CCER_CC2NP;
bogdanm	0:9b334a45a8ff	4641	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4642	tmpccer \|= (OC_Config->OCNPolarity << 4);
bogdanm	0:9b334a45a8ff	4643	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4644	tmpccer &= ~TIM_CCER_CC2NE;
bogdanm	0:9b334a45a8ff	4645
bogdanm	0:9b334a45a8ff	4646	}
bogdanm	0:9b334a45a8ff	4647
bogdanm	0:9b334a45a8ff	4648	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4649	{
bogdanm	0:9b334a45a8ff	4650	/* Check parameters */
bogdanm	0:9b334a45a8ff	4651	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4652	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4653
bogdanm	0:9b334a45a8ff	4654	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4655	tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm	0:9b334a45a8ff	4656	tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm	0:9b334a45a8ff	4657	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4658	tmpcr2 \|= (OC_Config->OCIdleState << 2);
bogdanm	0:9b334a45a8ff	4659	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4660	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
bogdanm	0:9b334a45a8ff	4661	}
bogdanm	0:9b334a45a8ff	4662
bogdanm	0:9b334a45a8ff	4663	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4664	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4665
bogdanm	0:9b334a45a8ff	4666	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4667	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4668
bogdanm	0:9b334a45a8ff	4669	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4670	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4671
bogdanm	0:9b334a45a8ff	4672	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4673	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4674	}
bogdanm	0:9b334a45a8ff	4675
bogdanm	0:9b334a45a8ff	4676	/**
bogdanm	0:9b334a45a8ff	4677	* @brief Time Ouput Compare 3 configuration
bogdanm	0:9b334a45a8ff	4678	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4679	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4680	* @retval None
bogdanm	0:9b334a45a8ff	4681	*/
bogdanm	0:9b334a45a8ff	4682	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4683	{
bogdanm	0:9b334a45a8ff	4684	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4685	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4686	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4687
bogdanm	0:9b334a45a8ff	4688	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4689	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4690
bogdanm	0:9b334a45a8ff	4691	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4692	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4693	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4694	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4695
bogdanm	0:9b334a45a8ff	4696	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4697	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4698
bogdanm	0:9b334a45a8ff	4699	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4700	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4701	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4702	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4703	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4704
bogdanm	0:9b334a45a8ff	4705	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4706	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4707	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4708	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4709
bogdanm	0:9b334a45a8ff	4710	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	4711	{
bogdanm	0:9b334a45a8ff	4712	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4713	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4714	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4715
bogdanm	0:9b334a45a8ff	4716	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4717	tmpccer &= ~TIM_CCER_CC3NP;
bogdanm	0:9b334a45a8ff	4718	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4719	tmpccer \|= (OC_Config->OCNPolarity << 8);
bogdanm	0:9b334a45a8ff	4720	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4721	tmpccer &= ~TIM_CCER_CC3NE;
bogdanm	0:9b334a45a8ff	4722	}
bogdanm	0:9b334a45a8ff	4723
bogdanm	0:9b334a45a8ff	4724	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4725	{
bogdanm	0:9b334a45a8ff	4726	/* Check parameters */
bogdanm	0:9b334a45a8ff	4727	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4728	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4729
bogdanm	0:9b334a45a8ff	4730	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4731	tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm	0:9b334a45a8ff	4732	tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm	0:9b334a45a8ff	4733	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4734	tmpcr2 \|= (OC_Config->OCIdleState << 4);
bogdanm	0:9b334a45a8ff	4735	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4736	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
bogdanm	0:9b334a45a8ff	4737	}
bogdanm	0:9b334a45a8ff	4738
bogdanm	0:9b334a45a8ff	4739	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4740	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4741
bogdanm	0:9b334a45a8ff	4742	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4743	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4744
bogdanm	0:9b334a45a8ff	4745	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4746	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4747
bogdanm	0:9b334a45a8ff	4748	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4749	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4750	}
bogdanm	0:9b334a45a8ff	4751
bogdanm	0:9b334a45a8ff	4752	/**
bogdanm	0:9b334a45a8ff	4753	* @brief Time Ouput Compare 4 configuration
bogdanm	0:9b334a45a8ff	4754	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4755	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4756	* @retval None
bogdanm	0:9b334a45a8ff	4757	*/
bogdanm	0:9b334a45a8ff	4758	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4759	{
bogdanm	0:9b334a45a8ff	4760	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4761	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4762	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4763
bogdanm	0:9b334a45a8ff	4764	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4765	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4766
bogdanm	0:9b334a45a8ff	4767	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4768	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4769	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4770	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4771
bogdanm	0:9b334a45a8ff	4772	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4773	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4774
bogdanm	0:9b334a45a8ff	4775	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4776	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4777	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4778
bogdanm	0:9b334a45a8ff	4779	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4780	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4781
bogdanm	0:9b334a45a8ff	4782	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4783	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4784	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4785	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4786
bogdanm	0:9b334a45a8ff	4787	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4788	{
bogdanm	0:9b334a45a8ff	4789	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4790
bogdanm	0:9b334a45a8ff	4791	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	4792	tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm	0:9b334a45a8ff	4793	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4794	tmpcr2 \|= (OC_Config->OCIdleState << 6);
bogdanm	0:9b334a45a8ff	4795	}
bogdanm	0:9b334a45a8ff	4796
bogdanm	0:9b334a45a8ff	4797	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4798	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4799
bogdanm	0:9b334a45a8ff	4800	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4801	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4802
bogdanm	0:9b334a45a8ff	4803	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4804	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4805
bogdanm	0:9b334a45a8ff	4806	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4807	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4808	}
bogdanm	0:9b334a45a8ff	4809
bogdanm	0:9b334a45a8ff	4810	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4811	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4812	{
bogdanm	0:9b334a45a8ff	4813	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4814	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4815	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4816
bogdanm	0:9b334a45a8ff	4817	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4818	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4819
bogdanm	0:9b334a45a8ff	4820	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4821	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4822	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4823	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4824
bogdanm	0:9b334a45a8ff	4825	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4826	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4827	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4828	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4829
bogdanm	0:9b334a45a8ff	4830	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4831	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4832
bogdanm	0:9b334a45a8ff	4833	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4834	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4835	{
bogdanm	0:9b334a45a8ff	4836	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4837	{
bogdanm	0:9b334a45a8ff	4838	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4839	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4840	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4841	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4842	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4843	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4844	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4845	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4846	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4847	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4848	}
bogdanm	0:9b334a45a8ff	4849	break;
bogdanm	0:9b334a45a8ff	4850
bogdanm	0:9b334a45a8ff	4851	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	4852	{
bogdanm	0:9b334a45a8ff	4853	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4854	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4855	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4856
bogdanm	0:9b334a45a8ff	4857	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4858	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	4859	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4860	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	4861
bogdanm	0:9b334a45a8ff	4862	/* Set the filter */
bogdanm	0:9b334a45a8ff	4863	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4864	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	4865
bogdanm	0:9b334a45a8ff	4866	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4867	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4868	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4869
bogdanm	0:9b334a45a8ff	4870	}
bogdanm	0:9b334a45a8ff	4871	break;
bogdanm	0:9b334a45a8ff	4872
bogdanm	0:9b334a45a8ff	4873	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	4874	{
bogdanm	0:9b334a45a8ff	4875	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4876	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4877	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4878	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4879
bogdanm	0:9b334a45a8ff	4880	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4881	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4882	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4883	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4884	}
bogdanm	0:9b334a45a8ff	4885	break;
bogdanm	0:9b334a45a8ff	4886
bogdanm	0:9b334a45a8ff	4887	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	4888	{
bogdanm	0:9b334a45a8ff	4889	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4890	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4891	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4892	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4893
bogdanm	0:9b334a45a8ff	4894	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4895	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4896	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4897	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4898	}
bogdanm	0:9b334a45a8ff	4899	break;
bogdanm	0:9b334a45a8ff	4900
bogdanm	0:9b334a45a8ff	4901	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	4902	{
bogdanm	0:9b334a45a8ff	4903	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4904	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4905	}
bogdanm	0:9b334a45a8ff	4906	break;
bogdanm	0:9b334a45a8ff	4907
bogdanm	0:9b334a45a8ff	4908	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	4909	{
bogdanm	0:9b334a45a8ff	4910	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4911	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4912	}
bogdanm	0:9b334a45a8ff	4913	break;
bogdanm	0:9b334a45a8ff	4914
bogdanm	0:9b334a45a8ff	4915	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	4916	{
bogdanm	0:9b334a45a8ff	4917	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4918	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4919	}
bogdanm	0:9b334a45a8ff	4920	break;
bogdanm	0:9b334a45a8ff	4921
bogdanm	0:9b334a45a8ff	4922	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	4923	{
bogdanm	0:9b334a45a8ff	4924	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4925	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4926	}
bogdanm	0:9b334a45a8ff	4927	break;
bogdanm	0:9b334a45a8ff	4928
bogdanm	0:9b334a45a8ff	4929	default:
bogdanm	0:9b334a45a8ff	4930	break;
bogdanm	0:9b334a45a8ff	4931	}
bogdanm	0:9b334a45a8ff	4932	}
bogdanm	0:9b334a45a8ff	4933
bogdanm	0:9b334a45a8ff	4934	/**
bogdanm	0:9b334a45a8ff	4935	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	4936	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4937	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4938	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4939	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4940	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4941	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4942	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4943	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4944	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	4945	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	4946	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4947	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4948	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4949	* @retval None
bogdanm	0:9b334a45a8ff	4950	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm	0:9b334a45a8ff	4951	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	4952	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	4953	*/
bogdanm	0:9b334a45a8ff	4954	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4955	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4956	{
bogdanm	0:9b334a45a8ff	4957	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4958	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4959
bogdanm	0:9b334a45a8ff	4960	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4961	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4962	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4963	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4964
bogdanm	0:9b334a45a8ff	4965	/* Select the Input */
bogdanm	0:9b334a45a8ff	4966	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4967	{
bogdanm	0:9b334a45a8ff	4968	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4969	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	4970	}
bogdanm	0:9b334a45a8ff	4971	else
bogdanm	0:9b334a45a8ff	4972	{
bogdanm	0:9b334a45a8ff	4973	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	4974	}
bogdanm	0:9b334a45a8ff	4975
bogdanm	0:9b334a45a8ff	4976	/* Set the filter */
bogdanm	0:9b334a45a8ff	4977	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4978	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	4979
bogdanm	0:9b334a45a8ff	4980	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	4981	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	4982	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	4983
bogdanm	0:9b334a45a8ff	4984	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4985	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4986	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4987	}
bogdanm	0:9b334a45a8ff	4988
bogdanm	0:9b334a45a8ff	4989	/**
bogdanm	0:9b334a45a8ff	4990	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	4991	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4992	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4993	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4994	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4995	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4996	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4997	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4998	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4999	* @retval None
bogdanm	0:9b334a45a8ff	5000	*/
bogdanm	0:9b334a45a8ff	5001	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5002	{
bogdanm	0:9b334a45a8ff	5003	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5004	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5005
bogdanm	0:9b334a45a8ff	5006	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5007	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5008	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5009	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5010
bogdanm	0:9b334a45a8ff	5011	/* Set the filter */
bogdanm	0:9b334a45a8ff	5012	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5013	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	5014
bogdanm	0:9b334a45a8ff	5015	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5016	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5017	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	5018
bogdanm	0:9b334a45a8ff	5019	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5020	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5021	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5022	}
bogdanm	0:9b334a45a8ff	5023
bogdanm	0:9b334a45a8ff	5024	/**
bogdanm	0:9b334a45a8ff	5025	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	5026	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5027	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5028	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5029	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5030	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5031	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5032	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5033	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5034	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	5035	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	5036	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5037	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5038	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5039	* @retval None
bogdanm	0:9b334a45a8ff	5040	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm	0:9b334a45a8ff	5041	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5042	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5043	*/
bogdanm	0:9b334a45a8ff	5044	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5045	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5046	{
bogdanm	0:9b334a45a8ff	5047	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5048	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5049
bogdanm	0:9b334a45a8ff	5050	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5051	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5052	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5053	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5054
bogdanm	0:9b334a45a8ff	5055	/* Select the Input */
bogdanm	0:9b334a45a8ff	5056	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	5057	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5058
bogdanm	0:9b334a45a8ff	5059	/* Set the filter */
bogdanm	0:9b334a45a8ff	5060	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5061	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	5062
bogdanm	0:9b334a45a8ff	5063	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5064	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5065	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	5066
bogdanm	0:9b334a45a8ff	5067	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5068	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5069	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5070	}
bogdanm	0:9b334a45a8ff	5071
bogdanm	0:9b334a45a8ff	5072	/**
bogdanm	0:9b334a45a8ff	5073	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	5074	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5075	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5076	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5077	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5078	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5079	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5080	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5081	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5082	* @retval None
bogdanm	0:9b334a45a8ff	5083	*/
bogdanm	0:9b334a45a8ff	5084	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5085	{
bogdanm	0:9b334a45a8ff	5086	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5087	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5088
bogdanm	0:9b334a45a8ff	5089	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5090	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5091	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5092	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5093
bogdanm	0:9b334a45a8ff	5094	/* Set the filter */
bogdanm	0:9b334a45a8ff	5095	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5096	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	5097
bogdanm	0:9b334a45a8ff	5098	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5099	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5100	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	5101
bogdanm	0:9b334a45a8ff	5102	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5103	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5104	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5105	}
bogdanm	0:9b334a45a8ff	5106
bogdanm	0:9b334a45a8ff	5107	/**
bogdanm	0:9b334a45a8ff	5108	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	5109	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5110	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5111	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5112	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5113	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5114	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5115	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5116	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5117	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5118	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5119	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5120	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5121	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5122	* @retval None
bogdanm	0:9b334a45a8ff	5123	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm	0:9b334a45a8ff	5124	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5125	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5126	*/
bogdanm	0:9b334a45a8ff	5127	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5128	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5129	{
bogdanm	0:9b334a45a8ff	5130	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5131	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5132
bogdanm	0:9b334a45a8ff	5133	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	5134	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	5135	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5136	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5137
bogdanm	0:9b334a45a8ff	5138	/* Select the Input */
bogdanm	0:9b334a45a8ff	5139	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	5140	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5141
bogdanm	0:9b334a45a8ff	5142	/* Set the filter */
bogdanm	0:9b334a45a8ff	5143	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	5144	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	5145
bogdanm	0:9b334a45a8ff	5146	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	5147	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	5148	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	5149
bogdanm	0:9b334a45a8ff	5150	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5151	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5152	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5153	}
bogdanm	0:9b334a45a8ff	5154
bogdanm	0:9b334a45a8ff	5155	/**
bogdanm	0:9b334a45a8ff	5156	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	5157	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5158	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5159	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5160	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5161	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5162	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5163	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5164	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5165	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5166	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5167	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5168	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5169	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5170	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm	0:9b334a45a8ff	5171	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5172	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5173	* @retval None
bogdanm	0:9b334a45a8ff	5174	*/
bogdanm	0:9b334a45a8ff	5175	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5176	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5177	{
bogdanm	0:9b334a45a8ff	5178	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5179	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5180
bogdanm	0:9b334a45a8ff	5181	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	5182	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	5183	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5184	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5185
bogdanm	0:9b334a45a8ff	5186	/* Select the Input */
bogdanm	0:9b334a45a8ff	5187	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	5188	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5189
bogdanm	0:9b334a45a8ff	5190	/* Set the filter */
bogdanm	0:9b334a45a8ff	5191	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	5192	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	5193
bogdanm	0:9b334a45a8ff	5194	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	5195	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	5196	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	5197
bogdanm	0:9b334a45a8ff	5198	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5199	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5200	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	5201	}
bogdanm	0:9b334a45a8ff	5202
bogdanm	0:9b334a45a8ff	5203	/**
bogdanm	0:9b334a45a8ff	5204	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	5205	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5206	* @param InputTriggerSource: The Input Trigger source.
bogdanm	0:9b334a45a8ff	5207	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5208	* @arg TIM_TS_ITR0: Internal Trigger 0
bogdanm	0:9b334a45a8ff	5209	* @arg TIM_TS_ITR1: Internal Trigger 1
bogdanm	0:9b334a45a8ff	5210	* @arg TIM_TS_ITR2: Internal Trigger 2
bogdanm	0:9b334a45a8ff	5211	* @arg TIM_TS_ITR3: Internal Trigger 3
bogdanm	0:9b334a45a8ff	5212	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
bogdanm	0:9b334a45a8ff	5213	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	5214	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	5215	* @arg TIM_TS_ETRF: External Trigger input
bogdanm	0:9b334a45a8ff	5216	* @retval None
bogdanm	0:9b334a45a8ff	5217	*/
bogdanm	0:9b334a45a8ff	5218	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
bogdanm	0:9b334a45a8ff	5219	{
bogdanm	0:9b334a45a8ff	5220	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5221
bogdanm	0:9b334a45a8ff	5222	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5223	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5224	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	5225	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5226	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	5227	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	5228	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5229	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5230	}
bogdanm	0:9b334a45a8ff	5231	/**
bogdanm	0:9b334a45a8ff	5232	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	5233	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5234	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	5235	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5236	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
bogdanm	0:9b334a45a8ff	5237	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
bogdanm	0:9b334a45a8ff	5238	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
bogdanm	0:9b334a45a8ff	5239	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	5240	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	5241	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5242	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
bogdanm	0:9b334a45a8ff	5243	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
bogdanm	0:9b334a45a8ff	5244	* @param ExtTRGFilter: External Trigger Filter.
bogdanm	0:9b334a45a8ff	5245	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	5246	* @retval None
bogdanm	0:9b334a45a8ff	5247	*/
bogdanm	0:9b334a45a8ff	5248	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	5249	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	5250	{
bogdanm	0:9b334a45a8ff	5251	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5252
bogdanm	0:9b334a45a8ff	5253	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5254
bogdanm	0:9b334a45a8ff	5255	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	5256	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	5257
bogdanm	0:9b334a45a8ff	5258	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	5259	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	5260
bogdanm	0:9b334a45a8ff	5261	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5262	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5263	}
bogdanm	0:9b334a45a8ff	5264
bogdanm	0:9b334a45a8ff	5265	/**
bogdanm	0:9b334a45a8ff	5266	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	5267	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5268	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	5269	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5270	* @arg TIM_CHANNEL_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	5271	* @arg TIM_CHANNEL_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	5272	* @arg TIM_CHANNEL_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	5273	* @arg TIM_CHANNEL_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	5274	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	5275	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	5276	* @retval None
bogdanm	0:9b334a45a8ff	5277	*/
bogdanm	0:9b334a45a8ff	5278	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	5279	{
bogdanm	0:9b334a45a8ff	5280	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	5281
bogdanm	0:9b334a45a8ff	5282	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5283	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm	0:9b334a45a8ff	5284	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	5285
bogdanm	0:9b334a45a8ff	5286	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	5287
bogdanm	0:9b334a45a8ff	5288	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5289	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	5290
bogdanm	0:9b334a45a8ff	5291	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5292	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	5293	}
bogdanm	0:9b334a45a8ff	5294
bogdanm	0:9b334a45a8ff	5295
bogdanm	0:9b334a45a8ff	5296	/**
bogdanm	0:9b334a45a8ff	5297	* @}
bogdanm	0:9b334a45a8ff	5298	*/
bogdanm	0:9b334a45a8ff	5299
bogdanm	0:9b334a45a8ff	5300	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	5301	/**
bogdanm	0:9b334a45a8ff	5302	* @}
bogdanm	0:9b334a45a8ff	5303	*/
bogdanm	0:9b334a45a8ff	5304
bogdanm	0:9b334a45a8ff	5305	/**
bogdanm	0:9b334a45a8ff	5306	* @}
bogdanm	0:9b334a45a8ff	5307	*/
bogdanm	0:9b334a45a8ff	5308	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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