mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customized HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	@endverbatim
bogdanm	0:9b334a45a8ff	57	******************************************************************************
bogdanm	0:9b334a45a8ff	58	* @attention
bogdanm	0:9b334a45a8ff	59	*
bogdanm	0:9b334a45a8ff	60	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	61	*
bogdanm	0:9b334a45a8ff	62	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	63	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	64	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	65	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	66	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	67	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	68	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	69	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	70	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	71	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	72	*
bogdanm	0:9b334a45a8ff	73	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	74	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	75	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	76	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	77	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	78	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	79	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	80	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	81	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	82	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	83	*
bogdanm	0:9b334a45a8ff	84	******************************************************************************
bogdanm	0:9b334a45a8ff	85	*/
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	88	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	91	* @{
bogdanm	0:9b334a45a8ff	92	*/
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	95	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	96	* @{
bogdanm	0:9b334a45a8ff	97	*/
bogdanm	0:9b334a45a8ff	98	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	101	/* Private defines -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	102	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	103	* @{
bogdanm	0:9b334a45a8ff	104	*/
bogdanm	0:9b334a45a8ff	105	#define SPI_DEFAULT_TIMEOUT 50
bogdanm	0:9b334a45a8ff	106	/**
bogdanm	0:9b334a45a8ff	107	* @}
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	111	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	112	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	113	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	114	* @{
bogdanm	0:9b334a45a8ff	115	*/
bogdanm	0:9b334a45a8ff	116	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	117	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	118	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	119	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	120	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	121	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	122	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	123	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	124	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	125	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	126	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	127	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	128	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	129	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	130	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	131	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	132	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	133	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	134	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	135	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	136	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	137	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	138	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	139	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	140	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	141	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	142	/**
bogdanm	0:9b334a45a8ff	143	* @}
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	149	* @{
bogdanm	0:9b334a45a8ff	150	*/
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	153	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	154	*
bogdanm	0:9b334a45a8ff	155	@verbatim
bogdanm	0:9b334a45a8ff	156	===============================================================================
bogdanm	0:9b334a45a8ff	157	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	158	===============================================================================
bogdanm	0:9b334a45a8ff	159	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	160	de-initialize the SPIx peripheral:
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	163	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	166	the selected configuration:
bogdanm	0:9b334a45a8ff	167	(++) Mode
bogdanm	0:9b334a45a8ff	168	(++) Direction
bogdanm	0:9b334a45a8ff	169	(++) Data Size
bogdanm	0:9b334a45a8ff	170	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	171	(++) NSS Management
bogdanm	0:9b334a45a8ff	172	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	173	(++) FirstBit
bogdanm	0:9b334a45a8ff	174	(++) TIMode
bogdanm	0:9b334a45a8ff	175	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	176	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	177	(++) CRC Length, used only with Data8 and Data16
bogdanm	0:9b334a45a8ff	178	(++) FIFO reception threshold
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	181	of the selected SPIx peripheral.
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	@endverbatim
bogdanm	0:9b334a45a8ff	184	* @{
bogdanm	0:9b334a45a8ff	185	*/
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	/**
bogdanm	0:9b334a45a8ff	188	* @brief Initialize the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	189	* in the SPI_InitTypeDef and initialize the associated handle.
bogdanm	0:9b334a45a8ff	190	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	191	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	192	* @retval HAL status
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	195	{
bogdanm	0:9b334a45a8ff	196	uint32_t frxth;
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	199	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	200	{
bogdanm	0:9b334a45a8ff	201	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	202	}
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/* Check the parameters */
bogdanm	0:9b334a45a8ff	205	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	206	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	207	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	208	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	209	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	210	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	211	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	212	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
bogdanm	0:9b334a45a8ff	213	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	214	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	215	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	216	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	217	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	218	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	221	{
bogdanm	0:9b334a45a8ff	222	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	223	hspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	226	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	227	}
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/* Disable the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	232	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/* Align by default the rs fifo threshold on the data size */
bogdanm	0:9b334a45a8ff	235	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	236	{
bogdanm	0:9b334a45a8ff	237	frxth = SPI_RXFIFO_THRESHOLD_HF;
bogdanm	0:9b334a45a8ff	238	}
bogdanm	0:9b334a45a8ff	239	else
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	frxth = SPI_RXFIFO_THRESHOLD_QF;
bogdanm	0:9b334a45a8ff	242	}
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* CRC calculation is valid only for 16Bit and 8 Bit */
bogdanm	0:9b334a45a8ff	245	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	/* CRC must be disabled */
bogdanm	0:9b334a45a8ff	248	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
bogdanm	0:9b334a45a8ff	249	}
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	/* Align the CRC Length on the data size */
bogdanm	0:9b334a45a8ff	252	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
bogdanm	0:9b334a45a8ff	253	{
bogdanm	0:9b334a45a8ff	254	/* CRC Length aligned on the data size : value set by default */
bogdanm	0:9b334a45a8ff	255	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	256	{
bogdanm	0:9b334a45a8ff	257	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
bogdanm	0:9b334a45a8ff	258	}
bogdanm	0:9b334a45a8ff	259	else
bogdanm	0:9b334a45a8ff	260	{
bogdanm	0:9b334a45a8ff	261	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
bogdanm	0:9b334a45a8ff	262	}
bogdanm	0:9b334a45a8ff	263	}
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
bogdanm	0:9b334a45a8ff	266	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	267	Communication speed, First bit, CRC calculation state, CRC Length */
bogdanm	0:9b334a45a8ff	268	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
bogdanm	0:9b334a45a8ff	269	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	270	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	273	{
bogdanm	0:9b334a45a8ff	274	hspi->Instance->CR1\|= SPI_CR1_CRCL;
bogdanm	0:9b334a45a8ff	275	}
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	278	/* Configure : Rx Fifo Threshold */
bogdanm	0:9b334a45a8ff	279	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
bogdanm	0:9b334a45a8ff	280	hspi->Init.DataSize ) \| frxth;
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/---------------------------- SPIx CRCPOLY Configuration --------------------/
bogdanm	0:9b334a45a8ff	283	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	284	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	287	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	return HAL_OK;
bogdanm	0:9b334a45a8ff	290	}
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/**
bogdanm	0:9b334a45a8ff	293	* @brief DeInitialize the SPI peripheral.
bogdanm	0:9b334a45a8ff	294	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	295	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	296	* @retval HAL status
bogdanm	0:9b334a45a8ff	297	*/
bogdanm	0:9b334a45a8ff	298	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	299	{
bogdanm	0:9b334a45a8ff	300	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	301	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	302	{
bogdanm	0:9b334a45a8ff	303	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	304	}
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Check the parameters */
bogdanm	0:9b334a45a8ff	307	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	308	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	311	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	314	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	317	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	return HAL_OK;
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/**
bogdanm	0:9b334a45a8ff	325	* @brief Initialize the SPI MSP.
bogdanm	0:9b334a45a8ff	326	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	327	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	328	* @retval None
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	331	{
bogdanm	0:9b334a45a8ff	332	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	333	the HAL_SPI_MspInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335	}
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/**
bogdanm	0:9b334a45a8ff	338	* @brief DeInitialize the SPI MSP.
bogdanm	0:9b334a45a8ff	339	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	340	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	341	* @retval None
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	344	{
bogdanm	0:9b334a45a8ff	345	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	346	the HAL_SPI_MspDeInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348	}
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	/**
bogdanm	0:9b334a45a8ff	351	* @}
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	355	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	356	*
bogdanm	0:9b334a45a8ff	357	@verbatim
bogdanm	0:9b334a45a8ff	358	==============================================================================
bogdanm	0:9b334a45a8ff	359	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	360	===============================================================================
bogdanm	0:9b334a45a8ff	361	[..]
bogdanm	0:9b334a45a8ff	362	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	363	data transfers.
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	368	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	369	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	370	after finishing transfer.
bogdanm	0:9b334a45a8ff	371	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	372	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	373	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	374	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	375	using DMA mode.
bogdanm	0:9b334a45a8ff	376	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	377	will be executed respectively at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	378	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	381	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	@endverbatim
bogdanm	0:9b334a45a8ff	384	* @{
bogdanm	0:9b334a45a8ff	385	*/
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @brief Transmit an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	389	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	390	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	391	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	392	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	393	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	394	* @retval HAL status
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	397	{
bogdanm	0:9b334a45a8ff	398	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	399	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/* Process Locked */
bogdanm	0:9b334a45a8ff	404	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	409	goto error;
bogdanm	0:9b334a45a8ff	410	}
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	413	{
bogdanm	0:9b334a45a8ff	414	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	415	goto error;
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Set the transaction information */
bogdanm	0:9b334a45a8ff	419	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	420	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	421	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	422	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	423	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	424	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	425	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	426	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	429	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	430	{
bogdanm	0:9b334a45a8ff	431	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	435	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	436	{
bogdanm	0:9b334a45a8ff	437	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	438	}
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	441	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	442	{
bogdanm	0:9b334a45a8ff	443	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	444	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	445	}
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	448	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	449	{
bogdanm	0:9b334a45a8ff	450	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	451	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	452	{
bogdanm	0:9b334a45a8ff	453	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	454	if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
bogdanm	0:9b334a45a8ff	455	{
bogdanm	0:9b334a45a8ff	456	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	457	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	458	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	459	}
bogdanm	0:9b334a45a8ff	460	else
bogdanm	0:9b334a45a8ff	461	{
bogdanm	0:9b334a45a8ff	462	/* Timeout management */
bogdanm	0:9b334a45a8ff	463	if((Timeout == 0) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
bogdanm	0:9b334a45a8ff	464	{
bogdanm	0:9b334a45a8ff	465	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	466	goto error;
bogdanm	0:9b334a45a8ff	467	}
bogdanm	0:9b334a45a8ff	468	}
bogdanm	0:9b334a45a8ff	469	}
bogdanm	0:9b334a45a8ff	470	}
bogdanm	0:9b334a45a8ff	471	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	472	else
bogdanm	0:9b334a45a8ff	473	{
bogdanm	0:9b334a45a8ff	474	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	477	if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
bogdanm	0:9b334a45a8ff	478	{
bogdanm	0:9b334a45a8ff	479	if(hspi->TxXferCount > 1)
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	/* write on the data register in packing mode */
bogdanm	0:9b334a45a8ff	482	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	483	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	484	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	485	}
bogdanm	0:9b334a45a8ff	486	else
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	489	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	490	}
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492	else
bogdanm	0:9b334a45a8ff	493	{
bogdanm	0:9b334a45a8ff	494	/* Timeout management */
bogdanm	0:9b334a45a8ff	495	if((Timeout == 0) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	498	goto error;
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	505	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	506	{
bogdanm	0:9b334a45a8ff	507	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	508	}
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	511	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	514	}
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/* Clear overrun flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	517	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	520	}
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	523	{
bogdanm	0:9b334a45a8ff	524	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	525	}
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	error:
bogdanm	0:9b334a45a8ff	528	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	529	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	530	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	531	return errorcode;
bogdanm	0:9b334a45a8ff	532	}
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/**
bogdanm	0:9b334a45a8ff	535	* @brief Receive an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	536	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	537	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	538	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	539	* @param Size: amount of data to be received
bogdanm	0:9b334a45a8ff	540	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	541	* @retval HAL status
bogdanm	0:9b334a45a8ff	542	*/
bogdanm	0:9b334a45a8ff	543	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	544	{
bogdanm	0:9b334a45a8ff	545	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	546	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	547	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	550	{
bogdanm	0:9b334a45a8ff	551	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	552	/* in this case we call the TransmitReceive process */
bogdanm	0:9b334a45a8ff	553	/* Process Locked */
bogdanm	0:9b334a45a8ff	554	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
bogdanm	0:9b334a45a8ff	555	}
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/* Process Locked */
bogdanm	0:9b334a45a8ff	558	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	561	{
bogdanm	0:9b334a45a8ff	562	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	563	goto error;
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	567	{
bogdanm	0:9b334a45a8ff	568	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	569	goto error;
bogdanm	0:9b334a45a8ff	570	}
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	573	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	574	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	575	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	576	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	577	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	578	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	579	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	582	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	583	{
bogdanm	0:9b334a45a8ff	584	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	585	/* this is done to handle the CRCNEXT before the latest data */
bogdanm	0:9b334a45a8ff	586	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	587	}
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	590	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	591	{
bogdanm	0:9b334a45a8ff	592	/* set fiforxthresold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	593	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	594	}
bogdanm	0:9b334a45a8ff	595	else
bogdanm	0:9b334a45a8ff	596	{
bogdanm	0:9b334a45a8ff	597	/* set fiforxthresold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	598	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	599	}
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Configure communication direction 1Line and enabled SPI if needed */
bogdanm	0:9b334a45a8ff	602	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	603	{
bogdanm	0:9b334a45a8ff	604	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	608	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	609	{
bogdanm	0:9b334a45a8ff	610	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	611	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	612	}
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	615	{
bogdanm	0:9b334a45a8ff	616	/* Transfer loop */
bogdanm	0:9b334a45a8ff	617	while(hspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	/* Check the RXNE flag */
bogdanm	0:9b334a45a8ff	620	if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
bogdanm	0:9b334a45a8ff	621	{
bogdanm	0:9b334a45a8ff	622	/* read the received data */
bogdanm	0:9b334a45a8ff	623	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	624	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	625	}
bogdanm	0:9b334a45a8ff	626	else
bogdanm	0:9b334a45a8ff	627	{
bogdanm	0:9b334a45a8ff	628	/* Timeout management */
bogdanm	0:9b334a45a8ff	629	if((Timeout == 0) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
bogdanm	0:9b334a45a8ff	630	{
bogdanm	0:9b334a45a8ff	631	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	632	goto error;
bogdanm	0:9b334a45a8ff	633	}
bogdanm	0:9b334a45a8ff	634	}
bogdanm	0:9b334a45a8ff	635	}
bogdanm	0:9b334a45a8ff	636	}
bogdanm	0:9b334a45a8ff	637	else
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	/* Transfer loop */
bogdanm	0:9b334a45a8ff	640	while(hspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	641	{
bogdanm	0:9b334a45a8ff	642	/* Check the RXNE flag */
bogdanm	0:9b334a45a8ff	643	if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	646	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	647	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649	else
bogdanm	0:9b334a45a8ff	650	{
bogdanm	0:9b334a45a8ff	651	/* Timeout management */
bogdanm	0:9b334a45a8ff	652	if((Timeout == 0) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	655	goto error;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657	}
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659	}
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/* Handle the CRC Transmission */
bogdanm	0:9b334a45a8ff	662	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	663	{
bogdanm	0:9b334a45a8ff	664	/* freeze the CRC before the latest data */
bogdanm	0:9b334a45a8ff	665	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	/* Read the latest data */
bogdanm	0:9b334a45a8ff	668	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	669	{
bogdanm	0:9b334a45a8ff	670	/* the latest data has not been received */
bogdanm	0:9b334a45a8ff	671	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	672	goto error;
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	676	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	677	{
bogdanm	0:9b334a45a8ff	678	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	679	}
bogdanm	0:9b334a45a8ff	680	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	681	else
bogdanm	0:9b334a45a8ff	682	{
bogdanm	0:9b334a45a8ff	683	hspi->pRxBuffPtr = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	684	}
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	687	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* Flag Error*/
bogdanm	0:9b334a45a8ff	690	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	691	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	692	goto error;
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	696	{
bogdanm	0:9b334a45a8ff	697	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	698	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700	else
bogdanm	0:9b334a45a8ff	701	{
bogdanm	0:9b334a45a8ff	702	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	703	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	706	{
bogdanm	0:9b334a45a8ff	707	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	708	{
bogdanm	0:9b334a45a8ff	709	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	710	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	711	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	712	goto error;
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	715	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717	}
bogdanm	0:9b334a45a8ff	718	}
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	721	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	727	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	728	{
bogdanm	0:9b334a45a8ff	729	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	730	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	731	}
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	734	{
bogdanm	0:9b334a45a8ff	735	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	736	}
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	error :
bogdanm	0:9b334a45a8ff	739	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	740	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	741	return errorcode;
bogdanm	0:9b334a45a8ff	742	}
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/**
bogdanm	0:9b334a45a8ff	745	* @brief Transmit and Receive an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	746	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	747	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	748	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	749	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	750	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	751	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	752	* @retval HAL status
bogdanm	0:9b334a45a8ff	753	*/
bogdanm	0:9b334a45a8ff	754	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	755	{
bogdanm	0:9b334a45a8ff	756	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	757	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	758	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/* Process Locked */
bogdanm	0:9b334a45a8ff	763	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	766	{
bogdanm	0:9b334a45a8ff	767	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	768	goto error;
bogdanm	0:9b334a45a8ff	769	}
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	772	{
bogdanm	0:9b334a45a8ff	773	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	774	goto error;
bogdanm	0:9b334a45a8ff	775	}
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	778	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	779	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	780	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	781	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	782	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	783	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	784	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	787	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	793	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	796	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798	else
bogdanm	0:9b334a45a8ff	799	{
bogdanm	0:9b334a45a8ff	800	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	801	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	805	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	808	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	812	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	815	{
bogdanm	0:9b334a45a8ff	816	/* Check TXE flag */
bogdanm	0:9b334a45a8ff	817	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	820	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	821	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	824	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	825	{
bogdanm	0:9b334a45a8ff	826	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	827	}
bogdanm	0:9b334a45a8ff	828	}
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Check RXNE flag */
bogdanm	0:9b334a45a8ff	831	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	834	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	835	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	840	goto error;
bogdanm	0:9b334a45a8ff	841	}
bogdanm	0:9b334a45a8ff	842	}
bogdanm	0:9b334a45a8ff	843	}
bogdanm	0:9b334a45a8ff	844	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	845	else
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	848	{
bogdanm	0:9b334a45a8ff	849	/* check TXE flag */
bogdanm	0:9b334a45a8ff	850	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	851	{
bogdanm	0:9b334a45a8ff	852	if(hspi->TxXferCount > 1)
bogdanm	0:9b334a45a8ff	853	{
bogdanm	0:9b334a45a8ff	854	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	855	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	856	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	857	}
bogdanm	0:9b334a45a8ff	858	else
bogdanm	0:9b334a45a8ff	859	{
bogdanm	0:9b334a45a8ff	860	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	861	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	865	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	866	{
bogdanm	0:9b334a45a8ff	867	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	868	}
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	872	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	875	{
bogdanm	0:9b334a45a8ff	876	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	877	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	878	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	879	if(hspi->RxXferCount <= 1)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	/* set fiforxthresold before to switch on 8 bit data size */
bogdanm	0:9b334a45a8ff	882	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884	}
bogdanm	0:9b334a45a8ff	885	else
bogdanm	0:9b334a45a8ff	886	{
bogdanm	0:9b334a45a8ff	887	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	888	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	889	}
bogdanm	0:9b334a45a8ff	890	}
bogdanm	0:9b334a45a8ff	891	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	892	{
bogdanm	0:9b334a45a8ff	893	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	894	goto error;
bogdanm	0:9b334a45a8ff	895	}
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	900	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	901	{
bogdanm	0:9b334a45a8ff	902	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	903	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	904	{
bogdanm	0:9b334a45a8ff	905	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	906	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	907	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	908	goto error;
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	912	{
bogdanm	0:9b334a45a8ff	913	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	914	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	915	}
bogdanm	0:9b334a45a8ff	916	else
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	919	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	922	{
bogdanm	0:9b334a45a8ff	923	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	924	{
bogdanm	0:9b334a45a8ff	925	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	926	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	927	errorcode = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	928	goto error;
bogdanm	0:9b334a45a8ff	929	}
bogdanm	0:9b334a45a8ff	930	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	931	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	937	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	938	{
bogdanm	0:9b334a45a8ff	939	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	940	/* Clear CRC Flag */
bogdanm	0:9b334a45a8ff	941	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	944	}
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	947	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	948	{
bogdanm	0:9b334a45a8ff	949	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	953	{
bogdanm	0:9b334a45a8ff	954	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	955	}
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	error :
bogdanm	0:9b334a45a8ff	958	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	959	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	960	return errorcode;
bogdanm	0:9b334a45a8ff	961	}
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/**
bogdanm	0:9b334a45a8ff	964	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
bogdanm	0:9b334a45a8ff	965	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	966	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	967	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	968	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	969	* @retval HAL status
bogdanm	0:9b334a45a8ff	970	*/
bogdanm	0:9b334a45a8ff	971	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	972	{
bogdanm	0:9b334a45a8ff	973	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	974	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	/* Process Locked */
bogdanm	0:9b334a45a8ff	977	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	982	goto error;
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	986	{
bogdanm	0:9b334a45a8ff	987	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	988	goto error;
bogdanm	0:9b334a45a8ff	989	}
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* prepare the transfer */
bogdanm	0:9b334a45a8ff	992	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	993	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	994	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	995	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	996	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	997	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	998	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	999	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1000	hspi->RxISR = NULL;
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/* Set the function for IT treatment */
bogdanm	0:9b334a45a8ff	1003	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1004	{
bogdanm	0:9b334a45a8ff	1005	hspi->TxISR = SPI_TxISR_16BIT;
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007	else
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	hspi->TxISR = SPI_TxISR_8BIT;
bogdanm	0:9b334a45a8ff	1010	}
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1013	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1014	{
bogdanm	0:9b334a45a8ff	1015	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1019	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1025	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1032	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	error :
bogdanm	0:9b334a45a8ff	1036	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1037	return errorcode;
bogdanm	0:9b334a45a8ff	1038	}
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/**
bogdanm	0:9b334a45a8ff	1041	* @brief Receive an amount of data in non-blocking mode with Interrupt.
bogdanm	0:9b334a45a8ff	1042	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1043	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1044	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1045	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1046	* @retval HAL status
bogdanm	0:9b334a45a8ff	1047	*/
bogdanm	0:9b334a45a8ff	1048	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1049	{
bogdanm	0:9b334a45a8ff	1050	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	/* Process Locked */
bogdanm	0:9b334a45a8ff	1053	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1058	goto error;
bogdanm	0:9b334a45a8ff	1059	}
bogdanm	0:9b334a45a8ff	1060	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1061	{
bogdanm	0:9b334a45a8ff	1062	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1063	goto error;
bogdanm	0:9b334a45a8ff	1064	}
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	/* Configure communication */
bogdanm	0:9b334a45a8ff	1067	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1068	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1069	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1070	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1071	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1072	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1073	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1074	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1077	{
bogdanm	0:9b334a45a8ff	1078	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1079	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1080	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1081	/* in this we call the TransmitReceive process */
bogdanm	0:9b334a45a8ff	1082	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1086	{
bogdanm	0:9b334a45a8ff	1087	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1088	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1089	{
bogdanm	0:9b334a45a8ff	1090	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1091	}
bogdanm	0:9b334a45a8ff	1092	}
bogdanm	0:9b334a45a8ff	1093	else
bogdanm	0:9b334a45a8ff	1094	{
bogdanm	0:9b334a45a8ff	1095	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	hspi->TxISR = NULL;
bogdanm	0:9b334a45a8ff	1099	/* check the data size to adapt Rx threshold and the set the function for IT treatment */
bogdanm	0:9b334a45a8ff	1100	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1101	{
bogdanm	0:9b334a45a8ff	1102	/* set fiforxthresold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1103	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1104	hspi->RxISR = SPI_RxISR_16BIT;
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106	else
bogdanm	0:9b334a45a8ff	1107	{
bogdanm	0:9b334a45a8ff	1108	/* set fiforxthresold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1109	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1110	hspi->RxISR = SPI_RxISR_8BIT;
bogdanm	0:9b334a45a8ff	1111	}
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1114	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1115	{
bogdanm	0:9b334a45a8ff	1116	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1117	}
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1120	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1121	{
bogdanm	0:9b334a45a8ff	1122	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1123	}
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1126	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1129	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1130	{
bogdanm	0:9b334a45a8ff	1131	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1132	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1133	}
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	error :
bogdanm	0:9b334a45a8ff	1136	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1137	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1138	return errorcode;
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/**
bogdanm	0:9b334a45a8ff	1142	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
bogdanm	0:9b334a45a8ff	1143	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1144	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1145	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1146	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1147	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	1148	* @retval HAL status
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	1153	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/* Process locked */
bogdanm	0:9b334a45a8ff	1156	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	if(!((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1159	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
bogdanm	0:9b334a45a8ff	1160	{
bogdanm	0:9b334a45a8ff	1161	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1162	goto error;
bogdanm	0:9b334a45a8ff	1163	}
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1168	goto error;
bogdanm	0:9b334a45a8ff	1169	}
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1172	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1173	{
bogdanm	0:9b334a45a8ff	1174	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1175	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1176	{
bogdanm	0:9b334a45a8ff	1177	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1178	}
bogdanm	0:9b334a45a8ff	1179	}
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1182	{
bogdanm	0:9b334a45a8ff	1183	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1187	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1188	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1189	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1190	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1191	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1192	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/* Set the function for IT treatment */
bogdanm	0:9b334a45a8ff	1195	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1196	{
bogdanm	0:9b334a45a8ff	1197	hspi->RxISR = SPI_2linesRxISR_16BIT;
bogdanm	0:9b334a45a8ff	1198	hspi->TxISR = SPI_2linesTxISR_16BIT;
bogdanm	0:9b334a45a8ff	1199	}
bogdanm	0:9b334a45a8ff	1200	else
bogdanm	0:9b334a45a8ff	1201	{
bogdanm	0:9b334a45a8ff	1202	hspi->RxISR = SPI_2linesRxISR_8BIT;
bogdanm	0:9b334a45a8ff	1203	hspi->TxISR = SPI_2linesTxISR_8BIT;
bogdanm	0:9b334a45a8ff	1204	}
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1207	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1208	{
bogdanm	0:9b334a45a8ff	1209	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1210	}
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* check if packing mode is enabled and if there is more than 2 data to receive */
bogdanm	0:9b334a45a8ff	1213	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
bogdanm	0:9b334a45a8ff	1214	{
bogdanm	0:9b334a45a8ff	1215	/* set fiforxthresold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1216	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1217	}
bogdanm	0:9b334a45a8ff	1218	else
bogdanm	0:9b334a45a8ff	1219	{
bogdanm	0:9b334a45a8ff	1220	/* set fiforxthresold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1221	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1222	}
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1225	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1228	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1229	{
bogdanm	0:9b334a45a8ff	1230	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1231	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1232	}
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	error :
bogdanm	0:9b334a45a8ff	1235	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1236	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1237	return errorcode;
bogdanm	0:9b334a45a8ff	1238	}
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/**
bogdanm	0:9b334a45a8ff	1241	* @brief Transmit an amount of data in non-blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1242	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1243	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1244	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1245	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1246	* @retval HAL status
bogdanm	0:9b334a45a8ff	1247	*/
bogdanm	0:9b334a45a8ff	1248	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1249	{
bogdanm	0:9b334a45a8ff	1250	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	1251	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/* Process Locked */
bogdanm	0:9b334a45a8ff	1254	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1257	{
bogdanm	0:9b334a45a8ff	1258	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1259	goto error;
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1263	{
bogdanm	0:9b334a45a8ff	1264	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1265	goto error;
bogdanm	0:9b334a45a8ff	1266	}
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1269	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1270	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1271	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1272	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1273	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1274	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1275	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1278	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1279	{
bogdanm	0:9b334a45a8ff	1280	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1284	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1285	{
bogdanm	0:9b334a45a8ff	1286	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1287	}
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1290	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1293	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1296	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1299	/* packing mode is enabled only if the DMA setting is HALWORD */
bogdanm	0:9b334a45a8ff	1300	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1301	{
bogdanm	0:9b334a45a8ff	1302	/* Check the even/odd of the data size + crc if enabled */
bogdanm	0:9b334a45a8ff	1303	if((hspi->TxXferCount & 0x1) == 0)
bogdanm	0:9b334a45a8ff	1304	{
bogdanm	0:9b334a45a8ff	1305	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1306	hspi->TxXferCount = (hspi->TxXferCount >> 1);
bogdanm	0:9b334a45a8ff	1307	}
bogdanm	0:9b334a45a8ff	1308	else
bogdanm	0:9b334a45a8ff	1309	{
bogdanm	0:9b334a45a8ff	1310	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1311	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1312	}
bogdanm	0:9b334a45a8ff	1313	}
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1316	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1319	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1320	{
bogdanm	0:9b334a45a8ff	1321	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1322	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1323	}
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1326	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	error :
bogdanm	0:9b334a45a8ff	1329	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1330	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1331	return errorcode;
bogdanm	0:9b334a45a8ff	1332	}
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/**
bogdanm	0:9b334a45a8ff	1335	* @brief Receive an amount of data in non-blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1336	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1337	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1338	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1339	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1340	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1341	* @retval HAL status
bogdanm	0:9b334a45a8ff	1342	*/
bogdanm	0:9b334a45a8ff	1343	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1344	{
bogdanm	0:9b334a45a8ff	1345	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* Process Locked */
bogdanm	0:9b334a45a8ff	1348	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1351	{
bogdanm	0:9b334a45a8ff	1352	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1353	goto error;
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1357	{
bogdanm	0:9b334a45a8ff	1358	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1359	goto error;
bogdanm	0:9b334a45a8ff	1360	}
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1363	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1364	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1365	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1366	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1367	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1368	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1369	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1372	{
bogdanm	0:9b334a45a8ff	1373	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1374	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1375	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1376	/* in this case we call the TransmitReceive process */
bogdanm	0:9b334a45a8ff	1377	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1381	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1382	{
bogdanm	0:9b334a45a8ff	1383	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1384	}
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1387	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1388	{
bogdanm	0:9b334a45a8ff	1389	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/* packing mode management is enabled by the DMA settings */
bogdanm	0:9b334a45a8ff	1393	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	/* Restriction the DMA data received is not allowed in this mode */
bogdanm	0:9b334a45a8ff	1396	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1397	goto error;
bogdanm	0:9b334a45a8ff	1398	}
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1401	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1402	{
bogdanm	0:9b334a45a8ff	1403	/* set fiforxthresold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1404	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1405	}
bogdanm	0:9b334a45a8ff	1406	else
bogdanm	0:9b334a45a8ff	1407	{
bogdanm	0:9b334a45a8ff	1408	/* set fiforxthresold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1409	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1410	}
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1413	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1416	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1419	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1422	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1425	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1428	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1429	{
bogdanm	0:9b334a45a8ff	1430	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1431	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1432	}
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	error:
bogdanm	0:9b334a45a8ff	1435	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1436	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1437	return errorcode;
bogdanm	0:9b334a45a8ff	1438	}
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/**
bogdanm	0:9b334a45a8ff	1441	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1442	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1443	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1444	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1445	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1446	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1447	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1448	* @retval HAL status
bogdanm	0:9b334a45a8ff	1449	*/
bogdanm	0:9b334a45a8ff	1450	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1451	{
bogdanm	0:9b334a45a8ff	1452	HAL_StatusTypeDef errorcode = HAL_OK;
bogdanm	0:9b334a45a8ff	1453	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/* Process locked */
bogdanm	0:9b334a45a8ff	1456	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	if(!((hspi->State == HAL_SPI_STATE_READY) \|\|
bogdanm	0:9b334a45a8ff	1459	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
bogdanm	0:9b334a45a8ff	1460	{
bogdanm	0:9b334a45a8ff	1461	errorcode = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1462	goto error;
bogdanm	0:9b334a45a8ff	1463	}
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1466	{
bogdanm	0:9b334a45a8ff	1467	errorcode = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1468	goto error;
bogdanm	0:9b334a45a8ff	1469	}
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	/* check if the transmit Receive function is not called by a receive master */
bogdanm	0:9b334a45a8ff	1472	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1475	}
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1478	hspi->pTxBuffPtr = (uint8_t *)pTxData;
bogdanm	0:9b334a45a8ff	1479	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1480	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1481	hspi->pRxBuffPtr = (uint8_t *)pRxData;
bogdanm	0:9b334a45a8ff	1482	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1483	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	/* Reset CRC Calculation + increase the rxsize */
bogdanm	0:9b334a45a8ff	1486	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1487	{
bogdanm	0:9b334a45a8ff	1488	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1489	}
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/* Reset the threshold bit */
bogdanm	0:9b334a45a8ff	1492	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX \| SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/* the packing mode management is enabled by the DMA settings according the spi data size */
bogdanm	0:9b334a45a8ff	1495	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1496	{
bogdanm	0:9b334a45a8ff	1497	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1498	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1499	}
bogdanm	0:9b334a45a8ff	1500	else
bogdanm	0:9b334a45a8ff	1501	{
bogdanm	0:9b334a45a8ff	1502	/* set fiforxthresold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1503	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1506	{
bogdanm	0:9b334a45a8ff	1507	if((hspi->TxXferSize & 0x1) == 0x0)
bogdanm	0:9b334a45a8ff	1508	{
bogdanm	0:9b334a45a8ff	1509	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1510	hspi->TxXferCount = hspi->TxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1511	}
bogdanm	0:9b334a45a8ff	1512	else
bogdanm	0:9b334a45a8ff	1513	{
bogdanm	0:9b334a45a8ff	1514	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1515	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1516	}
bogdanm	0:9b334a45a8ff	1517	}
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1520	{
bogdanm	0:9b334a45a8ff	1521	/* set fiforxthresold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1522	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524	if((hspi->RxXferCount & 0x1) == 0x0 )
bogdanm	0:9b334a45a8ff	1525	{
bogdanm	0:9b334a45a8ff	1526	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1527	hspi->RxXferCount = hspi->RxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529	else
bogdanm	0:9b334a45a8ff	1530	{
bogdanm	0:9b334a45a8ff	1531	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1532	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1533	}
bogdanm	0:9b334a45a8ff	1534	}
bogdanm	0:9b334a45a8ff	1535	}
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	/* Set the SPI Rx DMA transfer complete callback if the transfer request is a
bogdanm	0:9b334a45a8ff	1538	reception request (RXNE) */
bogdanm	0:9b334a45a8ff	1539	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1540	{
bogdanm	0:9b334a45a8ff	1541	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1542	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1543	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1544	}
bogdanm	0:9b334a45a8ff	1545	else
bogdanm	0:9b334a45a8ff	1546	{
bogdanm	0:9b334a45a8ff	1547	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1548	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1549	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1550	}
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1553	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1556	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1559	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1562	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1563	hspi->hdmatx->XferHalfCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1564	hspi->hdmatx->XferCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1567	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1570	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1573	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1574	{
bogdanm	0:9b334a45a8ff	1575	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1576	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1577	}
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1580	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	error :
bogdanm	0:9b334a45a8ff	1583	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1584	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1585	return errorcode;
bogdanm	0:9b334a45a8ff	1586	}
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/**
bogdanm	0:9b334a45a8ff	1589	* @brief Pause the DMA Transfer.
bogdanm	0:9b334a45a8ff	1590	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1591	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1592	* @retval HAL status
bogdanm	0:9b334a45a8ff	1593	*/
bogdanm	0:9b334a45a8ff	1594	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1595	{
bogdanm	0:9b334a45a8ff	1596	/* Process Locked */
bogdanm	0:9b334a45a8ff	1597	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1600	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1603	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	return HAL_OK;
bogdanm	0:9b334a45a8ff	1606	}
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	/**
bogdanm	0:9b334a45a8ff	1609	* @brief Resume the DMA Transfer.
bogdanm	0:9b334a45a8ff	1610	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1611	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1612	* @retval HAL status
bogdanm	0:9b334a45a8ff	1613	*/
bogdanm	0:9b334a45a8ff	1614	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1615	{
bogdanm	0:9b334a45a8ff	1616	/* Process Locked */
bogdanm	0:9b334a45a8ff	1617	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1620	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1623	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	return HAL_OK;
bogdanm	0:9b334a45a8ff	1626	}
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/**
bogdanm	0:9b334a45a8ff	1629	* @brief Stop the DMA Transfer.
bogdanm	0:9b334a45a8ff	1630	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1631	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1632	* @retval HAL status
bogdanm	0:9b334a45a8ff	1633	*/
bogdanm	0:9b334a45a8ff	1634	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1635	{
bogdanm	0:9b334a45a8ff	1636	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1637	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1638	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1639	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1640	*/
bogdanm	0:9b334a45a8ff	1641
bogdanm	0:9b334a45a8ff	1642	/* Abort the SPI DMA tx channel */
bogdanm	0:9b334a45a8ff	1643	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1644	{
bogdanm	0:9b334a45a8ff	1645	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1646	}
bogdanm	0:9b334a45a8ff	1647	/* Abort the SPI DMA rx channel */
bogdanm	0:9b334a45a8ff	1648	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1649	{
bogdanm	0:9b334a45a8ff	1650	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1651	}
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1654	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1655	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1656	return HAL_OK;
bogdanm	0:9b334a45a8ff	1657	}
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	/**
bogdanm	0:9b334a45a8ff	1660	* @brief Handle SPI interrupt request.
bogdanm	0:9b334a45a8ff	1661	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1662	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1663	* @retval None
bogdanm	0:9b334a45a8ff	1664	*/
bogdanm	0:9b334a45a8ff	1665	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1666	{
bogdanm	0:9b334a45a8ff	1667	uint32_t itsource = hspi->Instance->CR2;
bogdanm	0:9b334a45a8ff	1668	uint32_t itflag = hspi->Instance->SR;
bogdanm	0:9b334a45a8ff	1669
bogdanm	0:9b334a45a8ff	1670	/* SPI in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1671	if(((itflag & SPI_FLAG_OVR) == RESET) &&
bogdanm	0:9b334a45a8ff	1672	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	1673	{
bogdanm	0:9b334a45a8ff	1674	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1675	return;
bogdanm	0:9b334a45a8ff	1676	}
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	/* SPI in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1679	if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1680	{
bogdanm	0:9b334a45a8ff	1681	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1682	return;
bogdanm	0:9b334a45a8ff	1683	}
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/* SPI in Error Treatment ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1686	if((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
bogdanm	0:9b334a45a8ff	1687	{
bogdanm	0:9b334a45a8ff	1688	/* SPI Overrun error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1689	if((itflag & SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1690	{
bogdanm	0:9b334a45a8ff	1691	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1692	{
bogdanm	0:9b334a45a8ff	1693	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1694	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1695	}
bogdanm	0:9b334a45a8ff	1696	else
bogdanm	0:9b334a45a8ff	1697	{
bogdanm	0:9b334a45a8ff	1698	return;
bogdanm	0:9b334a45a8ff	1699	}
bogdanm	0:9b334a45a8ff	1700	}
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	/* SPI Mode Fault error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1703	if((itflag & SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1704	{
bogdanm	0:9b334a45a8ff	1705	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
bogdanm	0:9b334a45a8ff	1706	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1707	}
bogdanm	0:9b334a45a8ff	1708
bogdanm	0:9b334a45a8ff	1709	/* SPI Frame error interrupt occurred ----------------------------------------*/
bogdanm	0:9b334a45a8ff	1710	if((itflag & SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1711	{
bogdanm	0:9b334a45a8ff	1712	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
bogdanm	0:9b334a45a8ff	1713	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715
bogdanm	0:9b334a45a8ff	1716	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1717	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1718	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1719	return;
bogdanm	0:9b334a45a8ff	1720	}
bogdanm	0:9b334a45a8ff	1721	}
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	/**
bogdanm	0:9b334a45a8ff	1724	* @brief Tx Transfer completed callback.
bogdanm	0:9b334a45a8ff	1725	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1726	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1727	* @retval None
bogdanm	0:9b334a45a8ff	1728	*/
bogdanm	0:9b334a45a8ff	1729	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1730	{
bogdanm	0:9b334a45a8ff	1731	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1732	the HAL_SPI_TxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1733	*/
bogdanm	0:9b334a45a8ff	1734	}
bogdanm	0:9b334a45a8ff	1735
bogdanm	0:9b334a45a8ff	1736	/**
bogdanm	0:9b334a45a8ff	1737	* @brief Rx Transfer completed callback.
bogdanm	0:9b334a45a8ff	1738	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1739	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1740	* @retval None
bogdanm	0:9b334a45a8ff	1741	*/
bogdanm	0:9b334a45a8ff	1742	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1743	{
bogdanm	0:9b334a45a8ff	1744	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1745	the HAL_SPI_RxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1746	*/
bogdanm	0:9b334a45a8ff	1747	}
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	/**
bogdanm	0:9b334a45a8ff	1750	* @brief Tx and Rx Transfer completed callback.
bogdanm	0:9b334a45a8ff	1751	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1752	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1753	* @retval None
bogdanm	0:9b334a45a8ff	1754	*/
bogdanm	0:9b334a45a8ff	1755	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1756	{
bogdanm	0:9b334a45a8ff	1757	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1758	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1759	*/
bogdanm	0:9b334a45a8ff	1760	}
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762	/**
bogdanm	0:9b334a45a8ff	1763	* @brief Tx Half Transfer completed callback.
bogdanm	0:9b334a45a8ff	1764	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1765	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1766	* @retval None
bogdanm	0:9b334a45a8ff	1767	*/
bogdanm	0:9b334a45a8ff	1768	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1769	{
bogdanm	0:9b334a45a8ff	1770	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1771	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1772	*/
bogdanm	0:9b334a45a8ff	1773	}
bogdanm	0:9b334a45a8ff	1774
bogdanm	0:9b334a45a8ff	1775	/**
bogdanm	0:9b334a45a8ff	1776	* @brief Rx Half Transfer completed callback.
bogdanm	0:9b334a45a8ff	1777	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1778	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1779	* @retval None
bogdanm	0:9b334a45a8ff	1780	*/
bogdanm	0:9b334a45a8ff	1781	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1782	{
bogdanm	0:9b334a45a8ff	1783	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1784	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1785	*/
bogdanm	0:9b334a45a8ff	1786	}
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788	/**
bogdanm	0:9b334a45a8ff	1789	* @brief Tx and Rx Half Transfer callback.
bogdanm	0:9b334a45a8ff	1790	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1791	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1792	* @retval None
bogdanm	0:9b334a45a8ff	1793	*/
bogdanm	0:9b334a45a8ff	1794	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1795	{
bogdanm	0:9b334a45a8ff	1796	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1797	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1798	*/
bogdanm	0:9b334a45a8ff	1799	}
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	/**
bogdanm	0:9b334a45a8ff	1802	* @brief SPI error callback.
bogdanm	0:9b334a45a8ff	1803	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1804	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1805	* @retval None
bogdanm	0:9b334a45a8ff	1806	*/
bogdanm	0:9b334a45a8ff	1807	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1808	{
bogdanm	0:9b334a45a8ff	1809	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1810	the HAL_SPI_ErrorCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1811	*/
bogdanm	0:9b334a45a8ff	1812	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1813	and user can use HAL_SPI_GetError() API to check the latest error occurred
bogdanm	0:9b334a45a8ff	1814	*/
bogdanm	0:9b334a45a8ff	1815	}
bogdanm	0:9b334a45a8ff	1816
bogdanm	0:9b334a45a8ff	1817	/**
bogdanm	0:9b334a45a8ff	1818	* @}
bogdanm	0:9b334a45a8ff	1819	*/
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1822	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1823	*
bogdanm	0:9b334a45a8ff	1824	@verbatim
bogdanm	0:9b334a45a8ff	1825	===============================================================================
bogdanm	0:9b334a45a8ff	1826	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1827	===============================================================================
bogdanm	0:9b334a45a8ff	1828	[..]
bogdanm	0:9b334a45a8ff	1829	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1830	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1831	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1832	@endverbatim
bogdanm	0:9b334a45a8ff	1833	* @{
bogdanm	0:9b334a45a8ff	1834	*/
bogdanm	0:9b334a45a8ff	1835
bogdanm	0:9b334a45a8ff	1836	/**
bogdanm	0:9b334a45a8ff	1837	* @brief Return the SPI handle state.
bogdanm	0:9b334a45a8ff	1838	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1839	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1840	* @retval SPI state
bogdanm	0:9b334a45a8ff	1841	*/
bogdanm	0:9b334a45a8ff	1842	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1843	{
bogdanm	0:9b334a45a8ff	1844	/* Return SPI handle state */
bogdanm	0:9b334a45a8ff	1845	return hspi->State;
bogdanm	0:9b334a45a8ff	1846	}
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	/**
bogdanm	0:9b334a45a8ff	1849	* @brief Return the SPI error code.
bogdanm	0:9b334a45a8ff	1850	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1851	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1852	* @retval SPI error code in bitmap format
bogdanm	0:9b334a45a8ff	1853	*/
bogdanm	0:9b334a45a8ff	1854	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1855	{
bogdanm	0:9b334a45a8ff	1856	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1857	}
bogdanm	0:9b334a45a8ff	1858
bogdanm	0:9b334a45a8ff	1859	/**
bogdanm	0:9b334a45a8ff	1860	* @}
bogdanm	0:9b334a45a8ff	1861	*/
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863
bogdanm	0:9b334a45a8ff	1864	/**
bogdanm	0:9b334a45a8ff	1865	* @}
bogdanm	0:9b334a45a8ff	1866	*/
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	1869	* @brief Private functions
bogdanm	0:9b334a45a8ff	1870	* @{
bogdanm	0:9b334a45a8ff	1871	*/
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	/**
bogdanm	0:9b334a45a8ff	1874	* @brief DMA SPI transmit process complete callback.
bogdanm	0:9b334a45a8ff	1875	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1876	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1877	* @retval None
bogdanm	0:9b334a45a8ff	1878	*/
bogdanm	0:9b334a45a8ff	1879	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1880	{
bogdanm	0:9b334a45a8ff	1881	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
bogdanm	0:9b334a45a8ff	1884	{
bogdanm	0:9b334a45a8ff	1885	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1886	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	1889	if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1890	{
bogdanm	0:9b334a45a8ff	1891	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1892	}
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
bogdanm	0:9b334a45a8ff	1895	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1896	{
bogdanm	0:9b334a45a8ff	1897	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1898	}
bogdanm	0:9b334a45a8ff	1899
bogdanm	0:9b334a45a8ff	1900	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1901	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1902
bogdanm	0:9b334a45a8ff	1903	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1904	{
bogdanm	0:9b334a45a8ff	1905	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1906	return;
bogdanm	0:9b334a45a8ff	1907	}
bogdanm	0:9b334a45a8ff	1908	}
bogdanm	0:9b334a45a8ff	1909	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1910	}
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	/**
bogdanm	0:9b334a45a8ff	1913	* @brief DMA SPI receive process complete callback.
bogdanm	0:9b334a45a8ff	1914	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1915	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1916	* @retval None
bogdanm	0:9b334a45a8ff	1917	*/
bogdanm	0:9b334a45a8ff	1918	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1919	{
bogdanm	0:9b334a45a8ff	1920	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
bogdanm	0:9b334a45a8ff	1923	{
bogdanm	0:9b334a45a8ff	1924	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	/* CRC handling */
bogdanm	0:9b334a45a8ff	1927	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1928	{
bogdanm	0:9b334a45a8ff	1929	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	1930	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1931	{
bogdanm	0:9b334a45a8ff	1932	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1933	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1934	}
bogdanm	0:9b334a45a8ff	1935	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1936	{
bogdanm	0:9b334a45a8ff	1937	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1938	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1939	}
bogdanm	0:9b334a45a8ff	1940	else
bogdanm	0:9b334a45a8ff	1941	{
bogdanm	0:9b334a45a8ff	1942	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1943	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	1946	{
bogdanm	0:9b334a45a8ff	1947	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1948	{
bogdanm	0:9b334a45a8ff	1949	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1950	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1951	}
bogdanm	0:9b334a45a8ff	1952	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1953	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1954	}
bogdanm	0:9b334a45a8ff	1955	}
bogdanm	0:9b334a45a8ff	1956	}
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
bogdanm	0:9b334a45a8ff	1959	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1960
bogdanm	0:9b334a45a8ff	1961	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	1962	if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1965	}
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1968	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1971	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1972	{
bogdanm	0:9b334a45a8ff	1973	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1974	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1975	}
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1978	{
bogdanm	0:9b334a45a8ff	1979	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1980	return;
bogdanm	0:9b334a45a8ff	1981	}
bogdanm	0:9b334a45a8ff	1982	}
bogdanm	0:9b334a45a8ff	1983	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1984	}
bogdanm	0:9b334a45a8ff	1985
bogdanm	0:9b334a45a8ff	1986	/**
bogdanm	0:9b334a45a8ff	1987	* @brief DMA SPI transmit receive process complete callback.
bogdanm	0:9b334a45a8ff	1988	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1989	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1990	* @retval None
bogdanm	0:9b334a45a8ff	1991	*/
bogdanm	0:9b334a45a8ff	1992	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1993	{
bogdanm	0:9b334a45a8ff	1994	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1995
bogdanm	0:9b334a45a8ff	1996	if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
bogdanm	0:9b334a45a8ff	1997	{
bogdanm	0:9b334a45a8ff	1998	__IO int16_t tmpreg;
bogdanm	0:9b334a45a8ff	1999	/* CRC handling */
bogdanm	0:9b334a45a8ff	2000	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2001	{
bogdanm	0:9b334a45a8ff	2002	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
bogdanm	0:9b334a45a8ff	2003	{
bogdanm	0:9b334a45a8ff	2004	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2005	{
bogdanm	0:9b334a45a8ff	2006	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2007	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2008	}
bogdanm	0:9b334a45a8ff	2009	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2010	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2011	}
bogdanm	0:9b334a45a8ff	2012	else
bogdanm	0:9b334a45a8ff	2013	{
bogdanm	0:9b334a45a8ff	2014	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2015	{
bogdanm	0:9b334a45a8ff	2016	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2017	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2018	}
bogdanm	0:9b334a45a8ff	2019	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2020	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2021	}
bogdanm	0:9b334a45a8ff	2022	}
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2025	if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2026	{
bogdanm	0:9b334a45a8ff	2027	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2028	}
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	/* Disable Rx/Tx DMA Request */
bogdanm	0:9b334a45a8ff	2031	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2034	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2035	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2038	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2039	{
bogdanm	0:9b334a45a8ff	2040	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2041	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2042	}
bogdanm	0:9b334a45a8ff	2043
bogdanm	0:9b334a45a8ff	2044	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2045	{
bogdanm	0:9b334a45a8ff	2046	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2047	return;
bogdanm	0:9b334a45a8ff	2048	}
bogdanm	0:9b334a45a8ff	2049	}
bogdanm	0:9b334a45a8ff	2050	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2051	}
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	/**
bogdanm	0:9b334a45a8ff	2054	* @brief DMA SPI half transmit process complete callback.
bogdanm	0:9b334a45a8ff	2055	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2056	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2057	* @retval None
bogdanm	0:9b334a45a8ff	2058	*/
bogdanm	0:9b334a45a8ff	2059	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2060	{
bogdanm	0:9b334a45a8ff	2061	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2062
bogdanm	0:9b334a45a8ff	2063	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2064	}
bogdanm	0:9b334a45a8ff	2065
bogdanm	0:9b334a45a8ff	2066	/**
bogdanm	0:9b334a45a8ff	2067	* @brief DMA SPI half receive process complete callback.
bogdanm	0:9b334a45a8ff	2068	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2069	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2070	* @retval None
bogdanm	0:9b334a45a8ff	2071	*/
bogdanm	0:9b334a45a8ff	2072	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2075
bogdanm	0:9b334a45a8ff	2076	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2077	}
bogdanm	0:9b334a45a8ff	2078
bogdanm	0:9b334a45a8ff	2079	/**
bogdanm	0:9b334a45a8ff	2080	* @brief DMA SPI half transmit receive process complete callback.
bogdanm	0:9b334a45a8ff	2081	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2082	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2083	* @retval None
bogdanm	0:9b334a45a8ff	2084	*/
bogdanm	0:9b334a45a8ff	2085	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2086	{
bogdanm	0:9b334a45a8ff	2087	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2090	}
bogdanm	0:9b334a45a8ff	2091
bogdanm	0:9b334a45a8ff	2092	/**
bogdanm	0:9b334a45a8ff	2093	* @brief DMA SPI communication error callback.
bogdanm	0:9b334a45a8ff	2094	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2095	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2096	* @retval None
bogdanm	0:9b334a45a8ff	2097	*/
bogdanm	0:9b334a45a8ff	2098	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2099	{
bogdanm	0:9b334a45a8ff	2100	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2101
bogdanm	0:9b334a45a8ff	2102	/* Stop the disable DMA transfer on SPI side */
bogdanm	0:9b334a45a8ff	2103	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2104
bogdanm	0:9b334a45a8ff	2105	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	2106	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2107	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2108	}
bogdanm	0:9b334a45a8ff	2109
bogdanm	0:9b334a45a8ff	2110	/**
bogdanm	0:9b334a45a8ff	2111	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2112	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2113	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2114	* @retval None
bogdanm	0:9b334a45a8ff	2115	*/
bogdanm	0:9b334a45a8ff	2116	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2117	{
bogdanm	0:9b334a45a8ff	2118	/* Receive data in packing mode */
bogdanm	0:9b334a45a8ff	2119	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	2120	{
bogdanm	0:9b334a45a8ff	2121	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2122	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2123	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2124	if(hspi->RxXferCount == 1)
bogdanm	0:9b334a45a8ff	2125	{
bogdanm	0:9b334a45a8ff	2126	/* set fiforxthresold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	2127	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	2128	}
bogdanm	0:9b334a45a8ff	2129	}
bogdanm	0:9b334a45a8ff	2130	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2131	else
bogdanm	0:9b334a45a8ff	2132	{
bogdanm	0:9b334a45a8ff	2133	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2134	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2135	}
bogdanm	0:9b334a45a8ff	2136
bogdanm	0:9b334a45a8ff	2137	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2138	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2139	{
bogdanm	0:9b334a45a8ff	2140	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2141	{
bogdanm	0:9b334a45a8ff	2142	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2143	return;
bogdanm	0:9b334a45a8ff	2144	}
bogdanm	0:9b334a45a8ff	2145
bogdanm	0:9b334a45a8ff	2146	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2147	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2148
bogdanm	0:9b334a45a8ff	2149	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2150	{
bogdanm	0:9b334a45a8ff	2151	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2152	}
bogdanm	0:9b334a45a8ff	2153	}
bogdanm	0:9b334a45a8ff	2154	}
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	/**
bogdanm	0:9b334a45a8ff	2157	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2158	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2159	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2160	* @retval None
bogdanm	0:9b334a45a8ff	2161	*/
bogdanm	0:9b334a45a8ff	2162	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2163	{
bogdanm	0:9b334a45a8ff	2164	__IO uint8_t tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2165	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2170	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2171	{
bogdanm	0:9b334a45a8ff	2172	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2173	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2176	{
bogdanm	0:9b334a45a8ff	2177	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2178	}
bogdanm	0:9b334a45a8ff	2179	}
bogdanm	0:9b334a45a8ff	2180	}
bogdanm	0:9b334a45a8ff	2181
bogdanm	0:9b334a45a8ff	2182	/**
bogdanm	0:9b334a45a8ff	2183	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2184	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2185	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2186	* @retval None
bogdanm	0:9b334a45a8ff	2187	*/
bogdanm	0:9b334a45a8ff	2188	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2189	{
bogdanm	0:9b334a45a8ff	2190	/* Transmit data in packing Bit mode */
bogdanm	0:9b334a45a8ff	2191	if(hspi->TxXferCount >= 2)
bogdanm	0:9b334a45a8ff	2192	{
bogdanm	0:9b334a45a8ff	2193	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2194	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2195	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2196	}
bogdanm	0:9b334a45a8ff	2197	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2198	else
bogdanm	0:9b334a45a8ff	2199	{
bogdanm	0:9b334a45a8ff	2200	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2201	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2202	}
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	/* check the end of the transmission */
bogdanm	0:9b334a45a8ff	2205	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2206	{
bogdanm	0:9b334a45a8ff	2207	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2208	{
bogdanm	0:9b334a45a8ff	2209	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2210	}
bogdanm	0:9b334a45a8ff	2211	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2212	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2213
bogdanm	0:9b334a45a8ff	2214	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2215	{
bogdanm	0:9b334a45a8ff	2216	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2217	}
bogdanm	0:9b334a45a8ff	2218	}
bogdanm	0:9b334a45a8ff	2219	}
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	/**
bogdanm	0:9b334a45a8ff	2222	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2223	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2224	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2225	* @retval None
bogdanm	0:9b334a45a8ff	2226	*/
bogdanm	0:9b334a45a8ff	2227	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2228	{
bogdanm	0:9b334a45a8ff	2229	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2230	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2231	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2232	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2233
bogdanm	0:9b334a45a8ff	2234	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2235	{
bogdanm	0:9b334a45a8ff	2236	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2237	{
bogdanm	0:9b334a45a8ff	2238	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2239	return;
bogdanm	0:9b334a45a8ff	2240	}
bogdanm	0:9b334a45a8ff	2241
bogdanm	0:9b334a45a8ff	2242	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2243	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2246	{
bogdanm	0:9b334a45a8ff	2247	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2248	}
bogdanm	0:9b334a45a8ff	2249	}
bogdanm	0:9b334a45a8ff	2250	}
bogdanm	0:9b334a45a8ff	2251
bogdanm	0:9b334a45a8ff	2252	/**
bogdanm	0:9b334a45a8ff	2253	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2254	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2255	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2256	* @retval None
bogdanm	0:9b334a45a8ff	2257	*/
bogdanm	0:9b334a45a8ff	2258	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2259	{
bogdanm	0:9b334a45a8ff	2260	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2261	__IO uint16_t tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2262	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2263
bogdanm	0:9b334a45a8ff	2264	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2265	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2266
bogdanm	0:9b334a45a8ff	2267	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2268	}
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	/**
bogdanm	0:9b334a45a8ff	2271	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
bogdanm	0:9b334a45a8ff	2272	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2273	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2274	* @retval None
bogdanm	0:9b334a45a8ff	2275	*/
bogdanm	0:9b334a45a8ff	2276	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2277	{
bogdanm	0:9b334a45a8ff	2278	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2279	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2280	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2281	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2282
bogdanm	0:9b334a45a8ff	2283	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2284	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2285	{
bogdanm	0:9b334a45a8ff	2286	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2287	{
bogdanm	0:9b334a45a8ff	2288	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2289	}
bogdanm	0:9b334a45a8ff	2290	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2291	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2294	{
bogdanm	0:9b334a45a8ff	2295	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2296	}
bogdanm	0:9b334a45a8ff	2297	}
bogdanm	0:9b334a45a8ff	2298	}
bogdanm	0:9b334a45a8ff	2299
bogdanm	0:9b334a45a8ff	2300	/**
bogdanm	0:9b334a45a8ff	2301	* @brief Manage the CRC 8-bit receive in Interrupt context.
bogdanm	0:9b334a45a8ff	2302	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2303	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2304	* @retval None
bogdanm	0:9b334a45a8ff	2305	*/
bogdanm	0:9b334a45a8ff	2306	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2307	{
bogdanm	0:9b334a45a8ff	2308	__IO uint8_t tmpreg = ((uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2309	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2312
bogdanm	0:9b334a45a8ff	2313	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2314	{
bogdanm	0:9b334a45a8ff	2315	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2316	}
bogdanm	0:9b334a45a8ff	2317	}
bogdanm	0:9b334a45a8ff	2318
bogdanm	0:9b334a45a8ff	2319	/**
bogdanm	0:9b334a45a8ff	2320	* @brief Manage the receive 8-bit in Interrupt context.
bogdanm	0:9b334a45a8ff	2321	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2322	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2323	* @retval None
bogdanm	0:9b334a45a8ff	2324	*/
bogdanm	0:9b334a45a8ff	2325	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2326	{
bogdanm	0:9b334a45a8ff	2327	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2328	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2331	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2332	{
bogdanm	0:9b334a45a8ff	2333	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2334	}
bogdanm	0:9b334a45a8ff	2335
bogdanm	0:9b334a45a8ff	2336	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2337	{
bogdanm	0:9b334a45a8ff	2338	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2339	{
bogdanm	0:9b334a45a8ff	2340	hspi->RxISR = SPI_RxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2341	return;
bogdanm	0:9b334a45a8ff	2342	}
bogdanm	0:9b334a45a8ff	2343	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2344	}
bogdanm	0:9b334a45a8ff	2345	}
bogdanm	0:9b334a45a8ff	2346
bogdanm	0:9b334a45a8ff	2347	/**
bogdanm	0:9b334a45a8ff	2348	* @brief Manage the CRC 16-bit receive in Interrupt context.
bogdanm	0:9b334a45a8ff	2349	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2350	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2351	* @retval None
bogdanm	0:9b334a45a8ff	2352	*/
bogdanm	0:9b334a45a8ff	2353	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2354	{
bogdanm	0:9b334a45a8ff	2355	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	2356
bogdanm	0:9b334a45a8ff	2357	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2358	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2359
bogdanm	0:9b334a45a8ff	2360	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2361	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2364	}
bogdanm	0:9b334a45a8ff	2365
bogdanm	0:9b334a45a8ff	2366	/**
bogdanm	0:9b334a45a8ff	2367	* @brief Manage the 16-bit receive in Interrupt context.
bogdanm	0:9b334a45a8ff	2368	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2369	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2370	* @retval None
bogdanm	0:9b334a45a8ff	2371	*/
bogdanm	0:9b334a45a8ff	2372	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2373	{
bogdanm	0:9b334a45a8ff	2374	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2375	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2376	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2377
bogdanm	0:9b334a45a8ff	2378	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2379	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2380	{
bogdanm	0:9b334a45a8ff	2381	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2382	}
bogdanm	0:9b334a45a8ff	2383
bogdanm	0:9b334a45a8ff	2384	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2385	{
bogdanm	0:9b334a45a8ff	2386	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2387	{
bogdanm	0:9b334a45a8ff	2388	hspi->RxISR = SPI_RxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2389	return;
bogdanm	0:9b334a45a8ff	2390	}
bogdanm	0:9b334a45a8ff	2391	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2392	}
bogdanm	0:9b334a45a8ff	2393	}
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	/**
bogdanm	0:9b334a45a8ff	2396	* @brief Handle the data 8-bit transmit in Interrupt mode.
bogdanm	0:9b334a45a8ff	2397	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2398	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2399	* @retval None
bogdanm	0:9b334a45a8ff	2400	*/
bogdanm	0:9b334a45a8ff	2401	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2402	{
bogdanm	0:9b334a45a8ff	2403	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2404	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2405
bogdanm	0:9b334a45a8ff	2406	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2407	{
bogdanm	0:9b334a45a8ff	2408	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2409	{
bogdanm	0:9b334a45a8ff	2410	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2411	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2412	}
bogdanm	0:9b334a45a8ff	2413
bogdanm	0:9b334a45a8ff	2414	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2415	}
bogdanm	0:9b334a45a8ff	2416	}
bogdanm	0:9b334a45a8ff	2417
bogdanm	0:9b334a45a8ff	2418	/**
bogdanm	0:9b334a45a8ff	2419	* @brief Handle the data 16-bit transmit in Interrupt mode.
bogdanm	0:9b334a45a8ff	2420	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2421	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2422	* @retval None
bogdanm	0:9b334a45a8ff	2423	*/
bogdanm	0:9b334a45a8ff	2424	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2425	{
bogdanm	0:9b334a45a8ff	2426	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2427	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2428	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2429	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2430
bogdanm	0:9b334a45a8ff	2431	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2432	{
bogdanm	0:9b334a45a8ff	2433	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2434	{
bogdanm	0:9b334a45a8ff	2435	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2436	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2437	}
bogdanm	0:9b334a45a8ff	2438	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2439	}
bogdanm	0:9b334a45a8ff	2440	}
bogdanm	0:9b334a45a8ff	2441
bogdanm	0:9b334a45a8ff	2442	/**
bogdanm	0:9b334a45a8ff	2443	* @brief Handle SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2444	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2445	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2446	* @param Flag : SPI flag to check
bogdanm	0:9b334a45a8ff	2447	* @param State : flag state to check
bogdanm	0:9b334a45a8ff	2448	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2449	* @retval HAL status
bogdanm	0:9b334a45a8ff	2450	*/
bogdanm	0:9b334a45a8ff	2451	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2452	{
bogdanm	0:9b334a45a8ff	2453	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2454
bogdanm	0:9b334a45a8ff	2455	while((hspi->Instance->SR & Flag) != State)
bogdanm	0:9b334a45a8ff	2456	{
bogdanm	0:9b334a45a8ff	2457	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2458	{
bogdanm	0:9b334a45a8ff	2459	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2460	{
bogdanm	0:9b334a45a8ff	2461	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2462	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2463	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2464
bogdanm	0:9b334a45a8ff	2465	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2466	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2467
bogdanm	0:9b334a45a8ff	2468	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2469	{
bogdanm	0:9b334a45a8ff	2470	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2471	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2472	}
bogdanm	0:9b334a45a8ff	2473
bogdanm	0:9b334a45a8ff	2474	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2475	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2476	{
bogdanm	0:9b334a45a8ff	2477	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2478	}
bogdanm	0:9b334a45a8ff	2479
bogdanm	0:9b334a45a8ff	2480	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2483	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2486	}
bogdanm	0:9b334a45a8ff	2487	}
bogdanm	0:9b334a45a8ff	2488	}
bogdanm	0:9b334a45a8ff	2489
bogdanm	0:9b334a45a8ff	2490	return HAL_OK;
bogdanm	0:9b334a45a8ff	2491	}
bogdanm	0:9b334a45a8ff	2492
bogdanm	0:9b334a45a8ff	2493	/**
bogdanm	0:9b334a45a8ff	2494	* @brief Handle SPI FIFO Communication Timeout.
bogdanm	0:9b334a45a8ff	2495	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2496	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2497	* @param Fifo : Fifo to check
bogdanm	0:9b334a45a8ff	2498	* @param State : Fifo state to check
bogdanm	0:9b334a45a8ff	2499	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2500	* @retval HAL status
bogdanm	0:9b334a45a8ff	2501	*/
bogdanm	0:9b334a45a8ff	2502	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2503	{
bogdanm	0:9b334a45a8ff	2504	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2505	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2506
bogdanm	0:9b334a45a8ff	2507	while((hspi->Instance->SR & Fifo) != State)
bogdanm	0:9b334a45a8ff	2508	{
bogdanm	0:9b334a45a8ff	2509	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
bogdanm	0:9b334a45a8ff	2510	{
bogdanm	0:9b334a45a8ff	2511	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2512	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2513	}
bogdanm	0:9b334a45a8ff	2514
bogdanm	0:9b334a45a8ff	2515	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2516	{
bogdanm	0:9b334a45a8ff	2517	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2518	{
bogdanm	0:9b334a45a8ff	2519	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2520	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2521	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2522
bogdanm	0:9b334a45a8ff	2523	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2524	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2525
bogdanm	0:9b334a45a8ff	2526	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2527	{
bogdanm	0:9b334a45a8ff	2528	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2529	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2530	}
bogdanm	0:9b334a45a8ff	2531
bogdanm	0:9b334a45a8ff	2532	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2533	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2534	{
bogdanm	0:9b334a45a8ff	2535	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2536	}
bogdanm	0:9b334a45a8ff	2537
bogdanm	0:9b334a45a8ff	2538	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2539
bogdanm	0:9b334a45a8ff	2540	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2541	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2542
bogdanm	0:9b334a45a8ff	2543	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2544	}
bogdanm	0:9b334a45a8ff	2545	}
bogdanm	0:9b334a45a8ff	2546	}
bogdanm	0:9b334a45a8ff	2547
bogdanm	0:9b334a45a8ff	2548	return HAL_OK;
bogdanm	0:9b334a45a8ff	2549	}
bogdanm	0:9b334a45a8ff	2550
bogdanm	0:9b334a45a8ff	2551	/**
bogdanm	0:9b334a45a8ff	2552	* @brief Handle the check of the RX transaction complete.
bogdanm	0:9b334a45a8ff	2553	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2554	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2555	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2556	* @retval None
bogdanm	0:9b334a45a8ff	2557	*/
bogdanm	0:9b334a45a8ff	2558	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2559	{
bogdanm	0:9b334a45a8ff	2560	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2561	{
bogdanm	0:9b334a45a8ff	2562	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2563	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2564	}
bogdanm	0:9b334a45a8ff	2565
bogdanm	0:9b334a45a8ff	2566	/* Control the BSY flag */
bogdanm	0:9b334a45a8ff	2567	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2568	{
bogdanm	0:9b334a45a8ff	2569	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2570	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2571	}
bogdanm	0:9b334a45a8ff	2572
bogdanm	0:9b334a45a8ff	2573	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2574	{
bogdanm	0:9b334a45a8ff	2575	/* Empty the FRLVL fifo */
bogdanm	0:9b334a45a8ff	2576	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2577	{
bogdanm	0:9b334a45a8ff	2578	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2579	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2580	}
bogdanm	0:9b334a45a8ff	2581	}
bogdanm	0:9b334a45a8ff	2582	return HAL_OK;
bogdanm	0:9b334a45a8ff	2583	}
bogdanm	0:9b334a45a8ff	2584
bogdanm	0:9b334a45a8ff	2585	/**
bogdanm	0:9b334a45a8ff	2586	* @brief Handle the check of the RXTX or TX transaction complete.
bogdanm	0:9b334a45a8ff	2587	* @param hspi: SPI handle
bogdanm	0:9b334a45a8ff	2588	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2589	*/
bogdanm	0:9b334a45a8ff	2590	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2591	{
bogdanm	0:9b334a45a8ff	2592	/* Control if the TX fifo is empty */
bogdanm	0:9b334a45a8ff	2593	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2594	{
bogdanm	0:9b334a45a8ff	2595	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2596	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2597	}
bogdanm	0:9b334a45a8ff	2598	/* Control the BSY flag */
bogdanm	0:9b334a45a8ff	2599	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2600	{
bogdanm	0:9b334a45a8ff	2601	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2602	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2603	}
bogdanm	0:9b334a45a8ff	2604	return HAL_OK;
bogdanm	0:9b334a45a8ff	2605	}
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	/**
bogdanm	0:9b334a45a8ff	2608	* @brief Handle the end of the RXTX transaction.
bogdanm	0:9b334a45a8ff	2609	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2610	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2611	* @retval None
bogdanm	0:9b334a45a8ff	2612	*/
bogdanm	0:9b334a45a8ff	2613	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2614	{
bogdanm	0:9b334a45a8ff	2615	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	2616	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2619	if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
bogdanm	0:9b334a45a8ff	2620	{
bogdanm	0:9b334a45a8ff	2621	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2622	}
bogdanm	0:9b334a45a8ff	2623
bogdanm	0:9b334a45a8ff	2624	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2625	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2626	{
bogdanm	0:9b334a45a8ff	2627	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2628	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2629	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2630	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2631	}
bogdanm	0:9b334a45a8ff	2632	else
bogdanm	0:9b334a45a8ff	2633	{
bogdanm	0:9b334a45a8ff	2634	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2635	{
bogdanm	0:9b334a45a8ff	2636	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	2637	{
bogdanm	0:9b334a45a8ff	2638	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2639	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2640	}
bogdanm	0:9b334a45a8ff	2641	else
bogdanm	0:9b334a45a8ff	2642	{
bogdanm	0:9b334a45a8ff	2643	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2644	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2645	}
bogdanm	0:9b334a45a8ff	2646	}
bogdanm	0:9b334a45a8ff	2647	else
bogdanm	0:9b334a45a8ff	2648	{
bogdanm	0:9b334a45a8ff	2649	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2650	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2651	}
bogdanm	0:9b334a45a8ff	2652	}
bogdanm	0:9b334a45a8ff	2653	}
bogdanm	0:9b334a45a8ff	2654
bogdanm	0:9b334a45a8ff	2655	/**
bogdanm	0:9b334a45a8ff	2656	* @brief Handle the end of the RX transaction.
bogdanm	0:9b334a45a8ff	2657	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2658	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2659	* @retval None
bogdanm	0:9b334a45a8ff	2660	*/
bogdanm	0:9b334a45a8ff	2661	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2662	{
bogdanm	0:9b334a45a8ff	2663	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2664	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2665
bogdanm	0:9b334a45a8ff	2666	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2667	if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
bogdanm	0:9b334a45a8ff	2668	{
bogdanm	0:9b334a45a8ff	2669	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2670	}
bogdanm	0:9b334a45a8ff	2671	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2672
bogdanm	0:9b334a45a8ff	2673	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2674	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2675	{
bogdanm	0:9b334a45a8ff	2676	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2677	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2678	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2679	}
bogdanm	0:9b334a45a8ff	2680	else
bogdanm	0:9b334a45a8ff	2681	{
bogdanm	0:9b334a45a8ff	2682	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2683	{
bogdanm	0:9b334a45a8ff	2684	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2685	}
bogdanm	0:9b334a45a8ff	2686	else
bogdanm	0:9b334a45a8ff	2687	{
bogdanm	0:9b334a45a8ff	2688	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2689	}
bogdanm	0:9b334a45a8ff	2690	}
bogdanm	0:9b334a45a8ff	2691	}
bogdanm	0:9b334a45a8ff	2692
bogdanm	0:9b334a45a8ff	2693	/**
bogdanm	0:9b334a45a8ff	2694	* @brief Handle the end of the TX transaction.
bogdanm	0:9b334a45a8ff	2695	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2696	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2697	* @retval None
bogdanm	0:9b334a45a8ff	2698	*/
bogdanm	0:9b334a45a8ff	2699	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2700	{
bogdanm	0:9b334a45a8ff	2701	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2702	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2703
bogdanm	0:9b334a45a8ff	2704	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2705	if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
bogdanm	0:9b334a45a8ff	2706	{
bogdanm	0:9b334a45a8ff	2707	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2708	}
bogdanm	0:9b334a45a8ff	2709
bogdanm	0:9b334a45a8ff	2710	/* Clear overrun flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2711	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2712	{
bogdanm	0:9b334a45a8ff	2713	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2714	}
bogdanm	0:9b334a45a8ff	2715
bogdanm	0:9b334a45a8ff	2716	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2717	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2718	{
bogdanm	0:9b334a45a8ff	2719	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2720	}
bogdanm	0:9b334a45a8ff	2721	else
bogdanm	0:9b334a45a8ff	2722	{
bogdanm	0:9b334a45a8ff	2723	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2724	}
bogdanm	0:9b334a45a8ff	2725	}
bogdanm	0:9b334a45a8ff	2726
bogdanm	0:9b334a45a8ff	2727	/**
bogdanm	0:9b334a45a8ff	2728	* @}
bogdanm	0:9b334a45a8ff	2729	*/
bogdanm	0:9b334a45a8ff	2730
bogdanm	0:9b334a45a8ff	2731	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2732
bogdanm	0:9b334a45a8ff	2733	/**
bogdanm	0:9b334a45a8ff	2734	* @}
bogdanm	0:9b334a45a8ff	2735	*/
bogdanm	0:9b334a45a8ff	2736
bogdanm	0:9b334a45a8ff	2737	/**
bogdanm	0:9b334a45a8ff	2738	* @}
bogdanm	0:9b334a45a8ff	2739	*/
bogdanm	0:9b334a45a8ff	2740
bogdanm	0:9b334a45a8ff	2741	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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