mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_rcc_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Extended RCC HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities RCC extended peripheral:
bogdanm	0:9b334a45a8ff	10	* + Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	******************************************************************************
bogdanm	0:9b334a45a8ff	13	* @attention
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	18	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	19	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	20	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	22	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	23	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	25	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	26	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	27	*
bogdanm	0:9b334a45a8ff	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	38	*
bogdanm	0:9b334a45a8ff	39	******************************************************************************
bogdanm	0:9b334a45a8ff	40	*/
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	43	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	46	* @{
bogdanm	0:9b334a45a8ff	47	*/
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @defgroup RCCEx RCCEx
bogdanm	0:9b334a45a8ff	50	* @brief RCC Extended HAL module driver
bogdanm	0:9b334a45a8ff	51	* @{
bogdanm	0:9b334a45a8ff	52	*/
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	#ifdef HAL_RCC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	57	/* Private defines -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	#define PLLSAI1_TIMEOUT_VALUE 1000U /* Timeout value fixed to 100 ms */
bogdanm	0:9b334a45a8ff	62	#define PLLSAI2_TIMEOUT_VALUE 1000U /* Timeout value fixed to 100 ms */
bogdanm	0:9b334a45a8ff	63	#define PLL_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
bogdanm	0:9b334a45a8ff	64
bogdanm	0:9b334a45a8ff	65	#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	66	#define LSCO_GPIO_PORT GPIOA
bogdanm	0:9b334a45a8ff	67	#define LSCO_PIN GPIO_PIN_2
bogdanm	0:9b334a45a8ff	68	/**
bogdanm	0:9b334a45a8ff	69	* @}
bogdanm	0:9b334a45a8ff	70	*/
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	73	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	74	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	75	/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
bogdanm	0:9b334a45a8ff	76	* @{
bogdanm	0:9b334a45a8ff	77	*/
bogdanm	0:9b334a45a8ff	78	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PllSai1);
bogdanm	0:9b334a45a8ff	79	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PllSai1);
bogdanm	0:9b334a45a8ff	80	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PllSai1);
bogdanm	0:9b334a45a8ff	81	static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNP(RCC_PLLSAI2InitTypeDef *PllSai2);
bogdanm	0:9b334a45a8ff	82	static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNR(RCC_PLLSAI2InitTypeDef *PllSai2);
bogdanm	0:9b334a45a8ff	83	/**
bogdanm	0:9b334a45a8ff	84	* @}
bogdanm	0:9b334a45a8ff	85	*/
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm	0:9b334a45a8ff	90	* @{
bogdanm	0:9b334a45a8ff	91	*/
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	94	* @brief Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	95	*
bogdanm	0:9b334a45a8ff	96	@verbatim
bogdanm	0:9b334a45a8ff	97	===============================================================================
bogdanm	0:9b334a45a8ff	98	##### Extended Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	99	===============================================================================
bogdanm	0:9b334a45a8ff	100	[..]
bogdanm	0:9b334a45a8ff	101	This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm	0:9b334a45a8ff	102	frequencies.
bogdanm	0:9b334a45a8ff	103	[..]
bogdanm	0:9b334a45a8ff	104	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm	0:9b334a45a8ff	105	select the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	106	order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	107	the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	@endverbatim
bogdanm	0:9b334a45a8ff	110	* @{
bogdanm	0:9b334a45a8ff	111	*/
bogdanm	0:9b334a45a8ff	112	/**
bogdanm	0:9b334a45a8ff	113	* @brief Initialize the RCC extended peripherals clocks according to the specified
bogdanm	0:9b334a45a8ff	114	* parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	115	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	116	* contains the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	117	* clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART,
bogdanm	0:9b334a45a8ff	118	* USART1, USART2, USART3, UART4, UART5, RTC, ADC1, DFSDM, SWPMI1 and USB).
bogdanm	0:9b334a45a8ff	119	*
bogdanm	0:9b334a45a8ff	120	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm	0:9b334a45a8ff	121	* the RTC clock source: in this case the access to Backup domain is enabled.
bogdanm	0:9b334a45a8ff	122	*
bogdanm	0:9b334a45a8ff	123	* @retval HAL status
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	126	{
bogdanm	0:9b334a45a8ff	127	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	128	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	129	HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
bogdanm	0:9b334a45a8ff	130	HAL_StatusTypeDef status = HAL_OK; /* Final status */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	/* Check the parameters */
bogdanm	0:9b334a45a8ff	133	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/-------------------------- SAI1 clock source configuration ---------------------/
bogdanm	0:9b334a45a8ff	136	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
bogdanm	0:9b334a45a8ff	137	{
bogdanm	0:9b334a45a8ff	138	switch(PeriphClkInit->Sai1ClockSelection)
bogdanm	0:9b334a45a8ff	139	{
bogdanm	0:9b334a45a8ff	140	case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
bogdanm	0:9b334a45a8ff	141	/* Enable SAI Clock output generated form System PLL . */
bogdanm	0:9b334a45a8ff	142	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
bogdanm	0:9b334a45a8ff	143	/* SAI1 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	144	break;
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
bogdanm	0:9b334a45a8ff	147	/* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	148	ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	149	/* SAI1 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	150	break;
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
bogdanm	0:9b334a45a8ff	153	/* PLLSAI2 parameters N & P configuration and clock output (PLLSAI2ClockOut) */
bogdanm	0:9b334a45a8ff	154	ret = RCCEx_PLLSAI2_ConfigNP(&(PeriphClkInit->PLLSAI2));
bogdanm	0:9b334a45a8ff	155	/* SAI1 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	156	break;
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
bogdanm	0:9b334a45a8ff	159	/* SAI1 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	160	break;
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	default:
bogdanm	0:9b334a45a8ff	163	ret = HAL_ERROR;
bogdanm	0:9b334a45a8ff	164	break;
bogdanm	0:9b334a45a8ff	165	}
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	if(ret == HAL_OK)
bogdanm	0:9b334a45a8ff	168	{
bogdanm	0:9b334a45a8ff	169	/* Set the source of SAI1 clock*/
bogdanm	0:9b334a45a8ff	170	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
bogdanm	0:9b334a45a8ff	171	}
bogdanm	0:9b334a45a8ff	172	else
bogdanm	0:9b334a45a8ff	173	{
bogdanm	0:9b334a45a8ff	174	/* set overall return value */
bogdanm	0:9b334a45a8ff	175	status = ret;
bogdanm	0:9b334a45a8ff	176	}
bogdanm	0:9b334a45a8ff	177	}
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	/-------------------------- SAI2 clock source configuration ---------------------/
bogdanm	0:9b334a45a8ff	180	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	181	{
bogdanm	0:9b334a45a8ff	182	switch(PeriphClkInit->Sai2ClockSelection)
bogdanm	0:9b334a45a8ff	183	{
bogdanm	0:9b334a45a8ff	184	case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
bogdanm	0:9b334a45a8ff	185	/* Enable SAI Clock output generated form System PLL . */
bogdanm	0:9b334a45a8ff	186	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
bogdanm	0:9b334a45a8ff	187	/* SAI2 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	188	break;
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
bogdanm	0:9b334a45a8ff	191	/* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	192	ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	193	/* SAI2 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	194	break;
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
bogdanm	0:9b334a45a8ff	197	/* PLLSAI2 parameters N & P configuration and clock output (PLLSAI2ClockOut) */
bogdanm	0:9b334a45a8ff	198	ret = RCCEx_PLLSAI2_ConfigNP(&(PeriphClkInit->PLLSAI2));
bogdanm	0:9b334a45a8ff	199	/* SAI2 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	200	break;
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
bogdanm	0:9b334a45a8ff	203	/* SAI2 clock source config set later after clock selection check */
bogdanm	0:9b334a45a8ff	204	break;
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	default:
bogdanm	0:9b334a45a8ff	207	ret = HAL_ERROR;
bogdanm	0:9b334a45a8ff	208	break;
bogdanm	0:9b334a45a8ff	209	}
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	if(ret == HAL_OK)
bogdanm	0:9b334a45a8ff	212	{
bogdanm	0:9b334a45a8ff	213	/* Set the source of SAI2 clock*/
bogdanm	0:9b334a45a8ff	214	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
bogdanm	0:9b334a45a8ff	215	}
bogdanm	0:9b334a45a8ff	216	else
bogdanm	0:9b334a45a8ff	217	{
bogdanm	0:9b334a45a8ff	218	/* set overall return value */
bogdanm	0:9b334a45a8ff	219	status = ret;
bogdanm	0:9b334a45a8ff	220	}
bogdanm	0:9b334a45a8ff	221	}
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/-------------------------- RTC clock source configuration ----------------------/
bogdanm	0:9b334a45a8ff	224	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
bogdanm	0:9b334a45a8ff	225	{
bogdanm	0:9b334a45a8ff	226	FlagStatus pwrclkchanged = RESET;
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/* Check for RTC Parameters used to output RTCCLK */
bogdanm	0:9b334a45a8ff	229	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm	0:9b334a45a8ff	232	if(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) != PeriphClkInit->RTCClockSelection)
bogdanm	0:9b334a45a8ff	233	{
bogdanm	0:9b334a45a8ff	234	/* Enable Power Clock */
bogdanm	0:9b334a45a8ff	235	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
bogdanm	0:9b334a45a8ff	236	{
bogdanm	0:9b334a45a8ff	237	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	238	pwrclkchanged = SET;
bogdanm	0:9b334a45a8ff	239	}
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	242	SET_BIT(PWR->CR1, PWR_CR1_DBP);
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* Wait for Backup domain Write protection disable */
bogdanm	0:9b334a45a8ff	245	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	while((PWR->CR1 & PWR_CR1_DBP) == RESET)
bogdanm	0:9b334a45a8ff	248	{
bogdanm	0:9b334a45a8ff	249	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	ret = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	252	break;
bogdanm	0:9b334a45a8ff	253	}
bogdanm	0:9b334a45a8ff	254	}
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	if(ret == HAL_OK)
bogdanm	0:9b334a45a8ff	257	{
bogdanm	0:9b334a45a8ff	258	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	259	tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	260	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	261	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	262	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	263	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	264	RCC->BDCR = tmpreg;
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
bogdanm	0:9b334a45a8ff	268	if (HAL_IS_BIT_SET(tmpreg, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	269	{
bogdanm	0:9b334a45a8ff	270	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	271	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	274	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	277	{
bogdanm	0:9b334a45a8ff	278	ret = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	279	break;
bogdanm	0:9b334a45a8ff	280	}
bogdanm	0:9b334a45a8ff	281	}
bogdanm	0:9b334a45a8ff	282	}
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	if(ret == HAL_OK)
bogdanm	0:9b334a45a8ff	285	{
bogdanm	0:9b334a45a8ff	286	/* Apply new RTC clock source selection */
bogdanm	0:9b334a45a8ff	287	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Restore clock configuration if changed */
bogdanm	0:9b334a45a8ff	290	if(pwrclkchanged == SET)
bogdanm	0:9b334a45a8ff	291	{
bogdanm	0:9b334a45a8ff	292	__HAL_RCC_PWR_CLK_DISABLE();
bogdanm	0:9b334a45a8ff	293	}
bogdanm	0:9b334a45a8ff	294	}
bogdanm	0:9b334a45a8ff	295	else
bogdanm	0:9b334a45a8ff	296	{
bogdanm	0:9b334a45a8ff	297	/* set overall return value */
bogdanm	0:9b334a45a8ff	298	status = ret;
bogdanm	0:9b334a45a8ff	299	}
bogdanm	0:9b334a45a8ff	300	}
bogdanm	0:9b334a45a8ff	301	else
bogdanm	0:9b334a45a8ff	302	{
bogdanm	0:9b334a45a8ff	303	/* set overall return value */
bogdanm	0:9b334a45a8ff	304	status = ret;
bogdanm	0:9b334a45a8ff	305	}
bogdanm	0:9b334a45a8ff	306	}
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/-------------------------- USART1 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	309	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
bogdanm	0:9b334a45a8ff	310	{
bogdanm	0:9b334a45a8ff	311	/* Check the parameters */
bogdanm	0:9b334a45a8ff	312	assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Configure the USART1 clock source */
bogdanm	0:9b334a45a8ff	315	__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
bogdanm	0:9b334a45a8ff	316	}
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/-------------------------- USART2 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	319	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	/* Check the parameters */
bogdanm	0:9b334a45a8ff	322	assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/* Configure the USART2 clock source */
bogdanm	0:9b334a45a8ff	325	__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
bogdanm	0:9b334a45a8ff	326	}
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/-------------------------- USART3 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	329	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
bogdanm	0:9b334a45a8ff	330	{
bogdanm	0:9b334a45a8ff	331	/* Check the parameters */
bogdanm	0:9b334a45a8ff	332	assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/* Configure the USART3 clock source */
bogdanm	0:9b334a45a8ff	335	__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
bogdanm	0:9b334a45a8ff	336	}
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/-------------------------- UART4 clock source configuration --------------------/
bogdanm	0:9b334a45a8ff	339	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
bogdanm	0:9b334a45a8ff	340	{
bogdanm	0:9b334a45a8ff	341	/* Check the parameters */
bogdanm	0:9b334a45a8ff	342	assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/* Configure the UART4 clock source */
bogdanm	0:9b334a45a8ff	345	__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/-------------------------- UART5 clock source configuration --------------------/
bogdanm	0:9b334a45a8ff	349	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
bogdanm	0:9b334a45a8ff	350	{
bogdanm	0:9b334a45a8ff	351	/* Check the parameters */
bogdanm	0:9b334a45a8ff	352	assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/* Configure the UART5 clock source */
bogdanm	0:9b334a45a8ff	355	__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
bogdanm	0:9b334a45a8ff	356	}
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/-------------------------- LPUART1 clock source configuration ------------------/
bogdanm	0:9b334a45a8ff	359	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
bogdanm	0:9b334a45a8ff	360	{
bogdanm	0:9b334a45a8ff	361	/* Check the parameters */
bogdanm	0:9b334a45a8ff	362	assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/* Configure the LPUAR1 clock source */
bogdanm	0:9b334a45a8ff	365	__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/-------------------------- LPTIM1 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	369	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
bogdanm	0:9b334a45a8ff	370	{
bogdanm	0:9b334a45a8ff	371	assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
bogdanm	0:9b334a45a8ff	372	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
bogdanm	0:9b334a45a8ff	373	}
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/-------------------------- LPTIM2 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	376	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
bogdanm	0:9b334a45a8ff	377	{
bogdanm	0:9b334a45a8ff	378	assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
bogdanm	0:9b334a45a8ff	379	__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
bogdanm	0:9b334a45a8ff	380	}
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/-------------------------- I2C1 clock source configuration ---------------------/
bogdanm	0:9b334a45a8ff	383	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
bogdanm	0:9b334a45a8ff	384	{
bogdanm	0:9b334a45a8ff	385	/* Check the parameters */
bogdanm	0:9b334a45a8ff	386	assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	/* Configure the I2C1 clock source */
bogdanm	0:9b334a45a8ff	389	__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
bogdanm	0:9b334a45a8ff	390	}
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/-------------------------- I2C2 clock source configuration ---------------------/
bogdanm	0:9b334a45a8ff	393	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
bogdanm	0:9b334a45a8ff	394	{
bogdanm	0:9b334a45a8ff	395	/* Check the parameters */
bogdanm	0:9b334a45a8ff	396	assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/* Configure the I2C2 clock source */
bogdanm	0:9b334a45a8ff	399	__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
bogdanm	0:9b334a45a8ff	400	}
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/-------------------------- I2C3 clock source configuration ---------------------/
bogdanm	0:9b334a45a8ff	403	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	/* Check the parameters */
bogdanm	0:9b334a45a8ff	406	assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
bogdanm	0:9b334a45a8ff	407
bogdanm	0:9b334a45a8ff	408	/* Configure the I2C3 clock source */
bogdanm	0:9b334a45a8ff	409	__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
bogdanm	0:9b334a45a8ff	410	}
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
bogdanm	0:9b334a45a8ff	413	/-------------------------- USB clock source configuration ----------------------/
bogdanm	0:9b334a45a8ff	414	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
bogdanm	0:9b334a45a8ff	415	{
bogdanm	0:9b334a45a8ff	416	assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
bogdanm	0:9b334a45a8ff	417	__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
bogdanm	0:9b334a45a8ff	420	{
bogdanm	0:9b334a45a8ff	421	/* Enable PLL48M1CLK output */
bogdanm	0:9b334a45a8ff	422	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
bogdanm	0:9b334a45a8ff	423	}
bogdanm	0:9b334a45a8ff	424	else if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	425	{
bogdanm	0:9b334a45a8ff	426	/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	427	ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	if(ret != HAL_OK)
bogdanm	0:9b334a45a8ff	430	{
bogdanm	0:9b334a45a8ff	431	/* set overall return value */
bogdanm	0:9b334a45a8ff	432	status = ret;
bogdanm	0:9b334a45a8ff	433	}
bogdanm	0:9b334a45a8ff	434	}
bogdanm	0:9b334a45a8ff	435	}
bogdanm	0:9b334a45a8ff	436	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	/-------------------------- SDMMC1 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	439	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
bogdanm	0:9b334a45a8ff	440	{
bogdanm	0:9b334a45a8ff	441	assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
bogdanm	0:9b334a45a8ff	442	__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)
bogdanm	0:9b334a45a8ff	445	{
bogdanm	0:9b334a45a8ff	446	/* Enable PLL48M1CLK output */
bogdanm	0:9b334a45a8ff	447	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
bogdanm	0:9b334a45a8ff	448	}
bogdanm	0:9b334a45a8ff	449	else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	450	{
bogdanm	0:9b334a45a8ff	451	/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	452	ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	if(ret != HAL_OK)
bogdanm	0:9b334a45a8ff	455	{
bogdanm	0:9b334a45a8ff	456	/* set overall return value */
bogdanm	0:9b334a45a8ff	457	status = ret;
bogdanm	0:9b334a45a8ff	458	}
bogdanm	0:9b334a45a8ff	459	}
bogdanm	0:9b334a45a8ff	460	}
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	/-------------------------- RNG clock source configuration ----------------------/
bogdanm	0:9b334a45a8ff	463	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
bogdanm	0:9b334a45a8ff	464	{
bogdanm	0:9b334a45a8ff	465	assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
bogdanm	0:9b334a45a8ff	466	__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
bogdanm	0:9b334a45a8ff	469	{
bogdanm	0:9b334a45a8ff	470	/* Enable PLL48M1CLK output */
bogdanm	0:9b334a45a8ff	471	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
bogdanm	0:9b334a45a8ff	472	}
bogdanm	0:9b334a45a8ff	473	else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	474	{
bogdanm	0:9b334a45a8ff	475	/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	476	ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	if(ret != HAL_OK)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	/* set overall return value */
bogdanm	0:9b334a45a8ff	481	status = ret;
bogdanm	0:9b334a45a8ff	482	}
bogdanm	0:9b334a45a8ff	483	}
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	/-------------------------- ADC clock source configuration ----------------------/
bogdanm	0:9b334a45a8ff	487	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
bogdanm	0:9b334a45a8ff	488	{
bogdanm	0:9b334a45a8ff	489	/* Check the parameters */
bogdanm	0:9b334a45a8ff	490	assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* Configure the ADC interface clock source */
bogdanm	0:9b334a45a8ff	493	__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	/* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
bogdanm	0:9b334a45a8ff	498	ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500	else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
bogdanm	0:9b334a45a8ff	501	{
bogdanm	0:9b334a45a8ff	502	/* PLLSAI2 parameters N & R configuration and clock output (PLLSAI2ClockOut) */
bogdanm	0:9b334a45a8ff	503	ret = RCCEx_PLLSAI2_ConfigNR(&(PeriphClkInit->PLLSAI2));
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	if(ret != HAL_OK)
bogdanm	0:9b334a45a8ff	506	{
bogdanm	0:9b334a45a8ff	507	/* set overall return value */
bogdanm	0:9b334a45a8ff	508	status = ret;
bogdanm	0:9b334a45a8ff	509	}
bogdanm	0:9b334a45a8ff	510	}
bogdanm	0:9b334a45a8ff	511	}
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/-------------------------- SWPMI1 clock source configuration -------------------/
bogdanm	0:9b334a45a8ff	514	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
bogdanm	0:9b334a45a8ff	515	{
bogdanm	0:9b334a45a8ff	516	/* Check the parameters */
bogdanm	0:9b334a45a8ff	517	assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/* Configure the SWPMI1 clock source */
bogdanm	0:9b334a45a8ff	520	__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
bogdanm	0:9b334a45a8ff	521	}
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/-------------------------- DFSDM clock source configuration --------------------/
bogdanm	0:9b334a45a8ff	524	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM)
bogdanm	0:9b334a45a8ff	525	{
bogdanm	0:9b334a45a8ff	526	/* Check the parameters */
bogdanm	0:9b334a45a8ff	527	assert_param(IS_RCC_DFSDMCLKSOURCE(PeriphClkInit->DfsdmClockSelection));
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/* Configure the DFSDM interface clock source */
bogdanm	0:9b334a45a8ff	530	__HAL_RCC_DFSDM_CONFIG(PeriphClkInit->DfsdmClockSelection);
bogdanm	0:9b334a45a8ff	531	}
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	return status;
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/**
bogdanm	0:9b334a45a8ff	537	* @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
bogdanm	0:9b334a45a8ff	538	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	539	* returns the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	540	* clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART,
bogdanm	0:9b334a45a8ff	541	* USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
bogdanm	0:9b334a45a8ff	542	* @retval None
bogdanm	0:9b334a45a8ff	543	*/
bogdanm	0:9b334a45a8ff	544	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	545	{
bogdanm	0:9b334a45a8ff	546	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	547	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
bogdanm	0:9b334a45a8ff	548	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	0:9b334a45a8ff	549	RCC_PERIPHCLK_LPUART1 \| RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_LPTIM1 \| \
bogdanm	0:9b334a45a8ff	550	RCC_PERIPHCLK_LPTIM2 \| RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \| RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_SDMMC1 \| \
bogdanm	0:9b334a45a8ff	551	RCC_PERIPHCLK_RNG \| RCC_PERIPHCLK_ADC \| RCC_PERIPHCLK_SWPMI1 \| RCC_PERIPHCLK_DFSDM \| RCC_PERIPHCLK_RTC ;
bogdanm	0:9b334a45a8ff	552	#else
bogdanm	0:9b334a45a8ff	553	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	0:9b334a45a8ff	554	RCC_PERIPHCLK_LPUART1 \| RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_LPTIM1 \| \
bogdanm	0:9b334a45a8ff	555	RCC_PERIPHCLK_LPTIM2 \| RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \| RCC_PERIPHCLK_SDMMC1 \| \
bogdanm	0:9b334a45a8ff	556	RCC_PERIPHCLK_RNG \| RCC_PERIPHCLK_ADC \| RCC_PERIPHCLK_SWPMI1 \| RCC_PERIPHCLK_DFSDM \| RCC_PERIPHCLK_RTC ;
bogdanm	0:9b334a45a8ff	557	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	560	PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
bogdanm	0:9b334a45a8ff	561	PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4)+7;
bogdanm	0:9b334a45a8ff	562	PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1)* 2;
bogdanm	0:9b334a45a8ff	563	PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1)* 2;
bogdanm	0:9b334a45a8ff	564	/* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	565	PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
bogdanm	0:9b334a45a8ff	566	PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4)+7;
bogdanm	0:9b334a45a8ff	567	PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1)* 2;
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/* Get the USART1 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	570	PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
bogdanm	0:9b334a45a8ff	571	/* Get the USART2 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	572	PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
bogdanm	0:9b334a45a8ff	573	/* Get the USART3 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	574	PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
bogdanm	0:9b334a45a8ff	575	/* Get the UART4 clock source ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	576	PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
bogdanm	0:9b334a45a8ff	577	/* Get the UART5 clock source ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	578	PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
bogdanm	0:9b334a45a8ff	579	/* Get the LPUART1 clock source --------------------------------------------*/
bogdanm	0:9b334a45a8ff	580	PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
bogdanm	0:9b334a45a8ff	581	/* Get the I2C1 clock source -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	582	PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
bogdanm	0:9b334a45a8ff	583	/* Get the I2C2 clock source ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	584	PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
bogdanm	0:9b334a45a8ff	585	/* Get the I2C3 clock source -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	586	PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
bogdanm	0:9b334a45a8ff	587	/* Get the LPTIM1 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	588	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
bogdanm	0:9b334a45a8ff	589	/* Get the LPTIM2 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	590	PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
bogdanm	0:9b334a45a8ff	591	/* Get the SAI1 clock source -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	592	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
bogdanm	0:9b334a45a8ff	593	/* Get the SAI2 clock source -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	594	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
bogdanm	0:9b334a45a8ff	595	/* Get the RTC clock source ------------------------------------------------*/
bogdanm	0:9b334a45a8ff	596	PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
bogdanm	0:9b334a45a8ff	599	/* Get the USB clock source ------------------------------------------------*/
bogdanm	0:9b334a45a8ff	600	PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
bogdanm	0:9b334a45a8ff	601	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* Get the SDMMC1 clock source ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	604	PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
bogdanm	0:9b334a45a8ff	605	/* Get the RNG clock source ------------------------------------------------*/
bogdanm	0:9b334a45a8ff	606	PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
bogdanm	0:9b334a45a8ff	607	/* Get the ADC clock source -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	608	PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
bogdanm	0:9b334a45a8ff	609	/* Get the SWPMI1 clock source ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	610	PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
bogdanm	0:9b334a45a8ff	611	/* Get the DFSDM clock source -------------------------------------------*/
bogdanm	0:9b334a45a8ff	612	PeriphClkInit->DfsdmClockSelection = __HAL_RCC_GET_DFSDM_SOURCE();
bogdanm	0:9b334a45a8ff	613	}
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs
bogdanm	0:9b334a45a8ff	617	* @note Return 0 if peripheral clock identifier not managed by this API
bogdanm	0:9b334a45a8ff	618	* @param PeriphClk: Peripheral clock identifier
bogdanm	0:9b334a45a8ff	619	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	620	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
bogdanm	0:9b334a45a8ff	621	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
bogdanm	0:9b334a45a8ff	622	* @arg RCC_PERIPHCLK_ADC: ADC peripheral clock
bogdanm	0:9b334a45a8ff	623	* @arg RCC_PERIPHCLK_USB: USB, RNG, SDMMC1 peripheral clock
bogdanm	0:9b334a45a8ff	624	* @retval Frequency in KHz
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
bogdanm	0:9b334a45a8ff	627	{
bogdanm	0:9b334a45a8ff	628	uint32_t frequency = 0;
bogdanm	0:9b334a45a8ff	629	uint32_t pllvco = 0, plln = 0;
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/* Compute PLL clock input */
bogdanm	0:9b334a45a8ff	632	if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	pllvco = (1 << ((__HAL_RCC_GET_MSI_RANGE() >> 4) - 4)) * 1000000;
bogdanm	0:9b334a45a8ff	635	}
bogdanm	0:9b334a45a8ff	636	else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	637	{
bogdanm	0:9b334a45a8ff	638	pllvco = HSI_VALUE;
bogdanm	0:9b334a45a8ff	639	}
bogdanm	0:9b334a45a8ff	640	else /* HSE source */
bogdanm	0:9b334a45a8ff	641	{
bogdanm	0:9b334a45a8ff	642	pllvco = HSE_VALUE;
bogdanm	0:9b334a45a8ff	643	}
bogdanm	0:9b334a45a8ff	644
bogdanm	0:9b334a45a8ff	645	/* f(PLL Source) / PLLM */
bogdanm	0:9b334a45a8ff	646	pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> 4) + 1));
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	if((PeriphClk == RCC_PERIPHCLK_SAI1) \|\| (PeriphClk == RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	649	{
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
bogdanm	0:9b334a45a8ff	652	{
bogdanm	0:9b334a45a8ff	653	/* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
bogdanm	0:9b334a45a8ff	654	plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> 8;
bogdanm	0:9b334a45a8ff	655	if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
bogdanm	0:9b334a45a8ff	656	{
bogdanm	0:9b334a45a8ff	657	frequency = (pllvco * plln) / 17;
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659	else
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	frequency = (pllvco * plln) / 7;
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	else if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
bogdanm	0:9b334a45a8ff	667	plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> 8;
bogdanm	0:9b334a45a8ff	668	if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
bogdanm	0:9b334a45a8ff	669	{
bogdanm	0:9b334a45a8ff	670	frequency = (pllvco * plln) / 17;
bogdanm	0:9b334a45a8ff	671	}
bogdanm	0:9b334a45a8ff	672	else
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	frequency = (pllvco * plln) / 7;
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677	else if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	/* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
bogdanm	0:9b334a45a8ff	680	plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> 8;
bogdanm	0:9b334a45a8ff	681	if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
bogdanm	0:9b334a45a8ff	682	{
bogdanm	0:9b334a45a8ff	683	frequency = (pllvco * plln) / 17;
bogdanm	0:9b334a45a8ff	684	}
bogdanm	0:9b334a45a8ff	685	else
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	frequency = (pllvco * plln) / 7;
bogdanm	0:9b334a45a8ff	688	}
bogdanm	0:9b334a45a8ff	689	}
bogdanm	0:9b334a45a8ff	690	else
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	if(PeriphClk == RCC_PERIPHCLK_SAI1)
bogdanm	0:9b334a45a8ff	693	{
bogdanm	0:9b334a45a8ff	694	frequency = EXTERNAL_SAI1_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	695	}
bogdanm	0:9b334a45a8ff	696	else
bogdanm	0:9b334a45a8ff	697	{
bogdanm	0:9b334a45a8ff	698	frequency = EXTERNAL_SAI2_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700	}
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702	else if(PeriphClk == RCC_PERIPHCLK_ADC)
bogdanm	0:9b334a45a8ff	703	{
bogdanm	0:9b334a45a8ff	704	if(__HAL_RCC_GET_ADC_SOURCE() == RCC_ADCCLKSOURCE_SYSCLK)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	frequency = HAL_RCC_GetSysClockFreq();
bogdanm	0:9b334a45a8ff	707	}
bogdanm	0:9b334a45a8ff	708	else if(__HAL_RCC_GET_ADC_SOURCE() == RCC_ADCCLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
bogdanm	0:9b334a45a8ff	713	plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> 8;
bogdanm	0:9b334a45a8ff	714	frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> 24) + 1) << 1);
bogdanm	0:9b334a45a8ff	715	}
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717	else /* RCC_ADCCLKSOURCE_PLLSAI2 */
bogdanm	0:9b334a45a8ff	718	{
bogdanm	0:9b334a45a8ff	719	if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
bogdanm	0:9b334a45a8ff	720	{
bogdanm	0:9b334a45a8ff	721	/* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
bogdanm	0:9b334a45a8ff	722	plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> 8;
bogdanm	0:9b334a45a8ff	723	frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> 24) + 1) << 1);
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725	}
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
bogdanm	0:9b334a45a8ff	729	else if(PeriphClk == RCC_PERIPHCLK_USB)
bogdanm	0:9b334a45a8ff	730	{
bogdanm	0:9b334a45a8ff	731	if(__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_MSI)
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	frequency = (1 << ((__HAL_RCC_GET_MSI_RANGE() >> 4) - 4)) * 1000000;
bogdanm	0:9b334a45a8ff	734	}
bogdanm	0:9b334a45a8ff	735	else if(__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
bogdanm	0:9b334a45a8ff	736	{
bogdanm	0:9b334a45a8ff	737	/* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
bogdanm	0:9b334a45a8ff	738	plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> 8;
bogdanm	0:9b334a45a8ff	739	frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> 21) + 1) << 1);
bogdanm	0:9b334a45a8ff	740	}
bogdanm	0:9b334a45a8ff	741	else if(__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLLSAI1)
bogdanm	0:9b334a45a8ff	742	{
bogdanm	0:9b334a45a8ff	743	/* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
bogdanm	0:9b334a45a8ff	744	plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> 8;
bogdanm	0:9b334a45a8ff	745	frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> 21) + 1) << 1);
bogdanm	0:9b334a45a8ff	746	}
bogdanm	0:9b334a45a8ff	747	else /* RCC_USBCLKSOURCE_NONE */
bogdanm	0:9b334a45a8ff	748	{
bogdanm	0:9b334a45a8ff	749	frequency = 0;
bogdanm	0:9b334a45a8ff	750	}
bogdanm	0:9b334a45a8ff	751	}
bogdanm	0:9b334a45a8ff	752	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	return(frequency);
bogdanm	0:9b334a45a8ff	755	}
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/**
bogdanm	0:9b334a45a8ff	758	* @}
bogdanm	0:9b334a45a8ff	759	*/
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/** @defgroup RCCEx_Exported_Functions_Group2 Extended clock management functions
bogdanm	0:9b334a45a8ff	762	* @brief Extended clock management functions
bogdanm	0:9b334a45a8ff	763	*
bogdanm	0:9b334a45a8ff	764	@verbatim
bogdanm	0:9b334a45a8ff	765	===============================================================================
bogdanm	0:9b334a45a8ff	766	##### Extended clock management functions #####
bogdanm	0:9b334a45a8ff	767	===============================================================================
bogdanm	0:9b334a45a8ff	768	[..]
bogdanm	0:9b334a45a8ff	769	This subsection provides a set of functions allowing to control the
bogdanm	0:9b334a45a8ff	770	activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
bogdanm	0:9b334a45a8ff	771	Low speed clock output and clock after wake-up from STOP mode.
bogdanm	0:9b334a45a8ff	772	@endverbatim
bogdanm	0:9b334a45a8ff	773	* @{
bogdanm	0:9b334a45a8ff	774	*/
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/**
bogdanm	0:9b334a45a8ff	777	* @brief Enable PLLSAI1.
bogdanm	0:9b334a45a8ff	778	* @param PLLSAI1Init: pointer to an RCC_PLLSAI1InitTypeDef structure that
bogdanm	0:9b334a45a8ff	779	* contains the configuration information for the PLLSAI1
bogdanm	0:9b334a45a8ff	780	* @retval HAL status
bogdanm	0:9b334a45a8ff	781	*/
bogdanm	0:9b334a45a8ff	782	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
bogdanm	0:9b334a45a8ff	783	{
bogdanm	0:9b334a45a8ff	784	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	785	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
bogdanm	0:9b334a45a8ff	788	assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
bogdanm	0:9b334a45a8ff	789	assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
bogdanm	0:9b334a45a8ff	790	assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
bogdanm	0:9b334a45a8ff	791	assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
bogdanm	0:9b334a45a8ff	792	assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* Disable the PLLSAI1 */
bogdanm	0:9b334a45a8ff	795	__HAL_RCC_PLLSAI1_DISABLE();
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	798	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Wait till PLLSAI1 is ready to be updated */
bogdanm	0:9b334a45a8ff	801	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) != RESET)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	806	break;
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808	}
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	/* Configure the PLLSAI1 Multiplication factor N */
bogdanm	0:9b334a45a8ff	813	/* Configure the PLLSAI1 Division factors P, Q and R */
bogdanm	0:9b334a45a8ff	814	__HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
bogdanm	0:9b334a45a8ff	815	/* Configure the PLLSAI1 Clock output(s) */
bogdanm	0:9b334a45a8ff	816	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818	/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
bogdanm	0:9b334a45a8ff	819	__HAL_RCC_PLLSAI1_ENABLE();
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	822	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/* Wait till PLLSAI1 is ready */
bogdanm	0:9b334a45a8ff	825	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) == RESET)
bogdanm	0:9b334a45a8ff	826	{
bogdanm	0:9b334a45a8ff	827	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	828	{
bogdanm	0:9b334a45a8ff	829	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	830	break;
bogdanm	0:9b334a45a8ff	831	}
bogdanm	0:9b334a45a8ff	832	}
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	return status;
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/**
bogdanm	0:9b334a45a8ff	839	* @brief Disable PLLSAI1.
bogdanm	0:9b334a45a8ff	840	* @retval HAL status
bogdanm	0:9b334a45a8ff	841	*/
bogdanm	0:9b334a45a8ff	842	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
bogdanm	0:9b334a45a8ff	843	{
bogdanm	0:9b334a45a8ff	844	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	845	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/* Disable the PLLSAI1 */
bogdanm	0:9b334a45a8ff	848	__HAL_RCC_PLLSAI1_DISABLE();
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	851	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	/* Wait till PLLSAI1 is ready */
bogdanm	0:9b334a45a8ff	854	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) != RESET)
bogdanm	0:9b334a45a8ff	855	{
bogdanm	0:9b334a45a8ff	856	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	857	{
bogdanm	0:9b334a45a8ff	858	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	859	break;
bogdanm	0:9b334a45a8ff	860	}
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	return status;
bogdanm	0:9b334a45a8ff	864	}
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	/**
bogdanm	0:9b334a45a8ff	867	* @brief Enable PLLSAI2.
bogdanm	0:9b334a45a8ff	868	* @param PLLSAI2Init: pointer to an RCC_PLLSAI2InitTypeDef structure that
bogdanm	0:9b334a45a8ff	869	* contains the configuration information for the PLLSAI2
bogdanm	0:9b334a45a8ff	870	* @retval HAL status
bogdanm	0:9b334a45a8ff	871	*/
bogdanm	0:9b334a45a8ff	872	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	875	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
bogdanm	0:9b334a45a8ff	878	assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
bogdanm	0:9b334a45a8ff	879	assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
bogdanm	0:9b334a45a8ff	880	assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
bogdanm	0:9b334a45a8ff	881	assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	/* Disable the PLLSAI2 */
bogdanm	0:9b334a45a8ff	884	__HAL_RCC_PLLSAI2_DISABLE();
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	887	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	/* Wait till PLLSAI2 is ready to be updated */
bogdanm	0:9b334a45a8ff	890	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) != RESET)
bogdanm	0:9b334a45a8ff	891	{
bogdanm	0:9b334a45a8ff	892	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	895	break;
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	/* Configure the PLLSAI2 Multiplication factor N */
bogdanm	0:9b334a45a8ff	902	/* Configure the PLLSAI2 Division factors P and R */
bogdanm	0:9b334a45a8ff	903	__HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
bogdanm	0:9b334a45a8ff	904	/* Configure the PLLSAI2 Clock output(s) */
bogdanm	0:9b334a45a8ff	905	__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
bogdanm	0:9b334a45a8ff	908	__HAL_RCC_PLLSAI2_ENABLE();
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	911	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	914	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) == RESET)
bogdanm	0:9b334a45a8ff	915	{
bogdanm	0:9b334a45a8ff	916	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	919	break;
bogdanm	0:9b334a45a8ff	920	}
bogdanm	0:9b334a45a8ff	921	}
bogdanm	0:9b334a45a8ff	922	}
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	return status;
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/**
bogdanm	0:9b334a45a8ff	928	* @brief Disable PLLISAI2.
bogdanm	0:9b334a45a8ff	929	* @retval HAL status
bogdanm	0:9b334a45a8ff	930	*/
bogdanm	0:9b334a45a8ff	931	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
bogdanm	0:9b334a45a8ff	932	{
bogdanm	0:9b334a45a8ff	933	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	934	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* Disable the PLLSAI2 */
bogdanm	0:9b334a45a8ff	937	__HAL_RCC_PLLSAI2_DISABLE();
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	940	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	943	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) != RESET)
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	946	{
bogdanm	0:9b334a45a8ff	947	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	948	break;
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	return status;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
bogdanm	0:9b334a45a8ff	957	* @param WakeUpClk: Wakeup clock
bogdanm	0:9b334a45a8ff	958	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	959	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI oscillator selection
bogdanm	0:9b334a45a8ff	960	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
bogdanm	0:9b334a45a8ff	961	* @note This function shall not be called after the Clock Security System on HSE has been
bogdanm	0:9b334a45a8ff	962	* enabled.
bogdanm	0:9b334a45a8ff	963	* @retval None
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965	void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
bogdanm	0:9b334a45a8ff	966	{
bogdanm	0:9b334a45a8ff	967	assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
bogdanm	0:9b334a45a8ff	970	}
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/**
bogdanm	0:9b334a45a8ff	973	* @brief Configure the MSI range after standby mode.
bogdanm	0:9b334a45a8ff	974	* @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
bogdanm	0:9b334a45a8ff	975	* @param MSIRange: MSI range
bogdanm	0:9b334a45a8ff	976	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	977	* @arg RCC_MSIRANGE_4: Range 4 around 1 MHz
bogdanm	0:9b334a45a8ff	978	* @arg RCC_MSIRANGE_5: Range 5 around 2 MHz
bogdanm	0:9b334a45a8ff	979	* @arg RCC_MSIRANGE_6: Range 6 around 4 MHz (reset value)
bogdanm	0:9b334a45a8ff	980	* @arg RCC_MSIRANGE_7: Range 7 around 8 MHz
bogdanm	0:9b334a45a8ff	981	* @retval None
bogdanm	0:9b334a45a8ff	982	*/
bogdanm	0:9b334a45a8ff	983	void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
bogdanm	0:9b334a45a8ff	984	{
bogdanm	0:9b334a45a8ff	985	assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	__HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
bogdanm	0:9b334a45a8ff	988	}
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	/**
bogdanm	0:9b334a45a8ff	991	* @brief Enable the LSE Clock Security System.
bogdanm	0:9b334a45a8ff	992	* @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
bogdanm	0:9b334a45a8ff	993	* with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
bogdanm	0:9b334a45a8ff	994	* clock with HAL_RCCEx_PeriphCLKConfig().
bogdanm	0:9b334a45a8ff	995	* @retval None
bogdanm	0:9b334a45a8ff	996	*/
bogdanm	0:9b334a45a8ff	997	void HAL_RCCEx_EnableLSECSS(void)
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
bogdanm	0:9b334a45a8ff	1000	}
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/**
bogdanm	0:9b334a45a8ff	1003	* @brief Disable the LSE Clock Security System.
bogdanm	0:9b334a45a8ff	1004	* @note LSE Clock Security System can only be disabled after a LSE failure detection.
bogdanm	0:9b334a45a8ff	1005	* @retval None
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007	void HAL_RCCEx_DisableLSECSS(void)
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
bogdanm	0:9b334a45a8ff	1010	}
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/**
bogdanm	0:9b334a45a8ff	1013	* @brief Select the Low Speed clock source to output on LSCO pin (PA2).
bogdanm	0:9b334a45a8ff	1014	* @param LSCOSource: specifies the Low Speed clock source to output.
bogdanm	0:9b334a45a8ff	1015	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1016	* @arg RCC_LSCOSOURCE_LSI: LSI clock selected as LSCO source
bogdanm	0:9b334a45a8ff	1017	* @arg RCC_LSCOSOURCE_LSE: LSE clock selected as LSCO source
bogdanm	0:9b334a45a8ff	1018	* @retval None
bogdanm	0:9b334a45a8ff	1019	*/
bogdanm	0:9b334a45a8ff	1020	void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
bogdanm	0:9b334a45a8ff	1021	{
bogdanm	0:9b334a45a8ff	1022	GPIO_InitTypeDef GPIO_InitStruct;
bogdanm	0:9b334a45a8ff	1023	FlagStatus pwrclkchanged = RESET;
bogdanm	0:9b334a45a8ff	1024	FlagStatus backupchanged = RESET;
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1027	assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	/* LSCO Pin Clock Enable */
bogdanm	0:9b334a45a8ff	1030	__LSCO_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/* Configue the LSCO pin in analog mode */
bogdanm	0:9b334a45a8ff	1033	GPIO_InitStruct.Pin = LSCO_PIN;
bogdanm	0:9b334a45a8ff	1034	GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
bogdanm	0:9b334a45a8ff	1035	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
bogdanm	0:9b334a45a8ff	1036	GPIO_InitStruct.Pull = GPIO_NOPULL;
bogdanm	0:9b334a45a8ff	1037	HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Update LSCOSEL clock source in Backup Domain control register */
bogdanm	0:9b334a45a8ff	1040	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
bogdanm	0:9b334a45a8ff	1041	{
bogdanm	0:9b334a45a8ff	1042	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1043	pwrclkchanged = SET;
bogdanm	0:9b334a45a8ff	1044	}
bogdanm	0:9b334a45a8ff	1045	if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
bogdanm	0:9b334a45a8ff	1046	{
bogdanm	0:9b334a45a8ff	1047	HAL_PWR_EnableBkUpAccess();
bogdanm	0:9b334a45a8ff	1048	backupchanged = SET;
bogdanm	0:9b334a45a8ff	1049	}
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL \| RCC_BDCR_LSCOEN, LSCOSource \| RCC_BDCR_LSCOEN);
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	if(backupchanged == SET)
bogdanm	0:9b334a45a8ff	1054	{
bogdanm	0:9b334a45a8ff	1055	HAL_PWR_DisableBkUpAccess();
bogdanm	0:9b334a45a8ff	1056	}
bogdanm	0:9b334a45a8ff	1057	if(pwrclkchanged == SET)
bogdanm	0:9b334a45a8ff	1058	{
bogdanm	0:9b334a45a8ff	1059	__HAL_RCC_PWR_CLK_DISABLE();
bogdanm	0:9b334a45a8ff	1060	}
bogdanm	0:9b334a45a8ff	1061	}
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/**
bogdanm	0:9b334a45a8ff	1064	* @brief Disable the Low Speed clock output.
bogdanm	0:9b334a45a8ff	1065	* @retval None
bogdanm	0:9b334a45a8ff	1066	*/
bogdanm	0:9b334a45a8ff	1067	void HAL_RCCEx_DisableLSCO(void)
bogdanm	0:9b334a45a8ff	1068	{
bogdanm	0:9b334a45a8ff	1069	FlagStatus pwrclkchanged = RESET;
bogdanm	0:9b334a45a8ff	1070	FlagStatus backupchanged = RESET;
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	/* Update LSCOEN bit in Backup Domain control register */
bogdanm	0:9b334a45a8ff	1073	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1076	pwrclkchanged = SET;
bogdanm	0:9b334a45a8ff	1077	}
bogdanm	0:9b334a45a8ff	1078	if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
bogdanm	0:9b334a45a8ff	1079	{
bogdanm	0:9b334a45a8ff	1080	/* Enable access to the backup domain */
bogdanm	0:9b334a45a8ff	1081	HAL_PWR_EnableBkUpAccess();
bogdanm	0:9b334a45a8ff	1082	backupchanged = SET;
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/* Restore previous configuration */
bogdanm	0:9b334a45a8ff	1088	if(backupchanged == SET)
bogdanm	0:9b334a45a8ff	1089	{
bogdanm	0:9b334a45a8ff	1090	/* Disable access to the backup domain */
bogdanm	0:9b334a45a8ff	1091	HAL_PWR_DisableBkUpAccess();
bogdanm	0:9b334a45a8ff	1092	}
bogdanm	0:9b334a45a8ff	1093	if(pwrclkchanged == SET)
bogdanm	0:9b334a45a8ff	1094	{
bogdanm	0:9b334a45a8ff	1095	__HAL_RCC_PWR_CLK_DISABLE();
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/**
bogdanm	0:9b334a45a8ff	1100	* @brief Enable the PLL-mode of the MSI.
bogdanm	0:9b334a45a8ff	1101	* @note Prior to enable the PLL-mode of the MSI for automatic hardware
bogdanm	0:9b334a45a8ff	1102	* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
bogdanm	0:9b334a45a8ff	1103	* @retval None
bogdanm	0:9b334a45a8ff	1104	*/
bogdanm	0:9b334a45a8ff	1105	void HAL_RCCEx_EnableMSIPLLMode(void)
bogdanm	0:9b334a45a8ff	1106	{
bogdanm	0:9b334a45a8ff	1107	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
bogdanm	0:9b334a45a8ff	1108	}
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/**
bogdanm	0:9b334a45a8ff	1111	* @brief Disable the PLL-mode of the MSI.
bogdanm	0:9b334a45a8ff	1112	* @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
bogdanm	0:9b334a45a8ff	1113	* @retval None
bogdanm	0:9b334a45a8ff	1114	*/
bogdanm	0:9b334a45a8ff	1115	void HAL_RCCEx_DisableMSIPLLMode(void)
bogdanm	0:9b334a45a8ff	1116	{
bogdanm	0:9b334a45a8ff	1117	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
bogdanm	0:9b334a45a8ff	1118	}
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/**
bogdanm	0:9b334a45a8ff	1121	* @}
bogdanm	0:9b334a45a8ff	1122	*/
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/**
bogdanm	0:9b334a45a8ff	1125	* @}
bogdanm	0:9b334a45a8ff	1126	*/
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/** @addtogroup RCCEx_Private_Functions
bogdanm	0:9b334a45a8ff	1129	* @{
bogdanm	0:9b334a45a8ff	1130	*/
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/**
bogdanm	0:9b334a45a8ff	1133	* @brief Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
bogdanm	0:9b334a45a8ff	1134	* @param PllSai1: pointer to an RCC_PLLSAI1InitTypeDef structure that
bogdanm	0:9b334a45a8ff	1135	* contains the configuration parameters N & P as well as PLLSAI1 output clock(s)
bogdanm	0:9b334a45a8ff	1136	*
bogdanm	0:9b334a45a8ff	1137	* @note PLLSAI1 is temporary disable to apply new parameters
bogdanm	0:9b334a45a8ff	1138	*
bogdanm	0:9b334a45a8ff	1139	* @retval HAL status
bogdanm	0:9b334a45a8ff	1140	*/
bogdanm	0:9b334a45a8ff	1141	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PllSai1)
bogdanm	0:9b334a45a8ff	1142	{
bogdanm	0:9b334a45a8ff	1143	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1144	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
bogdanm	0:9b334a45a8ff	1147	assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
bogdanm	0:9b334a45a8ff	1148	assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
bogdanm	0:9b334a45a8ff	1149	assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Disable the PLLSAI1 */
bogdanm	0:9b334a45a8ff	1152	__HAL_RCC_PLLSAI1_DISABLE();
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1155	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/* Wait till PLLSAI1 is ready to be updated */
bogdanm	0:9b334a45a8ff	1158	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) != RESET)
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1161	{
bogdanm	0:9b334a45a8ff	1162	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1163	break;
bogdanm	0:9b334a45a8ff	1164	}
bogdanm	0:9b334a45a8ff	1165	}
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	1168	{
bogdanm	0:9b334a45a8ff	1169	/* Configure the PLLSAI1 Multiplication factor N */
bogdanm	0:9b334a45a8ff	1170	__HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
bogdanm	0:9b334a45a8ff	1171	/* Configure the PLLSAI1 Division factor P */
bogdanm	0:9b334a45a8ff	1172	__HAL_RCC_PLLSAI1_DIVP_CONFIG(PllSai1->PLLSAI1P);
bogdanm	0:9b334a45a8ff	1173	/* Configure the PLLSAI1 Clock output(s) */
bogdanm	0:9b334a45a8ff	1174	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
bogdanm	0:9b334a45a8ff	1177	__HAL_RCC_PLLSAI1_ENABLE();
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1180	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Wait till PLLSAI1 is ready */
bogdanm	0:9b334a45a8ff	1183	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) == RESET)
bogdanm	0:9b334a45a8ff	1184	{
bogdanm	0:9b334a45a8ff	1185	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1186	{
bogdanm	0:9b334a45a8ff	1187	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1188	break;
bogdanm	0:9b334a45a8ff	1189	}
bogdanm	0:9b334a45a8ff	1190	}
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	return status;
bogdanm	0:9b334a45a8ff	1194	}
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/**
bogdanm	0:9b334a45a8ff	1197	* @brief Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).
bogdanm	0:9b334a45a8ff	1198	* @param PllSai1: pointer to an RCC_PLLSAI1InitTypeDef structure that
bogdanm	0:9b334a45a8ff	1199	* contains the configuration parameters N & Q as well as PLLSAI1 output clock(s)
bogdanm	0:9b334a45a8ff	1200	*
bogdanm	0:9b334a45a8ff	1201	* @note PLLSAI1 is temporary disable to apply new parameters
bogdanm	0:9b334a45a8ff	1202	*
bogdanm	0:9b334a45a8ff	1203	* @retval HAL status
bogdanm	0:9b334a45a8ff	1204	*/
bogdanm	0:9b334a45a8ff	1205	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PllSai1)
bogdanm	0:9b334a45a8ff	1206	{
bogdanm	0:9b334a45a8ff	1207	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1208	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
bogdanm	0:9b334a45a8ff	1211	assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
bogdanm	0:9b334a45a8ff	1212	assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
bogdanm	0:9b334a45a8ff	1213	assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	/* Disable the PLLSAI1 */
bogdanm	0:9b334a45a8ff	1216	__HAL_RCC_PLLSAI1_DISABLE();
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1219	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Wait till PLLSAI1 is ready to be updated */
bogdanm	0:9b334a45a8ff	1222	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) != RESET)
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1225	{
bogdanm	0:9b334a45a8ff	1226	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1227	break;
bogdanm	0:9b334a45a8ff	1228	}
bogdanm	0:9b334a45a8ff	1229	}
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	1232	{
bogdanm	0:9b334a45a8ff	1233	/* Configure the PLLSAI1 Multiplication factor N */
bogdanm	0:9b334a45a8ff	1234	__HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
bogdanm	0:9b334a45a8ff	1235	/* Configure the PLLSAI1 Division factor Q */
bogdanm	0:9b334a45a8ff	1236	__HAL_RCC_PLLSAI1_DIVQ_CONFIG(PllSai1->PLLSAI1Q);
bogdanm	0:9b334a45a8ff	1237	/* Configure the PLLSAI1 Clock output(s) */
bogdanm	0:9b334a45a8ff	1238	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
bogdanm	0:9b334a45a8ff	1241	__HAL_RCC_PLLSAI1_ENABLE();
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1244	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* Wait till PLLSAI1 is ready */
bogdanm	0:9b334a45a8ff	1247	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) == RESET)
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1250	{
bogdanm	0:9b334a45a8ff	1251	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1252	break;
bogdanm	0:9b334a45a8ff	1253	}
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255	}
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	return status;
bogdanm	0:9b334a45a8ff	1258	}
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/**
bogdanm	0:9b334a45a8ff	1261	* @brief Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).
bogdanm	0:9b334a45a8ff	1262	* @param PllSai1: pointer to an RCC_PLLSAI1InitTypeDef structure that
bogdanm	0:9b334a45a8ff	1263	* contains the configuration parameters N & R as well as PLLSAI1 output clock(s)
bogdanm	0:9b334a45a8ff	1264	*
bogdanm	0:9b334a45a8ff	1265	* @note PLLSAI1 is temporary disable to apply new parameters
bogdanm	0:9b334a45a8ff	1266	*
bogdanm	0:9b334a45a8ff	1267	* @retval HAL status
bogdanm	0:9b334a45a8ff	1268	*/
bogdanm	0:9b334a45a8ff	1269	static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PllSai1)
bogdanm	0:9b334a45a8ff	1270	{
bogdanm	0:9b334a45a8ff	1271	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1272	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
bogdanm	0:9b334a45a8ff	1275	assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
bogdanm	0:9b334a45a8ff	1276	assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
bogdanm	0:9b334a45a8ff	1277	assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/* Disable the PLLSAI1 */
bogdanm	0:9b334a45a8ff	1280	__HAL_RCC_PLLSAI1_DISABLE();
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1283	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	/* Wait till PLLSAI1 is ready to be updated */
bogdanm	0:9b334a45a8ff	1286	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) != RESET)
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1289	{
bogdanm	0:9b334a45a8ff	1290	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1291	break;
bogdanm	0:9b334a45a8ff	1292	}
bogdanm	0:9b334a45a8ff	1293	}
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	1296	{
bogdanm	0:9b334a45a8ff	1297	/* Configure the PLLSAI1 Multiplication factor N */
bogdanm	0:9b334a45a8ff	1298	__HAL_RCC_PLLSAI1_MULN_CONFIG(PllSai1->PLLSAI1N);
bogdanm	0:9b334a45a8ff	1299	/* Configure the PLLSAI1 Division factor R */
bogdanm	0:9b334a45a8ff	1300	__HAL_RCC_PLLSAI1_DIVR_CONFIG(PllSai1->PLLSAI1R);
bogdanm	0:9b334a45a8ff	1301	/* Configure the PLLSAI1 Clock output(s) */
bogdanm	0:9b334a45a8ff	1302	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
bogdanm	0:9b334a45a8ff	1305	__HAL_RCC_PLLSAI1_ENABLE();
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1308	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/* Wait till PLLSAI1 is ready */
bogdanm	0:9b334a45a8ff	1311	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI1RDY) == RESET)
bogdanm	0:9b334a45a8ff	1312	{
bogdanm	0:9b334a45a8ff	1313	if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1316	break;
bogdanm	0:9b334a45a8ff	1317	}
bogdanm	0:9b334a45a8ff	1318	}
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	return status;
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/**
bogdanm	0:9b334a45a8ff	1325	* @brief Configure the parameters N & P of PLLSAI2 and enable PLLSAI2 output clock(s).
bogdanm	0:9b334a45a8ff	1326	* @param PllSai2: pointer to an RCC_PLLSAI2InitTypeDef structure that
bogdanm	0:9b334a45a8ff	1327	* contains the configuration parameters N & P as well as PLLSAI2 output clock(s)
bogdanm	0:9b334a45a8ff	1328	*
bogdanm	0:9b334a45a8ff	1329	* @note PLLSAI2 is temporary disable to apply new parameters
bogdanm	0:9b334a45a8ff	1330	*
bogdanm	0:9b334a45a8ff	1331	* @retval HAL status
bogdanm	0:9b334a45a8ff	1332	*/
bogdanm	0:9b334a45a8ff	1333	static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNP(RCC_PLLSAI2InitTypeDef *PllSai2)
bogdanm	0:9b334a45a8ff	1334	{
bogdanm	0:9b334a45a8ff	1335	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1336	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	/* check for PLLSAI2 Parameters */
bogdanm	0:9b334a45a8ff	1339	assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
bogdanm	0:9b334a45a8ff	1340	assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
bogdanm	0:9b334a45a8ff	1341	assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	/* Disable the PLLSAI2 */
bogdanm	0:9b334a45a8ff	1344	__HAL_RCC_PLLSAI2_DISABLE();
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1347	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	1350	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) != RESET)
bogdanm	0:9b334a45a8ff	1351	{
bogdanm	0:9b334a45a8ff	1352	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1355	break;
bogdanm	0:9b334a45a8ff	1356	}
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	1360	{
bogdanm	0:9b334a45a8ff	1361	/* Configure the PLLSAI2 Multiplication factor N */
bogdanm	0:9b334a45a8ff	1362	__HAL_RCC_PLLSAI2_MULN_CONFIG(PllSai2->PLLSAI2N);
bogdanm	0:9b334a45a8ff	1363	/* Configure the PLLSAI2 Division factor P */
bogdanm	0:9b334a45a8ff	1364	__HAL_RCC_PLLSAI2_DIVP_CONFIG(PllSai2->PLLSAI2P);
bogdanm	0:9b334a45a8ff	1365	/* Configure the PLLSAI2 Clock output(s) */
bogdanm	0:9b334a45a8ff	1366	__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
bogdanm	0:9b334a45a8ff	1369	__HAL_RCC_PLLSAI2_ENABLE();
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1372	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	1375	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) == RESET)
bogdanm	0:9b334a45a8ff	1376	{
bogdanm	0:9b334a45a8ff	1377	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1380	break;
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382	}
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	return status;
bogdanm	0:9b334a45a8ff	1386	}
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/**
bogdanm	0:9b334a45a8ff	1389	* @brief Configure the parameters N & R of PLLSAI2 and enable PLLSAI2 output clock(s).
bogdanm	0:9b334a45a8ff	1390	* @param PllSai2: pointer to an RCC_PLLSAI2InitTypeDef structure that
bogdanm	0:9b334a45a8ff	1391	* contains the configuration parameters N & R as well as PLLSAI2 output clock(s)
bogdanm	0:9b334a45a8ff	1392	*
bogdanm	0:9b334a45a8ff	1393	* @note PLLSAI2 is temporary disable to apply new parameters
bogdanm	0:9b334a45a8ff	1394	*
bogdanm	0:9b334a45a8ff	1395	* @retval HAL status
bogdanm	0:9b334a45a8ff	1396	*/
bogdanm	0:9b334a45a8ff	1397	static HAL_StatusTypeDef RCCEx_PLLSAI2_ConfigNR(RCC_PLLSAI2InitTypeDef *PllSai2)
bogdanm	0:9b334a45a8ff	1398	{
bogdanm	0:9b334a45a8ff	1399	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1400	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	/* check for PLLSAI2 Parameters */
bogdanm	0:9b334a45a8ff	1403	assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
bogdanm	0:9b334a45a8ff	1404	assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
bogdanm	0:9b334a45a8ff	1405	assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	/* Disable the PLLSAI2 */
bogdanm	0:9b334a45a8ff	1408	__HAL_RCC_PLLSAI2_DISABLE();
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1411	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	1414	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) != RESET)
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1417	{
bogdanm	0:9b334a45a8ff	1418	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1419	break;
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421	}
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	/* Configure the PLLSAI2 Multiplication factor N */
bogdanm	0:9b334a45a8ff	1426	__HAL_RCC_PLLSAI2_MULN_CONFIG(PllSai2->PLLSAI2N);
bogdanm	0:9b334a45a8ff	1427	/* Configure the PLLSAI2 Division factor R */
bogdanm	0:9b334a45a8ff	1428	__HAL_RCC_PLLSAI2_DIVR_CONFIG(PllSai2->PLLSAI2R);
bogdanm	0:9b334a45a8ff	1429	/* Configure the PLLSAI2 Clock output(s) */
bogdanm	0:9b334a45a8ff	1430	__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
bogdanm	0:9b334a45a8ff	1433	__HAL_RCC_PLLSAI2_ENABLE();
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1436	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* Wait till PLLSAI2 is ready */
bogdanm	0:9b334a45a8ff	1439	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLSAI2RDY) == RESET)
bogdanm	0:9b334a45a8ff	1440	{
bogdanm	0:9b334a45a8ff	1441	if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1442	{
bogdanm	0:9b334a45a8ff	1443	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1444	break;
bogdanm	0:9b334a45a8ff	1445	}
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447	}
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	return status;
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/**
bogdanm	0:9b334a45a8ff	1453	* @}
bogdanm	0:9b334a45a8ff	1454	*/
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/**
bogdanm	0:9b334a45a8ff	1457	* @}
bogdanm	0:9b334a45a8ff	1458	*/
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	#endif /* HAL_RCC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1461	/**
bogdanm	0:9b334a45a8ff	1462	* @}
bogdanm	0:9b334a45a8ff	1463	*/
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	/**
bogdanm	0:9b334a45a8ff	1466	* @}
bogdanm	0:9b334a45a8ff	1467	*/
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1470

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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