en 129
fix LPC812 PWM
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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_qspi.h@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_hal_qspi.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of QSPI HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L4xx_HAL_QSPI_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L4xx_HAL_QSPI_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l4xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup QSPI |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | /** @defgroup QSPI_Exported_Types QSPI Exported Types |
| bogdanm | 0:9b334a45a8ff | 59 | * @{ |
| bogdanm | 0:9b334a45a8ff | 60 | */ |
| bogdanm | 0:9b334a45a8ff | 61 | |
| bogdanm | 0:9b334a45a8ff | 62 | /** |
| bogdanm | 0:9b334a45a8ff | 63 | * @brief QSPI Init structure definition |
| bogdanm | 0:9b334a45a8ff | 64 | */ |
| bogdanm | 0:9b334a45a8ff | 65 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 66 | { |
| bogdanm | 0:9b334a45a8ff | 67 | uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. |
| bogdanm | 0:9b334a45a8ff | 68 | This parameter can be a number between 0 and 255 */ |
| bogdanm | 0:9b334a45a8ff | 69 | uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) |
| bogdanm | 0:9b334a45a8ff | 70 | This parameter can be a value between 1 and 16 */ |
| bogdanm | 0:9b334a45a8ff | 71 | uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to |
| bogdanm | 0:9b334a45a8ff | 72 | take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
| bogdanm | 0:9b334a45a8ff | 73 | This parameter can be a value of @ref QSPI_SampleShifting */ |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits |
| bogdanm | 0:9b334a45a8ff | 75 | required to address the flash memory. The flash capacity can be up to 4GB |
| bogdanm | 0:9b334a45a8ff | 76 | (addressed using 32 bits) in indirect mode, but the addressable space in |
| bogdanm | 0:9b334a45a8ff | 77 | memory-mapped mode is limited to 256MB |
| bogdanm | 0:9b334a45a8ff | 78 | This parameter can be a number between 0 and 31 */ |
| bogdanm | 0:9b334a45a8ff | 79 | uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number |
| bogdanm | 0:9b334a45a8ff | 80 | of clock cycles which the chip select must remain high between commands. |
| bogdanm | 0:9b334a45a8ff | 81 | This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
| bogdanm | 0:9b334a45a8ff | 82 | uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. |
| bogdanm | 0:9b334a45a8ff | 83 | This parameter can be a value of @ref QSPI_ClockMode */ |
| bogdanm | 0:9b334a45a8ff | 84 | }QSPI_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | /** |
| bogdanm | 0:9b334a45a8ff | 87 | * @brief HAL QSPI State structures definition |
| bogdanm | 0:9b334a45a8ff | 88 | */ |
| bogdanm | 0:9b334a45a8ff | 89 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 90 | { |
| bogdanm | 0:9b334a45a8ff | 91 | HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ |
| bogdanm | 0:9b334a45a8ff | 92 | HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ |
| bogdanm | 0:9b334a45a8ff | 93 | HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ |
| bogdanm | 0:9b334a45a8ff | 94 | HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ |
| bogdanm | 0:9b334a45a8ff | 95 | HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ |
| bogdanm | 0:9b334a45a8ff | 96 | HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ |
| bogdanm | 0:9b334a45a8ff | 97 | HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ |
| bogdanm | 0:9b334a45a8ff | 98 | HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ |
| bogdanm | 0:9b334a45a8ff | 99 | }HAL_QSPI_StateTypeDef; |
| bogdanm | 0:9b334a45a8ff | 100 | |
| bogdanm | 0:9b334a45a8ff | 101 | /** |
| bogdanm | 0:9b334a45a8ff | 102 | * @brief QSPI Handle Structure definition |
| bogdanm | 0:9b334a45a8ff | 103 | */ |
| bogdanm | 0:9b334a45a8ff | 104 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 105 | { |
| bogdanm | 0:9b334a45a8ff | 106 | QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
| bogdanm | 0:9b334a45a8ff | 107 | QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
| bogdanm | 0:9b334a45a8ff | 108 | uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
| bogdanm | 0:9b334a45a8ff | 109 | __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */ |
| bogdanm | 0:9b334a45a8ff | 110 | __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */ |
| bogdanm | 0:9b334a45a8ff | 111 | uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
| bogdanm | 0:9b334a45a8ff | 112 | __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */ |
| bogdanm | 0:9b334a45a8ff | 113 | __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */ |
| bogdanm | 0:9b334a45a8ff | 114 | DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
| bogdanm | 0:9b334a45a8ff | 115 | __IO HAL_LockTypeDef Lock; /* Locking object */ |
| bogdanm | 0:9b334a45a8ff | 116 | __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
| bogdanm | 0:9b334a45a8ff | 117 | __IO uint32_t ErrorCode; /* QSPI Error code */ |
| bogdanm | 0:9b334a45a8ff | 118 | uint32_t Timeout; /* Timeout for the QSPI memory access */ |
| bogdanm | 0:9b334a45a8ff | 119 | }QSPI_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 120 | |
| bogdanm | 0:9b334a45a8ff | 121 | /** |
| bogdanm | 0:9b334a45a8ff | 122 | * @brief QSPI Command structure definition |
| bogdanm | 0:9b334a45a8ff | 123 | */ |
| bogdanm | 0:9b334a45a8ff | 124 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 125 | { |
| bogdanm | 0:9b334a45a8ff | 126 | uint32_t Instruction; /* Specifies the Instruction to be sent |
| bogdanm | 0:9b334a45a8ff | 127 | This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
| bogdanm | 0:9b334a45a8ff | 128 | uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) |
| bogdanm | 0:9b334a45a8ff | 129 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
| bogdanm | 0:9b334a45a8ff | 130 | uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) |
| bogdanm | 0:9b334a45a8ff | 131 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
| bogdanm | 0:9b334a45a8ff | 132 | uint32_t AddressSize; /* Specifies the Address Size |
| bogdanm | 0:9b334a45a8ff | 133 | This parameter can be a value of @ref QSPI_AddressSize */ |
| bogdanm | 0:9b334a45a8ff | 134 | uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size |
| bogdanm | 0:9b334a45a8ff | 135 | This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
| bogdanm | 0:9b334a45a8ff | 136 | uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. |
| bogdanm | 0:9b334a45a8ff | 137 | This parameter can be a number between 0 and 31 */ |
| bogdanm | 0:9b334a45a8ff | 138 | uint32_t InstructionMode; /* Specifies the Instruction Mode |
| bogdanm | 0:9b334a45a8ff | 139 | This parameter can be a value of @ref QSPI_InstructionMode */ |
| bogdanm | 0:9b334a45a8ff | 140 | uint32_t AddressMode; /* Specifies the Address Mode |
| bogdanm | 0:9b334a45a8ff | 141 | This parameter can be a value of @ref QSPI_AddressMode */ |
| bogdanm | 0:9b334a45a8ff | 142 | uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode |
| bogdanm | 0:9b334a45a8ff | 143 | This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
| bogdanm | 0:9b334a45a8ff | 144 | uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) |
| bogdanm | 0:9b334a45a8ff | 145 | This parameter can be a value of @ref QSPI_DataMode */ |
| bogdanm | 0:9b334a45a8ff | 146 | uint32_t NbData; /* Specifies the number of data to transfer. |
| bogdanm | 0:9b334a45a8ff | 147 | This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length |
| bogdanm | 0:9b334a45a8ff | 148 | until end of memory)*/ |
| bogdanm | 0:9b334a45a8ff | 149 | uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase |
| bogdanm | 0:9b334a45a8ff | 150 | This parameter can be a value of @ref QSPI_DdrMode */ |
| bogdanm | 0:9b334a45a8ff | 151 | uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of |
| bogdanm | 0:9b334a45a8ff | 152 | system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. |
| bogdanm | 0:9b334a45a8ff | 153 | This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
| bogdanm | 0:9b334a45a8ff | 154 | uint32_t SIOOMode; /* Specifies the send instruction only once mode |
| bogdanm | 0:9b334a45a8ff | 155 | This parameter can be a value of @ref QSPI_SIOOMode */ |
| bogdanm | 0:9b334a45a8ff | 156 | }QSPI_CommandTypeDef; |
| bogdanm | 0:9b334a45a8ff | 157 | |
| bogdanm | 0:9b334a45a8ff | 158 | /** |
| bogdanm | 0:9b334a45a8ff | 159 | * @brief QSPI Auto Polling mode configuration structure definition |
| bogdanm | 0:9b334a45a8ff | 160 | */ |
| bogdanm | 0:9b334a45a8ff | 161 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 162 | { |
| bogdanm | 0:9b334a45a8ff | 163 | uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. |
| bogdanm | 0:9b334a45a8ff | 164 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
| bogdanm | 0:9b334a45a8ff | 165 | uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. |
| bogdanm | 0:9b334a45a8ff | 166 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
| bogdanm | 0:9b334a45a8ff | 167 | uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. |
| bogdanm | 0:9b334a45a8ff | 168 | This parameter can be any value between 0 and 0xFFFF */ |
| bogdanm | 0:9b334a45a8ff | 169 | uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. |
| bogdanm | 0:9b334a45a8ff | 170 | This parameter can be any value between 1 and 4 */ |
| bogdanm | 0:9b334a45a8ff | 171 | uint32_t MatchMode; /* Specifies the method used for determining a match. |
| bogdanm | 0:9b334a45a8ff | 172 | This parameter can be a value of @ref QSPI_MatchMode */ |
| bogdanm | 0:9b334a45a8ff | 173 | uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. |
| bogdanm | 0:9b334a45a8ff | 174 | This parameter can be a value of @ref QSPI_AutomaticStop */ |
| bogdanm | 0:9b334a45a8ff | 175 | }QSPI_AutoPollingTypeDef; |
| bogdanm | 0:9b334a45a8ff | 176 | |
| bogdanm | 0:9b334a45a8ff | 177 | /** |
| bogdanm | 0:9b334a45a8ff | 178 | * @brief QSPI Memory Mapped mode configuration structure definition |
| bogdanm | 0:9b334a45a8ff | 179 | */ |
| bogdanm | 0:9b334a45a8ff | 180 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 181 | { |
| bogdanm | 0:9b334a45a8ff | 182 | uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. |
| bogdanm | 0:9b334a45a8ff | 183 | This parameter can be any value between 0 and 0xFFFF */ |
| bogdanm | 0:9b334a45a8ff | 184 | uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. |
| bogdanm | 0:9b334a45a8ff | 185 | This parameter can be a value of @ref QSPI_TimeOutActivation */ |
| bogdanm | 0:9b334a45a8ff | 186 | }QSPI_MemoryMappedTypeDef; |
| bogdanm | 0:9b334a45a8ff | 187 | |
| bogdanm | 0:9b334a45a8ff | 188 | /** |
| bogdanm | 0:9b334a45a8ff | 189 | * @} |
| bogdanm | 0:9b334a45a8ff | 190 | */ |
| bogdanm | 0:9b334a45a8ff | 191 | |
| bogdanm | 0:9b334a45a8ff | 192 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 193 | /** @defgroup QSPI_Exported_Constants QSPI Exported Constants |
| bogdanm | 0:9b334a45a8ff | 194 | * @{ |
| bogdanm | 0:9b334a45a8ff | 195 | */ |
| bogdanm | 0:9b334a45a8ff | 196 | |
| bogdanm | 0:9b334a45a8ff | 197 | /** @defgroup QSPI_ErrorCode |
| bogdanm | 0:9b334a45a8ff | 198 | * @{ |
| bogdanm | 0:9b334a45a8ff | 199 | */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ |
| bogdanm | 0:9b334a45a8ff | 204 | /** |
| bogdanm | 0:9b334a45a8ff | 205 | * @} |
| bogdanm | 0:9b334a45a8ff | 206 | */ |
| bogdanm | 0:9b334a45a8ff | 207 | |
| bogdanm | 0:9b334a45a8ff | 208 | /** @defgroup QSPI_SampleShifting |
| bogdanm | 0:9b334a45a8ff | 209 | * @{ |
| bogdanm | 0:9b334a45a8ff | 210 | */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/ |
| bogdanm | 0:9b334a45a8ff | 212 | #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
| bogdanm | 0:9b334a45a8ff | 213 | /** |
| bogdanm | 0:9b334a45a8ff | 214 | * @} |
| bogdanm | 0:9b334a45a8ff | 215 | */ |
| bogdanm | 0:9b334a45a8ff | 216 | |
| bogdanm | 0:9b334a45a8ff | 217 | /** @defgroup QSPI_ChipSelectHighTime |
| bogdanm | 0:9b334a45a8ff | 218 | * @{ |
| bogdanm | 0:9b334a45a8ff | 219 | */ |
| bogdanm | 0:9b334a45a8ff | 220 | #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/ |
| bogdanm | 0:9b334a45a8ff | 221 | #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 222 | #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 223 | #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 224 | #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 225 | #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 226 | #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 227 | #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
| bogdanm | 0:9b334a45a8ff | 228 | /** |
| bogdanm | 0:9b334a45a8ff | 229 | * @} |
| bogdanm | 0:9b334a45a8ff | 230 | */ |
| bogdanm | 0:9b334a45a8ff | 231 | |
| bogdanm | 0:9b334a45a8ff | 232 | /** @defgroup QSPI_ClockMode |
| bogdanm | 0:9b334a45a8ff | 233 | * @{ |
| bogdanm | 0:9b334a45a8ff | 234 | */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/ |
| bogdanm | 0:9b334a45a8ff | 236 | #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
| bogdanm | 0:9b334a45a8ff | 237 | /** |
| bogdanm | 0:9b334a45a8ff | 238 | * @} |
| bogdanm | 0:9b334a45a8ff | 239 | */ |
| bogdanm | 0:9b334a45a8ff | 240 | |
| bogdanm | 0:9b334a45a8ff | 241 | /** @defgroup QSPI_AddressSize |
| bogdanm | 0:9b334a45a8ff | 242 | * @{ |
| bogdanm | 0:9b334a45a8ff | 243 | */ |
| bogdanm | 0:9b334a45a8ff | 244 | #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/ |
| bogdanm | 0:9b334a45a8ff | 245 | #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
| bogdanm | 0:9b334a45a8ff | 246 | #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
| bogdanm | 0:9b334a45a8ff | 247 | #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
| bogdanm | 0:9b334a45a8ff | 248 | /** |
| bogdanm | 0:9b334a45a8ff | 249 | * @} |
| bogdanm | 0:9b334a45a8ff | 250 | */ |
| bogdanm | 0:9b334a45a8ff | 251 | |
| bogdanm | 0:9b334a45a8ff | 252 | /** @defgroup QSPI_AlternateBytesSize |
| bogdanm | 0:9b334a45a8ff | 253 | * @{ |
| bogdanm | 0:9b334a45a8ff | 254 | */ |
| bogdanm | 0:9b334a45a8ff | 255 | #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/ |
| bogdanm | 0:9b334a45a8ff | 256 | #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
| bogdanm | 0:9b334a45a8ff | 257 | #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
| bogdanm | 0:9b334a45a8ff | 258 | #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
| bogdanm | 0:9b334a45a8ff | 259 | /** |
| bogdanm | 0:9b334a45a8ff | 260 | * @} |
| bogdanm | 0:9b334a45a8ff | 261 | */ |
| bogdanm | 0:9b334a45a8ff | 262 | |
| bogdanm | 0:9b334a45a8ff | 263 | /** @defgroup QSPI_InstructionMode |
| bogdanm | 0:9b334a45a8ff | 264 | * @{ |
| bogdanm | 0:9b334a45a8ff | 265 | */ |
| bogdanm | 0:9b334a45a8ff | 266 | #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/ |
| bogdanm | 0:9b334a45a8ff | 267 | #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
| bogdanm | 0:9b334a45a8ff | 268 | #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
| bogdanm | 0:9b334a45a8ff | 269 | #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
| bogdanm | 0:9b334a45a8ff | 270 | /** |
| bogdanm | 0:9b334a45a8ff | 271 | * @} |
| bogdanm | 0:9b334a45a8ff | 272 | */ |
| bogdanm | 0:9b334a45a8ff | 273 | |
| bogdanm | 0:9b334a45a8ff | 274 | /** @defgroup QSPI_AddressMode |
| bogdanm | 0:9b334a45a8ff | 275 | * @{ |
| bogdanm | 0:9b334a45a8ff | 276 | */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/ |
| bogdanm | 0:9b334a45a8ff | 278 | #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
| bogdanm | 0:9b334a45a8ff | 279 | #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
| bogdanm | 0:9b334a45a8ff | 280 | #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
| bogdanm | 0:9b334a45a8ff | 281 | /** |
| bogdanm | 0:9b334a45a8ff | 282 | * @} |
| bogdanm | 0:9b334a45a8ff | 283 | */ |
| bogdanm | 0:9b334a45a8ff | 284 | |
| bogdanm | 0:9b334a45a8ff | 285 | /** @defgroup QSPI_AlternateBytesMode |
| bogdanm | 0:9b334a45a8ff | 286 | * @{ |
| bogdanm | 0:9b334a45a8ff | 287 | */ |
| bogdanm | 0:9b334a45a8ff | 288 | #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/ |
| bogdanm | 0:9b334a45a8ff | 289 | #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
| bogdanm | 0:9b334a45a8ff | 290 | #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
| bogdanm | 0:9b334a45a8ff | 291 | #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
| bogdanm | 0:9b334a45a8ff | 292 | /** |
| bogdanm | 0:9b334a45a8ff | 293 | * @} |
| bogdanm | 0:9b334a45a8ff | 294 | */ |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | /** @defgroup QSPI_DataMode |
| bogdanm | 0:9b334a45a8ff | 297 | * @{ |
| bogdanm | 0:9b334a45a8ff | 298 | */ |
| bogdanm | 0:9b334a45a8ff | 299 | #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ |
| bogdanm | 0:9b334a45a8ff | 300 | #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
| bogdanm | 0:9b334a45a8ff | 301 | #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
| bogdanm | 0:9b334a45a8ff | 302 | #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
| bogdanm | 0:9b334a45a8ff | 303 | /** |
| bogdanm | 0:9b334a45a8ff | 304 | * @} |
| bogdanm | 0:9b334a45a8ff | 305 | */ |
| bogdanm | 0:9b334a45a8ff | 306 | |
| bogdanm | 0:9b334a45a8ff | 307 | /** @defgroup QSPI_DdrMode |
| bogdanm | 0:9b334a45a8ff | 308 | * @{ |
| bogdanm | 0:9b334a45a8ff | 309 | */ |
| bogdanm | 0:9b334a45a8ff | 310 | #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/ |
| bogdanm | 0:9b334a45a8ff | 311 | #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
| bogdanm | 0:9b334a45a8ff | 312 | /** |
| bogdanm | 0:9b334a45a8ff | 313 | * @} |
| bogdanm | 0:9b334a45a8ff | 314 | */ |
| bogdanm | 0:9b334a45a8ff | 315 | |
| bogdanm | 0:9b334a45a8ff | 316 | /** @defgroup QSPI_DdrHoldHalfCycle |
| bogdanm | 0:9b334a45a8ff | 317 | * @{ |
| bogdanm | 0:9b334a45a8ff | 318 | */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/ |
| bogdanm | 0:9b334a45a8ff | 320 | /** |
| bogdanm | 0:9b334a45a8ff | 321 | * @} |
| bogdanm | 0:9b334a45a8ff | 322 | */ |
| bogdanm | 0:9b334a45a8ff | 323 | |
| bogdanm | 0:9b334a45a8ff | 324 | /** @defgroup QSPI_SIOOMode |
| bogdanm | 0:9b334a45a8ff | 325 | * @{ |
| bogdanm | 0:9b334a45a8ff | 326 | */ |
| bogdanm | 0:9b334a45a8ff | 327 | #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/ |
| bogdanm | 0:9b334a45a8ff | 328 | #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
| bogdanm | 0:9b334a45a8ff | 329 | /** |
| bogdanm | 0:9b334a45a8ff | 330 | * @} |
| bogdanm | 0:9b334a45a8ff | 331 | */ |
| bogdanm | 0:9b334a45a8ff | 332 | |
| bogdanm | 0:9b334a45a8ff | 333 | /** @defgroup QSPI_MatchMode |
| bogdanm | 0:9b334a45a8ff | 334 | * @{ |
| bogdanm | 0:9b334a45a8ff | 335 | */ |
| bogdanm | 0:9b334a45a8ff | 336 | #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/ |
| bogdanm | 0:9b334a45a8ff | 337 | #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
| bogdanm | 0:9b334a45a8ff | 338 | /** |
| bogdanm | 0:9b334a45a8ff | 339 | * @} |
| bogdanm | 0:9b334a45a8ff | 340 | */ |
| bogdanm | 0:9b334a45a8ff | 341 | |
| bogdanm | 0:9b334a45a8ff | 342 | /** @defgroup QSPI_AutomaticStop |
| bogdanm | 0:9b334a45a8ff | 343 | * @{ |
| bogdanm | 0:9b334a45a8ff | 344 | */ |
| bogdanm | 0:9b334a45a8ff | 345 | #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/ |
| bogdanm | 0:9b334a45a8ff | 346 | #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
| bogdanm | 0:9b334a45a8ff | 347 | /** |
| bogdanm | 0:9b334a45a8ff | 348 | * @} |
| bogdanm | 0:9b334a45a8ff | 349 | */ |
| bogdanm | 0:9b334a45a8ff | 350 | |
| bogdanm | 0:9b334a45a8ff | 351 | /** @defgroup QSPI_TimeOutActivation |
| bogdanm | 0:9b334a45a8ff | 352 | * @{ |
| bogdanm | 0:9b334a45a8ff | 353 | */ |
| bogdanm | 0:9b334a45a8ff | 354 | #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/ |
| bogdanm | 0:9b334a45a8ff | 355 | #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
| bogdanm | 0:9b334a45a8ff | 356 | /** |
| bogdanm | 0:9b334a45a8ff | 357 | * @} |
| bogdanm | 0:9b334a45a8ff | 358 | */ |
| bogdanm | 0:9b334a45a8ff | 359 | |
| bogdanm | 0:9b334a45a8ff | 360 | /** @defgroup QSPI_Flags |
| bogdanm | 0:9b334a45a8ff | 361 | * @{ |
| bogdanm | 0:9b334a45a8ff | 362 | */ |
| bogdanm | 0:9b334a45a8ff | 363 | #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
| bogdanm | 0:9b334a45a8ff | 364 | #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
| bogdanm | 0:9b334a45a8ff | 365 | #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
| bogdanm | 0:9b334a45a8ff | 366 | #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
| bogdanm | 0:9b334a45a8ff | 367 | #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
| bogdanm | 0:9b334a45a8ff | 368 | #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
| bogdanm | 0:9b334a45a8ff | 369 | /** |
| bogdanm | 0:9b334a45a8ff | 370 | * @} |
| bogdanm | 0:9b334a45a8ff | 371 | */ |
| bogdanm | 0:9b334a45a8ff | 372 | |
| bogdanm | 0:9b334a45a8ff | 373 | /** @defgroup QSPI_Interrupts |
| bogdanm | 0:9b334a45a8ff | 374 | * @{ |
| bogdanm | 0:9b334a45a8ff | 375 | */ |
| bogdanm | 0:9b334a45a8ff | 376 | #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
| bogdanm | 0:9b334a45a8ff | 377 | #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
| bogdanm | 0:9b334a45a8ff | 378 | #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
| bogdanm | 0:9b334a45a8ff | 379 | #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
| bogdanm | 0:9b334a45a8ff | 380 | #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
| bogdanm | 0:9b334a45a8ff | 381 | /** |
| bogdanm | 0:9b334a45a8ff | 382 | * @} |
| bogdanm | 0:9b334a45a8ff | 383 | */ |
| bogdanm | 0:9b334a45a8ff | 384 | |
| bogdanm | 0:9b334a45a8ff | 385 | /** @defgroup QSPI_Timeout_definition |
| bogdanm | 0:9b334a45a8ff | 386 | * @brief QSPI Timeout definition |
| bogdanm | 0:9b334a45a8ff | 387 | * @{ |
| bogdanm | 0:9b334a45a8ff | 388 | */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ |
| bogdanm | 0:9b334a45a8ff | 390 | /** |
| bogdanm | 0:9b334a45a8ff | 391 | * @} |
| bogdanm | 0:9b334a45a8ff | 392 | */ |
| bogdanm | 0:9b334a45a8ff | 393 | |
| bogdanm | 0:9b334a45a8ff | 394 | /** |
| bogdanm | 0:9b334a45a8ff | 395 | * @} |
| bogdanm | 0:9b334a45a8ff | 396 | */ |
| bogdanm | 0:9b334a45a8ff | 397 | |
| bogdanm | 0:9b334a45a8ff | 398 | /* Exported macros -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 399 | /** @defgroup QSPI_Exported_Macros QSPI Exported Macros |
| bogdanm | 0:9b334a45a8ff | 400 | * @{ |
| bogdanm | 0:9b334a45a8ff | 401 | */ |
| bogdanm | 0:9b334a45a8ff | 402 | /** @brief Reset QSPI handle state. |
| bogdanm | 0:9b334a45a8ff | 403 | * @param __HANDLE__: QSPI handle. |
| bogdanm | 0:9b334a45a8ff | 404 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 405 | */ |
| bogdanm | 0:9b334a45a8ff | 406 | #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | /** @brief Enable the QSPI peripheral. |
| bogdanm | 0:9b334a45a8ff | 409 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 410 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 411 | */ |
| bogdanm | 0:9b334a45a8ff | 412 | #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| bogdanm | 0:9b334a45a8ff | 413 | |
| bogdanm | 0:9b334a45a8ff | 414 | /** @brief Disable the QSPI peripheral. |
| bogdanm | 0:9b334a45a8ff | 415 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 416 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 417 | */ |
| bogdanm | 0:9b334a45a8ff | 418 | #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| bogdanm | 0:9b334a45a8ff | 419 | |
| bogdanm | 0:9b334a45a8ff | 420 | /** @brief Enable the specified QSPI interrupt. |
| bogdanm | 0:9b334a45a8ff | 421 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 422 | * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. |
| bogdanm | 0:9b334a45a8ff | 423 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 424 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| bogdanm | 0:9b334a45a8ff | 425 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| bogdanm | 0:9b334a45a8ff | 426 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| bogdanm | 0:9b334a45a8ff | 427 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| bogdanm | 0:9b334a45a8ff | 428 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| bogdanm | 0:9b334a45a8ff | 429 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 430 | */ |
| bogdanm | 0:9b334a45a8ff | 431 | #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 432 | |
| bogdanm | 0:9b334a45a8ff | 433 | |
| bogdanm | 0:9b334a45a8ff | 434 | /** @brief Disable the specified QSPI interrupt. |
| bogdanm | 0:9b334a45a8ff | 435 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 436 | * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. |
| bogdanm | 0:9b334a45a8ff | 437 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 438 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| bogdanm | 0:9b334a45a8ff | 439 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| bogdanm | 0:9b334a45a8ff | 440 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| bogdanm | 0:9b334a45a8ff | 441 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| bogdanm | 0:9b334a45a8ff | 442 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| bogdanm | 0:9b334a45a8ff | 443 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 444 | */ |
| bogdanm | 0:9b334a45a8ff | 445 | #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 446 | |
| bogdanm | 0:9b334a45a8ff | 447 | /** @brief Check whether the specified QSPI interrupt source is enabled or not. |
| bogdanm | 0:9b334a45a8ff | 448 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 449 | * @param __INTERRUPT__: specifies the QSPI interrupt source to check. |
| bogdanm | 0:9b334a45a8ff | 450 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 451 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| bogdanm | 0:9b334a45a8ff | 452 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| bogdanm | 0:9b334a45a8ff | 453 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| bogdanm | 0:9b334a45a8ff | 454 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| bogdanm | 0:9b334a45a8ff | 455 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| bogdanm | 0:9b334a45a8ff | 456 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| bogdanm | 0:9b334a45a8ff | 457 | */ |
| bogdanm | 0:9b334a45a8ff | 458 | #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 459 | |
| bogdanm | 0:9b334a45a8ff | 460 | /** |
| bogdanm | 0:9b334a45a8ff | 461 | * @brief Check whether the selected QSPI flag is set or not. |
| bogdanm | 0:9b334a45a8ff | 462 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 463 | * @param __FLAG__: specifies the QSPI flag to check. |
| bogdanm | 0:9b334a45a8ff | 464 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 465 | * @arg QSPI_FLAG_BUSY: QSPI Busy flag |
| bogdanm | 0:9b334a45a8ff | 466 | * @arg QSPI_FLAG_TO: QSPI Timeout flag |
| bogdanm | 0:9b334a45a8ff | 467 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| bogdanm | 0:9b334a45a8ff | 468 | * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
| bogdanm | 0:9b334a45a8ff | 469 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 470 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 471 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 472 | */ |
| bogdanm | 0:9b334a45a8ff | 473 | #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) |
| bogdanm | 0:9b334a45a8ff | 474 | |
| bogdanm | 0:9b334a45a8ff | 475 | /** @brief Clears the specified QSPI's flag status. |
| bogdanm | 0:9b334a45a8ff | 476 | * @param __HANDLE__: specifies the QSPI Handle. |
| bogdanm | 0:9b334a45a8ff | 477 | * @param __FLAG__: specifies the QSPI clear register flag that needs to be set |
| bogdanm | 0:9b334a45a8ff | 478 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 479 | * @arg QSPI_FLAG_TO: QSPI Timeout flag |
| bogdanm | 0:9b334a45a8ff | 480 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| bogdanm | 0:9b334a45a8ff | 481 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 482 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 483 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 484 | */ |
| bogdanm | 0:9b334a45a8ff | 485 | #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 486 | /** |
| bogdanm | 0:9b334a45a8ff | 487 | * @} |
| bogdanm | 0:9b334a45a8ff | 488 | */ |
| bogdanm | 0:9b334a45a8ff | 489 | |
| bogdanm | 0:9b334a45a8ff | 490 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 491 | /** @addtogroup QSPI_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 492 | * @{ |
| bogdanm | 0:9b334a45a8ff | 493 | */ |
| bogdanm | 0:9b334a45a8ff | 494 | /* Initialization/de-initialization functions ********************************/ |
| bogdanm | 0:9b334a45a8ff | 495 | HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 496 | HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 497 | void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 498 | void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 499 | |
| bogdanm | 0:9b334a45a8ff | 500 | /* IO operation functions *****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 501 | /* QSPI IRQ handler method */ |
| bogdanm | 0:9b334a45a8ff | 502 | void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 503 | |
| bogdanm | 0:9b334a45a8ff | 504 | /* QSPI indirect mode */ |
| bogdanm | 0:9b334a45a8ff | 505 | HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 506 | HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 507 | HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 508 | HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
| bogdanm | 0:9b334a45a8ff | 509 | HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| bogdanm | 0:9b334a45a8ff | 510 | HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| bogdanm | 0:9b334a45a8ff | 511 | HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| bogdanm | 0:9b334a45a8ff | 512 | HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| bogdanm | 0:9b334a45a8ff | 513 | |
| bogdanm | 0:9b334a45a8ff | 514 | /* QSPI status flag polling mode */ |
| bogdanm | 0:9b334a45a8ff | 515 | HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 516 | HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
| bogdanm | 0:9b334a45a8ff | 517 | |
| bogdanm | 0:9b334a45a8ff | 518 | /* QSPI memory-mapped mode */ |
| bogdanm | 0:9b334a45a8ff | 519 | HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
| bogdanm | 0:9b334a45a8ff | 520 | |
| bogdanm | 0:9b334a45a8ff | 521 | /* Callback functions in non-blocking modes ***********************************/ |
| bogdanm | 0:9b334a45a8ff | 522 | void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 523 | void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 524 | |
| bogdanm | 0:9b334a45a8ff | 525 | /* QSPI indirect mode */ |
| bogdanm | 0:9b334a45a8ff | 526 | void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 527 | void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 528 | void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 529 | void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 530 | void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 531 | |
| bogdanm | 0:9b334a45a8ff | 532 | /* QSPI status flag polling mode */ |
| bogdanm | 0:9b334a45a8ff | 533 | void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 534 | |
| bogdanm | 0:9b334a45a8ff | 535 | /* QSPI memory-mapped mode */ |
| bogdanm | 0:9b334a45a8ff | 536 | void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 537 | |
| bogdanm | 0:9b334a45a8ff | 538 | /* Peripheral Control and State functions ************************************/ |
| bogdanm | 0:9b334a45a8ff | 539 | HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 540 | uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 541 | HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
| bogdanm | 0:9b334a45a8ff | 542 | void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 543 | /** |
| bogdanm | 0:9b334a45a8ff | 544 | * @} |
| bogdanm | 0:9b334a45a8ff | 545 | */ |
| bogdanm | 0:9b334a45a8ff | 546 | /* End of exported functions -------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 547 | |
| bogdanm | 0:9b334a45a8ff | 548 | /* Private macros ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 549 | /** @defgroup QSPI_Private_Macros QSPI Private Macros |
| bogdanm | 0:9b334a45a8ff | 550 | * @{ |
| bogdanm | 0:9b334a45a8ff | 551 | */ |
| bogdanm | 0:9b334a45a8ff | 552 | #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) |
| bogdanm | 0:9b334a45a8ff | 555 | |
| bogdanm | 0:9b334a45a8ff | 556 | #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 557 | ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
| bogdanm | 0:9b334a45a8ff | 558 | |
| bogdanm | 0:9b334a45a8ff | 559 | #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) |
| bogdanm | 0:9b334a45a8ff | 560 | |
| bogdanm | 0:9b334a45a8ff | 561 | #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 562 | ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 563 | ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 564 | ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 565 | ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 566 | ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 567 | ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
| bogdanm | 0:9b334a45a8ff | 568 | ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
| bogdanm | 0:9b334a45a8ff | 569 | |
| bogdanm | 0:9b334a45a8ff | 570 | #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
| bogdanm | 0:9b334a45a8ff | 571 | ((CLKMODE) == QSPI_CLOCK_MODE_3)) |
| bogdanm | 0:9b334a45a8ff | 572 | |
| bogdanm | 0:9b334a45a8ff | 573 | #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 576 | ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 577 | ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 578 | ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
| bogdanm | 0:9b334a45a8ff | 579 | |
| bogdanm | 0:9b334a45a8ff | 580 | #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 581 | ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 582 | ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
| bogdanm | 0:9b334a45a8ff | 583 | ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
| bogdanm | 0:9b334a45a8ff | 584 | |
| bogdanm | 0:9b334a45a8ff | 585 | #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) |
| bogdanm | 0:9b334a45a8ff | 586 | |
| bogdanm | 0:9b334a45a8ff | 587 | #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 588 | ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
| bogdanm | 0:9b334a45a8ff | 589 | ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
| bogdanm | 0:9b334a45a8ff | 590 | ((MODE) == QSPI_INSTRUCTION_4_LINES)) |
| bogdanm | 0:9b334a45a8ff | 591 | |
| bogdanm | 0:9b334a45a8ff | 592 | #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 593 | ((MODE) == QSPI_ADDRESS_1_LINE) || \ |
| bogdanm | 0:9b334a45a8ff | 594 | ((MODE) == QSPI_ADDRESS_2_LINES) || \ |
| bogdanm | 0:9b334a45a8ff | 595 | ((MODE) == QSPI_ADDRESS_4_LINES)) |
| bogdanm | 0:9b334a45a8ff | 596 | |
| bogdanm | 0:9b334a45a8ff | 597 | #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 598 | ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
| bogdanm | 0:9b334a45a8ff | 599 | ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
| bogdanm | 0:9b334a45a8ff | 600 | ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
| bogdanm | 0:9b334a45a8ff | 601 | |
| bogdanm | 0:9b334a45a8ff | 602 | #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 603 | ((MODE) == QSPI_DATA_1_LINE) || \ |
| bogdanm | 0:9b334a45a8ff | 604 | ((MODE) == QSPI_DATA_2_LINES) || \ |
| bogdanm | 0:9b334a45a8ff | 605 | ((MODE) == QSPI_DATA_4_LINES)) |
| bogdanm | 0:9b334a45a8ff | 606 | |
| bogdanm | 0:9b334a45a8ff | 607 | #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 608 | ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 609 | |
| bogdanm | 0:9b334a45a8ff | 610 | #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) |
| bogdanm | 0:9b334a45a8ff | 611 | |
| bogdanm | 0:9b334a45a8ff | 612 | #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
| bogdanm | 0:9b334a45a8ff | 613 | ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
| bogdanm | 0:9b334a45a8ff | 614 | |
| bogdanm | 0:9b334a45a8ff | 615 | #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) |
| bogdanm | 0:9b334a45a8ff | 618 | |
| bogdanm | 0:9b334a45a8ff | 619 | #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
| bogdanm | 0:9b334a45a8ff | 620 | ((MODE) == QSPI_MATCH_MODE_OR)) |
| bogdanm | 0:9b334a45a8ff | 621 | |
| bogdanm | 0:9b334a45a8ff | 622 | #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 623 | ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 624 | |
| bogdanm | 0:9b334a45a8ff | 625 | #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 626 | ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 627 | |
| bogdanm | 0:9b334a45a8ff | 628 | #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) |
| bogdanm | 0:9b334a45a8ff | 629 | /** |
| bogdanm | 0:9b334a45a8ff | 630 | * @} |
| bogdanm | 0:9b334a45a8ff | 631 | */ |
| bogdanm | 0:9b334a45a8ff | 632 | /* End of private macros -----------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 633 | |
| bogdanm | 0:9b334a45a8ff | 634 | /** |
| bogdanm | 0:9b334a45a8ff | 635 | * @} |
| bogdanm | 0:9b334a45a8ff | 636 | */ |
| bogdanm | 0:9b334a45a8ff | 637 | |
| bogdanm | 0:9b334a45a8ff | 638 | /** |
| bogdanm | 0:9b334a45a8ff | 639 | * @} |
| bogdanm | 0:9b334a45a8ff | 640 | */ |
| bogdanm | 0:9b334a45a8ff | 641 | |
| bogdanm | 0:9b334a45a8ff | 642 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 643 | } |
| bogdanm | 0:9b334a45a8ff | 644 | #endif |
| bogdanm | 0:9b334a45a8ff | 645 | |
| bogdanm | 0:9b334a45a8ff | 646 | #endif /* __STM32L4xx_HAL_QSPI_H */ |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |