en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_nor.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_nor.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief NOR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NOR memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NOR flash memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NOR devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both normal and extended mode.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NOR flash memory by read/write data unit operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NOR_Read(), HAL_NOR_Program().
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 (+) Perform NOR flash erase block/chip operations using the functions
bogdanm 0:9b334a45a8ff 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
bogdanm 0:9b334a45a8ff 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
bogdanm 0:9b334a45a8ff 35 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) You can monitor the NOR device HAL state by calling the function
bogdanm 0:9b334a45a8ff 41 HAL_NOR_GetState()
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
bogdanm 0:9b334a45a8ff 44 If a NOR flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 45 it should be implemented separately.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** NOR HAL driver macros list ***
bogdanm 0:9b334a45a8ff 48 =============================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 Below the list of most used macros in NOR HAL driver.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (+) NOR_WRITE : NOR memory write data to specified address
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32l4xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NOR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /** @defgroup NOR NOR
bogdanm 0:9b334a45a8ff 95 * @brief NOR HAL module driver
bogdanm 0:9b334a45a8ff 96 * @{
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 99 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100 /** @defgroup NOR_Private_Constants NOR Private Constants
bogdanm 0:9b334a45a8ff 101 * @{
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /* Constants to define address to set to write a command */
bogdanm 0:9b334a45a8ff 105 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 106 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 107 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 108 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 109 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 110 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 111 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /* Constants to define data to program a command */
bogdanm 0:9b334a45a8ff 114 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
bogdanm 0:9b334a45a8ff 115 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 116 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 117 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
bogdanm 0:9b334a45a8ff 118 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
bogdanm 0:9b334a45a8ff 119 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
bogdanm 0:9b334a45a8ff 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 122 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
bogdanm 0:9b334a45a8ff 123 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
bogdanm 0:9b334a45a8ff 126 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
bogdanm 0:9b334a45a8ff 127 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* Mask on NOR STATUS REGISTER */
bogdanm 0:9b334a45a8ff 130 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
bogdanm 0:9b334a45a8ff 131 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /**
bogdanm 0:9b334a45a8ff 134 * @}
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 138 /** @defgroup NOR_Private_Macros NOR Private Macros
bogdanm 0:9b334a45a8ff 139 * @{
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /** @defgroup NOR_Private_Variables NOR Private Variables
bogdanm 0:9b334a45a8ff 149 * @{
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /**
bogdanm 0:9b334a45a8ff 155 * @}
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /** @defgroup NOR_Exported_Functions NOR Exported Functions
bogdanm 0:9b334a45a8ff 161 * @{
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 165 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 166 *
bogdanm 0:9b334a45a8ff 167 @verbatim
bogdanm 0:9b334a45a8ff 168 ==============================================================================
bogdanm 0:9b334a45a8ff 169 ##### NOR Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 170 ==============================================================================
bogdanm 0:9b334a45a8ff 171 [..]
bogdanm 0:9b334a45a8ff 172 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 173 the NOR memory
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 @endverbatim
bogdanm 0:9b334a45a8ff 176 * @{
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /**
bogdanm 0:9b334a45a8ff 180 * @brief Perform the NOR memory Initialization sequence.
bogdanm 0:9b334a45a8ff 181 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 182 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 183 * @param Timing: pointer to NOR control timing structure
bogdanm 0:9b334a45a8ff 184 * @param ExtTiming: pointer to NOR extended mode timing structure
bogdanm 0:9b334a45a8ff 185 * @retval HAL status
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 188 {
bogdanm 0:9b334a45a8ff 189 /* Check the NOR handle parameter */
bogdanm 0:9b334a45a8ff 190 if(hnor == NULL)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 if(hnor->State == HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 196 {
bogdanm 0:9b334a45a8ff 197 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 198 hnor->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 201 HAL_NOR_MspInit(hnor);
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Initialize NOR control Interface */
bogdanm 0:9b334a45a8ff 205 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Initialize NOR timing Interface */
bogdanm 0:9b334a45a8ff 208 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Initialize NOR extended mode timing Interface */
bogdanm 0:9b334a45a8ff 211 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 214 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Initialize NOR Memory Data Width*/
bogdanm 0:9b334a45a8ff 217 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
bogdanm 0:9b334a45a8ff 218 {
bogdanm 0:9b334a45a8ff 219 uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221 else
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 uwNORMemoryDataWidth = NOR_MEMORY_16B;
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 227 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 return HAL_OK;
bogdanm 0:9b334a45a8ff 230 }
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /**
bogdanm 0:9b334a45a8ff 233 * @brief Perform NOR memory De-Initialization sequence.
bogdanm 0:9b334a45a8ff 234 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 235 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 236 * @retval HAL status
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 239 {
bogdanm 0:9b334a45a8ff 240 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 241 HAL_NOR_MspDeInit(hnor);
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /* Configure the NOR registers with their reset values */
bogdanm 0:9b334a45a8ff 244 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 247 hnor->State = HAL_NOR_STATE_RESET;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* Release Lock */
bogdanm 0:9b334a45a8ff 250 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 return HAL_OK;
bogdanm 0:9b334a45a8ff 253 }
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /**
bogdanm 0:9b334a45a8ff 256 * @brief Initialize the NOR MSP.
bogdanm 0:9b334a45a8ff 257 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 258 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 259 * @retval None
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 264 the HAL_NOR_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 265 */
bogdanm 0:9b334a45a8ff 266 }
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /**
bogdanm 0:9b334a45a8ff 269 * @brief DeInitialize the NOR MSP.
bogdanm 0:9b334a45a8ff 270 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 271 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 272 * @retval None
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 275 {
bogdanm 0:9b334a45a8ff 276 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 277 the HAL_NOR_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 278 */
bogdanm 0:9b334a45a8ff 279 }
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 /**
bogdanm 0:9b334a45a8ff 282 * @brief NOR MSP Wait for Ready/Busy signal.
bogdanm 0:9b334a45a8ff 283 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 284 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 285 * @param Timeout: Maximum timeout value
bogdanm 0:9b334a45a8ff 286 * @retval None
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 289 {
bogdanm 0:9b334a45a8ff 290 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 291 the HAL_NOR_MspWait could be implemented in the user file
bogdanm 0:9b334a45a8ff 292 */
bogdanm 0:9b334a45a8ff 293 }
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /**
bogdanm 0:9b334a45a8ff 296 * @}
bogdanm 0:9b334a45a8ff 297 */
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 300 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 301 *
bogdanm 0:9b334a45a8ff 302 @verbatim
bogdanm 0:9b334a45a8ff 303 ==============================================================================
bogdanm 0:9b334a45a8ff 304 ##### NOR Input and Output functions #####
bogdanm 0:9b334a45a8ff 305 ==============================================================================
bogdanm 0:9b334a45a8ff 306 [..]
bogdanm 0:9b334a45a8ff 307 This section provides functions allowing to use and control the NOR memory
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 @endverbatim
bogdanm 0:9b334a45a8ff 310 * @{
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 /**
bogdanm 0:9b334a45a8ff 314 * @brief Read NOR flash IDs.
bogdanm 0:9b334a45a8ff 315 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 316 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 317 * @param pNOR_ID : pointer to NOR ID structure
bogdanm 0:9b334a45a8ff 318 * @retval HAL status
bogdanm 0:9b334a45a8ff 319 */
bogdanm 0:9b334a45a8ff 320 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
bogdanm 0:9b334a45a8ff 321 {
bogdanm 0:9b334a45a8ff 322 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 /* Process Locked */
bogdanm 0:9b334a45a8ff 325 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 328 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 329 {
bogdanm 0:9b334a45a8ff 330 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 334 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 341 }
bogdanm 0:9b334a45a8ff 342 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 347 {
bogdanm 0:9b334a45a8ff 348 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 352 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Send read ID command */
bogdanm 0:9b334a45a8ff 355 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Read the NOR IDs */
bogdanm 0:9b334a45a8ff 360 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
bogdanm 0:9b334a45a8ff 361 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
bogdanm 0:9b334a45a8ff 362 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
bogdanm 0:9b334a45a8ff 363 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 366 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* Process unlocked */
bogdanm 0:9b334a45a8ff 369 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 return HAL_OK;
bogdanm 0:9b334a45a8ff 372 }
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /**
bogdanm 0:9b334a45a8ff 375 * @brief Return the NOR memory to Read mode.
bogdanm 0:9b334a45a8ff 376 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 377 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 378 * @retval HAL status
bogdanm 0:9b334a45a8ff 379 */
bogdanm 0:9b334a45a8ff 380 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 /* Process Locked */
bogdanm 0:9b334a45a8ff 385 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 388 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 394 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 401 }
bogdanm 0:9b334a45a8ff 402 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 414 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Process unlocked */
bogdanm 0:9b334a45a8ff 417 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 return HAL_OK;
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /**
bogdanm 0:9b334a45a8ff 423 * @brief Read data from NOR memory.
bogdanm 0:9b334a45a8ff 424 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 425 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 426 * @param pAddress: pointer to Device address
bogdanm 0:9b334a45a8ff 427 * @param pData : pointer to read data
bogdanm 0:9b334a45a8ff 428 * @retval HAL status
bogdanm 0:9b334a45a8ff 429 */
bogdanm 0:9b334a45a8ff 430 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 431 {
bogdanm 0:9b334a45a8ff 432 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 /* Process Locked */
bogdanm 0:9b334a45a8ff 435 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 438 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 444 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 445 {
bogdanm 0:9b334a45a8ff 446 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 447 }
bogdanm 0:9b334a45a8ff 448 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 453 {
bogdanm 0:9b334a45a8ff 454 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 462 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Send read data command */
bogdanm 0:9b334a45a8ff 465 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 467 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Read the data */
bogdanm 0:9b334a45a8ff 470 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 473 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /* Process unlocked */
bogdanm 0:9b334a45a8ff 476 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 return HAL_OK;
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /**
bogdanm 0:9b334a45a8ff 482 * @brief Program data to NOR memory.
bogdanm 0:9b334a45a8ff 483 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 484 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 485 * @param pAddress: Device address
bogdanm 0:9b334a45a8ff 486 * @param pData : pointer to the data to write
bogdanm 0:9b334a45a8ff 487 * @retval HAL status
bogdanm 0:9b334a45a8ff 488 */
bogdanm 0:9b334a45a8ff 489 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Process Locked */
bogdanm 0:9b334a45a8ff 494 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 497 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 503 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 516 {
bogdanm 0:9b334a45a8ff 517 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 518 }
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 521 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Send program data command */
bogdanm 0:9b334a45a8ff 524 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /* Write the data */
bogdanm 0:9b334a45a8ff 529 NOR_WRITE(pAddress, *pData);
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 532 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /* Process unlocked */
bogdanm 0:9b334a45a8ff 535 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 return HAL_OK;
bogdanm 0:9b334a45a8ff 538 }
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /**
bogdanm 0:9b334a45a8ff 541 * @brief Read a block of data from the FMC NOR memory.
bogdanm 0:9b334a45a8ff 542 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 543 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 544 * @param uwAddress: NOR memory internal address to read from.
bogdanm 0:9b334a45a8ff 545 * @param pData: pointer to the buffer that receives the data read from the
bogdanm 0:9b334a45a8ff 546 * NOR memory.
bogdanm 0:9b334a45a8ff 547 * @param uwBufferSize : number of Half word to read.
bogdanm 0:9b334a45a8ff 548 * @retval HAL status
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 551 {
bogdanm 0:9b334a45a8ff 552 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Process Locked */
bogdanm 0:9b334a45a8ff 555 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 558 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 564 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 571 }
bogdanm 0:9b334a45a8ff 572 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 573 {
bogdanm 0:9b334a45a8ff 574 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 577 {
bogdanm 0:9b334a45a8ff 578 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 582 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 /* Send read data command */
bogdanm 0:9b334a45a8ff 585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 587 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /* Read buffer */
bogdanm 0:9b334a45a8ff 590 while( uwBufferSize > 0)
bogdanm 0:9b334a45a8ff 591 {
bogdanm 0:9b334a45a8ff 592 *pData++ = *(__IO uint16_t *)uwAddress;
bogdanm 0:9b334a45a8ff 593 uwAddress += 2;
bogdanm 0:9b334a45a8ff 594 uwBufferSize--;
bogdanm 0:9b334a45a8ff 595 }
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 598 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* Process unlocked */
bogdanm 0:9b334a45a8ff 601 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 return HAL_OK;
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /**
bogdanm 0:9b334a45a8ff 607 * @brief Write a half-word buffer to the FMC NOR memory. This function
bogdanm 0:9b334a45a8ff 608 * must be used only with S29GL128P NOR memory.
bogdanm 0:9b334a45a8ff 609 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 610 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 611 * @param uwAddress: NOR memory internal address from which the data
bogdanm 0:9b334a45a8ff 612 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
bogdanm 0:9b334a45a8ff 613 * 64 bytes boundary for example).
bogdanm 0:9b334a45a8ff 614 * @param pData: pointer to source data buffer.
bogdanm 0:9b334a45a8ff 615 * @param uwBufferSize: number of Half words to write.
bogdanm 0:9b334a45a8ff 616 * @note The maximum buffer size allowed is NOR memory dependent
bogdanm 0:9b334a45a8ff 617 * (can be 64 Bytes max for example).
bogdanm 0:9b334a45a8ff 618 * @retval HAL status
bogdanm 0:9b334a45a8ff 619 */
bogdanm 0:9b334a45a8ff 620 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 621 {
bogdanm 0:9b334a45a8ff 622 uint16_t * p_currentaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 623 uint16_t * p_endaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 624 uint32_t lastloadedaddress = 0, deviceaddress = 0;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Process Locked */
bogdanm 0:9b334a45a8ff 627 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 630 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 633 }
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 636 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 637 {
bogdanm 0:9b334a45a8ff 638 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 639 }
bogdanm 0:9b334a45a8ff 640 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 641 {
bogdanm 0:9b334a45a8ff 642 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 647 }
bogdanm 0:9b334a45a8ff 648 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 651 }
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 654 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /* Initialize variables */
bogdanm 0:9b334a45a8ff 657 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
bogdanm 0:9b334a45a8ff 658 p_endaddress = p_currentaddress + (uwBufferSize-1);
bogdanm 0:9b334a45a8ff 659 lastloadedaddress = (uint32_t)(uwAddress);
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /* Issue unlock command sequence */
bogdanm 0:9b334a45a8ff 662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 663 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /* Write Buffer Load Command */
bogdanm 0:9b334a45a8ff 666 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
bogdanm 0:9b334a45a8ff 667 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /* Load Data into NOR Buffer */
bogdanm 0:9b334a45a8ff 670 while(p_currentaddress <= p_endaddress)
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 /* Store last loaded address & data value (for polling) */
bogdanm 0:9b334a45a8ff 673 lastloadedaddress = (uint32_t)p_currentaddress;
bogdanm 0:9b334a45a8ff 674
bogdanm 0:9b334a45a8ff 675 NOR_WRITE(p_currentaddress, *pData++);
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 p_currentaddress++;
bogdanm 0:9b334a45a8ff 678 }
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 683 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /* Process unlocked */
bogdanm 0:9b334a45a8ff 686 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 return HAL_OK;
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /**
bogdanm 0:9b334a45a8ff 693 * @brief Erase the specified block of the NOR memory.
bogdanm 0:9b334a45a8ff 694 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 695 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 696 * @param BlockAddress : Block to erase address
bogdanm 0:9b334a45a8ff 697 * @param Address: Device address
bogdanm 0:9b334a45a8ff 698 * @retval HAL status
bogdanm 0:9b334a45a8ff 699 */
bogdanm 0:9b334a45a8ff 700 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
bogdanm 0:9b334a45a8ff 701 {
bogdanm 0:9b334a45a8ff 702 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Process Locked */
bogdanm 0:9b334a45a8ff 705 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 708 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 714 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 715 {
bogdanm 0:9b334a45a8ff 716 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 717 }
bogdanm 0:9b334a45a8ff 718 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 719 {
bogdanm 0:9b334a45a8ff 720 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 721 }
bogdanm 0:9b334a45a8ff 722 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 723 {
bogdanm 0:9b334a45a8ff 724 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 725 }
bogdanm 0:9b334a45a8ff 726 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 727 {
bogdanm 0:9b334a45a8ff 728 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 732 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /* Send block erase command sequence */
bogdanm 0:9b334a45a8ff 735 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 736 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 737 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 738 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 739 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 740 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 743 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Process unlocked */
bogdanm 0:9b334a45a8ff 746 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 return HAL_OK;
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 }
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /**
bogdanm 0:9b334a45a8ff 753 * @brief Erase the entire NOR chip.
bogdanm 0:9b334a45a8ff 754 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 755 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 756 * @param Address : Device address
bogdanm 0:9b334a45a8ff 757 * @retval HAL status
bogdanm 0:9b334a45a8ff 758 */
bogdanm 0:9b334a45a8ff 759 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
bogdanm 0:9b334a45a8ff 760 {
bogdanm 0:9b334a45a8ff 761 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /* Process Locked */
bogdanm 0:9b334a45a8ff 764 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 767 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 770 }
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 773 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 774 {
bogdanm 0:9b334a45a8ff 775 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 776 }
bogdanm 0:9b334a45a8ff 777 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 778 {
bogdanm 0:9b334a45a8ff 779 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 780 }
bogdanm 0:9b334a45a8ff 781 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 782 {
bogdanm 0:9b334a45a8ff 783 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 784 }
bogdanm 0:9b334a45a8ff 785 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 786 {
bogdanm 0:9b334a45a8ff 787 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 788 }
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 791 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /* Send NOR chip erase command sequence */
bogdanm 0:9b334a45a8ff 794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 795 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 796 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 797 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 798 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 799 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 802 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* Process unlocked */
bogdanm 0:9b334a45a8ff 805 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 return HAL_OK;
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 /**
bogdanm 0:9b334a45a8ff 811 * @brief Read NOR flash CFI IDs.
bogdanm 0:9b334a45a8ff 812 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 813 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 814 * @param pNOR_CFI : pointer to NOR CFI IDs structure
bogdanm 0:9b334a45a8ff 815 * @retval HAL status
bogdanm 0:9b334a45a8ff 816 */
bogdanm 0:9b334a45a8ff 817 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
bogdanm 0:9b334a45a8ff 818 {
bogdanm 0:9b334a45a8ff 819 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 820
bogdanm 0:9b334a45a8ff 821 /* Process Locked */
bogdanm 0:9b334a45a8ff 822 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 823
bogdanm 0:9b334a45a8ff 824 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 825 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 826 {
bogdanm 0:9b334a45a8ff 827 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 828 }
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 831 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 832 {
bogdanm 0:9b334a45a8ff 833 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 834 }
bogdanm 0:9b334a45a8ff 835 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 836 {
bogdanm 0:9b334a45a8ff 837 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 838 }
bogdanm 0:9b334a45a8ff 839 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 840 {
bogdanm 0:9b334a45a8ff 841 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 842 }
bogdanm 0:9b334a45a8ff 843 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847
bogdanm 0:9b334a45a8ff 848 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 849 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 850
bogdanm 0:9b334a45a8ff 851 /* Send read CFI query command */
bogdanm 0:9b334a45a8ff 852 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
bogdanm 0:9b334a45a8ff 853
bogdanm 0:9b334a45a8ff 854 /* read the NOR CFI information */
bogdanm 0:9b334a45a8ff 855 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
bogdanm 0:9b334a45a8ff 856 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
bogdanm 0:9b334a45a8ff 857 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
bogdanm 0:9b334a45a8ff 858 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 861 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 /* Process unlocked */
bogdanm 0:9b334a45a8ff 864 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 return HAL_OK;
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /**
bogdanm 0:9b334a45a8ff 870 * @}
bogdanm 0:9b334a45a8ff 871 */
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 874 * @brief management functions
bogdanm 0:9b334a45a8ff 875 *
bogdanm 0:9b334a45a8ff 876 @verbatim
bogdanm 0:9b334a45a8ff 877 ==============================================================================
bogdanm 0:9b334a45a8ff 878 ##### NOR Control functions #####
bogdanm 0:9b334a45a8ff 879 ==============================================================================
bogdanm 0:9b334a45a8ff 880 [..]
bogdanm 0:9b334a45a8ff 881 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 882 the NOR interface.
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 @endverbatim
bogdanm 0:9b334a45a8ff 885 * @{
bogdanm 0:9b334a45a8ff 886 */
bogdanm 0:9b334a45a8ff 887
bogdanm 0:9b334a45a8ff 888 /**
bogdanm 0:9b334a45a8ff 889 * @brief Enable dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 890 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 891 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 892 * @retval HAL status
bogdanm 0:9b334a45a8ff 893 */
bogdanm 0:9b334a45a8ff 894 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 895 {
bogdanm 0:9b334a45a8ff 896 /* Process Locked */
bogdanm 0:9b334a45a8ff 897 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 /* Enable write operation */
bogdanm 0:9b334a45a8ff 900 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 903 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /* Process unlocked */
bogdanm 0:9b334a45a8ff 906 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 907
bogdanm 0:9b334a45a8ff 908 return HAL_OK;
bogdanm 0:9b334a45a8ff 909 }
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 /**
bogdanm 0:9b334a45a8ff 912 * @brief Disable dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 913 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 914 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 915 * @retval HAL status
bogdanm 0:9b334a45a8ff 916 */
bogdanm 0:9b334a45a8ff 917 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 /* Process Locked */
bogdanm 0:9b334a45a8ff 920 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 921
bogdanm 0:9b334a45a8ff 922 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 923 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 924
bogdanm 0:9b334a45a8ff 925 /* Disable write operation */
bogdanm 0:9b334a45a8ff 926 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 929 hnor->State = HAL_NOR_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 930
bogdanm 0:9b334a45a8ff 931 /* Process unlocked */
bogdanm 0:9b334a45a8ff 932 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 933
bogdanm 0:9b334a45a8ff 934 return HAL_OK;
bogdanm 0:9b334a45a8ff 935 }
bogdanm 0:9b334a45a8ff 936
bogdanm 0:9b334a45a8ff 937 /**
bogdanm 0:9b334a45a8ff 938 * @}
bogdanm 0:9b334a45a8ff 939 */
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 942 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 943 *
bogdanm 0:9b334a45a8ff 944 @verbatim
bogdanm 0:9b334a45a8ff 945 ==============================================================================
bogdanm 0:9b334a45a8ff 946 ##### NOR State functions #####
bogdanm 0:9b334a45a8ff 947 ==============================================================================
bogdanm 0:9b334a45a8ff 948 [..]
bogdanm 0:9b334a45a8ff 949 This subsection permits to get in run-time the status of the NOR controller
bogdanm 0:9b334a45a8ff 950 and the data flow.
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 @endverbatim
bogdanm 0:9b334a45a8ff 953 * @{
bogdanm 0:9b334a45a8ff 954 */
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /**
bogdanm 0:9b334a45a8ff 957 * @brief Return the NOR controller handle state.
bogdanm 0:9b334a45a8ff 958 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 959 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 960 * @retval NOR controller state
bogdanm 0:9b334a45a8ff 961 */
bogdanm 0:9b334a45a8ff 962 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 963 {
bogdanm 0:9b334a45a8ff 964 /* Return NOR handle state */
bogdanm 0:9b334a45a8ff 965 return hnor->State;
bogdanm 0:9b334a45a8ff 966 }
bogdanm 0:9b334a45a8ff 967
bogdanm 0:9b334a45a8ff 968 /**
bogdanm 0:9b334a45a8ff 969 * @brief Return the NOR operation status.
bogdanm 0:9b334a45a8ff 970 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 971 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 972 * @param Address: Device address
bogdanm 0:9b334a45a8ff 973 * @param Timeout: NOR programming Timeout
bogdanm 0:9b334a45a8ff 974 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
bogdanm 0:9b334a45a8ff 975 * or HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 976 */
bogdanm 0:9b334a45a8ff 977 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 978 {
bogdanm 0:9b334a45a8ff 979 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 980 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
bogdanm 0:9b334a45a8ff 981 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 982
bogdanm 0:9b334a45a8ff 983 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
bogdanm 0:9b334a45a8ff 984 HAL_NOR_MspWait(hnor, Timeout);
bogdanm 0:9b334a45a8ff 985
bogdanm 0:9b334a45a8ff 986 /* Get tick */
bogdanm 0:9b334a45a8ff 987 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 988 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
bogdanm 0:9b334a45a8ff 989 {
bogdanm 0:9b334a45a8ff 990 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 991 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 992 {
bogdanm 0:9b334a45a8ff 993 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 994 {
bogdanm 0:9b334a45a8ff 995 status = HAL_NOR_STATUS_TIMEOUT;
bogdanm 0:9b334a45a8ff 996 }
bogdanm 0:9b334a45a8ff 997 }
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 /* Read NOR status register (DQ6 and DQ5) */
bogdanm 0:9b334a45a8ff 1000 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1001 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1004 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1005 {
bogdanm 0:9b334a45a8ff 1006 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1007 }
bogdanm 0:9b334a45a8ff 1008
bogdanm 0:9b334a45a8ff 1009 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1010 {
bogdanm 0:9b334a45a8ff 1011 status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 1012 }
bogdanm 0:9b334a45a8ff 1013
bogdanm 0:9b334a45a8ff 1014 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1015 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1016
bogdanm 0:9b334a45a8ff 1017 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1018 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1019 {
bogdanm 0:9b334a45a8ff 1020 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1021 }
bogdanm 0:9b334a45a8ff 1022 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1023 {
bogdanm 0:9b334a45a8ff 1024 return HAL_NOR_STATUS_ERROR;
bogdanm 0:9b334a45a8ff 1025 }
bogdanm 0:9b334a45a8ff 1026 }
bogdanm 0:9b334a45a8ff 1027
bogdanm 0:9b334a45a8ff 1028 /* Return the operation status */
bogdanm 0:9b334a45a8ff 1029 return status;
bogdanm 0:9b334a45a8ff 1030 }
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /**
bogdanm 0:9b334a45a8ff 1033 * @}
bogdanm 0:9b334a45a8ff 1034 */
bogdanm 0:9b334a45a8ff 1035
bogdanm 0:9b334a45a8ff 1036 /**
bogdanm 0:9b334a45a8ff 1037 * @}
bogdanm 0:9b334a45a8ff 1038 */
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @}
bogdanm 0:9b334a45a8ff 1041 */
bogdanm 0:9b334a45a8ff 1042 #endif /* HAL_NOR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /**
bogdanm 0:9b334a45a8ff 1045 * @}
bogdanm 0:9b334a45a8ff 1046 */
bogdanm 0:9b334a45a8ff 1047
bogdanm 0:9b334a45a8ff 1048 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/