en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_nand.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_nand.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of NAND HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L4xx_HAL_NAND_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L4xx_HAL_NAND_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32l4xx_ll_fmc.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup NAND
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /** @addtogroup NAND_Private_Constants
bogdanm 0:9b334a45a8ff 58 * @{
bogdanm 0:9b334a45a8ff 59 */
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 #define NAND_DEVICE FMC_BANK3
bogdanm 0:9b334a45a8ff 62 #define NAND_WRITE_TIMEOUT ((uint32_t)1000)
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
bogdanm 0:9b334a45a8ff 65 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 #define NAND_CMD_AREA_A ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 68 #define NAND_CMD_AREA_B ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 69 #define NAND_CMD_AREA_C ((uint8_t)0x50)
bogdanm 0:9b334a45a8ff 70 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
bogdanm 0:9b334a45a8ff 73 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
bogdanm 0:9b334a45a8ff 74 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
bogdanm 0:9b334a45a8ff 75 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
bogdanm 0:9b334a45a8ff 76 #define NAND_CMD_READID ((uint8_t)0x90)
bogdanm 0:9b334a45a8ff 77 #define NAND_CMD_STATUS ((uint8_t)0x70)
bogdanm 0:9b334a45a8ff 78 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
bogdanm 0:9b334a45a8ff 79 #define NAND_CMD_RESET ((uint8_t)0xFF)
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /* NAND memory status */
bogdanm 0:9b334a45a8ff 82 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 83 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 84 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 85 #define NAND_BUSY ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 86 #define NAND_ERROR ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 87 #define NAND_READY ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /**
bogdanm 0:9b334a45a8ff 90 * @}
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /** @addtogroup NAND_Private_Macros
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /**
bogdanm 0:9b334a45a8ff 98 * @brief NAND memory address computation.
bogdanm 0:9b334a45a8ff 99 * @param __ADDRESS__: NAND memory address.
bogdanm 0:9b334a45a8ff 100 * @param __HANDLE__: NAND handle.
bogdanm 0:9b334a45a8ff 101 * @retval NAND Raw address value
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
bogdanm 0:9b334a45a8ff 104 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /**
bogdanm 0:9b334a45a8ff 107 * @brief NAND memory address cycling.
bogdanm 0:9b334a45a8ff 108 * @param __ADDRESS__: NAND memory address.
bogdanm 0:9b334a45a8ff 109 * @retval NAND address cycling value.
bogdanm 0:9b334a45a8ff 110 */
bogdanm 0:9b334a45a8ff 111 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
bogdanm 0:9b334a45a8ff 112 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
bogdanm 0:9b334a45a8ff 113 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
bogdanm 0:9b334a45a8ff 114 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
bogdanm 0:9b334a45a8ff 117 * @}
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* Exported typedef ----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 /** @defgroup NAND_Exported_Types NAND Exported Types
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /**
bogdanm 0:9b334a45a8ff 127 * @brief HAL NAND State structures definition
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129 typedef enum
bogdanm 0:9b334a45a8ff 130 {
bogdanm 0:9b334a45a8ff 131 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 132 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
bogdanm 0:9b334a45a8ff 133 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
bogdanm 0:9b334a45a8ff 134 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
bogdanm 0:9b334a45a8ff 135 }HAL_NAND_StateTypeDef;
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @brief NAND Memory electronic signature Structure definition
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140 typedef struct
bogdanm 0:9b334a45a8ff 141 {
bogdanm 0:9b334a45a8ff 142 /*<! NAND memory electronic signature maker and device IDs */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 uint8_t Maker_Id;
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 uint8_t Device_Id;
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 uint8_t Third_Id;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 uint8_t Fourth_Id;
bogdanm 0:9b334a45a8ff 151 }NAND_IDTypeDef;
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /**
bogdanm 0:9b334a45a8ff 154 * @brief NAND Memory address Structure definition
bogdanm 0:9b334a45a8ff 155 */
bogdanm 0:9b334a45a8ff 156 typedef struct
bogdanm 0:9b334a45a8ff 157 {
bogdanm 0:9b334a45a8ff 158 uint16_t Page; /*!< NAND memory Page address */
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 uint16_t Zone; /*!< NAND memory Zone address */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 uint16_t Block; /*!< NAND memory Block address */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 }NAND_AddressTypeDef;
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @brief NAND Memory info Structure definition
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169 typedef struct
bogdanm 0:9b334a45a8ff 170 {
bogdanm 0:9b334a45a8ff 171 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 uint32_t BlockSize; /*!< NAND memory block size number of pages */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 uint32_t BlockNbr; /*!< NAND memory number of blocks */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
bogdanm 0:9b334a45a8ff 180 }NAND_InfoTypeDef;
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /**
bogdanm 0:9b334a45a8ff 183 * @brief NAND handle Structure definition
bogdanm 0:9b334a45a8ff 184 */
bogdanm 0:9b334a45a8ff 185 typedef struct
bogdanm 0:9b334a45a8ff 186 {
bogdanm 0:9b334a45a8ff 187 FMC_NAND_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 HAL_LockTypeDef Lock; /*!< NAND locking object */
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
bogdanm 0:9b334a45a8ff 196 }NAND_HandleTypeDef;
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /**
bogdanm 0:9b334a45a8ff 199 * @}
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 203 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 204 /** @defgroup NAND_Exported_Macros NAND Exported Macros
bogdanm 0:9b334a45a8ff 205 * @{
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /** @brief Reset NAND handle state.
bogdanm 0:9b334a45a8ff 209 * @param __HANDLE__: specifies the NAND handle.
bogdanm 0:9b334a45a8ff 210 * @retval None
bogdanm 0:9b334a45a8ff 211 */
bogdanm 0:9b334a45a8ff 212 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /**
bogdanm 0:9b334a45a8ff 215 * @}
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 219 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
bogdanm 0:9b334a45a8ff 220 * @{
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 224 * @{
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Initialization/de-initialization functions ********************************/
bogdanm 0:9b334a45a8ff 228 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
bogdanm 0:9b334a45a8ff 229 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 230 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 231 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 232 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 233 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /**
bogdanm 0:9b334a45a8ff 236 * @}
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 240 * @{
bogdanm 0:9b334a45a8ff 241 */
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /* IO operation functions ****************************************************/
bogdanm 0:9b334a45a8ff 244 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
bogdanm 0:9b334a45a8ff 245 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 246 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
bogdanm 0:9b334a45a8ff 247 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
bogdanm 0:9b334a45a8ff 248 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
bogdanm 0:9b334a45a8ff 249 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
bogdanm 0:9b334a45a8ff 250 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
bogdanm 0:9b334a45a8ff 251 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 252 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /**
bogdanm 0:9b334a45a8ff 255 * @}
bogdanm 0:9b334a45a8ff 256 */
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 259 * @{
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* NAND Control functions ****************************************************/
bogdanm 0:9b334a45a8ff 263 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 264 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 265 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /**
bogdanm 0:9b334a45a8ff 268 * @}
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 272 * @{
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /* NAND State functions *******************************************************/
bogdanm 0:9b334a45a8ff 276 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 277 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /**
bogdanm 0:9b334a45a8ff 280 * @}
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /**
bogdanm 0:9b334a45a8ff 284 * @}
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /**
bogdanm 0:9b334a45a8ff 288 * @}
bogdanm 0:9b334a45a8ff 289 */
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @}
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297 #endif
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 #endif /* __STM32L4xx_HAL_NAND_H */
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/