en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_nand.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_nand.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief NAND HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NAND memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NAND flash memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NAND devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both common and attribute spaces.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NAND flash memory maker and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NAND flash memory by read/write operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
bogdanm 0:9b334a45a8ff 29 to read/write page(s)/spare area(s). These functions use specific device
bogdanm 0:9b334a45a8ff 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
bogdanm 0:9b334a45a8ff 31 structure. The read/write address information is contained by the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 32 structure passed as parameter.
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
bogdanm 0:9b334a45a8ff 37 The erase block address information is contained in the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 38 structure passed as parameter.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
bogdanm 0:9b334a45a8ff 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
bogdanm 0:9b334a45a8ff 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 (+) You can monitor the NAND device HAL state by calling the function
bogdanm 0:9b334a45a8ff 47 HAL_NAND_GetState()
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
bogdanm 0:9b334a45a8ff 51 If a NAND flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 52 it should be implemented separately.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32l4xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NAND_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /** @defgroup NAND NAND
bogdanm 0:9b334a45a8ff 95 * @brief NAND HAL module driver
bogdanm 0:9b334a45a8ff 96 * @{
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /** @defgroup NAND_Private_Constants NAND Private Constants
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /**
bogdanm 0:9b334a45a8ff 106 * @}
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 110 /** @defgroup NAND_Private_Macros NAND Private Macros
bogdanm 0:9b334a45a8ff 111 * @{
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /**
bogdanm 0:9b334a45a8ff 115 * @}
bogdanm 0:9b334a45a8ff 116 */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /** @defgroup NAND_Private_Functions NAND Private Functions
bogdanm 0:9b334a45a8ff 121 * @{
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
bogdanm 0:9b334a45a8ff 124 /**
bogdanm 0:9b334a45a8ff 125 * @}
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /** @defgroup NAND_Exported_Functions NAND Exported Functions
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 135 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 136 *
bogdanm 0:9b334a45a8ff 137 @verbatim
bogdanm 0:9b334a45a8ff 138 ==============================================================================
bogdanm 0:9b334a45a8ff 139 ##### NAND Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 140 ==============================================================================
bogdanm 0:9b334a45a8ff 141 [..]
bogdanm 0:9b334a45a8ff 142 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 143 the NAND memory
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 @endverbatim
bogdanm 0:9b334a45a8ff 146 * @{
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /**
bogdanm 0:9b334a45a8ff 150 * @brief Perform NAND memory Initialization sequence.
bogdanm 0:9b334a45a8ff 151 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 152 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 153 * @param ComSpace_Timing: pointer to Common space timing structure
bogdanm 0:9b334a45a8ff 154 * @param AttSpace_Timing: pointer to Attribute space timing structure
bogdanm 0:9b334a45a8ff 155 * @retval HAL status
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
bogdanm 0:9b334a45a8ff 158 {
bogdanm 0:9b334a45a8ff 159 /* Check the NAND handle state */
bogdanm 0:9b334a45a8ff 160 if(hnand == NULL)
bogdanm 0:9b334a45a8ff 161 {
bogdanm 0:9b334a45a8ff 162 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 if(hnand->State == HAL_NAND_STATE_RESET)
bogdanm 0:9b334a45a8ff 166 {
bogdanm 0:9b334a45a8ff 167 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 168 hnand->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 171 HAL_NAND_MspInit(hnand);
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Initialize NAND control Interface */
bogdanm 0:9b334a45a8ff 175 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /* Initialize NAND common space timing Interface */
bogdanm 0:9b334a45a8ff 178 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* Initialize NAND attribute space timing Interface */
bogdanm 0:9b334a45a8ff 181 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Enable the NAND device */
bogdanm 0:9b334a45a8ff 184 __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 187 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 return HAL_OK;
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /**
bogdanm 0:9b334a45a8ff 193 * @brief Perform NAND memory De-Initialization sequence.
bogdanm 0:9b334a45a8ff 194 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 195 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 196 * @retval HAL status
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 201 HAL_NAND_MspDeInit(hnand);
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Configure the NAND registers with their reset values */
bogdanm 0:9b334a45a8ff 204 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Reset the NAND controller state */
bogdanm 0:9b334a45a8ff 207 hnand->State = HAL_NAND_STATE_RESET;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Release Lock */
bogdanm 0:9b334a45a8ff 210 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 return HAL_OK;
bogdanm 0:9b334a45a8ff 213 }
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /**
bogdanm 0:9b334a45a8ff 216 * @brief Initialize the NAND MSP.
bogdanm 0:9b334a45a8ff 217 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 218 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 219 * @retval None
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 224 the HAL_NAND_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /**
bogdanm 0:9b334a45a8ff 229 * @brief DeInitialize the NAND MSP.
bogdanm 0:9b334a45a8ff 230 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 231 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 232 * @retval None
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 235 {
bogdanm 0:9b334a45a8ff 236 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 237 the HAL_NAND_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 238 */
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /**
bogdanm 0:9b334a45a8ff 243 * @brief This function handles NAND device interrupt request.
bogdanm 0:9b334a45a8ff 244 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 245 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 246 * @retval HAL status
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 249 {
bogdanm 0:9b334a45a8ff 250 /* Check NAND interrupt Rising edge flag */
bogdanm 0:9b334a45a8ff 251 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
bogdanm 0:9b334a45a8ff 252 {
bogdanm 0:9b334a45a8ff 253 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 254 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* Clear NAND interrupt Rising edge pending bit */
bogdanm 0:9b334a45a8ff 257 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
bogdanm 0:9b334a45a8ff 258 }
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* Check NAND interrupt Level flag */
bogdanm 0:9b334a45a8ff 261 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 264 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Clear NAND interrupt Level pending bit */
bogdanm 0:9b334a45a8ff 267 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /* Check NAND interrupt Falling edge flag */
bogdanm 0:9b334a45a8ff 271 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 274 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Clear NAND interrupt Falling edge pending bit */
bogdanm 0:9b334a45a8ff 277 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
bogdanm 0:9b334a45a8ff 278 }
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* Check NAND interrupt FIFO empty flag */
bogdanm 0:9b334a45a8ff 281 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 284 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Clear NAND interrupt FIFO empty pending bit */
bogdanm 0:9b334a45a8ff 287 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @brief NAND interrupt feature callback.
bogdanm 0:9b334a45a8ff 293 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 294 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 295 * @retval None
bogdanm 0:9b334a45a8ff 296 */
bogdanm 0:9b334a45a8ff 297 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 300 the HAL_NAND_ITCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /**
bogdanm 0:9b334a45a8ff 305 * @}
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 309 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 310 *
bogdanm 0:9b334a45a8ff 311 @verbatim
bogdanm 0:9b334a45a8ff 312 ==============================================================================
bogdanm 0:9b334a45a8ff 313 ##### NAND Input and Output functions #####
bogdanm 0:9b334a45a8ff 314 ==============================================================================
bogdanm 0:9b334a45a8ff 315 [..]
bogdanm 0:9b334a45a8ff 316 This section provides functions allowing to use and control the NAND
bogdanm 0:9b334a45a8ff 317 memory
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 @endverbatim
bogdanm 0:9b334a45a8ff 320 * @{
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /**
bogdanm 0:9b334a45a8ff 324 * @brief Read the NAND memory electronic signature.
bogdanm 0:9b334a45a8ff 325 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 326 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 327 * @param pNAND_ID: NAND ID structure
bogdanm 0:9b334a45a8ff 328 * @retval HAL status
bogdanm 0:9b334a45a8ff 329 */
bogdanm 0:9b334a45a8ff 330 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 __IO uint32_t data = 0;
bogdanm 0:9b334a45a8ff 333 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Process Locked */
bogdanm 0:9b334a45a8ff 336 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 339 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 342 }
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /* Identify the device address */
bogdanm 0:9b334a45a8ff 345 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 348 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 /* Send Read ID command sequence */
bogdanm 0:9b334a45a8ff 351 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
bogdanm 0:9b334a45a8ff 352 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Read the electronic signature from NAND flash */
bogdanm 0:9b334a45a8ff 355 data = *(__IO uint32_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* Return the data read */
bogdanm 0:9b334a45a8ff 358 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
bogdanm 0:9b334a45a8ff 359 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
bogdanm 0:9b334a45a8ff 360 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
bogdanm 0:9b334a45a8ff 361 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 364 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Process unlocked */
bogdanm 0:9b334a45a8ff 367 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 return HAL_OK;
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /**
bogdanm 0:9b334a45a8ff 373 * @brief NAND memory reset.
bogdanm 0:9b334a45a8ff 374 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 375 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 376 * @retval HAL status
bogdanm 0:9b334a45a8ff 377 */
bogdanm 0:9b334a45a8ff 378 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Process Locked */
bogdanm 0:9b334a45a8ff 383 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 386 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /* Identify the device address */
bogdanm 0:9b334a45a8ff 392 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 395 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* Send NAND reset command */
bogdanm 0:9b334a45a8ff 398 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 402 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Process unlocked */
bogdanm 0:9b334a45a8ff 405 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 return HAL_OK;
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /**
bogdanm 0:9b334a45a8ff 412 * @brief Read Page(s) from NAND memory block.
bogdanm 0:9b334a45a8ff 413 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 414 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 415 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 416 * @param pBuffer: pointer to destination read buffer
bogdanm 0:9b334a45a8ff 417 * @param NumPageToRead: number of pages to read from block
bogdanm 0:9b334a45a8ff 418 * @retval HAL status
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
bogdanm 0:9b334a45a8ff 421 {
bogdanm 0:9b334a45a8ff 422 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 423 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 424 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 425 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Process Locked */
bogdanm 0:9b334a45a8ff 428 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 431 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 434 }
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Identify the device address */
bogdanm 0:9b334a45a8ff 437 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 440 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 443 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 444 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 445 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Page(s) read loop */
bogdanm 0:9b334a45a8ff 448 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 /* update the buffer size */
bogdanm 0:9b334a45a8ff 451 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Get the address offset */
bogdanm 0:9b334a45a8ff 454 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Send read page command sequence */
bogdanm 0:9b334a45a8ff 457 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 460 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 461 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 462 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 465 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 473 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Increment read pages number */
bogdanm 0:9b334a45a8ff 479 numpagesread++;
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /* Decrement pages to read */
bogdanm 0:9b334a45a8ff 482 NumPageToRead--;
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 485 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 489 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Process unlocked */
bogdanm 0:9b334a45a8ff 492 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 return HAL_OK;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /**
bogdanm 0:9b334a45a8ff 499 * @brief Write Page(s) to NAND memory block.
bogdanm 0:9b334a45a8ff 500 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 501 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 502 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 503 * @param pBuffer: pointer to source buffer to write
bogdanm 0:9b334a45a8ff 504 * @param NumPageToWrite: number of pages to write to block
bogdanm 0:9b334a45a8ff 505 * @retval HAL status
bogdanm 0:9b334a45a8ff 506 */
bogdanm 0:9b334a45a8ff 507 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 510 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 511 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 512 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 513 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* Process Locked */
bogdanm 0:9b334a45a8ff 516 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 519 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 520 {
bogdanm 0:9b334a45a8ff 521 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Identify the device address */
bogdanm 0:9b334a45a8ff 525 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 528 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 531 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 532 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 533 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 /* Page(s) write loop */
bogdanm 0:9b334a45a8ff 536 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 537 {
bogdanm 0:9b334a45a8ff 538 /* update the buffer size */
bogdanm 0:9b334a45a8ff 539 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /* Get the address offset */
bogdanm 0:9b334a45a8ff 542 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /* Send write page command sequence */
bogdanm 0:9b334a45a8ff 545 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 546 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 549 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 550 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 551 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 554 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 555 {
bogdanm 0:9b334a45a8ff 556 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Write data to memory */
bogdanm 0:9b334a45a8ff 560 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 563 }
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Get tick */
bogdanm 0:9b334a45a8ff 568 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 571 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Increment written pages number */
bogdanm 0:9b334a45a8ff 580 numpageswritten++;
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 /* Decrement pages to write */
bogdanm 0:9b334a45a8ff 583 NumPageToWrite--;
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 586 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 590 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /* Process unlocked */
bogdanm 0:9b334a45a8ff 593 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 return HAL_OK;
bogdanm 0:9b334a45a8ff 596 }
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /**
bogdanm 0:9b334a45a8ff 599 * @brief Read Spare area(s) from NAND memory.
bogdanm 0:9b334a45a8ff 600 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 601 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 602 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 603 * @param pBuffer: pointer to source buffer to write
bogdanm 0:9b334a45a8ff 604 * @param NumSpareAreaToRead: Number of spare area to read
bogdanm 0:9b334a45a8ff 605 * @retval HAL status
bogdanm 0:9b334a45a8ff 606 */
bogdanm 0:9b334a45a8ff 607 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
bogdanm 0:9b334a45a8ff 608 {
bogdanm 0:9b334a45a8ff 609 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 610 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 611 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 612 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 /* Process Locked */
bogdanm 0:9b334a45a8ff 615 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 618 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 621 }
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Identify the device address */
bogdanm 0:9b334a45a8ff 624 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 627 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 630 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 631 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 632 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /* Spare area(s) read loop */
bogdanm 0:9b334a45a8ff 635 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 /* update the buffer size */
bogdanm 0:9b334a45a8ff 638 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /* Get the address offset */
bogdanm 0:9b334a45a8ff 641 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /* Send read spare area command sequence */
bogdanm 0:9b334a45a8ff 644 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 647 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 648 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 649 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 652 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 653 {
bogdanm 0:9b334a45a8ff 654 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 660 for ( ;index < size; index++)
bogdanm 0:9b334a45a8ff 661 {
bogdanm 0:9b334a45a8ff 662 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /* Increment read spare areas number */
bogdanm 0:9b334a45a8ff 666 num_spare_area_read++;
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 /* Decrement spare areas to read */
bogdanm 0:9b334a45a8ff 669 NumSpareAreaToRead--;
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 672 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 673 }
bogdanm 0:9b334a45a8ff 674
bogdanm 0:9b334a45a8ff 675 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 676 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /* Process unlocked */
bogdanm 0:9b334a45a8ff 679 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 return HAL_OK;
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /**
bogdanm 0:9b334a45a8ff 685 * @brief Write Spare area(s) to NAND memory.
bogdanm 0:9b334a45a8ff 686 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 687 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 688 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 689 * @param pBuffer: pointer to source buffer to write
bogdanm 0:9b334a45a8ff 690 * @param NumSpareAreaTowrite: number of spare areas to write to block
bogdanm 0:9b334a45a8ff 691 * @retval HAL status
bogdanm 0:9b334a45a8ff 692 */
bogdanm 0:9b334a45a8ff 693 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
bogdanm 0:9b334a45a8ff 694 {
bogdanm 0:9b334a45a8ff 695 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 696 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 697 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 698 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 699 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Process Locked */
bogdanm 0:9b334a45a8ff 702 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 705 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 706 {
bogdanm 0:9b334a45a8ff 707 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 708 }
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 /* Identify the device address */
bogdanm 0:9b334a45a8ff 711 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* Update the FMC_NAND controller state */
bogdanm 0:9b334a45a8ff 714 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 717 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 718 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 719 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /* Spare area(s) write loop */
bogdanm 0:9b334a45a8ff 722 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 723 {
bogdanm 0:9b334a45a8ff 724 /* update the buffer size */
bogdanm 0:9b334a45a8ff 725 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 /* Get the address offset */
bogdanm 0:9b334a45a8ff 728 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /* Send write Spare area command sequence */
bogdanm 0:9b334a45a8ff 731 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 732 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 735 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 736 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 737 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 740 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 743 }
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Write data to memory */
bogdanm 0:9b334a45a8ff 746 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 747 {
bogdanm 0:9b334a45a8ff 748 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 749 }
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /* Get tick */
bogdanm 0:9b334a45a8ff 754 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 757 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 758 {
bogdanm 0:9b334a45a8ff 759 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 760 {
bogdanm 0:9b334a45a8ff 761 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 762 }
bogdanm 0:9b334a45a8ff 763 }
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /* Increment written spare areas number */
bogdanm 0:9b334a45a8ff 766 num_spare_area_written++;
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* Decrement spare areas to write */
bogdanm 0:9b334a45a8ff 769 NumSpareAreaTowrite--;
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 772 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 773 }
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 776 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778 /* Process unlocked */
bogdanm 0:9b334a45a8ff 779 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 return HAL_OK;
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /**
bogdanm 0:9b334a45a8ff 785 * @brief NAND memory Block erase.
bogdanm 0:9b334a45a8ff 786 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 787 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 788 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 789 * @retval HAL status
bogdanm 0:9b334a45a8ff 790 */
bogdanm 0:9b334a45a8ff 791 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 794 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /* Process Locked */
bogdanm 0:9b334a45a8ff 797 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 800 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 801 {
bogdanm 0:9b334a45a8ff 802 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /* Identify the device address */
bogdanm 0:9b334a45a8ff 806 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 807
bogdanm 0:9b334a45a8ff 808 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 809 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 /* Send Erase block command sequence */
bogdanm 0:9b334a45a8ff 812 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 815 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 816 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 819 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 820 {
bogdanm 0:9b334a45a8ff 821 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 822 }
bogdanm 0:9b334a45a8ff 823
bogdanm 0:9b334a45a8ff 824 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 827 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* Get tick */
bogdanm 0:9b334a45a8ff 830 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 833 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 834 {
bogdanm 0:9b334a45a8ff 835 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 836 {
bogdanm 0:9b334a45a8ff 837 /* Process unlocked */
bogdanm 0:9b334a45a8ff 838 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842 }
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Process unlocked */
bogdanm 0:9b334a45a8ff 845 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 return HAL_OK;
bogdanm 0:9b334a45a8ff 848 }
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /**
bogdanm 0:9b334a45a8ff 851 * @brief NAND memory read status.
bogdanm 0:9b334a45a8ff 852 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 853 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 854 * @retval NAND status
bogdanm 0:9b334a45a8ff 855 */
bogdanm 0:9b334a45a8ff 856 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 857 {
bogdanm 0:9b334a45a8ff 858 uint32_t data = 0;
bogdanm 0:9b334a45a8ff 859 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 860
bogdanm 0:9b334a45a8ff 861 /* Identify the device address */
bogdanm 0:9b334a45a8ff 862 deviceaddress = NAND_DEVICE;
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Send Read status operation command */
bogdanm 0:9b334a45a8ff 865 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 /* Read status register data */
bogdanm 0:9b334a45a8ff 868 data = *(__IO uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* Return the status */
bogdanm 0:9b334a45a8ff 871 if((data & NAND_ERROR) == NAND_ERROR)
bogdanm 0:9b334a45a8ff 872 {
bogdanm 0:9b334a45a8ff 873 return NAND_ERROR;
bogdanm 0:9b334a45a8ff 874 }
bogdanm 0:9b334a45a8ff 875 else if((data & NAND_READY) == NAND_READY)
bogdanm 0:9b334a45a8ff 876 {
bogdanm 0:9b334a45a8ff 877 return NAND_READY;
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 return NAND_BUSY;
bogdanm 0:9b334a45a8ff 881 }
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 /**
bogdanm 0:9b334a45a8ff 884 * @brief Increment the NAND memory address.
bogdanm 0:9b334a45a8ff 885 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 886 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 887 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 888 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 889 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 890 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 891 */
bogdanm 0:9b334a45a8ff 892 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 893 {
bogdanm 0:9b334a45a8ff 894 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /* Increment page address */
bogdanm 0:9b334a45a8ff 897 pAddress->Page++;
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 /* Check NAND address is valid */
bogdanm 0:9b334a45a8ff 900 if(pAddress->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 901 {
bogdanm 0:9b334a45a8ff 902 pAddress->Page = 0;
bogdanm 0:9b334a45a8ff 903 pAddress->Block++;
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 if(pAddress->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 906 {
bogdanm 0:9b334a45a8ff 907 pAddress->Block = 0;
bogdanm 0:9b334a45a8ff 908 pAddress->Zone++;
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
bogdanm 0:9b334a45a8ff 911 {
bogdanm 0:9b334a45a8ff 912 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 913 }
bogdanm 0:9b334a45a8ff 914 }
bogdanm 0:9b334a45a8ff 915 }
bogdanm 0:9b334a45a8ff 916
bogdanm 0:9b334a45a8ff 917 return (status);
bogdanm 0:9b334a45a8ff 918 }
bogdanm 0:9b334a45a8ff 919 /**
bogdanm 0:9b334a45a8ff 920 * @}
bogdanm 0:9b334a45a8ff 921 */
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 924 * @brief management functions
bogdanm 0:9b334a45a8ff 925 *
bogdanm 0:9b334a45a8ff 926 @verbatim
bogdanm 0:9b334a45a8ff 927 ==============================================================================
bogdanm 0:9b334a45a8ff 928 ##### NAND Control functions #####
bogdanm 0:9b334a45a8ff 929 ==============================================================================
bogdanm 0:9b334a45a8ff 930 [..]
bogdanm 0:9b334a45a8ff 931 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 932 the NAND interface.
bogdanm 0:9b334a45a8ff 933
bogdanm 0:9b334a45a8ff 934 @endverbatim
bogdanm 0:9b334a45a8ff 935 * @{
bogdanm 0:9b334a45a8ff 936 */
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /**
bogdanm 0:9b334a45a8ff 940 * @brief Enable dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 941 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 942 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 943 * @retval HAL status
bogdanm 0:9b334a45a8ff 944 */
bogdanm 0:9b334a45a8ff 945 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 946 {
bogdanm 0:9b334a45a8ff 947 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 948 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 949 {
bogdanm 0:9b334a45a8ff 950 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 951 }
bogdanm 0:9b334a45a8ff 952
bogdanm 0:9b334a45a8ff 953 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 954 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /* Enable ECC feature */
bogdanm 0:9b334a45a8ff 957 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 960 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 961
bogdanm 0:9b334a45a8ff 962 return HAL_OK;
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 /**
bogdanm 0:9b334a45a8ff 966 * @brief Disable dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 967 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 968 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 969 * @retval HAL status
bogdanm 0:9b334a45a8ff 970 */
bogdanm 0:9b334a45a8ff 971 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 972 {
bogdanm 0:9b334a45a8ff 973 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 974 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 975 {
bogdanm 0:9b334a45a8ff 976 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 977 }
bogdanm 0:9b334a45a8ff 978
bogdanm 0:9b334a45a8ff 979 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 980 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 /* Disable ECC feature */
bogdanm 0:9b334a45a8ff 983 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 984
bogdanm 0:9b334a45a8ff 985 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 986 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 return HAL_OK;
bogdanm 0:9b334a45a8ff 989 }
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /**
bogdanm 0:9b334a45a8ff 992 * @brief Disable dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 993 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 994 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 995 * @param ECCval: pointer to ECC value
bogdanm 0:9b334a45a8ff 996 * @param Timeout: maximum timeout to wait
bogdanm 0:9b334a45a8ff 997 * @retval HAL status
bogdanm 0:9b334a45a8ff 998 */
bogdanm 0:9b334a45a8ff 999 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1000 {
bogdanm 0:9b334a45a8ff 1001 HAL_StatusTypeDef status = HAL_OK;
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1004 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1005 {
bogdanm 0:9b334a45a8ff 1006 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1007 }
bogdanm 0:9b334a45a8ff 1008
bogdanm 0:9b334a45a8ff 1009 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1010 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /* Get NAND ECC value */
bogdanm 0:9b334a45a8ff 1013 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1016 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 return status;
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /**
bogdanm 0:9b334a45a8ff 1022 * @}
bogdanm 0:9b334a45a8ff 1023 */
bogdanm 0:9b334a45a8ff 1024
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1027 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1028 *
bogdanm 0:9b334a45a8ff 1029 @verbatim
bogdanm 0:9b334a45a8ff 1030 ==============================================================================
bogdanm 0:9b334a45a8ff 1031 ##### NAND State functions #####
bogdanm 0:9b334a45a8ff 1032 ==============================================================================
bogdanm 0:9b334a45a8ff 1033 [..]
bogdanm 0:9b334a45a8ff 1034 This subsection permits to get in run-time the status of the NAND controller
bogdanm 0:9b334a45a8ff 1035 and the data flow.
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 @endverbatim
bogdanm 0:9b334a45a8ff 1038 * @{
bogdanm 0:9b334a45a8ff 1039 */
bogdanm 0:9b334a45a8ff 1040
bogdanm 0:9b334a45a8ff 1041 /**
bogdanm 0:9b334a45a8ff 1042 * @brief Return the NAND handle state.
bogdanm 0:9b334a45a8ff 1043 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1044 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1045 * @retval HAL state
bogdanm 0:9b334a45a8ff 1046 */
bogdanm 0:9b334a45a8ff 1047 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1048 {
bogdanm 0:9b334a45a8ff 1049 /* Return NAND handle state */
bogdanm 0:9b334a45a8ff 1050 return hnand->State;
bogdanm 0:9b334a45a8ff 1051 }
bogdanm 0:9b334a45a8ff 1052
bogdanm 0:9b334a45a8ff 1053 /**
bogdanm 0:9b334a45a8ff 1054 * @}
bogdanm 0:9b334a45a8ff 1055 */
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /**
bogdanm 0:9b334a45a8ff 1058 * @}
bogdanm 0:9b334a45a8ff 1059 */
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 /** @addtogroup NAND_Private_Functions
bogdanm 0:9b334a45a8ff 1062 * @{
bogdanm 0:9b334a45a8ff 1063 */
bogdanm 0:9b334a45a8ff 1064
bogdanm 0:9b334a45a8ff 1065 /**
bogdanm 0:9b334a45a8ff 1066 * @brief Increment the NAND memory address.
bogdanm 0:9b334a45a8ff 1067 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1068 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1069 * @param Address: address to be incremented.
bogdanm 0:9b334a45a8ff 1070 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 1071 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 1072 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 1073 */
bogdanm 0:9b334a45a8ff 1074 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
bogdanm 0:9b334a45a8ff 1075 {
bogdanm 0:9b334a45a8ff 1076 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 Address->Page++;
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 if(Address->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 1081 {
bogdanm 0:9b334a45a8ff 1082 Address->Page = 0;
bogdanm 0:9b334a45a8ff 1083 Address->Block++;
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 if(Address->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 1086 {
bogdanm 0:9b334a45a8ff 1087 Address->Block = 0;
bogdanm 0:9b334a45a8ff 1088 Address->Zone++;
bogdanm 0:9b334a45a8ff 1089
bogdanm 0:9b334a45a8ff 1090 if(Address->Zone == hnand->Info.BlockNbr)
bogdanm 0:9b334a45a8ff 1091 {
bogdanm 0:9b334a45a8ff 1092 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1093 }
bogdanm 0:9b334a45a8ff 1094 }
bogdanm 0:9b334a45a8ff 1095 }
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 return (status);
bogdanm 0:9b334a45a8ff 1098 }
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 /**
bogdanm 0:9b334a45a8ff 1101 * @}
bogdanm 0:9b334a45a8ff 1102 */
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 /**
bogdanm 0:9b334a45a8ff 1105 * @}
bogdanm 0:9b334a45a8ff 1106 */
bogdanm 0:9b334a45a8ff 1107
bogdanm 0:9b334a45a8ff 1108 #endif /* HAL_NAND_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1109
bogdanm 0:9b334a45a8ff 1110 /**
bogdanm 0:9b334a45a8ff 1111 * @}
bogdanm 0:9b334a45a8ff 1112 */
bogdanm 0:9b334a45a8ff 1113
bogdanm 0:9b334a45a8ff 1114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/