en 129
fix LPC812 PWM
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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_dfsdm.h@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_hal_dfsdm.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of DFSDM HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L4xx_HAL_DFSDM_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L4xx_HAL_DFSDM_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l4xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup DFSDM |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | /** @defgroup DFSDM_Exported_Types DFSDM Exported Types |
| bogdanm | 0:9b334a45a8ff | 59 | * @{ |
| bogdanm | 0:9b334a45a8ff | 60 | */ |
| bogdanm | 0:9b334a45a8ff | 61 | |
| bogdanm | 0:9b334a45a8ff | 62 | /** |
| bogdanm | 0:9b334a45a8ff | 63 | * @brief HAL DFSDM Channel states definition |
| bogdanm | 0:9b334a45a8ff | 64 | */ |
| bogdanm | 0:9b334a45a8ff | 65 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 66 | { |
| bogdanm | 0:9b334a45a8ff | 67 | HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, /*!< DFSDM channel not initialized */ |
| bogdanm | 0:9b334a45a8ff | 68 | HAL_DFSDM_CHANNEL_STATE_READY = 0x01, /*!< DFSDM channel initialized and ready for use */ |
| bogdanm | 0:9b334a45a8ff | 69 | HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF /*!< DFSDM channel state error */ |
| bogdanm | 0:9b334a45a8ff | 70 | }HAL_DFSDM_Channel_StateTypeDef; |
| bogdanm | 0:9b334a45a8ff | 71 | |
| bogdanm | 0:9b334a45a8ff | 72 | /** |
| bogdanm | 0:9b334a45a8ff | 73 | * @brief DFSDM channel output clock structure definition |
| bogdanm | 0:9b334a45a8ff | 74 | */ |
| bogdanm | 0:9b334a45a8ff | 75 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 76 | { |
| bogdanm | 0:9b334a45a8ff | 77 | FunctionalState Activation; /*!< Output clock enable/disable */ |
| bogdanm | 0:9b334a45a8ff | 78 | uint32_t Selection; /*!< Output clock is system clock or audio clock. |
| bogdanm | 0:9b334a45a8ff | 79 | This parameter can be a value of @ref DFSDM_Channel_OuputClock */ |
| bogdanm | 0:9b334a45a8ff | 80 | uint32_t Divider; /*!< Output clock divider. |
| bogdanm | 0:9b334a45a8ff | 81 | This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ |
| bogdanm | 0:9b334a45a8ff | 82 | }DFSDM_Channel_OutputClockTypeDef; |
| bogdanm | 0:9b334a45a8ff | 83 | |
| bogdanm | 0:9b334a45a8ff | 84 | /** |
| bogdanm | 0:9b334a45a8ff | 85 | * @brief DFSDM channel input structure definition |
| bogdanm | 0:9b334a45a8ff | 86 | */ |
| bogdanm | 0:9b334a45a8ff | 87 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 88 | { |
| bogdanm | 0:9b334a45a8ff | 89 | uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. |
| bogdanm | 0:9b334a45a8ff | 90 | This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ |
| bogdanm | 0:9b334a45a8ff | 91 | uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. |
| bogdanm | 0:9b334a45a8ff | 92 | This parameter can be a value of @ref DFSDM_Channel_DataPacking */ |
| bogdanm | 0:9b334a45a8ff | 93 | uint32_t Pins; /*!< Input pins are taken from same or following channel. |
| bogdanm | 0:9b334a45a8ff | 94 | This parameter can be a value of @ref DFSDM_Channel_InputPins */ |
| bogdanm | 0:9b334a45a8ff | 95 | }DFSDM_Channel_InputTypeDef; |
| bogdanm | 0:9b334a45a8ff | 96 | |
| bogdanm | 0:9b334a45a8ff | 97 | /** |
| bogdanm | 0:9b334a45a8ff | 98 | * @brief DFSDM channel serial interface structure definition |
| bogdanm | 0:9b334a45a8ff | 99 | */ |
| bogdanm | 0:9b334a45a8ff | 100 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 101 | { |
| bogdanm | 0:9b334a45a8ff | 102 | uint32_t Type; /*!< SPI or Manchester modes. |
| bogdanm | 0:9b334a45a8ff | 103 | This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ |
| bogdanm | 0:9b334a45a8ff | 104 | uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). |
| bogdanm | 0:9b334a45a8ff | 105 | This parameter can be a value of @ref DFSDM_Channel_SpiClock */ |
| bogdanm | 0:9b334a45a8ff | 106 | }DFSDM_Channel_SerialInterfaceTypeDef; |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | /** |
| bogdanm | 0:9b334a45a8ff | 109 | * @brief DFSDM channel analog watchdog structure definition |
| bogdanm | 0:9b334a45a8ff | 110 | */ |
| bogdanm | 0:9b334a45a8ff | 111 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 112 | { |
| bogdanm | 0:9b334a45a8ff | 113 | uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. |
| bogdanm | 0:9b334a45a8ff | 114 | This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ |
| bogdanm | 0:9b334a45a8ff | 115 | uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. |
| bogdanm | 0:9b334a45a8ff | 116 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ |
| bogdanm | 0:9b334a45a8ff | 117 | }DFSDM_Channel_AwdTypeDef; |
| bogdanm | 0:9b334a45a8ff | 118 | |
| bogdanm | 0:9b334a45a8ff | 119 | /** |
| bogdanm | 0:9b334a45a8ff | 120 | * @brief DFSDM channel init structure definition |
| bogdanm | 0:9b334a45a8ff | 121 | */ |
| bogdanm | 0:9b334a45a8ff | 122 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 123 | { |
| bogdanm | 0:9b334a45a8ff | 124 | DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ |
| bogdanm | 0:9b334a45a8ff | 125 | DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ |
| bogdanm | 0:9b334a45a8ff | 126 | DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ |
| bogdanm | 0:9b334a45a8ff | 127 | DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ |
| bogdanm | 0:9b334a45a8ff | 128 | int32_t Offset; /*!< DFSDM channel offset. |
| bogdanm | 0:9b334a45a8ff | 129 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| bogdanm | 0:9b334a45a8ff | 130 | uint32_t RightBitShift; /*!< DFSDM channel right bit shift. |
| bogdanm | 0:9b334a45a8ff | 131 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
| bogdanm | 0:9b334a45a8ff | 132 | }DFSDM_Channel_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 133 | |
| bogdanm | 0:9b334a45a8ff | 134 | /** |
| bogdanm | 0:9b334a45a8ff | 135 | * @brief DFSDM channel handle structure definition |
| bogdanm | 0:9b334a45a8ff | 136 | */ |
| bogdanm | 0:9b334a45a8ff | 137 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 138 | { |
| bogdanm | 0:9b334a45a8ff | 139 | DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ |
| bogdanm | 0:9b334a45a8ff | 140 | DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ |
| bogdanm | 0:9b334a45a8ff | 141 | HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ |
| bogdanm | 0:9b334a45a8ff | 142 | }DFSDM_Channel_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 143 | |
| bogdanm | 0:9b334a45a8ff | 144 | /** |
| bogdanm | 0:9b334a45a8ff | 145 | * @brief HAL DFSDM Filter states definition |
| bogdanm | 0:9b334a45a8ff | 146 | */ |
| bogdanm | 0:9b334a45a8ff | 147 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 148 | { |
| bogdanm | 0:9b334a45a8ff | 149 | HAL_DFSDM_FILTER_STATE_RESET = 0x00, /*!< DFSDM filter not initialized */ |
| bogdanm | 0:9b334a45a8ff | 150 | HAL_DFSDM_FILTER_STATE_READY = 0x01, /*!< DFSDM filter initialized and ready for use */ |
| bogdanm | 0:9b334a45a8ff | 151 | HAL_DFSDM_FILTER_STATE_REG = 0x02, /*!< DFSDM filter regular conversion in progress */ |
| bogdanm | 0:9b334a45a8ff | 152 | HAL_DFSDM_FILTER_STATE_INJ = 0x03, /*!< DFSDM filter injected conversion in progress */ |
| bogdanm | 0:9b334a45a8ff | 153 | HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, /*!< DFSDM filter regular and injected conversions in progress */ |
| bogdanm | 0:9b334a45a8ff | 154 | HAL_DFSDM_FILTER_STATE_ERROR = 0xFF /*!< DFSDM filter state error */ |
| bogdanm | 0:9b334a45a8ff | 155 | }HAL_DFSDM_Filter_StateTypeDef; |
| bogdanm | 0:9b334a45a8ff | 156 | |
| bogdanm | 0:9b334a45a8ff | 157 | /** |
| bogdanm | 0:9b334a45a8ff | 158 | * @brief DFSDM filter regular conversion parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 159 | */ |
| bogdanm | 0:9b334a45a8ff | 160 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 161 | { |
| bogdanm | 0:9b334a45a8ff | 162 | uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. |
| bogdanm | 0:9b334a45a8ff | 163 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
| bogdanm | 0:9b334a45a8ff | 164 | FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ |
| bogdanm | 0:9b334a45a8ff | 165 | FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ |
| bogdanm | 0:9b334a45a8ff | 166 | }DFSDM_Filter_RegularParamTypeDef; |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | /** |
| bogdanm | 0:9b334a45a8ff | 169 | * @brief DFSDM filter injected conversion parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 170 | */ |
| bogdanm | 0:9b334a45a8ff | 171 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 172 | { |
| bogdanm | 0:9b334a45a8ff | 173 | uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. |
| bogdanm | 0:9b334a45a8ff | 174 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
| bogdanm | 0:9b334a45a8ff | 175 | FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ |
| bogdanm | 0:9b334a45a8ff | 176 | FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ |
| bogdanm | 0:9b334a45a8ff | 177 | uint32_t ExtTrigger; /*!< External trigger. |
| bogdanm | 0:9b334a45a8ff | 178 | This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ |
| bogdanm | 0:9b334a45a8ff | 179 | uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. |
| bogdanm | 0:9b334a45a8ff | 180 | This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ |
| bogdanm | 0:9b334a45a8ff | 181 | }DFSDM_Filter_InjectedParamTypeDef; |
| bogdanm | 0:9b334a45a8ff | 182 | |
| bogdanm | 0:9b334a45a8ff | 183 | /** |
| bogdanm | 0:9b334a45a8ff | 184 | * @brief DFSDM filter parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 185 | */ |
| bogdanm | 0:9b334a45a8ff | 186 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 187 | { |
| bogdanm | 0:9b334a45a8ff | 188 | uint32_t SincOrder; /*!< Sinc filter order. |
| bogdanm | 0:9b334a45a8ff | 189 | This parameter can be a value of @ref DFSDM_Filter_SincOrder */ |
| bogdanm | 0:9b334a45a8ff | 190 | uint32_t Oversampling; /*!< Filter oversampling ratio. |
| bogdanm | 0:9b334a45a8ff | 191 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
| bogdanm | 0:9b334a45a8ff | 192 | uint32_t IntOversampling; /*!< Integrator oversampling ratio. |
| bogdanm | 0:9b334a45a8ff | 193 | This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ |
| bogdanm | 0:9b334a45a8ff | 194 | }DFSDM_Filter_FilterParamTypeDef; |
| bogdanm | 0:9b334a45a8ff | 195 | |
| bogdanm | 0:9b334a45a8ff | 196 | /** |
| bogdanm | 0:9b334a45a8ff | 197 | * @brief DFSDM filter init structure definition |
| bogdanm | 0:9b334a45a8ff | 198 | */ |
| bogdanm | 0:9b334a45a8ff | 199 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 200 | { |
| bogdanm | 0:9b334a45a8ff | 201 | DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ |
| bogdanm | 0:9b334a45a8ff | 202 | DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ |
| bogdanm | 0:9b334a45a8ff | 203 | DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ |
| bogdanm | 0:9b334a45a8ff | 204 | }DFSDM_Filter_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 205 | |
| bogdanm | 0:9b334a45a8ff | 206 | /** |
| bogdanm | 0:9b334a45a8ff | 207 | * @brief DFSDM filter handle structure definition |
| bogdanm | 0:9b334a45a8ff | 208 | */ |
| bogdanm | 0:9b334a45a8ff | 209 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 210 | { |
| bogdanm | 0:9b334a45a8ff | 211 | DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ |
| bogdanm | 0:9b334a45a8ff | 212 | DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ |
| bogdanm | 0:9b334a45a8ff | 213 | DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ |
| bogdanm | 0:9b334a45a8ff | 214 | DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ |
| bogdanm | 0:9b334a45a8ff | 215 | uint32_t RegularContMode; /*!< Regular conversion continuous mode */ |
| bogdanm | 0:9b334a45a8ff | 216 | uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ |
| bogdanm | 0:9b334a45a8ff | 217 | uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ |
| bogdanm | 0:9b334a45a8ff | 218 | uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ |
| bogdanm | 0:9b334a45a8ff | 219 | FunctionalState InjectedScanMode; /*!< Injected scanning mode */ |
| bogdanm | 0:9b334a45a8ff | 220 | uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ |
| bogdanm | 0:9b334a45a8ff | 221 | uint32_t InjConvRemaining; /*!< Injected conversions remaining */ |
| bogdanm | 0:9b334a45a8ff | 222 | HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ |
| bogdanm | 0:9b334a45a8ff | 223 | uint32_t ErrorCode; /*!< DFSDM filter error code */ |
| bogdanm | 0:9b334a45a8ff | 224 | }DFSDM_Filter_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 225 | |
| bogdanm | 0:9b334a45a8ff | 226 | /** |
| bogdanm | 0:9b334a45a8ff | 227 | * @brief DFSDM filter analog watchdog parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 228 | */ |
| bogdanm | 0:9b334a45a8ff | 229 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 230 | { |
| bogdanm | 0:9b334a45a8ff | 231 | uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. |
| bogdanm | 0:9b334a45a8ff | 232 | This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ |
| bogdanm | 0:9b334a45a8ff | 233 | uint32_t Channel; /*!< Analog watchdog channel selection. |
| bogdanm | 0:9b334a45a8ff | 234 | This parameter can be a values combination of @ref DFSDM_Channel_Selection */ |
| bogdanm | 0:9b334a45a8ff | 235 | int32_t HighThreshold; /*!< High threshold for the analog watchdog. |
| bogdanm | 0:9b334a45a8ff | 236 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| bogdanm | 0:9b334a45a8ff | 237 | int32_t LowThreshold; /*!< Low threshold for the analog watchdog. |
| bogdanm | 0:9b334a45a8ff | 238 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| bogdanm | 0:9b334a45a8ff | 239 | uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. |
| bogdanm | 0:9b334a45a8ff | 240 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
| bogdanm | 0:9b334a45a8ff | 241 | uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. |
| bogdanm | 0:9b334a45a8ff | 242 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
| bogdanm | 0:9b334a45a8ff | 243 | }DFSDM_Filter_AwdParamTypeDef; |
| bogdanm | 0:9b334a45a8ff | 244 | |
| bogdanm | 0:9b334a45a8ff | 245 | /** |
| bogdanm | 0:9b334a45a8ff | 246 | * @} |
| bogdanm | 0:9b334a45a8ff | 247 | */ |
| bogdanm | 0:9b334a45a8ff | 248 | /* End of exported types -----------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 249 | |
| bogdanm | 0:9b334a45a8ff | 250 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 251 | /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants |
| bogdanm | 0:9b334a45a8ff | 252 | * @{ |
| bogdanm | 0:9b334a45a8ff | 253 | */ |
| bogdanm | 0:9b334a45a8ff | 254 | |
| bogdanm | 0:9b334a45a8ff | 255 | /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection |
| bogdanm | 0:9b334a45a8ff | 256 | * @{ |
| bogdanm | 0:9b334a45a8ff | 257 | */ |
| bogdanm | 0:9b334a45a8ff | 258 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000) /*!< Source for ouput clock is system clock */ |
| bogdanm | 0:9b334a45a8ff | 259 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ |
| bogdanm | 0:9b334a45a8ff | 260 | /** |
| bogdanm | 0:9b334a45a8ff | 261 | * @} |
| bogdanm | 0:9b334a45a8ff | 262 | */ |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer |
| bogdanm | 0:9b334a45a8ff | 265 | * @{ |
| bogdanm | 0:9b334a45a8ff | 266 | */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000) /*!< Data are taken from external inputs */ |
| bogdanm | 0:9b334a45a8ff | 268 | #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ |
| bogdanm | 0:9b334a45a8ff | 269 | /** |
| bogdanm | 0:9b334a45a8ff | 270 | * @} |
| bogdanm | 0:9b334a45a8ff | 271 | */ |
| bogdanm | 0:9b334a45a8ff | 272 | |
| bogdanm | 0:9b334a45a8ff | 273 | /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing |
| bogdanm | 0:9b334a45a8ff | 274 | * @{ |
| bogdanm | 0:9b334a45a8ff | 275 | */ |
| bogdanm | 0:9b334a45a8ff | 276 | #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000) /*!< Standard data packing mode */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ |
| bogdanm | 0:9b334a45a8ff | 279 | /** |
| bogdanm | 0:9b334a45a8ff | 280 | * @} |
| bogdanm | 0:9b334a45a8ff | 281 | */ |
| bogdanm | 0:9b334a45a8ff | 282 | |
| bogdanm | 0:9b334a45a8ff | 283 | /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins |
| bogdanm | 0:9b334a45a8ff | 284 | * @{ |
| bogdanm | 0:9b334a45a8ff | 285 | */ |
| bogdanm | 0:9b334a45a8ff | 286 | #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000) /*!< Input from pins on same channel */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ |
| bogdanm | 0:9b334a45a8ff | 288 | /** |
| bogdanm | 0:9b334a45a8ff | 289 | * @} |
| bogdanm | 0:9b334a45a8ff | 290 | */ |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type |
| bogdanm | 0:9b334a45a8ff | 293 | * @{ |
| bogdanm | 0:9b334a45a8ff | 294 | */ |
| bogdanm | 0:9b334a45a8ff | 295 | #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000) /*!< SPI with rising edge */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ |
| bogdanm | 0:9b334a45a8ff | 297 | #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ |
| bogdanm | 0:9b334a45a8ff | 298 | #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ |
| bogdanm | 0:9b334a45a8ff | 299 | /** |
| bogdanm | 0:9b334a45a8ff | 300 | * @} |
| bogdanm | 0:9b334a45a8ff | 301 | */ |
| bogdanm | 0:9b334a45a8ff | 302 | |
| bogdanm | 0:9b334a45a8ff | 303 | /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection |
| bogdanm | 0:9b334a45a8ff | 304 | * @{ |
| bogdanm | 0:9b334a45a8ff | 305 | */ |
| bogdanm | 0:9b334a45a8ff | 306 | #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000) /*!< External SPI clock */ |
| bogdanm | 0:9b334a45a8ff | 307 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ |
| bogdanm | 0:9b334a45a8ff | 308 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ |
| bogdanm | 0:9b334a45a8ff | 309 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ |
| bogdanm | 0:9b334a45a8ff | 310 | /** |
| bogdanm | 0:9b334a45a8ff | 311 | * @} |
| bogdanm | 0:9b334a45a8ff | 312 | */ |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order |
| bogdanm | 0:9b334a45a8ff | 315 | * @{ |
| bogdanm | 0:9b334a45a8ff | 316 | */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */ |
| bogdanm | 0:9b334a45a8ff | 318 | #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_AWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_AWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ |
| bogdanm | 0:9b334a45a8ff | 320 | #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_AWSCDR_AWFORD /*!< Sinc 3 filter type */ |
| bogdanm | 0:9b334a45a8ff | 321 | /** |
| bogdanm | 0:9b334a45a8ff | 322 | * @} |
| bogdanm | 0:9b334a45a8ff | 323 | */ |
| bogdanm | 0:9b334a45a8ff | 324 | |
| bogdanm | 0:9b334a45a8ff | 325 | /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger |
| bogdanm | 0:9b334a45a8ff | 326 | * @{ |
| bogdanm | 0:9b334a45a8ff | 327 | */ |
| bogdanm | 0:9b334a45a8ff | 328 | #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */ |
| bogdanm | 0:9b334a45a8ff | 329 | #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with DFSDM0 */ |
| bogdanm | 0:9b334a45a8ff | 330 | #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002) /*!< External trigger (only for injected conversion) */ |
| bogdanm | 0:9b334a45a8ff | 331 | /** |
| bogdanm | 0:9b334a45a8ff | 332 | * @} |
| bogdanm | 0:9b334a45a8ff | 333 | */ |
| bogdanm | 0:9b334a45a8ff | 334 | |
| bogdanm | 0:9b334a45a8ff | 335 | /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger |
| bogdanm | 0:9b334a45a8ff | 336 | * @{ |
| bogdanm | 0:9b334a45a8ff | 337 | */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000) /*!< For DFSDM 0, 1, 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 339 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_CR1_JEXTSEL_0 /*!< For DFSDM 0, 1, 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 340 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_CR1_JEXTSEL_1 /*!< For DFSDM 0, 1, 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 341 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */ |
| bogdanm | 0:9b334a45a8ff | 342 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_1) /*!< For DFSDM 3 */ |
| bogdanm | 0:9b334a45a8ff | 343 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_CR1_JEXTSEL_2 /*!< For DFSDM 0, 1 and 2 */ |
| bogdanm | 0:9b334a45a8ff | 344 | #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_CR1_JEXTSEL_2 /*!< For DFSDM 3 */ |
| bogdanm | 0:9b334a45a8ff | 345 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 0 and 1 */ |
| bogdanm | 0:9b334a45a8ff | 346 | #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_CR1_JEXTSEL_0 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_CR1_JEXTSEL_1 | DFSDM_CR1_JEXTSEL_2) /*!< For DFSDM 0, 1, 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 348 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_CR1_JEXTSEL /*!< For DFSDM 0, 1, 2 and 3 */ |
| bogdanm | 0:9b334a45a8ff | 349 | /** |
| bogdanm | 0:9b334a45a8ff | 350 | * @} |
| bogdanm | 0:9b334a45a8ff | 351 | */ |
| bogdanm | 0:9b334a45a8ff | 352 | |
| bogdanm | 0:9b334a45a8ff | 353 | /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge |
| bogdanm | 0:9b334a45a8ff | 354 | * @{ |
| bogdanm | 0:9b334a45a8ff | 355 | */ |
| bogdanm | 0:9b334a45a8ff | 356 | #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_CR1_JEXTEN_0 /*!< External rising edge */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_CR1_JEXTEN_1 /*!< External falling edge */ |
| bogdanm | 0:9b334a45a8ff | 358 | #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_CR1_JEXTEN /*!< External rising and falling edges */ |
| bogdanm | 0:9b334a45a8ff | 359 | /** |
| bogdanm | 0:9b334a45a8ff | 360 | * @} |
| bogdanm | 0:9b334a45a8ff | 361 | */ |
| bogdanm | 0:9b334a45a8ff | 362 | |
| bogdanm | 0:9b334a45a8ff | 363 | /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order |
| bogdanm | 0:9b334a45a8ff | 364 | * @{ |
| bogdanm | 0:9b334a45a8ff | 365 | */ |
| bogdanm | 0:9b334a45a8ff | 366 | #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */ |
| bogdanm | 0:9b334a45a8ff | 367 | #define DFSDM_FILTER_SINC1_ORDER DFSDM_FCR_FORD_0 /*!< Sinc 1 filter type */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define DFSDM_FILTER_SINC2_ORDER DFSDM_FCR_FORD_1 /*!< Sinc 2 filter type */ |
| bogdanm | 0:9b334a45a8ff | 369 | #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FCR_FORD_0 | DFSDM_FCR_FORD_1) /*!< Sinc 3 filter type */ |
| bogdanm | 0:9b334a45a8ff | 370 | #define DFSDM_FILTER_SINC4_ORDER DFSDM_FCR_FORD_2 /*!< Sinc 4 filter type */ |
| bogdanm | 0:9b334a45a8ff | 371 | #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FCR_FORD_0 | DFSDM_FCR_FORD_2) /*!< Sinc 5 filter type */ |
| bogdanm | 0:9b334a45a8ff | 372 | /** |
| bogdanm | 0:9b334a45a8ff | 373 | * @} |
| bogdanm | 0:9b334a45a8ff | 374 | */ |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source |
| bogdanm | 0:9b334a45a8ff | 377 | * @{ |
| bogdanm | 0:9b334a45a8ff | 378 | */ |
| bogdanm | 0:9b334a45a8ff | 379 | #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000) /*!< From digital filter */ |
| bogdanm | 0:9b334a45a8ff | 380 | #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_CR1_AWFSEL /*!< From analog watchdog channel */ |
| bogdanm | 0:9b334a45a8ff | 381 | /** |
| bogdanm | 0:9b334a45a8ff | 382 | * @} |
| bogdanm | 0:9b334a45a8ff | 383 | */ |
| bogdanm | 0:9b334a45a8ff | 384 | |
| bogdanm | 0:9b334a45a8ff | 385 | /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code |
| bogdanm | 0:9b334a45a8ff | 386 | * @{ |
| bogdanm | 0:9b334a45a8ff | 387 | */ |
| bogdanm | 0:9b334a45a8ff | 388 | #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */ |
| bogdanm | 0:9b334a45a8ff | 390 | #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */ |
| bogdanm | 0:9b334a45a8ff | 391 | #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */ |
| bogdanm | 0:9b334a45a8ff | 392 | /** |
| bogdanm | 0:9b334a45a8ff | 393 | * @} |
| bogdanm | 0:9b334a45a8ff | 394 | */ |
| bogdanm | 0:9b334a45a8ff | 395 | |
| bogdanm | 0:9b334a45a8ff | 396 | /** @defgroup DFSDM_BreakSignals DFSDM break signals |
| bogdanm | 0:9b334a45a8ff | 397 | * @{ |
| bogdanm | 0:9b334a45a8ff | 398 | */ |
| bogdanm | 0:9b334a45a8ff | 399 | #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000) /*!< No break signal */ |
| bogdanm | 0:9b334a45a8ff | 400 | #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001) /*!< Break signal 0 */ |
| bogdanm | 0:9b334a45a8ff | 401 | #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002) /*!< Break signal 1 */ |
| bogdanm | 0:9b334a45a8ff | 402 | #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004) /*!< Break signal 2 */ |
| bogdanm | 0:9b334a45a8ff | 403 | #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008) /*!< Break signal 3 */ |
| bogdanm | 0:9b334a45a8ff | 404 | /** |
| bogdanm | 0:9b334a45a8ff | 405 | * @} |
| bogdanm | 0:9b334a45a8ff | 406 | */ |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection |
| bogdanm | 0:9b334a45a8ff | 409 | * @{ |
| bogdanm | 0:9b334a45a8ff | 410 | */ |
| bogdanm | 0:9b334a45a8ff | 411 | /* DFSDM Channels ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 412 | /* The DFSDM channels are defined as follows: |
| bogdanm | 0:9b334a45a8ff | 413 | - in 16-bit LSB the channel mask is set |
| bogdanm | 0:9b334a45a8ff | 414 | - in 16-bit MSB the channel number is set |
| bogdanm | 0:9b334a45a8ff | 415 | e.g. for channel 5 definition: |
| bogdanm | 0:9b334a45a8ff | 416 | - the channel mask is 0x00000020 (bit 5 is set) |
| bogdanm | 0:9b334a45a8ff | 417 | - the channel number 5 is 0x00050000 |
| bogdanm | 0:9b334a45a8ff | 418 | --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ |
| bogdanm | 0:9b334a45a8ff | 419 | #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 420 | #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002) |
| bogdanm | 0:9b334a45a8ff | 421 | #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004) |
| bogdanm | 0:9b334a45a8ff | 422 | #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008) |
| bogdanm | 0:9b334a45a8ff | 423 | #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010) |
| bogdanm | 0:9b334a45a8ff | 424 | #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020) |
| bogdanm | 0:9b334a45a8ff | 425 | #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040) |
| bogdanm | 0:9b334a45a8ff | 426 | #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080) |
| bogdanm | 0:9b334a45a8ff | 427 | /** |
| bogdanm | 0:9b334a45a8ff | 428 | * @} |
| bogdanm | 0:9b334a45a8ff | 429 | */ |
| bogdanm | 0:9b334a45a8ff | 430 | |
| bogdanm | 0:9b334a45a8ff | 431 | /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode |
| bogdanm | 0:9b334a45a8ff | 432 | * @{ |
| bogdanm | 0:9b334a45a8ff | 433 | */ |
| bogdanm | 0:9b334a45a8ff | 434 | #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */ |
| bogdanm | 0:9b334a45a8ff | 435 | #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */ |
| bogdanm | 0:9b334a45a8ff | 436 | /** |
| bogdanm | 0:9b334a45a8ff | 437 | * @} |
| bogdanm | 0:9b334a45a8ff | 438 | */ |
| bogdanm | 0:9b334a45a8ff | 439 | |
| bogdanm | 0:9b334a45a8ff | 440 | /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold |
| bogdanm | 0:9b334a45a8ff | 441 | * @{ |
| bogdanm | 0:9b334a45a8ff | 442 | */ |
| bogdanm | 0:9b334a45a8ff | 443 | #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000) /*!< Analog watchdog high threshold */ |
| bogdanm | 0:9b334a45a8ff | 444 | #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001) /*!< Analog watchdog low threshold */ |
| bogdanm | 0:9b334a45a8ff | 445 | /** |
| bogdanm | 0:9b334a45a8ff | 446 | * @} |
| bogdanm | 0:9b334a45a8ff | 447 | */ |
| bogdanm | 0:9b334a45a8ff | 448 | |
| bogdanm | 0:9b334a45a8ff | 449 | /** |
| bogdanm | 0:9b334a45a8ff | 450 | * @} |
| bogdanm | 0:9b334a45a8ff | 451 | */ |
| bogdanm | 0:9b334a45a8ff | 452 | /* End of exported constants -------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 453 | |
| bogdanm | 0:9b334a45a8ff | 454 | /* Exported macros -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 455 | /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros |
| bogdanm | 0:9b334a45a8ff | 456 | * @{ |
| bogdanm | 0:9b334a45a8ff | 457 | */ |
| bogdanm | 0:9b334a45a8ff | 458 | |
| bogdanm | 0:9b334a45a8ff | 459 | /** @brief Reset DFSDM channel handle state. |
| bogdanm | 0:9b334a45a8ff | 460 | * @param __HANDLE__: DFSDM channel handle. |
| bogdanm | 0:9b334a45a8ff | 461 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 462 | */ |
| bogdanm | 0:9b334a45a8ff | 463 | #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 464 | |
| bogdanm | 0:9b334a45a8ff | 465 | /** @brief Reset DFSDM filter handle state. |
| bogdanm | 0:9b334a45a8ff | 466 | * @param __HANDLE__: DFSDM filter handle. |
| bogdanm | 0:9b334a45a8ff | 467 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 468 | */ |
| bogdanm | 0:9b334a45a8ff | 469 | #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 470 | |
| bogdanm | 0:9b334a45a8ff | 471 | /** |
| bogdanm | 0:9b334a45a8ff | 472 | * @} |
| bogdanm | 0:9b334a45a8ff | 473 | */ |
| bogdanm | 0:9b334a45a8ff | 474 | /* End of exported macros ----------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 475 | |
| bogdanm | 0:9b334a45a8ff | 476 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 477 | /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions |
| bogdanm | 0:9b334a45a8ff | 478 | * @{ |
| bogdanm | 0:9b334a45a8ff | 479 | */ |
| bogdanm | 0:9b334a45a8ff | 480 | |
| bogdanm | 0:9b334a45a8ff | 481 | /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 482 | * @{ |
| bogdanm | 0:9b334a45a8ff | 483 | */ |
| bogdanm | 0:9b334a45a8ff | 484 | /* Channel initialization and de-initialization functions *********************/ |
| bogdanm | 0:9b334a45a8ff | 485 | HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 486 | HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 487 | void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 488 | void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 489 | /** |
| bogdanm | 0:9b334a45a8ff | 490 | * @} |
| bogdanm | 0:9b334a45a8ff | 491 | */ |
| bogdanm | 0:9b334a45a8ff | 492 | |
| bogdanm | 0:9b334a45a8ff | 493 | /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions |
| bogdanm | 0:9b334a45a8ff | 494 | * @{ |
| bogdanm | 0:9b334a45a8ff | 495 | */ |
| bogdanm | 0:9b334a45a8ff | 496 | /* Channel operation functions ************************************************/ |
| bogdanm | 0:9b334a45a8ff | 497 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 498 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 499 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 500 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 501 | |
| bogdanm | 0:9b334a45a8ff | 502 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
| bogdanm | 0:9b334a45a8ff | 503 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
| bogdanm | 0:9b334a45a8ff | 504 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 505 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 506 | |
| bogdanm | 0:9b334a45a8ff | 507 | int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 508 | HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 511 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 512 | |
| bogdanm | 0:9b334a45a8ff | 513 | void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 514 | void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 515 | /** |
| bogdanm | 0:9b334a45a8ff | 516 | * @} |
| bogdanm | 0:9b334a45a8ff | 517 | */ |
| bogdanm | 0:9b334a45a8ff | 518 | |
| bogdanm | 0:9b334a45a8ff | 519 | /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function |
| bogdanm | 0:9b334a45a8ff | 520 | * @{ |
| bogdanm | 0:9b334a45a8ff | 521 | */ |
| bogdanm | 0:9b334a45a8ff | 522 | /* Channel state function *****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 523 | HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| bogdanm | 0:9b334a45a8ff | 524 | /** |
| bogdanm | 0:9b334a45a8ff | 525 | * @} |
| bogdanm | 0:9b334a45a8ff | 526 | */ |
| bogdanm | 0:9b334a45a8ff | 527 | |
| bogdanm | 0:9b334a45a8ff | 528 | /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 529 | * @{ |
| bogdanm | 0:9b334a45a8ff | 530 | */ |
| bogdanm | 0:9b334a45a8ff | 531 | /* Filter initialization and de-initialization functions *********************/ |
| bogdanm | 0:9b334a45a8ff | 532 | HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 533 | HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 534 | void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 535 | void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 536 | /** |
| bogdanm | 0:9b334a45a8ff | 537 | * @} |
| bogdanm | 0:9b334a45a8ff | 538 | */ |
| bogdanm | 0:9b334a45a8ff | 539 | |
| bogdanm | 0:9b334a45a8ff | 540 | /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions |
| bogdanm | 0:9b334a45a8ff | 541 | * @{ |
| bogdanm | 0:9b334a45a8ff | 542 | */ |
| bogdanm | 0:9b334a45a8ff | 543 | /* Filter control functions *********************/ |
| bogdanm | 0:9b334a45a8ff | 544 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| bogdanm | 0:9b334a45a8ff | 545 | uint32_t Channel, |
| bogdanm | 0:9b334a45a8ff | 546 | uint32_t ContinuousMode); |
| bogdanm | 0:9b334a45a8ff | 547 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| bogdanm | 0:9b334a45a8ff | 548 | uint32_t Channel); |
| bogdanm | 0:9b334a45a8ff | 549 | /** |
| bogdanm | 0:9b334a45a8ff | 550 | * @} |
| bogdanm | 0:9b334a45a8ff | 551 | */ |
| bogdanm | 0:9b334a45a8ff | 552 | |
| bogdanm | 0:9b334a45a8ff | 553 | /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions |
| bogdanm | 0:9b334a45a8ff | 554 | * @{ |
| bogdanm | 0:9b334a45a8ff | 555 | */ |
| bogdanm | 0:9b334a45a8ff | 556 | /* Filter operation functions *********************/ |
| bogdanm | 0:9b334a45a8ff | 557 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 558 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 559 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 560 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 561 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 562 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 563 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 564 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 565 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 566 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 567 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 568 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 569 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 570 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 571 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| bogdanm | 0:9b334a45a8ff | 572 | DFSDM_Filter_AwdParamTypeDef* awdParam); |
| bogdanm | 0:9b334a45a8ff | 573 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 574 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); |
| bogdanm | 0:9b334a45a8ff | 575 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 576 | |
| bogdanm | 0:9b334a45a8ff | 577 | int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| bogdanm | 0:9b334a45a8ff | 578 | int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| bogdanm | 0:9b334a45a8ff | 579 | int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| bogdanm | 0:9b334a45a8ff | 580 | int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| bogdanm | 0:9b334a45a8ff | 581 | uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 582 | |
| bogdanm | 0:9b334a45a8ff | 583 | void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 584 | |
| bogdanm | 0:9b334a45a8ff | 585 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 586 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 587 | |
| bogdanm | 0:9b334a45a8ff | 588 | void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 589 | void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 590 | void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 591 | void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 592 | void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); |
| bogdanm | 0:9b334a45a8ff | 593 | void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 594 | /** |
| bogdanm | 0:9b334a45a8ff | 595 | * @} |
| bogdanm | 0:9b334a45a8ff | 596 | */ |
| bogdanm | 0:9b334a45a8ff | 597 | |
| bogdanm | 0:9b334a45a8ff | 598 | /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions |
| bogdanm | 0:9b334a45a8ff | 599 | * @{ |
| bogdanm | 0:9b334a45a8ff | 600 | */ |
| bogdanm | 0:9b334a45a8ff | 601 | /* Filter state functions *****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 602 | HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 603 | uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| bogdanm | 0:9b334a45a8ff | 604 | /** |
| bogdanm | 0:9b334a45a8ff | 605 | * @} |
| bogdanm | 0:9b334a45a8ff | 606 | */ |
| bogdanm | 0:9b334a45a8ff | 607 | |
| bogdanm | 0:9b334a45a8ff | 608 | /** |
| bogdanm | 0:9b334a45a8ff | 609 | * @} |
| bogdanm | 0:9b334a45a8ff | 610 | */ |
| bogdanm | 0:9b334a45a8ff | 611 | /* End of exported functions -------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 612 | |
| bogdanm | 0:9b334a45a8ff | 613 | /* Private macros ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 614 | /** @defgroup DFSDM_Private_Macros DFSDM Private Macros |
| bogdanm | 0:9b334a45a8ff | 615 | * @{ |
| bogdanm | 0:9b334a45a8ff | 616 | */ |
| bogdanm | 0:9b334a45a8ff | 617 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ |
| bogdanm | 0:9b334a45a8ff | 618 | ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) |
| bogdanm | 0:9b334a45a8ff | 619 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) |
| bogdanm | 0:9b334a45a8ff | 620 | #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
| bogdanm | 0:9b334a45a8ff | 621 | ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
| bogdanm | 0:9b334a45a8ff | 622 | #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ |
| bogdanm | 0:9b334a45a8ff | 623 | ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ |
| bogdanm | 0:9b334a45a8ff | 624 | ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) |
| bogdanm | 0:9b334a45a8ff | 625 | #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ |
| bogdanm | 0:9b334a45a8ff | 626 | ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) |
| bogdanm | 0:9b334a45a8ff | 627 | #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ |
| bogdanm | 0:9b334a45a8ff | 628 | ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ |
| bogdanm | 0:9b334a45a8ff | 629 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ |
| bogdanm | 0:9b334a45a8ff | 630 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) |
| bogdanm | 0:9b334a45a8ff | 631 | #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ |
| bogdanm | 0:9b334a45a8ff | 632 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ |
| bogdanm | 0:9b334a45a8ff | 633 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ |
| bogdanm | 0:9b334a45a8ff | 634 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) |
| bogdanm | 0:9b334a45a8ff | 635 | #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 636 | ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 637 | ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 638 | ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) |
| bogdanm | 0:9b334a45a8ff | 639 | #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) |
| bogdanm | 0:9b334a45a8ff | 640 | #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
| bogdanm | 0:9b334a45a8ff | 641 | #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) |
| bogdanm | 0:9b334a45a8ff | 642 | #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) |
| bogdanm | 0:9b334a45a8ff | 643 | #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
| bogdanm | 0:9b334a45a8ff | 644 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) |
| bogdanm | 0:9b334a45a8ff | 645 | #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
| bogdanm | 0:9b334a45a8ff | 646 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ |
| bogdanm | 0:9b334a45a8ff | 647 | ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) |
| bogdanm | 0:9b334a45a8ff | 648 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 649 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ |
| bogdanm | 0:9b334a45a8ff | 650 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 651 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ |
| bogdanm | 0:9b334a45a8ff | 652 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 653 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 654 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ |
| bogdanm | 0:9b334a45a8ff | 655 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 656 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 657 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
| bogdanm | 0:9b334a45a8ff | 658 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
| bogdanm | 0:9b334a45a8ff | 659 | #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ |
| bogdanm | 0:9b334a45a8ff | 660 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ |
| bogdanm | 0:9b334a45a8ff | 661 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) |
| bogdanm | 0:9b334a45a8ff | 662 | #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 663 | ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 664 | ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 665 | ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 666 | ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ |
| bogdanm | 0:9b334a45a8ff | 667 | ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) |
| bogdanm | 0:9b334a45a8ff | 668 | #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) |
| bogdanm | 0:9b334a45a8ff | 669 | #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) |
| bogdanm | 0:9b334a45a8ff | 670 | #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ |
| bogdanm | 0:9b334a45a8ff | 671 | ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) |
| bogdanm | 0:9b334a45a8ff | 672 | #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
| bogdanm | 0:9b334a45a8ff | 673 | #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF) |
| bogdanm | 0:9b334a45a8ff | 674 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
| bogdanm | 0:9b334a45a8ff | 675 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
| bogdanm | 0:9b334a45a8ff | 676 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
| bogdanm | 0:9b334a45a8ff | 677 | ((CHANNEL) == DFSDM_CHANNEL_3) || \ |
| bogdanm | 0:9b334a45a8ff | 678 | ((CHANNEL) == DFSDM_CHANNEL_4) || \ |
| bogdanm | 0:9b334a45a8ff | 679 | ((CHANNEL) == DFSDM_CHANNEL_5) || \ |
| bogdanm | 0:9b334a45a8ff | 680 | ((CHANNEL) == DFSDM_CHANNEL_6) || \ |
| bogdanm | 0:9b334a45a8ff | 681 | ((CHANNEL) == DFSDM_CHANNEL_7)) |
| bogdanm | 0:9b334a45a8ff | 682 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF)) |
| bogdanm | 0:9b334a45a8ff | 683 | #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ |
| bogdanm | 0:9b334a45a8ff | 684 | ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) |
| bogdanm | 0:9b334a45a8ff | 685 | /** |
| bogdanm | 0:9b334a45a8ff | 686 | * @} |
| bogdanm | 0:9b334a45a8ff | 687 | */ |
| bogdanm | 0:9b334a45a8ff | 688 | /* End of private macros -----------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 689 | |
| bogdanm | 0:9b334a45a8ff | 690 | /** |
| bogdanm | 0:9b334a45a8ff | 691 | * @} |
| bogdanm | 0:9b334a45a8ff | 692 | */ |
| bogdanm | 0:9b334a45a8ff | 693 | |
| bogdanm | 0:9b334a45a8ff | 694 | /** |
| bogdanm | 0:9b334a45a8ff | 695 | * @} |
| bogdanm | 0:9b334a45a8ff | 696 | */ |
| bogdanm | 0:9b334a45a8ff | 697 | |
| bogdanm | 0:9b334a45a8ff | 698 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 699 | } |
| bogdanm | 0:9b334a45a8ff | 700 | #endif |
| bogdanm | 0:9b334a45a8ff | 701 | |
| bogdanm | 0:9b334a45a8ff | 702 | #endif /* __STM32L4xx_HAL_DFSDM_H */ |
| bogdanm | 0:9b334a45a8ff | 703 | |
| bogdanm | 0:9b334a45a8ff | 704 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |