en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_cortex.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_cortex.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of CORTEX HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L4xx_HAL_CORTEX_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L4xx_HAL_CORTEX_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32l4xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @defgroup CORTEX CORTEX
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 63 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
bogdanm 0:9b334a45a8ff 64 * @{
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 typedef struct
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 uint8_t Enable; /*!< Specifies the status of the region.
bogdanm 0:9b334a45a8ff 69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
bogdanm 0:9b334a45a8ff 70 uint8_t Number; /*!< Specifies the number of the region to protect.
bogdanm 0:9b334a45a8ff 71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
bogdanm 0:9b334a45a8ff 72 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
bogdanm 0:9b334a45a8ff 73 uint8_t Size; /*!< Specifies the size of the region to protect.
bogdanm 0:9b334a45a8ff 74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
bogdanm 0:9b334a45a8ff 75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
bogdanm 0:9b334a45a8ff 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 0:9b334a45a8ff 77 uint8_t TypeExtField; /*!< Specifies the TEX field level.
bogdanm 0:9b334a45a8ff 78 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
bogdanm 0:9b334a45a8ff 79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
bogdanm 0:9b334a45a8ff 80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
bogdanm 0:9b334a45a8ff 81 uint8_t DisableExec; /*!< Specifies the instruction access status.
bogdanm 0:9b334a45a8ff 82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
bogdanm 0:9b334a45a8ff 83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
bogdanm 0:9b334a45a8ff 84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
bogdanm 0:9b334a45a8ff 85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
bogdanm 0:9b334a45a8ff 86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
bogdanm 0:9b334a45a8ff 87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
bogdanm 0:9b334a45a8ff 88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
bogdanm 0:9b334a45a8ff 89 }MPU_Region_InitTypeDef;
bogdanm 0:9b334a45a8ff 90 /**
bogdanm 0:9b334a45a8ff 91 * @}
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93 #endif /* __MPU_PRESENT */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /**
bogdanm 0:9b334a45a8ff 96 * @}
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
bogdanm 0:9b334a45a8ff 106 * @{
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
bogdanm 0:9b334a45a8ff 109 4 bits for subpriority */
bogdanm 0:9b334a45a8ff 110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
bogdanm 0:9b334a45a8ff 111 3 bits for subpriority */
bogdanm 0:9b334a45a8ff 112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
bogdanm 0:9b334a45a8ff 113 2 bits for subpriority */
bogdanm 0:9b334a45a8ff 114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
bogdanm 0:9b334a45a8ff 115 1 bit for subpriority */
bogdanm 0:9b334a45a8ff 116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
bogdanm 0:9b334a45a8ff 117 0 bit for subpriority */
bogdanm 0:9b334a45a8ff 118 /**
bogdanm 0:9b334a45a8ff 119 * @}
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 127 /**
bogdanm 0:9b334a45a8ff 128 * @}
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 132 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
bogdanm 0:9b334a45a8ff 133 * @{
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 136 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 137 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 138 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 139 /**
bogdanm 0:9b334a45a8ff 140 * @}
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
bogdanm 0:9b334a45a8ff 144 * @{
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146 #define MPU_REGION_ENABLE ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 147 #define MPU_REGION_DISABLE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @}
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
bogdanm 0:9b334a45a8ff 153 * @{
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 156 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 157 /**
bogdanm 0:9b334a45a8ff 158 * @}
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
bogdanm 0:9b334a45a8ff 162 * @{
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 165 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @}
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 174 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 175 /**
bogdanm 0:9b334a45a8ff 176 * @}
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
bogdanm 0:9b334a45a8ff 180 * @{
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 183 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 184 /**
bogdanm 0:9b334a45a8ff 185 * @}
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
bogdanm 0:9b334a45a8ff 189 * @{
bogdanm 0:9b334a45a8ff 190 */
bogdanm 0:9b334a45a8ff 191 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 192 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 193 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @}
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
bogdanm 0:9b334a45a8ff 199 * @{
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
bogdanm 0:9b334a45a8ff 202 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
bogdanm 0:9b334a45a8ff 203 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
bogdanm 0:9b334a45a8ff 204 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
bogdanm 0:9b334a45a8ff 205 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
bogdanm 0:9b334a45a8ff 206 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
bogdanm 0:9b334a45a8ff 207 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
bogdanm 0:9b334a45a8ff 208 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
bogdanm 0:9b334a45a8ff 209 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
bogdanm 0:9b334a45a8ff 210 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
bogdanm 0:9b334a45a8ff 211 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
bogdanm 0:9b334a45a8ff 212 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
bogdanm 0:9b334a45a8ff 213 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
bogdanm 0:9b334a45a8ff 214 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
bogdanm 0:9b334a45a8ff 215 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
bogdanm 0:9b334a45a8ff 216 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
bogdanm 0:9b334a45a8ff 217 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
bogdanm 0:9b334a45a8ff 218 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
bogdanm 0:9b334a45a8ff 219 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
bogdanm 0:9b334a45a8ff 220 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
bogdanm 0:9b334a45a8ff 221 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
bogdanm 0:9b334a45a8ff 222 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
bogdanm 0:9b334a45a8ff 223 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
bogdanm 0:9b334a45a8ff 224 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
bogdanm 0:9b334a45a8ff 225 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
bogdanm 0:9b334a45a8ff 226 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
bogdanm 0:9b334a45a8ff 227 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
bogdanm 0:9b334a45a8ff 228 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
bogdanm 0:9b334a45a8ff 229 /**
bogdanm 0:9b334a45a8ff 230 * @}
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
bogdanm 0:9b334a45a8ff 234 * @{
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 237 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 238 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 239 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
bogdanm 0:9b334a45a8ff 240 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
bogdanm 0:9b334a45a8ff 241 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
bogdanm 0:9b334a45a8ff 242 /**
bogdanm 0:9b334a45a8ff 243 * @}
bogdanm 0:9b334a45a8ff 244 */
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
bogdanm 0:9b334a45a8ff 247 * @{
bogdanm 0:9b334a45a8ff 248 */
bogdanm 0:9b334a45a8ff 249 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 250 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 251 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 252 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
bogdanm 0:9b334a45a8ff 253 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
bogdanm 0:9b334a45a8ff 254 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
bogdanm 0:9b334a45a8ff 255 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
bogdanm 0:9b334a45a8ff 256 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @}
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 #endif /* __MPU_PRESENT */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /**
bogdanm 0:9b334a45a8ff 263 * @}
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Exported macros -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 267 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
bogdanm 0:9b334a45a8ff 268 * @{
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source
bogdanm 0:9b334a45a8ff 272 * @{
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /** @brief Configure the SysTick clock source.
bogdanm 0:9b334a45a8ff 276 * @param __CLKSRC__: specifies the SysTick clock source.
bogdanm 0:9b334a45a8ff 277 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 278 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
bogdanm 0:9b334a45a8ff 279 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
bogdanm 0:9b334a45a8ff 280 * @retval None
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282 #define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
bogdanm 0:9b334a45a8ff 283 do { \
bogdanm 0:9b334a45a8ff 284 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
bogdanm 0:9b334a45a8ff 285 { \
bogdanm 0:9b334a45a8ff 286 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
bogdanm 0:9b334a45a8ff 287 } \
bogdanm 0:9b334a45a8ff 288 else \
bogdanm 0:9b334a45a8ff 289 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
bogdanm 0:9b334a45a8ff 290 } while(0)
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /**
bogdanm 0:9b334a45a8ff 293 * @}
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /**
bogdanm 0:9b334a45a8ff 297 * @}
bogdanm 0:9b334a45a8ff 298 */
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 301 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
bogdanm 0:9b334a45a8ff 302 * @{
bogdanm 0:9b334a45a8ff 303 */
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 306 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 307 * @{
bogdanm 0:9b334a45a8ff 308 */
bogdanm 0:9b334a45a8ff 309 /* Initialization and Configuration functions *****************************/
bogdanm 0:9b334a45a8ff 310 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
bogdanm 0:9b334a45a8ff 311 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
bogdanm 0:9b334a45a8ff 312 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 313 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 314 void HAL_NVIC_SystemReset(void);
bogdanm 0:9b334a45a8ff 315 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief Disable the MPU.
bogdanm 0:9b334a45a8ff 320 * @retval None
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 __STATIC_INLINE void HAL_MPU_Disable(void)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 /* Disable fault exceptions */
bogdanm 0:9b334a45a8ff 325 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Disable the MPU */
bogdanm 0:9b334a45a8ff 328 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * @brief Enable the MPU.
bogdanm 0:9b334a45a8ff 333 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
bogdanm 0:9b334a45a8ff 334 * NMI, FAULTMASK and privileged accessto the default memory
bogdanm 0:9b334a45a8ff 335 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 336 * @arg MPU_HFNMI_PRIVDEF_NONE
bogdanm 0:9b334a45a8ff 337 * @arg MPU_HARDFAULT_NMI
bogdanm 0:9b334a45a8ff 338 * @arg MPU_PRIVILEGED_DEFAULT
bogdanm 0:9b334a45a8ff 339 * @arg MPU_HFNMI_PRIVDEF
bogdanm 0:9b334a45a8ff 340 * @retval None
bogdanm 0:9b334a45a8ff 341 */
bogdanm 0:9b334a45a8ff 342 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 /* Enable the MPU */
bogdanm 0:9b334a45a8ff 345 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Enable fault exceptions */
bogdanm 0:9b334a45a8ff 348 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 #endif /* __MPU_PRESENT */
bogdanm 0:9b334a45a8ff 351 /**
bogdanm 0:9b334a45a8ff 352 * @}
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 356 * @brief Cortex control functions
bogdanm 0:9b334a45a8ff 357 * @{
bogdanm 0:9b334a45a8ff 358 */
bogdanm 0:9b334a45a8ff 359 /* Peripheral Control functions ***********************************************/
bogdanm 0:9b334a45a8ff 360 uint32_t HAL_NVIC_GetPriorityGrouping(void);
bogdanm 0:9b334a45a8ff 361 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
bogdanm 0:9b334a45a8ff 362 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 363 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 364 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 365 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 366 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
bogdanm 0:9b334a45a8ff 367 void HAL_SYSTICK_IRQHandler(void);
bogdanm 0:9b334a45a8ff 368 void HAL_SYSTICK_Callback(void);
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 371 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
bogdanm 0:9b334a45a8ff 372 #endif /* __MPU_PRESENT */
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @}
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /**
bogdanm 0:9b334a45a8ff 378 * @}
bogdanm 0:9b334a45a8ff 379 */
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 382 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 383 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 384 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 385 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
bogdanm 0:9b334a45a8ff 386 * @{
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
bogdanm 0:9b334a45a8ff 389 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
bogdanm 0:9b334a45a8ff 390 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
bogdanm 0:9b334a45a8ff 391 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
bogdanm 0:9b334a45a8ff 392 ((GROUP) == NVIC_PRIORITYGROUP_4))
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
bogdanm 0:9b334a45a8ff 401 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 404 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
bogdanm 0:9b334a45a8ff 405 ((STATE) == MPU_REGION_DISABLE))
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
bogdanm 0:9b334a45a8ff 408 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
bogdanm 0:9b334a45a8ff 411 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
bogdanm 0:9b334a45a8ff 414 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
bogdanm 0:9b334a45a8ff 417 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
bogdanm 0:9b334a45a8ff 420 ((TYPE) == MPU_TEX_LEVEL1) || \
bogdanm 0:9b334a45a8ff 421 ((TYPE) == MPU_TEX_LEVEL2))
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
bogdanm 0:9b334a45a8ff 424 ((TYPE) == MPU_REGION_PRIV_RW) || \
bogdanm 0:9b334a45a8ff 425 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
bogdanm 0:9b334a45a8ff 426 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
bogdanm 0:9b334a45a8ff 427 ((TYPE) == MPU_REGION_PRIV_RO) || \
bogdanm 0:9b334a45a8ff 428 ((TYPE) == MPU_REGION_PRIV_RO_URO))
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
bogdanm 0:9b334a45a8ff 431 ((NUMBER) == MPU_REGION_NUMBER1) || \
bogdanm 0:9b334a45a8ff 432 ((NUMBER) == MPU_REGION_NUMBER2) || \
bogdanm 0:9b334a45a8ff 433 ((NUMBER) == MPU_REGION_NUMBER3) || \
bogdanm 0:9b334a45a8ff 434 ((NUMBER) == MPU_REGION_NUMBER4) || \
bogdanm 0:9b334a45a8ff 435 ((NUMBER) == MPU_REGION_NUMBER5) || \
bogdanm 0:9b334a45a8ff 436 ((NUMBER) == MPU_REGION_NUMBER6) || \
bogdanm 0:9b334a45a8ff 437 ((NUMBER) == MPU_REGION_NUMBER7))
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
bogdanm 0:9b334a45a8ff 440 ((SIZE) == MPU_REGION_SIZE_64B) || \
bogdanm 0:9b334a45a8ff 441 ((SIZE) == MPU_REGION_SIZE_128B) || \
bogdanm 0:9b334a45a8ff 442 ((SIZE) == MPU_REGION_SIZE_256B) || \
bogdanm 0:9b334a45a8ff 443 ((SIZE) == MPU_REGION_SIZE_512B) || \
bogdanm 0:9b334a45a8ff 444 ((SIZE) == MPU_REGION_SIZE_1KB) || \
bogdanm 0:9b334a45a8ff 445 ((SIZE) == MPU_REGION_SIZE_2KB) || \
bogdanm 0:9b334a45a8ff 446 ((SIZE) == MPU_REGION_SIZE_4KB) || \
bogdanm 0:9b334a45a8ff 447 ((SIZE) == MPU_REGION_SIZE_8KB) || \
bogdanm 0:9b334a45a8ff 448 ((SIZE) == MPU_REGION_SIZE_16KB) || \
bogdanm 0:9b334a45a8ff 449 ((SIZE) == MPU_REGION_SIZE_32KB) || \
bogdanm 0:9b334a45a8ff 450 ((SIZE) == MPU_REGION_SIZE_64KB) || \
bogdanm 0:9b334a45a8ff 451 ((SIZE) == MPU_REGION_SIZE_128KB) || \
bogdanm 0:9b334a45a8ff 452 ((SIZE) == MPU_REGION_SIZE_256KB) || \
bogdanm 0:9b334a45a8ff 453 ((SIZE) == MPU_REGION_SIZE_512KB) || \
bogdanm 0:9b334a45a8ff 454 ((SIZE) == MPU_REGION_SIZE_1MB) || \
bogdanm 0:9b334a45a8ff 455 ((SIZE) == MPU_REGION_SIZE_2MB) || \
bogdanm 0:9b334a45a8ff 456 ((SIZE) == MPU_REGION_SIZE_4MB) || \
bogdanm 0:9b334a45a8ff 457 ((SIZE) == MPU_REGION_SIZE_8MB) || \
bogdanm 0:9b334a45a8ff 458 ((SIZE) == MPU_REGION_SIZE_16MB) || \
bogdanm 0:9b334a45a8ff 459 ((SIZE) == MPU_REGION_SIZE_32MB) || \
bogdanm 0:9b334a45a8ff 460 ((SIZE) == MPU_REGION_SIZE_64MB) || \
bogdanm 0:9b334a45a8ff 461 ((SIZE) == MPU_REGION_SIZE_128MB) || \
bogdanm 0:9b334a45a8ff 462 ((SIZE) == MPU_REGION_SIZE_256MB) || \
bogdanm 0:9b334a45a8ff 463 ((SIZE) == MPU_REGION_SIZE_512MB) || \
bogdanm 0:9b334a45a8ff 464 ((SIZE) == MPU_REGION_SIZE_1GB) || \
bogdanm 0:9b334a45a8ff 465 ((SIZE) == MPU_REGION_SIZE_2GB) || \
bogdanm 0:9b334a45a8ff 466 ((SIZE) == MPU_REGION_SIZE_4GB))
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
bogdanm 0:9b334a45a8ff 469 #endif /* __MPU_PRESENT */
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /**
bogdanm 0:9b334a45a8ff 472 * @}
bogdanm 0:9b334a45a8ff 473 */
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /**
bogdanm 0:9b334a45a8ff 478 * @}
bogdanm 0:9b334a45a8ff 479 */
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /**
bogdanm 0:9b334a45a8ff 482 * @}
bogdanm 0:9b334a45a8ff 483 */
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487 #endif
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 #endif /* __STM32L4xx_HAL_CORTEX_H */
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/