mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_adc_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC)
bogdanm	0:9b334a45a8ff	9	* peripheral:
bogdanm	0:9b334a45a8ff	10	* + Calibration functions
bogdanm	0:9b334a45a8ff	11	* ++ Calibration start-up
bogdanm	0:9b334a45a8ff	12	* ++ Calibration value reading or setting
bogdanm	0:9b334a45a8ff	13	* + Operation functions
bogdanm	0:9b334a45a8ff	14	* ++ Start, stop, get result of conversions of injected
bogdanm	0:9b334a45a8ff	15	* groups, using 3 possible modes: polling or interruption.
bogdanm	0:9b334a45a8ff	16	* ++ Multimode feature
bogdanm	0:9b334a45a8ff	17	* + Control functions
bogdanm	0:9b334a45a8ff	18	* ++ Configure channels on injected group
bogdanm	0:9b334a45a8ff	19	* + State functions
bogdanm	0:9b334a45a8ff	20	* ++ Injected group queues management
bogdanm	0:9b334a45a8ff	21	*
bogdanm	0:9b334a45a8ff	22	@verbatim
bogdanm	0:9b334a45a8ff	23	==============================================================================
bogdanm	0:9b334a45a8ff	24	##### ADC specific features #####
bogdanm	0:9b334a45a8ff	25	==============================================================================
bogdanm	0:9b334a45a8ff	26	[..]
bogdanm	0:9b334a45a8ff	27	(#) Interrupt generation at the end of injected conversion and in case of
bogdanm	0:9b334a45a8ff	28	injected queues overflow.
bogdanm	0:9b334a45a8ff	29
bogdanm	0:9b334a45a8ff	30	(#) External trigger (timer or EXTI) with configurable polarity for
bogdanm	0:9b334a45a8ff	31	injected groups.
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	(#) Multimode Dual mode.
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	(#) Configurable DMA data storage in Multimode Dual mode.
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	(#) Configurable delay between conversions in Dual interleaved mode.
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	(#) ADC calibration.
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) ADC channels selectable single/differential input.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(#) ADC Injected sequencer&channels configuration context queue.
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	(#) ADC offset on injected groups.
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	(#) ADC oversampling.
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	51	==============================================================================
bogdanm	0:9b334a45a8ff	52	[..]
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	(#) Configure the ADC parameters (conversion resolution, data alignment,
bogdanm	0:9b334a45a8ff	55	continuous mode, ...) using the HAL_ADC_Init() function.
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	(#) Activate the ADC peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	58	HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
bogdanm	0:9b334a45a8ff	59	or
bogdanm	0:9b334a45a8ff	60	HAL_ADC_MultiModeStart_DMA() for multimode conversions.
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	* Channels to injected group configuration *
bogdanm	0:9b334a45a8ff	64	=============================================
bogdanm	0:9b334a45a8ff	65	[..]
bogdanm	0:9b334a45a8ff	66	(+) To configure the ADC Injected channels group features, use
bogdanm	0:9b334a45a8ff	67	HAL_ADCEx_InjectedConfigChannel() functions.
bogdanm	0:9b334a45a8ff	68	(+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
bogdanm	0:9b334a45a8ff	69	function.
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	* Multimode ADCs configuration *
bogdanm	0:9b334a45a8ff	73	======================================================
bogdanm	0:9b334a45a8ff	74	[..]
bogdanm	0:9b334a45a8ff	75	(+) Multimode feature is available and applicable to ADC1 (Master)
bogdanm	0:9b334a45a8ff	76	and ADC2 (Slave).
bogdanm	0:9b334a45a8ff	77	(+) Refer to "Channels to regular group configuration" description to
bogdanm	0:9b334a45a8ff	78	configure the ADC1 and ADC2 regular groups.
bogdanm	0:9b334a45a8ff	79	(+) Select the Multi mode ADC features (dual mode
bogdanm	0:9b334a45a8ff	80	simultaneous, interleaved, ...) and configure the DMA mode using
bogdanm	0:9b334a45a8ff	81	HAL_ADCEx_MultiModeConfigChannel() functions.
bogdanm	0:9b334a45a8ff	82	(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
bogdanm	0:9b334a45a8ff	83	function.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	@endverbatim
bogdanm	0:9b334a45a8ff	87	******************************************************************************
bogdanm	0:9b334a45a8ff	88	* @attention
bogdanm	0:9b334a45a8ff	89	*
bogdanm	0:9b334a45a8ff	90	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	91	*
bogdanm	0:9b334a45a8ff	92	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	93	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	94	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	95	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	96	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	97	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	98	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	99	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	100	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	101	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	104	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	105	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	106	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	107	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	108	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	109	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	110	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	111	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	112	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	******************************************************************************
bogdanm	0:9b334a45a8ff	115	*/
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	118	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	121	* @{
bogdanm	0:9b334a45a8ff	122	*/
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	/** @defgroup ADCEx ADCEx
bogdanm	0:9b334a45a8ff	125	* @brief ADC Extended HAL module driver
bogdanm	0:9b334a45a8ff	126	* @{
bogdanm	0:9b334a45a8ff	127	*/
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	#ifdef HAL_ADC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	132	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
bogdanm	0:9b334a45a8ff	135	* @{
bogdanm	0:9b334a45a8ff	136	*/
bogdanm	0:9b334a45a8ff	137
bogdanm	0:9b334a45a8ff	138	#define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL \| ADC_JSQR_JEXTSEL \| ADC_JSQR_JEXTEN \|\
bogdanm	0:9b334a45a8ff	139	ADC_JSQR_JSQ1 \| ADC_JSQR_JSQ2 \|\
bogdanm	0:9b334a45a8ff	140	ADC_JSQR_JSQ3 \| ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
bogdanm	0:9b334a45a8ff	141	once the ADC is enabled */
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE \| ADC_CFGR2_OVSR \|\
bogdanm	0:9b334a45a8ff	144	ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated
bogdanm	0:9b334a45a8ff	145	when no conversion is on-going (neither regular nor injected) */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/* Fixed timeout value for ADC calibration. */
bogdanm	0:9b334a45a8ff	148	/* Values defined to be higher than worst cases: low clock frequency, */
bogdanm	0:9b334a45a8ff	149	/* maximum prescalers. */
bogdanm	0:9b334a45a8ff	150	/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value */
bogdanm	0:9b334a45a8ff	151	/* according to Data sheet), calibration_time MAX = 112 / f_ADC */
bogdanm	0:9b334a45a8ff	152	/* 112 / 140,000 = 0.8 ms */
bogdanm	0:9b334a45a8ff	153	/* At maximum CPU speed (80 MHz), this means */
bogdanm	0:9b334a45a8ff	154	/* 0.8 ms * 80 MHz = 64000 CPU cycles */
bogdanm	0:9b334a45a8ff	155	#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /!< ADC calibration time-out value /
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	/**
bogdanm	0:9b334a45a8ff	158	* @}
bogdanm	0:9b334a45a8ff	159	*/
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	162	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	163	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	164	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
bogdanm	0:9b334a45a8ff	167	* @{
bogdanm	0:9b334a45a8ff	168	*/
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
bogdanm	0:9b334a45a8ff	173	* @brief Extended IO operation functions
bogdanm	0:9b334a45a8ff	174	*
bogdanm	0:9b334a45a8ff	175	@verbatim
bogdanm	0:9b334a45a8ff	176	===============================================================================
bogdanm	0:9b334a45a8ff	177	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	178	===============================================================================
bogdanm	0:9b334a45a8ff	179	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	(+) Perform the ADC self-calibration for single or differential ending.
bogdanm	0:9b334a45a8ff	182	(+) Get calibration factors for single or differential ending.
bogdanm	0:9b334a45a8ff	183	(+) Set calibration factors for single or differential ending.
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	(+) Start conversion of injected group.
bogdanm	0:9b334a45a8ff	186	(+) Stop conversion of injected group.
bogdanm	0:9b334a45a8ff	187	(+) Poll for conversion complete on injected group.
bogdanm	0:9b334a45a8ff	188	(+) Get result of injected channel conversion.
bogdanm	0:9b334a45a8ff	189	(+) Start conversion of injected group and enable interruptions.
bogdanm	0:9b334a45a8ff	190	(+) Stop conversion of injected group and disable interruptions.
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	(+) Start multimode and enable DMA transfer.
bogdanm	0:9b334a45a8ff	193	(+) Stop multimode and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	194	(+) Get result of multimode conversion.
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	@endverbatim
bogdanm	0:9b334a45a8ff	199	* @{
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/**
bogdanm	0:9b334a45a8ff	205	* @brief Perform an ADC automatic self-calibration
bogdanm	0:9b334a45a8ff	206	* Calibration prerequisite: ADC must be disabled (execute this
bogdanm	0:9b334a45a8ff	207	* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
bogdanm	0:9b334a45a8ff	208	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	209	* @param SingleDiff: Selection of single-ended or differential input
bogdanm	0:9b334a45a8ff	210	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	211	* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
bogdanm	0:9b334a45a8ff	212	* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
bogdanm	0:9b334a45a8ff	213	* @retval HAL status
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
bogdanm	0:9b334a45a8ff	216	{
bogdanm	0:9b334a45a8ff	217	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	218	uint32_t WaitLoopIndex = 0;
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/* Check the parameters */
bogdanm	0:9b334a45a8ff	221	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	222	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	/* Process locked */
bogdanm	0:9b334a45a8ff	225	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/* Calibration prerequisite: ADC must be disabled. */
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Disable the ADC (if not already disabled) */
bogdanm	0:9b334a45a8ff	230	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	233	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	234	{
bogdanm	0:9b334a45a8ff	235	/* Change ADC state */
bogdanm	0:9b334a45a8ff	236	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
bogdanm	0:9b334a45a8ff	237	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/* Select calibration mode single ended or differential ended */
bogdanm	0:9b334a45a8ff	240	MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/* Start ADC calibration */
bogdanm	0:9b334a45a8ff	243	SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/* Wait for calibration completion */
bogdanm	0:9b334a45a8ff	247	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
bogdanm	0:9b334a45a8ff	248	{
bogdanm	0:9b334a45a8ff	249	WaitLoopIndex++;
bogdanm	0:9b334a45a8ff	250	if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
bogdanm	0:9b334a45a8ff	251	{
bogdanm	0:9b334a45a8ff	252	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	253	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
bogdanm	0:9b334a45a8ff	254	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/* Process unlocked */
bogdanm	0:9b334a45a8ff	257	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	260	}
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	264	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266	else
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	269
bogdanm	0:9b334a45a8ff	270	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	271	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	272	}
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	/* Process unlocked */
bogdanm	0:9b334a45a8ff	276	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Return function status */
bogdanm	0:9b334a45a8ff	279	return tmp_status;
bogdanm	0:9b334a45a8ff	280	}
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/**
bogdanm	0:9b334a45a8ff	286	* @brief Get the calibration factor from automatic conversion result.
bogdanm	0:9b334a45a8ff	287	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	288	* @param SingleDiff: Selection of single-ended or differential input
bogdanm	0:9b334a45a8ff	289	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	290	* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
bogdanm	0:9b334a45a8ff	291	* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
bogdanm	0:9b334a45a8ff	292	* @retval Converted value
bogdanm	0:9b334a45a8ff	293	*/
bogdanm	0:9b334a45a8ff	294	uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
bogdanm	0:9b334a45a8ff	295	{
bogdanm	0:9b334a45a8ff	296	/* Check the parameters */
bogdanm	0:9b334a45a8ff	297	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	298	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Return the selected ADC calibration value */
bogdanm	0:9b334a45a8ff	301	if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	302	{
bogdanm	0:9b334a45a8ff	303	return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
bogdanm	0:9b334a45a8ff	304	}
bogdanm	0:9b334a45a8ff	305	else
bogdanm	0:9b334a45a8ff	306	{
bogdanm	0:9b334a45a8ff	307	return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
bogdanm	0:9b334a45a8ff	308	}
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/**
bogdanm	0:9b334a45a8ff	314	* @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
bogdanm	0:9b334a45a8ff	315	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	316	* @param SingleDiff: Selection of single-ended or differential input.
bogdanm	0:9b334a45a8ff	317	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	318	* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
bogdanm	0:9b334a45a8ff	319	* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
bogdanm	0:9b334a45a8ff	320	* @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
bogdanm	0:9b334a45a8ff	321	* @retval HAL state
bogdanm	0:9b334a45a8ff	322	*/
bogdanm	0:9b334a45a8ff	323	HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
bogdanm	0:9b334a45a8ff	324	{
bogdanm	0:9b334a45a8ff	325	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Check the parameters */
bogdanm	0:9b334a45a8ff	328	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	329	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
bogdanm	0:9b334a45a8ff	330	assert_param(IS_ADC_CALFACT(CalibrationFactor));
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Process locked */
bogdanm	0:9b334a45a8ff	333	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Verification of hardware constraints before modifying the calibration */
bogdanm	0:9b334a45a8ff	336	/* factors register: ADC must be enabled, no conversion on going. */
bogdanm	0:9b334a45a8ff	337	if ( (ADC_IS_ENABLE(hadc) != RESET) &&
bogdanm	0:9b334a45a8ff	338	(ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	339	{
bogdanm	0:9b334a45a8ff	340	/* Set the selected ADC calibration value */
bogdanm	0:9b334a45a8ff	341	if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	342	{
bogdanm	0:9b334a45a8ff	343	MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
bogdanm	0:9b334a45a8ff	344	}
bogdanm	0:9b334a45a8ff	345	else
bogdanm	0:9b334a45a8ff	346	{
bogdanm	0:9b334a45a8ff	347	MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
bogdanm	0:9b334a45a8ff	348	}
bogdanm	0:9b334a45a8ff	349	}
bogdanm	0:9b334a45a8ff	350	else
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	353	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	356	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	357	}
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/* Process unlocked */
bogdanm	0:9b334a45a8ff	360	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/* Return function status */
bogdanm	0:9b334a45a8ff	363	return tmp_status;
bogdanm	0:9b334a45a8ff	364	}
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/**
bogdanm	0:9b334a45a8ff	369	* @brief Enables ADC, starts conversion of injected group.
bogdanm	0:9b334a45a8ff	370	* @note Interruptions enabled in this function: None.
bogdanm	0:9b334a45a8ff	371	* @note Case of multimode enabled: HAL_ADCEx_InjectedStart() API
bogdanm	0:9b334a45a8ff	372	* must be called for ADC slave first, then ADC master.
bogdanm	0:9b334a45a8ff	373	* For ADC slave, ADC is enabled only (conversion is not started).
bogdanm	0:9b334a45a8ff	374	* For ADC master, ADC is enabled and multimode conversion is started.
bogdanm	0:9b334a45a8ff	375	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	376	* @retval HAL status
bogdanm	0:9b334a45a8ff	377	*/
bogdanm	0:9b334a45a8ff	378	HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	379	{
bogdanm	0:9b334a45a8ff	380	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/* Check the parameters */
bogdanm	0:9b334a45a8ff	383	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
bogdanm	0:9b334a45a8ff	386	{
bogdanm	0:9b334a45a8ff	387	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	388	}
bogdanm	0:9b334a45a8ff	389	else
bogdanm	0:9b334a45a8ff	390	{
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* In case of software trigger detection enabled, JQDIS must be set
bogdanm	0:9b334a45a8ff	393	(which can be done only if ADSTART and JADSTART are both cleared).
bogdanm	0:9b334a45a8ff	394	If JQDIS is not set at that point, returns an error
bogdanm	0:9b334a45a8ff	395	- since software trigger detection is disabled. User needs to
bogdanm	0:9b334a45a8ff	396	resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
bogdanm	0:9b334a45a8ff	397	- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
bogdanm	0:9b334a45a8ff	398	the queue is empty */
bogdanm	0:9b334a45a8ff	399	if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
bogdanm	0:9b334a45a8ff	400	&& (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	403	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/* Process locked */
bogdanm	0:9b334a45a8ff	408	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	411	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	414	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	415	{
bogdanm	0:9b334a45a8ff	416	/* Check if a regular conversion is ongoing */
bogdanm	0:9b334a45a8ff	417	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
bogdanm	0:9b334a45a8ff	418	{
bogdanm	0:9b334a45a8ff	419	/* Reset ADC error code field related to injected conversions only */
bogdanm	0:9b334a45a8ff	420	CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
bogdanm	0:9b334a45a8ff	421	}
bogdanm	0:9b334a45a8ff	422	else
bogdanm	0:9b334a45a8ff	423	{
bogdanm	0:9b334a45a8ff	424	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	425	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	426	}
bogdanm	0:9b334a45a8ff	427	/* Update ADC state */
bogdanm	0:9b334a45a8ff	428	/* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	429	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
bogdanm	0:9b334a45a8ff	432	- by default if ADC is Master or Independent
bogdanm	0:9b334a45a8ff	433	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
bogdanm	0:9b334a45a8ff	434	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	435	{
bogdanm	0:9b334a45a8ff	436	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	441	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	442	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC \| ADC_FLAG_JEOS));
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/* Enable conversion of injected group, if automatic injected conversion */
bogdanm	0:9b334a45a8ff	445	/* is disabled. */
bogdanm	0:9b334a45a8ff	446	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	447	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	448	/* trigger event. */
bogdanm	0:9b334a45a8ff	449	/* Case of multimode enabled: */
bogdanm	0:9b334a45a8ff	450	/* if ADC is slave, */
bogdanm	0:9b334a45a8ff	451	/* - ADC is enabled only (conversion is not started). */
bogdanm	0:9b334a45a8ff	452	/* - if multimode only concerns regular conversion, ADC is enabled */
bogdanm	0:9b334a45a8ff	453	/* and conversion is started. */
bogdanm	0:9b334a45a8ff	454	/* If ADC is master or independent, */
bogdanm	0:9b334a45a8ff	455	/* - ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/* Are injected conversions that of a dual Slave ? */
bogdanm	0:9b334a45a8ff	458	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	459	{
bogdanm	0:9b334a45a8ff	460	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	461	set ADSTART only if JAUTO is cleared */
bogdanm	0:9b334a45a8ff	462	/* Process unlocked */
bogdanm	0:9b334a45a8ff	463	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	464	if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
bogdanm	0:9b334a45a8ff	467	}
bogdanm	0:9b334a45a8ff	468	}
bogdanm	0:9b334a45a8ff	469	else
bogdanm	0:9b334a45a8ff	470	{
bogdanm	0:9b334a45a8ff	471	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	472	ADSTART is not set */
bogdanm	0:9b334a45a8ff	473	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	474	/* Process unlocked */
bogdanm	0:9b334a45a8ff	475	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477	}
bogdanm	0:9b334a45a8ff	478	else
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	/* Process unlocked */
bogdanm	0:9b334a45a8ff	481	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	482	} /* if (tmp_status == HAL_OK) */
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/* Return function status */
bogdanm	0:9b334a45a8ff	486	return tmp_status;
bogdanm	0:9b334a45a8ff	487	} /* if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
bogdanm	0:9b334a45a8ff	488	}
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/**
bogdanm	0:9b334a45a8ff	493	* @brief Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
bogdanm	0:9b334a45a8ff	494	* @note If ADC must be disabled and if regular conversion
bogdanm	0:9b334a45a8ff	495	* is on going, function HAL_ADC_Stop() must be used.
bogdanm	0:9b334a45a8ff	496	* @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
bogdanm	0:9b334a45a8ff	497	* @note In case of multimode enabled, HAL_ADCEx_InjectedStop()
bogdanm	0:9b334a45a8ff	498	* must be called for ADC master first, then ADC slave.
bogdanm	0:9b334a45a8ff	499	* For ADC master, conversion is stopped and ADC is disabled.
bogdanm	0:9b334a45a8ff	500	* For ADC slave, ADC is disabled only (conversion stop of ADC master
bogdanm	0:9b334a45a8ff	501	* has already stopped conversion of ADC slave).
bogdanm	0:9b334a45a8ff	502	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	503	* @retval None
bogdanm	0:9b334a45a8ff	504	*/
bogdanm	0:9b334a45a8ff	505	HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	506	{
bogdanm	0:9b334a45a8ff	507	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Check the parameters */
bogdanm	0:9b334a45a8ff	510	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	/* Process locked */
bogdanm	0:9b334a45a8ff	513	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/* 1. Stop potential conversion on going on injected group only. */
bogdanm	0:9b334a45a8ff	516	tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/* Disable ADC peripheral if injected conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	519	/* and if no conversion on regular group is on-going */
bogdanm	0:9b334a45a8ff	520	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	521	{
bogdanm	0:9b334a45a8ff	522	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
bogdanm	0:9b334a45a8ff	523	{
bogdanm	0:9b334a45a8ff	524	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	525	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	528	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	529	{
bogdanm	0:9b334a45a8ff	530	/* Change ADC state */
bogdanm	0:9b334a45a8ff	531	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	532	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535	/* Conversion on injected group is stopped, but ADC not disabled since */
bogdanm	0:9b334a45a8ff	536	/* conversion on regular group is still running. */
bogdanm	0:9b334a45a8ff	537	else
bogdanm	0:9b334a45a8ff	538	{
bogdanm	0:9b334a45a8ff	539	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	540	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* Process unlocked */
bogdanm	0:9b334a45a8ff	545	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/* Return function status */
bogdanm	0:9b334a45a8ff	548	return tmp_status;
bogdanm	0:9b334a45a8ff	549	}
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553	/**
bogdanm	0:9b334a45a8ff	554	* @brief Wait for injected group conversion to be completed.
bogdanm	0:9b334a45a8ff	555	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	556	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	557	* @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
bogdanm	0:9b334a45a8ff	558	* checked and cleared depending on AUTDLY bit status.
bogdanm	0:9b334a45a8ff	559	* @retval HAL status
bogdanm	0:9b334a45a8ff	560	*/
bogdanm	0:9b334a45a8ff	561	HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	562	{
bogdanm	0:9b334a45a8ff	563	uint32_t tickstart;
bogdanm	0:9b334a45a8ff	564	uint32_t tmp_Flag_End = 0x00;
bogdanm	0:9b334a45a8ff	565	ADC_TypeDef *tmpADC_Master;
bogdanm	0:9b334a45a8ff	566	uint32_t tmp_cfgr = 0x00;
bogdanm	0:9b334a45a8ff	567	uint32_t tmp_cfgr_jqm_autdly = 0x00;
bogdanm	0:9b334a45a8ff	568	uint32_t tmp_jeos_raised = 0x01; /* by default, assume that JEOS is set,
bogdanm	0:9b334a45a8ff	569	tmp_jeos_raised will be corrected
bogdanm	0:9b334a45a8ff	570	accordingly during API execution */
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/* Check the parameters */
bogdanm	0:9b334a45a8ff	573	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/* If end of sequence selected */
bogdanm	0:9b334a45a8ff	576	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	tmp_Flag_End = ADC_FLAG_JEOS;
bogdanm	0:9b334a45a8ff	579	}
bogdanm	0:9b334a45a8ff	580	else /* end of conversion selected */
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	tmp_Flag_End = ADC_FLAG_JEOC;
bogdanm	0:9b334a45a8ff	583	}
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	/* Get timeout */
bogdanm	0:9b334a45a8ff	586	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	/* Wait until End of Conversion or Sequence flag is raised */
bogdanm	0:9b334a45a8ff	589	while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	592	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	595	{
bogdanm	0:9b334a45a8ff	596	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	597	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Process unlocked */
bogdanm	0:9b334a45a8ff	600	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	603	}
bogdanm	0:9b334a45a8ff	604	}
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Next, to clear the polled flag as well as to update the handle State,
bogdanm	0:9b334a45a8ff	608	JEOS is checked and the relevant configuration registers are retrieved.
bogdanm	0:9b334a45a8ff	609	JQM, JAUTO and CONT bits will have to be read for the State update,
bogdanm	0:9b334a45a8ff	610	AUTDLY for JEOS clearing. */
bogdanm	0:9b334a45a8ff	611	/* 1. Check whether or not JEOS is set */
bogdanm	0:9b334a45a8ff	612	if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
bogdanm	0:9b334a45a8ff	613	{
bogdanm	0:9b334a45a8ff	614	tmp_jeos_raised = 0;
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616	/* 2. Check whether or not hadc is the handle of a Slave ADC with dual
bogdanm	0:9b334a45a8ff	617	injected conversions enabled. */
bogdanm	0:9b334a45a8ff	618	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	621	check JQM and AUTDLY bits directly in ADC CFGR register */
bogdanm	0:9b334a45a8ff	622	tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	623	}
bogdanm	0:9b334a45a8ff	624	else
bogdanm	0:9b334a45a8ff	625	{
bogdanm	0:9b334a45a8ff	626	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	627	need to check JQM and AUTDLY bits of Master ADC CFGR register */
bogdanm	0:9b334a45a8ff	628	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	629	tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	630	}
bogdanm	0:9b334a45a8ff	631	/* 3. Check whether or not hadc is the handle of a Slave ADC with dual
bogdanm	0:9b334a45a8ff	632	regular conversions enabled. */
bogdanm	0:9b334a45a8ff	633	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	634	{
bogdanm	0:9b334a45a8ff	635	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
bogdanm	0:9b334a45a8ff	636	check JAUTO and CONT bits directly in ADC CFGR register */
bogdanm	0:9b334a45a8ff	637	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639	else
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
bogdanm	0:9b334a45a8ff	642	check JAUTO and CONT bits of Master ADC CFGR register */
bogdanm	0:9b334a45a8ff	643	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	644	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	645	}
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	/* Clear polled flag */
bogdanm	0:9b334a45a8ff	650	if (tmp_Flag_End == ADC_FLAG_JEOS)
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	/* Clear end of sequence JEOS flag of injected group if low power feature */
bogdanm	0:9b334a45a8ff	653	/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
bogdanm	0:9b334a45a8ff	654	/* For injected groups, no new conversion will start before JEOS is */
bogdanm	0:9b334a45a8ff	655	/* cleared. */
bogdanm	0:9b334a45a8ff	656	/* Note that 1. reading ADCx_JDRy clears JEOC. */
bogdanm	0:9b334a45a8ff	657	/* 2. in MultiMode with dual injected conversions enabled, */
bogdanm	0:9b334a45a8ff	658	/* Master AUTDLY bit must be checked */
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
bogdanm	0:9b334a45a8ff	661	{
bogdanm	0:9b334a45a8ff	662	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	}
bogdanm	0:9b334a45a8ff	665	else
bogdanm	0:9b334a45a8ff	666	{
bogdanm	0:9b334a45a8ff	667	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	672	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
bogdanm	0:9b334a45a8ff	673	/* Are injected conversions over ? This is the case if JEOS is set AND
bogdanm	0:9b334a45a8ff	674	- injected conversions are software-triggered when injected queue management is disabled
bogdanm	0:9b334a45a8ff	675	OR
bogdanm	0:9b334a45a8ff	676	- auto-injection is enabled, continuous mode is disabled,
bogdanm	0:9b334a45a8ff	677	and regular conversions are software-triggered */
bogdanm	0:9b334a45a8ff	678
bogdanm	0:9b334a45a8ff	679	if (tmp_jeos_raised)
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))
bogdanm	0:9b334a45a8ff	682	&& (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) &&
bogdanm	0:9b334a45a8ff	683	(ADC_IS_SOFTWARE_START_REGULAR(hadc))) ))
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	686	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	687	/* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	688	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
bogdanm	0:9b334a45a8ff	689	{
bogdanm	0:9b334a45a8ff	690	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	691	}
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Return API HAL status */
bogdanm	0:9b334a45a8ff	698	return HAL_OK;
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	/**
bogdanm	0:9b334a45a8ff	704	* @brief Enable ADC, start conversion of injected group with interruption.
bogdanm	0:9b334a45a8ff	705	* @note Interruptions enabled in this function according to initialization
bogdanm	0:9b334a45a8ff	706	* setting : JEOC (end of conversion) or JEOS (end of sequence)
bogdanm	0:9b334a45a8ff	707	* @note Case of multimode enabled: HAL_ADCEx_InjectedStart_IT() API
bogdanm	0:9b334a45a8ff	708	* must be called for ADC slave first, then ADC master.
bogdanm	0:9b334a45a8ff	709	* For ADC slave, ADC is enabled only (conversion is not started).
bogdanm	0:9b334a45a8ff	710	* For ADC master, ADC is enabled and multimode conversion is started.
bogdanm	0:9b334a45a8ff	711	* @param hadc: ADC handle.
bogdanm	0:9b334a45a8ff	712	* @retval HAL status.
bogdanm	0:9b334a45a8ff	713	*/
bogdanm	0:9b334a45a8ff	714	HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	715	{
bogdanm	0:9b334a45a8ff	716	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Check the parameters */
bogdanm	0:9b334a45a8ff	719	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725	else
bogdanm	0:9b334a45a8ff	726	{
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/* In case of software trigger detection enabled, JQDIS must be set
bogdanm	0:9b334a45a8ff	729	(which can be done only if ADSTART and JADSTART are both cleared).
bogdanm	0:9b334a45a8ff	730	If JQDIS is not set at that point, returns an error
bogdanm	0:9b334a45a8ff	731	- since software trigger detection is disabled. User needs to
bogdanm	0:9b334a45a8ff	732	resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
bogdanm	0:9b334a45a8ff	733	- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
bogdanm	0:9b334a45a8ff	734	the queue is empty */
bogdanm	0:9b334a45a8ff	735	if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
bogdanm	0:9b334a45a8ff	736	&& (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
bogdanm	0:9b334a45a8ff	737	{
bogdanm	0:9b334a45a8ff	738	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	739	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	740	}
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	/* Process locked */
bogdanm	0:9b334a45a8ff	743	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	746	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	749	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	750	{
bogdanm	0:9b334a45a8ff	751	/* Check if a regular conversion is ongoing */
bogdanm	0:9b334a45a8ff	752	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
bogdanm	0:9b334a45a8ff	753	{
bogdanm	0:9b334a45a8ff	754	/* Reset ADC error code field related to injected conversions only */
bogdanm	0:9b334a45a8ff	755	CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
bogdanm	0:9b334a45a8ff	756	}
bogdanm	0:9b334a45a8ff	757	else
bogdanm	0:9b334a45a8ff	758	{
bogdanm	0:9b334a45a8ff	759	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	760	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	761	}
bogdanm	0:9b334a45a8ff	762	/* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	763	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
bogdanm	0:9b334a45a8ff	766	- by default if ADC is Master or Independent
bogdanm	0:9b334a45a8ff	767	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
bogdanm	0:9b334a45a8ff	768	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	769	{
bogdanm	0:9b334a45a8ff	770	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	771	}
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	774	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	775	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC \| ADC_FLAG_JEOS));
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/* Enable ADC Injected context queue overflow interrupt if this feature */
bogdanm	0:9b334a45a8ff	778	/* is enabled. */
bogdanm	0:9b334a45a8ff	779	if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	__HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/* Enable ADC end of conversion interrupt */
bogdanm	0:9b334a45a8ff	785	switch(hadc->Init.EOCSelection)
bogdanm	0:9b334a45a8ff	786	{
bogdanm	0:9b334a45a8ff	787	case ADC_EOC_SEQ_CONV:
bogdanm	0:9b334a45a8ff	788	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	789	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	790	break;
bogdanm	0:9b334a45a8ff	791	/* case ADC_EOC_SINGLE_CONV */
bogdanm	0:9b334a45a8ff	792	default:
bogdanm	0:9b334a45a8ff	793	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	794	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	795	break;
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/* Enable conversion of injected group, if automatic injected conversion */
bogdanm	0:9b334a45a8ff	799	/* is disabled. */
bogdanm	0:9b334a45a8ff	800	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	801	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	802	/* trigger event. */
bogdanm	0:9b334a45a8ff	803	/* Case of multimode enabled: */
bogdanm	0:9b334a45a8ff	804	/* if ADC is slave, */
bogdanm	0:9b334a45a8ff	805	/* - ADC is enabled only (conversion is not started), */
bogdanm	0:9b334a45a8ff	806	/* - if multimode only concerns regular conversion, ADC is enabled */
bogdanm	0:9b334a45a8ff	807	/* and conversion is started. */
bogdanm	0:9b334a45a8ff	808	/* If ADC is master or independent, */
bogdanm	0:9b334a45a8ff	809	/* - ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Are injected conversions that of a dual Slave ? */
bogdanm	0:9b334a45a8ff	812	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	815	set ADSTART only if JAUTO is cleared */
bogdanm	0:9b334a45a8ff	816	/* Process unlocked */
bogdanm	0:9b334a45a8ff	817	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	818	if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
bogdanm	0:9b334a45a8ff	819	{
bogdanm	0:9b334a45a8ff	820	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
bogdanm	0:9b334a45a8ff	821	}
bogdanm	0:9b334a45a8ff	822	}
bogdanm	0:9b334a45a8ff	823	else
bogdanm	0:9b334a45a8ff	824	{
bogdanm	0:9b334a45a8ff	825	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	826	ADSTART is not set */
bogdanm	0:9b334a45a8ff	827	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	828	/* Process unlocked */
bogdanm	0:9b334a45a8ff	829	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	830	}
bogdanm	0:9b334a45a8ff	831	}
bogdanm	0:9b334a45a8ff	832	else
bogdanm	0:9b334a45a8ff	833	{
bogdanm	0:9b334a45a8ff	834	/* Process unlocked */
bogdanm	0:9b334a45a8ff	835	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/* Return function status */
bogdanm	0:9b334a45a8ff	839	return tmp_status;
bogdanm	0:9b334a45a8ff	840	}
bogdanm	0:9b334a45a8ff	841	}
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/**
bogdanm	0:9b334a45a8ff	846	* @brief Stop conversion of injected channels, disable interruption of end-of-conversion.
bogdanm	0:9b334a45a8ff	847	* @note Disable ADC peripheral if no regular conversion
bogdanm	0:9b334a45a8ff	848	* is on going.
bogdanm	0:9b334a45a8ff	849	* @note If ADC must be disabled and if regular conversion
bogdanm	0:9b334a45a8ff	850	* is on going, function HAL_ADC_Stop must be used first.
bogdanm	0:9b334a45a8ff	851	* @note Case of multimode enabled: HAL_ADCEx_InjectedStop_IT() API
bogdanm	0:9b334a45a8ff	852	* must be called for ADC master first, then ADC slave.
bogdanm	0:9b334a45a8ff	853	* For ADC master, conversion is stopped and ADC is disabled.
bogdanm	0:9b334a45a8ff	854	* For ADC slave, ADC is disabled only (conversion stop of ADC master
bogdanm	0:9b334a45a8ff	855	* has already stopped conversion of ADC slave).
bogdanm	0:9b334a45a8ff	856	* @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
bogdanm	0:9b334a45a8ff	857	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	858	* @retval None
bogdanm	0:9b334a45a8ff	859	*/
bogdanm	0:9b334a45a8ff	860	HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Check the parameters */
bogdanm	0:9b334a45a8ff	865	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/* Process locked */
bogdanm	0:9b334a45a8ff	868	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/* 1. Stop potential conversion on going on injected group only. */
bogdanm	0:9b334a45a8ff	871	tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	/* Disable ADC peripheral if injected conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	874	/* and if no conversion on the other group (regular group) is intended to */
bogdanm	0:9b334a45a8ff	875	/* continue. */
bogdanm	0:9b334a45a8ff	876	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	877	{
bogdanm	0:9b334a45a8ff	878	/* Disable ADC end of conversion interrupt for injected channels */
bogdanm	0:9b334a45a8ff	879	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC \| ADC_IT_JEOS \| ADC_FLAG_JQOVF));
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	884	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	887	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	888	{
bogdanm	0:9b334a45a8ff	889	/* Change ADC state */
bogdanm	0:9b334a45a8ff	890	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	891	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893	}
bogdanm	0:9b334a45a8ff	894	/* Conversion on injected group is stopped, but ADC not disabled since */
bogdanm	0:9b334a45a8ff	895	/* conversion on regular group is still running. */
bogdanm	0:9b334a45a8ff	896	else
bogdanm	0:9b334a45a8ff	897	{
bogdanm	0:9b334a45a8ff	898	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	899	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	900	}
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/* Process unlocked */
bogdanm	0:9b334a45a8ff	904	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	/* Return function status */
bogdanm	0:9b334a45a8ff	907	return tmp_status;
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	/**
bogdanm	0:9b334a45a8ff	913	* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
bogdanm	0:9b334a45a8ff	914	* @note Multimode must have been previously configured using
bogdanm	0:9b334a45a8ff	915	* HAL_ADCEx_MultiModeConfigChannel() function.
bogdanm	0:9b334a45a8ff	916	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	917	* overrun, DMA half transfer, DMA transfer complete.
bogdanm	0:9b334a45a8ff	918	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	919	* @note State field of Slave ADC handle is not updated in this configuration:
bogdanm	0:9b334a45a8ff	920	* user should not rely on it for information related to Slave regular
bogdanm	0:9b334a45a8ff	921	* conversions.
bogdanm	0:9b334a45a8ff	922	* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm	0:9b334a45a8ff	923	* @param pData: Destination Buffer address.
bogdanm	0:9b334a45a8ff	924	* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
bogdanm	0:9b334a45a8ff	925	* @retval None
bogdanm	0:9b334a45a8ff	926	*/
bogdanm	0:9b334a45a8ff	927	HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	928	{
bogdanm	0:9b334a45a8ff	929	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	930	ADC_HandleTypeDef tmphadcSlave;
bogdanm	0:9b334a45a8ff	931	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	/* Check the parameters */
bogdanm	0:9b334a45a8ff	934	assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	935	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	936	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	937	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	940	{
bogdanm	0:9b334a45a8ff	941	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943	else
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	/* Process locked */
bogdanm	0:9b334a45a8ff	946	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm	0:9b334a45a8ff	949	ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	if (tmphadcSlave.Instance == NULL)
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	954	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/* Process unlocked */
bogdanm	0:9b334a45a8ff	957	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Enable the ADC peripherals: master and slave (in case if not already */
bogdanm	0:9b334a45a8ff	964	/* enabled previously) */
bogdanm	0:9b334a45a8ff	965	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	966	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	967	{
bogdanm	0:9b334a45a8ff	968	tmp_status = ADC_Enable(&tmphadcSlave);
bogdanm	0:9b334a45a8ff	969	}
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	/* Start multimode conversion of ADCs pair */
bogdanm	0:9b334a45a8ff	972	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	973	{
bogdanm	0:9b334a45a8ff	974	/* Update Master State */
bogdanm	0:9b334a45a8ff	975	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	976	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	980	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	984	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	987	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	990	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/* Pointer to the common control register */
bogdanm	0:9b334a45a8ff	993	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
bogdanm	0:9b334a45a8ff	997	/* start (in case of SW start): */
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1000	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	1001	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Enable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1004	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	/* Start the DMA channel */
bogdanm	0:9b334a45a8ff	1007	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1010	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1011	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1012	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1013	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1014	/* trigger event. */
bogdanm	0:9b334a45a8ff	1015	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	}
bogdanm	0:9b334a45a8ff	1018	else
bogdanm	0:9b334a45a8ff	1019	{
bogdanm	0:9b334a45a8ff	1020	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1021	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	/* Return function status */
bogdanm	0:9b334a45a8ff	1025	return tmp_status;
bogdanm	0:9b334a45a8ff	1026	}
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	/**
bogdanm	0:9b334a45a8ff	1030	* @brief Stop MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
bogdanm	0:9b334a45a8ff	1031	* @note MultiMode is kept enabled after this function. MultiMode DMA bits
bogdanm	0:9b334a45a8ff	1032	* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
bogdanm	0:9b334a45a8ff	1033	* MultiMode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
bogdanm	0:9b334a45a8ff	1034	* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
bogdanm	0:9b334a45a8ff	1035	* resort to HAL_ADCEx_DisableMultiMode() API.
bogdanm	0:9b334a45a8ff	1036	* @note In case of DMA configured in circular mode, function
bogdanm	0:9b334a45a8ff	1037	* HAL_ADC_Stop_DMA() must be called after this function with handle of
bogdanm	0:9b334a45a8ff	1038	* ADC slave, to properly disable the DMA channel.
bogdanm	0:9b334a45a8ff	1039	* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm	0:9b334a45a8ff	1040	* @retval None
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1045	uint32_t tickstart;
bogdanm	0:9b334a45a8ff	1046	ADC_HandleTypeDef tmphadcSlave;
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1049	assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	/* Process locked */
bogdanm	0:9b334a45a8ff	1052	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	/* 1. Stop potential multimode conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1056	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	1059	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	/* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm	0:9b334a45a8ff	1062	ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	if (tmphadcSlave.Instance == NULL)
bogdanm	0:9b334a45a8ff	1065	{
bogdanm	0:9b334a45a8ff	1066	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1067	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1070	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1073	}
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/* Procedure to disable the ADC peripheral: wait for conversions */
bogdanm	0:9b334a45a8ff	1076	/* effectively stopped (ADC master and ADC slave), then disable ADC */
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
bogdanm	0:9b334a45a8ff	1079	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) \|\|
bogdanm	0:9b334a45a8ff	1082	ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
bogdanm	0:9b334a45a8ff	1083	{
bogdanm	0:9b334a45a8ff	1084	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
bogdanm	0:9b334a45a8ff	1085	{
bogdanm	0:9b334a45a8ff	1086	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1087	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1090	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094	}
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/* Disable the DMA channel (in case of DMA in circular mode or stop */
bogdanm	0:9b334a45a8ff	1097	/* while DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1098	/* Note: DMA channel of ADC slave should be stopped after this function */
bogdanm	0:9b334a45a8ff	1099	/* with HAL_ADC_Stop_DMA() API. */
bogdanm	0:9b334a45a8ff	1100	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1103	if (tmp_status == HAL_ERROR)
bogdanm	0:9b334a45a8ff	1104	{
bogdanm	0:9b334a45a8ff	1105	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1106	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	1107	}
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Disable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1110	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* 2. Disable the ADC peripherals: master and slave */
bogdanm	0:9b334a45a8ff	1115	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
bogdanm	0:9b334a45a8ff	1116	/* memory a potential failing status. */
bogdanm	0:9b334a45a8ff	1117	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	/* Check if ADC are effectively disabled */
bogdanm	0:9b334a45a8ff	1120	if ((ADC_Disable(hadc) == HAL_OK) &&
bogdanm	0:9b334a45a8ff	1121	(ADC_Disable(&tmphadcSlave) == HAL_OK) )
bogdanm	0:9b334a45a8ff	1122	{
bogdanm	0:9b334a45a8ff	1123	tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1124	}
bogdanm	0:9b334a45a8ff	1125	}
bogdanm	0:9b334a45a8ff	1126	else
bogdanm	0:9b334a45a8ff	1127	{
bogdanm	0:9b334a45a8ff	1128	ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1129	ADC_Disable(&tmphadcSlave);
bogdanm	0:9b334a45a8ff	1130	}
bogdanm	0:9b334a45a8ff	1131	/* Change ADC state (ADC master) */
bogdanm	0:9b334a45a8ff	1132	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1133	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1138	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/* Return function status */
bogdanm	0:9b334a45a8ff	1141	return tmp_status;
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	/**
bogdanm	0:9b334a45a8ff	1146	* @brief Return the last ADC Master and Slave regular conversions results when in MultiMode configuration.
bogdanm	0:9b334a45a8ff	1147	* @param hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
bogdanm	0:9b334a45a8ff	1148	* @retval The converted data values.
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1155	assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/* Pointer to the common control register */
bogdanm	0:9b334a45a8ff	1158	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/* Return the multi mode conversion value */
bogdanm	0:9b334a45a8ff	1161	return tmpADC_Common->CDR;
bogdanm	0:9b334a45a8ff	1162	}
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/**
bogdanm	0:9b334a45a8ff	1166	* @brief Get ADC injected group conversion result.
bogdanm	0:9b334a45a8ff	1167	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1168	* @param InjectedRank: the converted ADC injected rank.
bogdanm	0:9b334a45a8ff	1169	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1170	* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
bogdanm	0:9b334a45a8ff	1171	* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
bogdanm	0:9b334a45a8ff	1172	* @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
bogdanm	0:9b334a45a8ff	1173	* @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
bogdanm	0:9b334a45a8ff	1174	* @note Reading JDRy register automatically clears JEOC flag. To reset JEOS
bogdanm	0:9b334a45a8ff	1175	* flag the user must resort to the macro
bogdanm	0:9b334a45a8ff	1176	* __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).
bogdanm	0:9b334a45a8ff	1177	* @retval None
bogdanm	0:9b334a45a8ff	1178	*/
bogdanm	0:9b334a45a8ff	1179	uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
bogdanm	0:9b334a45a8ff	1180	{
bogdanm	0:9b334a45a8ff	1181	uint32_t tmp_jdr = 0;
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1184	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1185	assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/* Get ADC converted value */
bogdanm	0:9b334a45a8ff	1189	switch(InjectedRank)
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	case ADC_INJECTED_RANK_4:
bogdanm	0:9b334a45a8ff	1192	tmp_jdr = hadc->Instance->JDR4;
bogdanm	0:9b334a45a8ff	1193	break;
bogdanm	0:9b334a45a8ff	1194	case ADC_INJECTED_RANK_3:
bogdanm	0:9b334a45a8ff	1195	tmp_jdr = hadc->Instance->JDR3;
bogdanm	0:9b334a45a8ff	1196	break;
bogdanm	0:9b334a45a8ff	1197	case ADC_INJECTED_RANK_2:
bogdanm	0:9b334a45a8ff	1198	tmp_jdr = hadc->Instance->JDR2;
bogdanm	0:9b334a45a8ff	1199	break;
bogdanm	0:9b334a45a8ff	1200	case ADC_INJECTED_RANK_1:
bogdanm	0:9b334a45a8ff	1201	default:
bogdanm	0:9b334a45a8ff	1202	tmp_jdr = hadc->Instance->JDR1;
bogdanm	0:9b334a45a8ff	1203	break;
bogdanm	0:9b334a45a8ff	1204	}
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/* Return ADC converted value */
bogdanm	0:9b334a45a8ff	1207	return tmp_jdr;
bogdanm	0:9b334a45a8ff	1208	}
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/**
bogdanm	0:9b334a45a8ff	1211	* @brief Injected conversion complete callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	1212	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1213	* @retval None
bogdanm	0:9b334a45a8ff	1214	*/
bogdanm	0:9b334a45a8ff	1215	__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1218	function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1219	*/
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/**
bogdanm	0:9b334a45a8ff	1224	* @brief Injected context queue overflow callback.
bogdanm	0:9b334a45a8ff	1225	* @note This callback is called if injected context queue is enabled
bogdanm	0:9b334a45a8ff	1226	(parameter "QueueInjectedContext" in injected channel configuration)
bogdanm	0:9b334a45a8ff	1227	and if a new injected context is set when queue is full (maximum 2
bogdanm	0:9b334a45a8ff	1228	contexts).
bogdanm	0:9b334a45a8ff	1229	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1230	* @retval None
bogdanm	0:9b334a45a8ff	1231	*/
bogdanm	0:9b334a45a8ff	1232	__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1235	function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1236	*/
bogdanm	0:9b334a45a8ff	1237	}
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	/**
bogdanm	0:9b334a45a8ff	1240	* @brief Analog watchdog 2 callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	1241	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1242	* @retval None
bogdanm	0:9b334a45a8ff	1243	*/
bogdanm	0:9b334a45a8ff	1244	__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1245	{
bogdanm	0:9b334a45a8ff	1246	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1247	function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1248	*/
bogdanm	0:9b334a45a8ff	1249	}
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/**
bogdanm	0:9b334a45a8ff	1252	* @brief Analog watchdog 3 callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	1253	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1254	* @retval None
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256	__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1257	{
bogdanm	0:9b334a45a8ff	1258	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1259	function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1260	*/
bogdanm	0:9b334a45a8ff	1261	}
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/**
bogdanm	0:9b334a45a8ff	1265	* @brief End Of Sampling callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	1266	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1267	* @retval None
bogdanm	0:9b334a45a8ff	1268	*/
bogdanm	0:9b334a45a8ff	1269	__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1270	{
bogdanm	0:9b334a45a8ff	1271	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1272	function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1273	*/
bogdanm	0:9b334a45a8ff	1274	}
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	/**
bogdanm	0:9b334a45a8ff	1279	* @brief Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
bogdanm	0:9b334a45a8ff	1280	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1281	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1282	*/
bogdanm	0:9b334a45a8ff	1283	HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1284	{
bogdanm	0:9b334a45a8ff	1285	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1288	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	/* Process locked */
bogdanm	0:9b334a45a8ff	1291	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* 1. Stop potential regular conversion on going */
bogdanm	0:9b334a45a8ff	1294	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* Disable ADC peripheral if regular conversions are effectively stopped
bogdanm	0:9b334a45a8ff	1297	and if no injected conversions are on-going */
bogdanm	0:9b334a45a8ff	1298	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1299	{
bogdanm	0:9b334a45a8ff	1300	/* Clear HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1301	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1304	{
bogdanm	0:9b334a45a8ff	1305	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1306	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1309	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1310	{
bogdanm	0:9b334a45a8ff	1311	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1312	/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1313	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1314	}
bogdanm	0:9b334a45a8ff	1315	}
bogdanm	0:9b334a45a8ff	1316	/* Conversion on injected group is stopped, but ADC not disabled since */
bogdanm	0:9b334a45a8ff	1317	/* conversion on regular group is still running. */
bogdanm	0:9b334a45a8ff	1318	else
bogdanm	0:9b334a45a8ff	1319	{
bogdanm	0:9b334a45a8ff	1320	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1321	}
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1325	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Return function status */
bogdanm	0:9b334a45a8ff	1328	return tmp_status;
bogdanm	0:9b334a45a8ff	1329	}
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/**
bogdanm	0:9b334a45a8ff	1333	* @brief Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
bogdanm	0:9b334a45a8ff	1334	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1335	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1336	*/
bogdanm	0:9b334a45a8ff	1337	HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1342	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1343
bogdanm	0:9b334a45a8ff	1344	/* Process locked */
bogdanm	0:9b334a45a8ff	1345	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* 1. Stop potential regular conversion on going */
bogdanm	0:9b334a45a8ff	1348	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Disable ADC peripheral if conversions are effectively stopped
bogdanm	0:9b334a45a8ff	1351	and if no injected conversion is on-going */
bogdanm	0:9b334a45a8ff	1352	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	/* Clear HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1355	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Disable all regular-related interrupts */
bogdanm	0:9b334a45a8ff	1358	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	/* 2. Disable ADC peripheral if no injected conversions are on-going */
bogdanm	0:9b334a45a8ff	1361	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1364	/* if no issue reported */
bogdanm	0:9b334a45a8ff	1365	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1366	{
bogdanm	0:9b334a45a8ff	1367	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1368	/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1369	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1370	}
bogdanm	0:9b334a45a8ff	1371	}
bogdanm	0:9b334a45a8ff	1372	else
bogdanm	0:9b334a45a8ff	1373	{
bogdanm	0:9b334a45a8ff	1374	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1379	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	/* Return function status */
bogdanm	0:9b334a45a8ff	1382	return tmp_status;
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/**
bogdanm	0:9b334a45a8ff	1387	* @brief Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
bogdanm	0:9b334a45a8ff	1388	* @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
bogdanm	0:9b334a45a8ff	1389	* For multimode, use HAL_ADCEx_RegularMultiModeStop_DMA() API.
bogdanm	0:9b334a45a8ff	1390	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1391	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1392	*/
bogdanm	0:9b334a45a8ff	1393	HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1398	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	/* Process locked */
bogdanm	0:9b334a45a8ff	1401	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/* 1. Stop potential regular conversion on going */
bogdanm	0:9b334a45a8ff	1404	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* Disable ADC peripheral if conversions are effectively stopped
bogdanm	0:9b334a45a8ff	1407	and if no injected conversion is on-going */
bogdanm	0:9b334a45a8ff	1408	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1409	{
bogdanm	0:9b334a45a8ff	1410	/* Clear HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1411	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
bogdanm	0:9b334a45a8ff	1414	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm	0:9b334a45a8ff	1417	/* while DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1418	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1419
bogdanm	0:9b334a45a8ff	1420	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1421	if (tmp_status != HAL_OK)
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1424	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	1425	}
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	/* Disable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1428	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1431	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
bogdanm	0:9b334a45a8ff	1432	/* memory a potential failing status. */
bogdanm	0:9b334a45a8ff	1433	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1434	{
bogdanm	0:9b334a45a8ff	1435	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1436	{
bogdanm	0:9b334a45a8ff	1437	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1438	}
bogdanm	0:9b334a45a8ff	1439	else
bogdanm	0:9b334a45a8ff	1440	{
bogdanm	0:9b334a45a8ff	1441	ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1442	}
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1445	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1446	{
bogdanm	0:9b334a45a8ff	1447	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1448	/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1449	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451	}
bogdanm	0:9b334a45a8ff	1452	else
bogdanm	0:9b334a45a8ff	1453	{
bogdanm	0:9b334a45a8ff	1454	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1455	}
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1459	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Return function status */
bogdanm	0:9b334a45a8ff	1462	return tmp_status;
bogdanm	0:9b334a45a8ff	1463	}
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/**
bogdanm	0:9b334a45a8ff	1468	* @brief Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
bogdanm	0:9b334a45a8ff	1469	* @note MultiMode is kept enabled after this function. MultiMode DMA bits
bogdanm	0:9b334a45a8ff	1470	* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
bogdanm	0:9b334a45a8ff	1471	* MultiMode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
bogdanm	0:9b334a45a8ff	1472	* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
bogdanm	0:9b334a45a8ff	1473	* resort to HAL_ADCEx_DisableMultiMode() API.
bogdanm	0:9b334a45a8ff	1474	* @note In case of DMA configured in circular mode, function
bogdanm	0:9b334a45a8ff	1475	* HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
bogdanm	0:9b334a45a8ff	1476	* ADC slave, to properly disable the DMA channel.
bogdanm	0:9b334a45a8ff	1477	* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm	0:9b334a45a8ff	1478	* @retval None
bogdanm	0:9b334a45a8ff	1479	*/
bogdanm	0:9b334a45a8ff	1480	HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1481	{
bogdanm	0:9b334a45a8ff	1482	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1483	uint32_t tickstart;
bogdanm	0:9b334a45a8ff	1484	ADC_HandleTypeDef tmphadcSlave;
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1487	assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/* Process locked */
bogdanm	0:9b334a45a8ff	1490	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492
bogdanm	0:9b334a45a8ff	1493	/* 1. Stop potential multimode conversion on going, on regular groups */
bogdanm	0:9b334a45a8ff	1494	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	1497	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1498	{
bogdanm	0:9b334a45a8ff	1499	/* Clear HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1500	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	/* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm	0:9b334a45a8ff	1503	ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	if (tmphadcSlave.Instance == NULL)
bogdanm	0:9b334a45a8ff	1506	{
bogdanm	0:9b334a45a8ff	1507	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1508	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1509
bogdanm	0:9b334a45a8ff	1510	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1511	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1514	}
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	/* Procedure to disable the ADC peripheral: wait for conversions */
bogdanm	0:9b334a45a8ff	1517	/* effectively stopped (ADC master and ADC slave), then disable ADC */
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	/* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
bogdanm	0:9b334a45a8ff	1520	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) \|\|
bogdanm	0:9b334a45a8ff	1523	ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
bogdanm	0:9b334a45a8ff	1524	{
bogdanm	0:9b334a45a8ff	1525	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
bogdanm	0:9b334a45a8ff	1526	{
bogdanm	0:9b334a45a8ff	1527	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1528	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1531	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1534	}
bogdanm	0:9b334a45a8ff	1535	}
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	/* Disable the DMA channel (in case of DMA in circular mode or stop */
bogdanm	0:9b334a45a8ff	1538	/* while DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1539	/* Note: DMA channel of ADC slave should be stopped after this function */
bogdanm	0:9b334a45a8ff	1540	/* with HAL_ADCEx_RegularStop_DMA() API. */
bogdanm	0:9b334a45a8ff	1541	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1544	if (tmp_status != HAL_OK)
bogdanm	0:9b334a45a8ff	1545	{
bogdanm	0:9b334a45a8ff	1546	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1547	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	1548	}
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	/* Disable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1551	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/* 2. Disable the ADC peripherals: master and slave if no injected */
bogdanm	0:9b334a45a8ff	1556	/* conversion is on-going. */
bogdanm	0:9b334a45a8ff	1557	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
bogdanm	0:9b334a45a8ff	1558	/* memory a potential failing status. */
bogdanm	0:9b334a45a8ff	1559	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1560	{
bogdanm	0:9b334a45a8ff	1561	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1562	{
bogdanm	0:9b334a45a8ff	1563	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1564	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1565	{
bogdanm	0:9b334a45a8ff	1566	if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
bogdanm	0:9b334a45a8ff	1567	{
bogdanm	0:9b334a45a8ff	1568	tmp_status = ADC_Disable(&tmphadcSlave);
bogdanm	0:9b334a45a8ff	1569	}
bogdanm	0:9b334a45a8ff	1570	}
bogdanm	0:9b334a45a8ff	1571	}
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1574	{
bogdanm	0:9b334a45a8ff	1575	/* Both Master and Slave ADC's could be disabled. Update Master State */
bogdanm	0:9b334a45a8ff	1576	/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1577	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1578	}
bogdanm	0:9b334a45a8ff	1579	else
bogdanm	0:9b334a45a8ff	1580	{
bogdanm	0:9b334a45a8ff	1581	/* injected (Master or Slave) conversions are still on-going,
bogdanm	0:9b334a45a8ff	1582	no Master State change */
bogdanm	0:9b334a45a8ff	1583	}
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	}
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	}
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1592	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/* Return function status */
bogdanm	0:9b334a45a8ff	1595	return tmp_status;
bogdanm	0:9b334a45a8ff	1596	}
bogdanm	0:9b334a45a8ff	1597
bogdanm	0:9b334a45a8ff	1598	/**
bogdanm	0:9b334a45a8ff	1599	* @}
bogdanm	0:9b334a45a8ff	1600	*/
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1603	* @brief Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1604	*
bogdanm	0:9b334a45a8ff	1605	@verbatim
bogdanm	0:9b334a45a8ff	1606	===============================================================================
bogdanm	0:9b334a45a8ff	1607	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1608	===============================================================================
bogdanm	0:9b334a45a8ff	1609	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1610	(+) Configure channels on injected group
bogdanm	0:9b334a45a8ff	1611	(+) Configure MultiMode
bogdanm	0:9b334a45a8ff	1612	(+) Enable or Disable Injected Queue
bogdanm	0:9b334a45a8ff	1613	(+) Disable ADC voltage regulator
bogdanm	0:9b334a45a8ff	1614	(+) Enter ADC deep-power-down mode
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	@endverbatim
bogdanm	0:9b334a45a8ff	1618	* @{
bogdanm	0:9b334a45a8ff	1619	*/
bogdanm	0:9b334a45a8ff	1620
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/**
bogdanm	0:9b334a45a8ff	1623	* @brief Configure the ADC injected group and the selected channel to be linked to the injected group.
bogdanm	0:9b334a45a8ff	1624	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	1625	* This function initializes injected group, consecutive calls to this
bogdanm	0:9b334a45a8ff	1626	* function can be used to reconfigure some parameters of structure
bogdanm	0:9b334a45a8ff	1627	* "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
bogdanm	0:9b334a45a8ff	1628	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	1629	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	1630	* "ADC_InjectionConfTypeDef".
bogdanm	0:9b334a45a8ff	1631	* @note In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor),
bogdanm	0:9b334a45a8ff	1632	* The internal paths can be disabled using function HAL_ADC_DeInit().
bogdanm	0:9b334a45a8ff	1633	* @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
bogdanm	0:9b334a45a8ff	1634	* be used.
bogdanm	0:9b334a45a8ff	1635	* @note Caution: For Injected Context Queue use, a context must be fully
bogdanm	0:9b334a45a8ff	1636	* defined before start of injected conversion. All channels are configured
bogdanm	0:9b334a45a8ff	1637	* consecutively for the same ADC instance. Therefore, the number of calls to
bogdanm	0:9b334a45a8ff	1638	* HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
bogdanm	0:9b334a45a8ff	1639	* InjectedNbrOfConversion for each context.
bogdanm	0:9b334a45a8ff	1640	* - Example 1: If 1 context is intended to be used (or if there is no use of the
bogdanm	0:9b334a45a8ff	1641	* Injected Queue Context feature) and if the context contains 3 injected ranks
bogdanm	0:9b334a45a8ff	1642	* (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
bogdanm	0:9b334a45a8ff	1643	* called once for each channel (i.e. 3 times) before starting a conversion.
bogdanm	0:9b334a45a8ff	1644	* This function must not be called to configure a 4th injected channel:
bogdanm	0:9b334a45a8ff	1645	* it would start a new context into context queue.
bogdanm	0:9b334a45a8ff	1646	* - Example 2: If 2 contexts are intended to be used and each of them contains
bogdanm	0:9b334a45a8ff	1647	* 3 injected ranks (InjectedNbrOfConversion = 3),
bogdanm	0:9b334a45a8ff	1648	* HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
bogdanm	0:9b334a45a8ff	1649	* for each context (3 channels x 2 contexts = 6 calls). Conversion can
bogdanm	0:9b334a45a8ff	1650	* start once the 1st context is set, that is after the first three
bogdanm	0:9b334a45a8ff	1651	* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
bogdanm	0:9b334a45a8ff	1652	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1653	* @param sConfigInjected: Structure of ADC injected group and ADC channel for
bogdanm	0:9b334a45a8ff	1654	* injected group.
bogdanm	0:9b334a45a8ff	1655	* @retval None
bogdanm	0:9b334a45a8ff	1656	*/
bogdanm	0:9b334a45a8ff	1657	HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
bogdanm	0:9b334a45a8ff	1658	{
bogdanm	0:9b334a45a8ff	1659	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1660	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	1661	uint32_t tmpOffsetShifted;
bogdanm	0:9b334a45a8ff	1662	uint32_t WaitLoopIndex = 0;
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1668	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1669	assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
bogdanm	0:9b334a45a8ff	1670	assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
bogdanm	0:9b334a45a8ff	1671	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
bogdanm	0:9b334a45a8ff	1672	assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
bogdanm	0:9b334a45a8ff	1673	assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	1674	assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
bogdanm	0:9b334a45a8ff	1675	assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
bogdanm	0:9b334a45a8ff	1676	assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
bogdanm	0:9b334a45a8ff	1677	assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
bogdanm	0:9b334a45a8ff	1678	assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
bogdanm	0:9b334a45a8ff	1679	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
bogdanm	0:9b334a45a8ff	1680	assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm	0:9b334a45a8ff	1683	{
bogdanm	0:9b334a45a8ff	1684	assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
bogdanm	0:9b334a45a8ff	1685	assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
bogdanm	0:9b334a45a8ff	1686	assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	1687	}
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
bogdanm	0:9b334a45a8ff	1691	ignored (considered as reset) */
bogdanm	0:9b334a45a8ff	1692	assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	/* JDISCEN and JAUTO bits can't be set at the same time */
bogdanm	0:9b334a45a8ff	1695	assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	/* DISCEN and JAUTO bits can't be set at the same time */
bogdanm	0:9b334a45a8ff	1698	assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/* Only rank 1 can be configured if there is only one conversion or if Scan conversion mode is disabled */
bogdanm	0:9b334a45a8ff	1701	assert_param(!(((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) \|\| (sConfigInjected->InjectedNbrOfConversion == 1) ) && (sConfigInjected->InjectedRank != ADC_INJECTED_RANK_1)));
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/* Verification of channel number.
bogdanm	0:9b334a45a8ff	1705	For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
bogdanm	0:9b334a45a8ff	1706	channels 16 to 18 can be only used in single-ended mode.
bogdanm	0:9b334a45a8ff	1707	For ADC3, channels 1 to 11 are available in differential mode,
bogdanm	0:9b334a45a8ff	1708	channels 12 to 18 can only be used in single-ended mode. */
bogdanm	0:9b334a45a8ff	1709	if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	1710	{
bogdanm	0:9b334a45a8ff	1711	assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	1712	}
bogdanm	0:9b334a45a8ff	1713	else
bogdanm	0:9b334a45a8ff	1714	{
bogdanm	0:9b334a45a8ff	1715	if (hadc->Instance == ADC3)
bogdanm	0:9b334a45a8ff	1716	{
bogdanm	0:9b334a45a8ff	1717	assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	1718	}
bogdanm	0:9b334a45a8ff	1719	else
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	assert_param(IS_ADC12_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	1722	}
bogdanm	0:9b334a45a8ff	1723	}
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	/* Process locked */
bogdanm	0:9b334a45a8ff	1726	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729
bogdanm	0:9b334a45a8ff	1730	/* Configuration of Injected group sequencer. */
bogdanm	0:9b334a45a8ff	1731	/* Hardware constraint: Must fully define injected context register JSQR */
bogdanm	0:9b334a45a8ff	1732	/* before make it entering into injected sequencer queue. */
bogdanm	0:9b334a45a8ff	1733	/* */
bogdanm	0:9b334a45a8ff	1734	/* - if scan mode is disabled: */
bogdanm	0:9b334a45a8ff	1735	/* * Injected channels sequence length is set to 0x00: 1 channel */
bogdanm	0:9b334a45a8ff	1736	/* converted (channel on injected rank 1) */
bogdanm	0:9b334a45a8ff	1737	/* Parameter "InjectedNbrOfConversion" is discarded. */
bogdanm	0:9b334a45a8ff	1738	/* * Injected context register JSQR setting is simple: register is fully */
bogdanm	0:9b334a45a8ff	1739	/* defined on one call of this function (for injected rank 1) and can */
bogdanm	0:9b334a45a8ff	1740	/* be entered into queue directly. */
bogdanm	0:9b334a45a8ff	1741	/* - if scan mode is enabled: */
bogdanm	0:9b334a45a8ff	1742	/* * Injected channels sequence length is set to parameter */
bogdanm	0:9b334a45a8ff	1743	/* "InjectedNbrOfConversion". */
bogdanm	0:9b334a45a8ff	1744	/* * Injected context register JSQR setting more complex: register is */
bogdanm	0:9b334a45a8ff	1745	/* fully defined over successive calls of this function, for each */
bogdanm	0:9b334a45a8ff	1746	/* injected channel rank. It is entered into queue only when all */
bogdanm	0:9b334a45a8ff	1747	/* injected ranks have been set. */
bogdanm	0:9b334a45a8ff	1748	/* Note: Scan mode is not present by hardware on this device, but used */
bogdanm	0:9b334a45a8ff	1749	/* by software for alignment over all STM32 devices. */
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) \|\|
bogdanm	0:9b334a45a8ff	1752	(sConfigInjected->InjectedNbrOfConversion == 1) )
bogdanm	0:9b334a45a8ff	1753	{
bogdanm	0:9b334a45a8ff	1754	/* Configuration of context register JSQR: */
bogdanm	0:9b334a45a8ff	1755	/* - number of ranks in injected group sequencer: fixed to 1st rank */
bogdanm	0:9b334a45a8ff	1756	/* (scan mode disabled, only rank 1 used) */
bogdanm	0:9b334a45a8ff	1757	/* - external trigger to start conversion */
bogdanm	0:9b334a45a8ff	1758	/* - external trigger polarity */
bogdanm	0:9b334a45a8ff	1759	/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
bogdanm	0:9b334a45a8ff	1762	{
bogdanm	0:9b334a45a8ff	1763	/* Enable external trigger if trigger selection is different of */
bogdanm	0:9b334a45a8ff	1764	/* software start. */
bogdanm	0:9b334a45a8ff	1765	/* Note: This configuration keeps the hardware feature of parameter */
bogdanm	0:9b334a45a8ff	1766	/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
bogdanm	0:9b334a45a8ff	1767	/* software start. */
bogdanm	0:9b334a45a8ff	1768	if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	1769	&& (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) \|
bogdanm	0:9b334a45a8ff	1772	sConfigInjected->ExternalTrigInjecConv \|
bogdanm	0:9b334a45a8ff	1773	sConfigInjected->ExternalTrigInjecConvEdge );
bogdanm	0:9b334a45a8ff	1774	}
bogdanm	0:9b334a45a8ff	1775	else
bogdanm	0:9b334a45a8ff	1776	{
bogdanm	0:9b334a45a8ff	1777	tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
bogdanm	0:9b334a45a8ff	1778	}
bogdanm	0:9b334a45a8ff	1779
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
bogdanm	0:9b334a45a8ff	1782	/* For debug and informative reasons, hadc handle saves JSQR setting */
bogdanm	0:9b334a45a8ff	1783	hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	}
bogdanm	0:9b334a45a8ff	1786	}
bogdanm	0:9b334a45a8ff	1787	else
bogdanm	0:9b334a45a8ff	1788	{
bogdanm	0:9b334a45a8ff	1789	/* Case of scan mode enabled, several channels to set into injected group */
bogdanm	0:9b334a45a8ff	1790	/* sequencer. */
bogdanm	0:9b334a45a8ff	1791	/* */
bogdanm	0:9b334a45a8ff	1792	/* Procedure to define injected context register JSQR over successive */
bogdanm	0:9b334a45a8ff	1793	/* calls of this function, for each injected channel rank: */
bogdanm	0:9b334a45a8ff	1794	/* 1. Start new context and set parameters related to all injected */
bogdanm	0:9b334a45a8ff	1795	/* channels: injected sequence length and trigger. */
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	/* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
bogdanm	0:9b334a45a8ff	1798	/* call of the context under setting */
bogdanm	0:9b334a45a8ff	1799	if (hadc->InjectionConfig.ChannelCount == 0)
bogdanm	0:9b334a45a8ff	1800	{
bogdanm	0:9b334a45a8ff	1801	/* Initialize number of channels that will be configured on the context */
bogdanm	0:9b334a45a8ff	1802	/* being built */
bogdanm	0:9b334a45a8ff	1803	hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
bogdanm	0:9b334a45a8ff	1804	/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
bogdanm	0:9b334a45a8ff	1805	call, this context will be written in JSQR register at the last call.
bogdanm	0:9b334a45a8ff	1806	At this point, the context is merely reset */
bogdanm	0:9b334a45a8ff	1807	hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/* Configuration of context register JSQR: */
bogdanm	0:9b334a45a8ff	1810	/* - number of ranks in injected group sequencer */
bogdanm	0:9b334a45a8ff	1811	/* - external trigger to start conversion */
bogdanm	0:9b334a45a8ff	1812	/* - external trigger polarity */
bogdanm	0:9b334a45a8ff	1813
bogdanm	0:9b334a45a8ff	1814	/* Enable external trigger if trigger selection is different of */
bogdanm	0:9b334a45a8ff	1815	/* software start. */
bogdanm	0:9b334a45a8ff	1816	/* Note: This configuration keeps the hardware feature of parameter */
bogdanm	0:9b334a45a8ff	1817	/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
bogdanm	0:9b334a45a8ff	1818	/* software start. */
bogdanm	0:9b334a45a8ff	1819	if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	1820	&& (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
bogdanm	0:9b334a45a8ff	1821	{
bogdanm	0:9b334a45a8ff	1822	tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) \|
bogdanm	0:9b334a45a8ff	1823	sConfigInjected->ExternalTrigInjecConv \|
bogdanm	0:9b334a45a8ff	1824	sConfigInjected->ExternalTrigInjecConvEdge );
bogdanm	0:9b334a45a8ff	1825	}
bogdanm	0:9b334a45a8ff	1826	else
bogdanm	0:9b334a45a8ff	1827	{
bogdanm	0:9b334a45a8ff	1828	tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
bogdanm	0:9b334a45a8ff	1829	}
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	} /* if (hadc->InjectionConfig.ChannelCount == 0) */
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/* 2. Continue setting of context under definition with parameter */
bogdanm	0:9b334a45a8ff	1836	/* related to each channel: channel rank sequence */
bogdanm	0:9b334a45a8ff	1837	/* Clear the old JSQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1838	tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	/* Set the JSQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1841	tmp_JSQR_ContextQueueBeingBuilt \|= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
bogdanm	0:9b334a45a8ff	1842
bogdanm	0:9b334a45a8ff	1843	/* Decrease channel count */
bogdanm	0:9b334a45a8ff	1844	hadc->InjectionConfig.ChannelCount--;
bogdanm	0:9b334a45a8ff	1845
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
bogdanm	0:9b334a45a8ff	1848	call, aggregate the setting to those already built during the previous
bogdanm	0:9b334a45a8ff	1849	HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
bogdanm	0:9b334a45a8ff	1850	hadc->InjectionConfig.ContextQueue \|= tmp_JSQR_ContextQueueBeingBuilt;
bogdanm	0:9b334a45a8ff	1851
bogdanm	0:9b334a45a8ff	1852	/* 4. End of context setting: if this is the last channel set, then write context
bogdanm	0:9b334a45a8ff	1853	into register JSQR and make it enter into queue */
bogdanm	0:9b334a45a8ff	1854	if (hadc->InjectionConfig.ChannelCount == 0)
bogdanm	0:9b334a45a8ff	1855	{
bogdanm	0:9b334a45a8ff	1856	MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
bogdanm	0:9b334a45a8ff	1857	}
bogdanm	0:9b334a45a8ff	1858
bogdanm	0:9b334a45a8ff	1859
bogdanm	0:9b334a45a8ff	1860	}
bogdanm	0:9b334a45a8ff	1861
bogdanm	0:9b334a45a8ff	1862	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	1863	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	1864	/* conversion on going on injected group: */
bogdanm	0:9b334a45a8ff	1865	/* - Injected context queue: Queue disable (active context is kept) or */
bogdanm	0:9b334a45a8ff	1866	/* enable (context decremented, up to 2 contexts queued) */
bogdanm	0:9b334a45a8ff	1867	/* - Injected discontinuous mode: can be enabled only if auto-injected */
bogdanm	0:9b334a45a8ff	1868	/* mode is disabled. */
bogdanm	0:9b334a45a8ff	1869	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1870	{
bogdanm	0:9b334a45a8ff	1871
bogdanm	0:9b334a45a8ff	1872	/* If auto-injected mode is disabled: no constraint */
bogdanm	0:9b334a45a8ff	1873	if (sConfigInjected->AutoInjectedConv == DISABLE)
bogdanm	0:9b334a45a8ff	1874	{
bogdanm	0:9b334a45a8ff	1875	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JDISCEN,
bogdanm	0:9b334a45a8ff	1876	ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) \|
bogdanm	0:9b334a45a8ff	1877	ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
bogdanm	0:9b334a45a8ff	1878	}
bogdanm	0:9b334a45a8ff	1879	/* If auto-injected mode is enabled: Injected discontinuous setting is */
bogdanm	0:9b334a45a8ff	1880	/* discarded. */
bogdanm	0:9b334a45a8ff	1881	else
bogdanm	0:9b334a45a8ff	1882	{
bogdanm	0:9b334a45a8ff	1883	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JDISCEN,
bogdanm	0:9b334a45a8ff	1884	ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
bogdanm	0:9b334a45a8ff	1885	}
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	}
bogdanm	0:9b334a45a8ff	1888
bogdanm	0:9b334a45a8ff	1889
bogdanm	0:9b334a45a8ff	1890	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	1891	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	1892	/* conversion on going on regular and injected groups: */
bogdanm	0:9b334a45a8ff	1893	/* - Automatic injected conversion: can be enabled if injected group */
bogdanm	0:9b334a45a8ff	1894	/* external triggers are disabled. */
bogdanm	0:9b334a45a8ff	1895	/* - Channel sampling time */
bogdanm	0:9b334a45a8ff	1896	/* - Channel offset */
bogdanm	0:9b334a45a8ff	1897	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1898	{
bogdanm	0:9b334a45a8ff	1899	/* If injected group external triggers are disabled (set to injected */
bogdanm	0:9b334a45a8ff	1900	/* software start): no constraint */
bogdanm	0:9b334a45a8ff	1901	if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	1902	\|\| (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
bogdanm	0:9b334a45a8ff	1903	{
bogdanm	0:9b334a45a8ff	1904	if (sConfigInjected->AutoInjectedConv == ENABLE)
bogdanm	0:9b334a45a8ff	1905	{
bogdanm	0:9b334a45a8ff	1906	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
bogdanm	0:9b334a45a8ff	1907	}
bogdanm	0:9b334a45a8ff	1908	else
bogdanm	0:9b334a45a8ff	1909	{
bogdanm	0:9b334a45a8ff	1910	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
bogdanm	0:9b334a45a8ff	1911	}
bogdanm	0:9b334a45a8ff	1912	}
bogdanm	0:9b334a45a8ff	1913	/* If Automatic injected conversion was intended to be set and could not */
bogdanm	0:9b334a45a8ff	1914	/* due to injected group external triggers enabled, error is reported. */
bogdanm	0:9b334a45a8ff	1915	else
bogdanm	0:9b334a45a8ff	1916	{
bogdanm	0:9b334a45a8ff	1917	if (sConfigInjected->AutoInjectedConv == ENABLE)
bogdanm	0:9b334a45a8ff	1918	{
bogdanm	0:9b334a45a8ff	1919	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1920	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1923	}
bogdanm	0:9b334a45a8ff	1924	else
bogdanm	0:9b334a45a8ff	1925	{
bogdanm	0:9b334a45a8ff	1926	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
bogdanm	0:9b334a45a8ff	1927	}
bogdanm	0:9b334a45a8ff	1928	}
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	if (sConfigInjected->InjecOversamplingMode == ENABLE)
bogdanm	0:9b334a45a8ff	1933	{
bogdanm	0:9b334a45a8ff	1934	assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
bogdanm	0:9b334a45a8ff	1935	assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	/* JOVSE must be reset in case of triggered regular mode */
bogdanm	0:9b334a45a8ff	1938	assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE\|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE\|ADC_CFGR2_TROVS)));
bogdanm	0:9b334a45a8ff	1939
bogdanm	0:9b334a45a8ff	1940	/* Configuration of Injected Oversampler: */
bogdanm	0:9b334a45a8ff	1941	/* - Oversampling Ratio */
bogdanm	0:9b334a45a8ff	1942	/* - Right bit shift */
bogdanm	0:9b334a45a8ff	1943
bogdanm	0:9b334a45a8ff	1944	/* Enable OverSampling mode */
bogdanm	0:9b334a45a8ff	1945
bogdanm	0:9b334a45a8ff	1946	MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
bogdanm	0:9b334a45a8ff	1947	ADC_CFGR2_JOVSE \|
bogdanm	0:9b334a45a8ff	1948	sConfigInjected->InjecOversampling.Ratio \|
bogdanm	0:9b334a45a8ff	1949	sConfigInjected->InjecOversampling.RightBitShift );
bogdanm	0:9b334a45a8ff	1950	}
bogdanm	0:9b334a45a8ff	1951	else
bogdanm	0:9b334a45a8ff	1952	{
bogdanm	0:9b334a45a8ff	1953	/* Disable Regular OverSampling */
bogdanm	0:9b334a45a8ff	1954	CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
bogdanm	0:9b334a45a8ff	1955	}
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	/* Sampling time configuration of the selected channel */
bogdanm	0:9b334a45a8ff	1959	/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
bogdanm	0:9b334a45a8ff	1960	if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
bogdanm	0:9b334a45a8ff	1961	{
bogdanm	0:9b334a45a8ff	1962	/* Clear the old sample time and set the new one */
bogdanm	0:9b334a45a8ff	1963	MODIFY_REG(hadc->Instance->SMPR2,
bogdanm	0:9b334a45a8ff	1964	ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
bogdanm	0:9b334a45a8ff	1965	ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	1966	}
bogdanm	0:9b334a45a8ff	1967	else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
bogdanm	0:9b334a45a8ff	1968	{
bogdanm	0:9b334a45a8ff	1969	/* Clear the old sample time and set the new one */
bogdanm	0:9b334a45a8ff	1970	MODIFY_REG(hadc->Instance->SMPR1,
bogdanm	0:9b334a45a8ff	1971	ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel),
bogdanm	0:9b334a45a8ff	1972	ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	1973	}
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	/* Configure the offset: offset enable/disable, channel, offset value */
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Shift the offset with respect to the selected ADC resolution. */
bogdanm	0:9b334a45a8ff	1979	/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
bogdanm	0:9b334a45a8ff	1980	tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
bogdanm	0:9b334a45a8ff	1981
bogdanm	0:9b334a45a8ff	1982	switch (sConfigInjected->InjectedOffsetNumber)
bogdanm	0:9b334a45a8ff	1983	{
bogdanm	0:9b334a45a8ff	1984	case ADC_OFFSET_1:
bogdanm	0:9b334a45a8ff	1985	/* Configure offset register 1: */
bogdanm	0:9b334a45a8ff	1986	/* - Enable offset */
bogdanm	0:9b334a45a8ff	1987	/* - Set channel number */
bogdanm	0:9b334a45a8ff	1988	/* - Set offset value */
bogdanm	0:9b334a45a8ff	1989	MODIFY_REG(hadc->Instance->OFR1,
bogdanm	0:9b334a45a8ff	1990	ADC_OFR1_OFFSET1 \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1_EN,
bogdanm	0:9b334a45a8ff	1991	ADC_OFR1_OFFSET1_EN \| ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	1992	break;
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	case ADC_OFFSET_2:
bogdanm	0:9b334a45a8ff	1995	/* Configure offset register 2: */
bogdanm	0:9b334a45a8ff	1996	/* - Enable offset */
bogdanm	0:9b334a45a8ff	1997	/* - Set channel number */
bogdanm	0:9b334a45a8ff	1998	/* - Set offset value */
bogdanm	0:9b334a45a8ff	1999	MODIFY_REG(hadc->Instance->OFR2,
bogdanm	0:9b334a45a8ff	2000	ADC_OFR2_OFFSET2 \| ADC_OFR2_OFFSET2_CH \| ADC_OFR2_OFFSET2_EN,
bogdanm	0:9b334a45a8ff	2001	ADC_OFR2_OFFSET2_EN \| ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2002	break;
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	case ADC_OFFSET_3:
bogdanm	0:9b334a45a8ff	2005	/* Configure offset register 3: */
bogdanm	0:9b334a45a8ff	2006	/* - Enable offset */
bogdanm	0:9b334a45a8ff	2007	/* - Set channel number */
bogdanm	0:9b334a45a8ff	2008	/* - Set offset value */
bogdanm	0:9b334a45a8ff	2009	MODIFY_REG(hadc->Instance->OFR3,
bogdanm	0:9b334a45a8ff	2010	ADC_OFR3_OFFSET3 \| ADC_OFR3_OFFSET3_CH \| ADC_OFR3_OFFSET3_EN,
bogdanm	0:9b334a45a8ff	2011	ADC_OFR3_OFFSET3_EN \| ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2012	break;
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	case ADC_OFFSET_4:
bogdanm	0:9b334a45a8ff	2015	/* Configure offset register 1: */
bogdanm	0:9b334a45a8ff	2016	/* - Enable offset */
bogdanm	0:9b334a45a8ff	2017	/* - Set channel number */
bogdanm	0:9b334a45a8ff	2018	/* - Set offset value */
bogdanm	0:9b334a45a8ff	2019	MODIFY_REG(hadc->Instance->OFR4,
bogdanm	0:9b334a45a8ff	2020	ADC_OFR4_OFFSET4 \| ADC_OFR4_OFFSET4_CH \| ADC_OFR4_OFFSET4_EN,
bogdanm	0:9b334a45a8ff	2021	ADC_OFR4_OFFSET4_EN \| ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2022	break;
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	/* Case ADC_OFFSET_NONE */
bogdanm	0:9b334a45a8ff	2025	default :
bogdanm	0:9b334a45a8ff	2026	/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
bogdanm	0:9b334a45a8ff	2027	if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
bogdanm	0:9b334a45a8ff	2028	{
bogdanm	0:9b334a45a8ff	2029	/* Disable offset OFR1*/
bogdanm	0:9b334a45a8ff	2030	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
bogdanm	0:9b334a45a8ff	2031	}
bogdanm	0:9b334a45a8ff	2032	if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
bogdanm	0:9b334a45a8ff	2033	{
bogdanm	0:9b334a45a8ff	2034	/* Disable offset OFR2*/
bogdanm	0:9b334a45a8ff	2035	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
bogdanm	0:9b334a45a8ff	2036	}
bogdanm	0:9b334a45a8ff	2037	if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
bogdanm	0:9b334a45a8ff	2038	{
bogdanm	0:9b334a45a8ff	2039	/* Disable offset OFR3*/
bogdanm	0:9b334a45a8ff	2040	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
bogdanm	0:9b334a45a8ff	2041	}
bogdanm	0:9b334a45a8ff	2042	if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
bogdanm	0:9b334a45a8ff	2043	{
bogdanm	0:9b334a45a8ff	2044	/* Disable offset OFR4*/
bogdanm	0:9b334a45a8ff	2045	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
bogdanm	0:9b334a45a8ff	2046	}
bogdanm	0:9b334a45a8ff	2047	break;
bogdanm	0:9b334a45a8ff	2048	}
bogdanm	0:9b334a45a8ff	2049
bogdanm	0:9b334a45a8ff	2050	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	2051
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2054	/* Parameters that can be updated only when ADC is disabled: */
bogdanm	0:9b334a45a8ff	2055	/* - Single or differential mode */
bogdanm	0:9b334a45a8ff	2056	/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
bogdanm	0:9b334a45a8ff	2057	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2058	{
bogdanm	0:9b334a45a8ff	2059	/* Configuration of differential mode */
bogdanm	0:9b334a45a8ff	2060	if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	2061	{
bogdanm	0:9b334a45a8ff	2062	/* Disable differential mode (default mode: single-ended) */
bogdanm	0:9b334a45a8ff	2063	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	2064	}
bogdanm	0:9b334a45a8ff	2065	else
bogdanm	0:9b334a45a8ff	2066	{
bogdanm	0:9b334a45a8ff	2067	/* Enable differential mode */
bogdanm	0:9b334a45a8ff	2068	SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm	0:9b334a45a8ff	2069
bogdanm	0:9b334a45a8ff	2070	/* Sampling time configuration of channel ADC_IN+1 (negative input) */
bogdanm	0:9b334a45a8ff	2071	/* For channels 9 to 15 for ADC1, ADC2, 9 to 11 for ADC3 */
bogdanm	0:9b334a45a8ff	2072	if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	/* Clear the old sample time and set the new one */
bogdanm	0:9b334a45a8ff	2075	MODIFY_REG(hadc->Instance->SMPR2,
bogdanm	0:9b334a45a8ff	2076	ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
bogdanm	0:9b334a45a8ff	2077	ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
bogdanm	0:9b334a45a8ff	2078	}
bogdanm	0:9b334a45a8ff	2079	else /* For channels 0 to 8 */
bogdanm	0:9b334a45a8ff	2080	{
bogdanm	0:9b334a45a8ff	2081	/* Clear the old sample time and set the new one */
bogdanm	0:9b334a45a8ff	2082	MODIFY_REG(hadc->Instance->SMPR1,
bogdanm	0:9b334a45a8ff	2083	ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
bogdanm	0:9b334a45a8ff	2084	ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
bogdanm	0:9b334a45a8ff	2085	}
bogdanm	0:9b334a45a8ff	2086	}
bogdanm	0:9b334a45a8ff	2087
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
bogdanm	0:9b334a45a8ff	2090	/* internal measurement paths enable: If internal channel selected, */
bogdanm	0:9b334a45a8ff	2091	/* enable dedicated internal buffers and path. */
bogdanm	0:9b334a45a8ff	2092	/* Note: these internal measurement paths can be disabled using */
bogdanm	0:9b334a45a8ff	2093	/* HAL_ADC_DeInit(). */
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/* Configuration of common ADC parameters */
bogdanm	0:9b334a45a8ff	2096
bogdanm	0:9b334a45a8ff	2097	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	2098
bogdanm	0:9b334a45a8ff	2099	/* If the requested internal measurement path has already been enabled, */
bogdanm	0:9b334a45a8ff	2100	/* bypass the configuration processing. */
bogdanm	0:9b334a45a8ff	2101	if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
bogdanm	0:9b334a45a8ff	2102	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) \|\|
bogdanm	0:9b334a45a8ff	2103	( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
bogdanm	0:9b334a45a8ff	2104	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) \|\|
bogdanm	0:9b334a45a8ff	2105	( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
bogdanm	0:9b334a45a8ff	2106	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
bogdanm	0:9b334a45a8ff	2107	)
bogdanm	0:9b334a45a8ff	2108	{
bogdanm	0:9b334a45a8ff	2109	/* Configuration of common ADC parameters (continuation) */
bogdanm	0:9b334a45a8ff	2110	/* Software is allowed to change common parameters only when all ADCs */
bogdanm	0:9b334a45a8ff	2111	/* of the common group are disabled. */
bogdanm	0:9b334a45a8ff	2112	if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm	0:9b334a45a8ff	2113	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	2114	{
bogdanm	0:9b334a45a8ff	2115	/* If Channel 17 is selected, enable Temp. sensor measurement path */
bogdanm	0:9b334a45a8ff	2116	/* Note: Temp. sensor internal channels available on ADC1 and ADC3 */
bogdanm	0:9b334a45a8ff	2117	if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
bogdanm	0:9b334a45a8ff	2118	((hadc->Instance == ADC1) \|\| (hadc->Instance == ADC3)))
bogdanm	0:9b334a45a8ff	2119	{
bogdanm	0:9b334a45a8ff	2120	SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
bogdanm	0:9b334a45a8ff	2121
bogdanm	0:9b334a45a8ff	2122	/* Delay for temperature sensor stabilization time */
bogdanm	0:9b334a45a8ff	2123	while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
bogdanm	0:9b334a45a8ff	2124	{
bogdanm	0:9b334a45a8ff	2125	WaitLoopIndex++;
bogdanm	0:9b334a45a8ff	2126	}
bogdanm	0:9b334a45a8ff	2127	}
bogdanm	0:9b334a45a8ff	2128	/* If Channel 18 is selected, enable VBAT measurement path */
bogdanm	0:9b334a45a8ff	2129	/* Note: VBAT internal channels available on ADC1 and ADC3 */
bogdanm	0:9b334a45a8ff	2130	else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
bogdanm	0:9b334a45a8ff	2131	((hadc->Instance == ADC1) \|\| (hadc->Instance == ADC3)))
bogdanm	0:9b334a45a8ff	2132	{
bogdanm	0:9b334a45a8ff	2133	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
bogdanm	0:9b334a45a8ff	2134	}
bogdanm	0:9b334a45a8ff	2135	/* If Channel 0 is selected, enable VREFINT measurement path */
bogdanm	0:9b334a45a8ff	2136	/* Note: VREFINT internal channels available only on ADC1 */
bogdanm	0:9b334a45a8ff	2137	else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
bogdanm	0:9b334a45a8ff	2138	&& (hadc->Instance == ADC1))
bogdanm	0:9b334a45a8ff	2139	{
bogdanm	0:9b334a45a8ff	2140	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
bogdanm	0:9b334a45a8ff	2141	}
bogdanm	0:9b334a45a8ff	2142	else
bogdanm	0:9b334a45a8ff	2143	{
bogdanm	0:9b334a45a8ff	2144	/* Discrepancy found out between ADC instance and internal
bogdanm	0:9b334a45a8ff	2145	channel request */
bogdanm	0:9b334a45a8ff	2146	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2147	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2148	}
bogdanm	0:9b334a45a8ff	2149	}
bogdanm	0:9b334a45a8ff	2150	/* If the requested internal measurement path has already been enabled */
bogdanm	0:9b334a45a8ff	2151	/* and other ADC of the common group are enabled, internal */
bogdanm	0:9b334a45a8ff	2152	/* measurement paths cannot be enabled. */
bogdanm	0:9b334a45a8ff	2153	else
bogdanm	0:9b334a45a8ff	2154	{
bogdanm	0:9b334a45a8ff	2155	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2156	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2159	}
bogdanm	0:9b334a45a8ff	2160	}
bogdanm	0:9b334a45a8ff	2161
bogdanm	0:9b334a45a8ff	2162	} /* if (ADC_IS_ENABLE(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	2163
bogdanm	0:9b334a45a8ff	2164	/* Process unlocked */
bogdanm	0:9b334a45a8ff	2165	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	/* Return function status */
bogdanm	0:9b334a45a8ff	2168	return tmp_status;
bogdanm	0:9b334a45a8ff	2169	}
bogdanm	0:9b334a45a8ff	2170
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172
bogdanm	0:9b334a45a8ff	2173
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/**
bogdanm	0:9b334a45a8ff	2176	* @brief Enable ADC multimode and configure multimode parameters
bogdanm	0:9b334a45a8ff	2177	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	2178	* This function initializes multimode parameters, following
bogdanm	0:9b334a45a8ff	2179	* calls to this function can be used to reconfigure some parameters
bogdanm	0:9b334a45a8ff	2180	* of structure "ADC_MultiModeTypeDef" on the fly, without resetting
bogdanm	0:9b334a45a8ff	2181	* the ADCs.
bogdanm	0:9b334a45a8ff	2182	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	2183	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	2184	* "ADC_MultiModeTypeDef".
bogdanm	0:9b334a45a8ff	2185	* @note To move back configuration from multimode to single mode, ADC must
bogdanm	0:9b334a45a8ff	2186	* be reset (using function HAL_ADC_Init() ).
bogdanm	0:9b334a45a8ff	2187	* @param hadc: Master ADC handle
bogdanm	0:9b334a45a8ff	2188	* @param multimode : Structure of ADC multimode configuration
bogdanm	0:9b334a45a8ff	2189	* @retval HAL status
bogdanm	0:9b334a45a8ff	2190	*/
bogdanm	0:9b334a45a8ff	2191	HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
bogdanm	0:9b334a45a8ff	2192	{
bogdanm	0:9b334a45a8ff	2193	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	2194	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	2195	ADC_HandleTypeDef tmphadcSlave;
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2198	assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2199	assert_param(IS_ADC_MULTIMODE(multimode->Mode));
bogdanm	0:9b334a45a8ff	2200	assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
bogdanm	0:9b334a45a8ff	2201	assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
bogdanm	0:9b334a45a8ff	2202
bogdanm	0:9b334a45a8ff	2203	/* Process locked */
bogdanm	0:9b334a45a8ff	2204	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	2205
bogdanm	0:9b334a45a8ff	2206	ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2209	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	2210	/* conversion on going on regular group: */
bogdanm	0:9b334a45a8ff	2211	/* - Multimode DMA configuration */
bogdanm	0:9b334a45a8ff	2212	/* - Multimode DMA mode */
bogdanm	0:9b334a45a8ff	2213	if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2214	&& (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
bogdanm	0:9b334a45a8ff	2215	{
bogdanm	0:9b334a45a8ff	2216
bogdanm	0:9b334a45a8ff	2217	/* Pointer to the common control register */
bogdanm	0:9b334a45a8ff	2218	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	2219
bogdanm	0:9b334a45a8ff	2220	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA \| ADC_CCR_DMACFG,
bogdanm	0:9b334a45a8ff	2221	multimode->DMAAccessMode \|
bogdanm	0:9b334a45a8ff	2222	ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/* Parameters that can be updated only when ADC is disabled: */
bogdanm	0:9b334a45a8ff	2225	/* - Multimode mode selection */
bogdanm	0:9b334a45a8ff	2226	/* - Multimode delay */
bogdanm	0:9b334a45a8ff	2227	if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm	0:9b334a45a8ff	2228	(ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
bogdanm	0:9b334a45a8ff	2229	{
bogdanm	0:9b334a45a8ff	2230	/* Configuration of ADC common group ADC1&ADC2 */
bogdanm	0:9b334a45a8ff	2231	/* - set the selected multimode */
bogdanm	0:9b334a45a8ff	2232	/* - Set delay between two sampling phases */
bogdanm	0:9b334a45a8ff	2233	/* Note: Delay range depends on selected resolution: */
bogdanm	0:9b334a45a8ff	2234	/* from 1 to 12 clock cycles for 12 bits */
bogdanm	0:9b334a45a8ff	2235	/* from 1 to 10 clock cycles for 10 bits, */
bogdanm	0:9b334a45a8ff	2236	/* from 1 to 8 clock cycles for 8 bits */
bogdanm	0:9b334a45a8ff	2237	/* from 1 to 6 clock cycles for 6 bits */
bogdanm	0:9b334a45a8ff	2238	/* If a higher delay is selected, it will be clipped to maximum delay */
bogdanm	0:9b334a45a8ff	2239	/* range */
bogdanm	0:9b334a45a8ff	2240
bogdanm	0:9b334a45a8ff	2241	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL \| ADC_CCR_DELAY,
bogdanm	0:9b334a45a8ff	2242	multimode->Mode \| multimode->TwoSamplingDelay );
bogdanm	0:9b334a45a8ff	2243	}
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	}
bogdanm	0:9b334a45a8ff	2247	/* If one of the ADC sharing the same common group is enabled, no update */
bogdanm	0:9b334a45a8ff	2248	/* could be done on neither of the multimode structure parameters. */
bogdanm	0:9b334a45a8ff	2249	else
bogdanm	0:9b334a45a8ff	2250	{
bogdanm	0:9b334a45a8ff	2251	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2252	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2253
bogdanm	0:9b334a45a8ff	2254	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2255	}
bogdanm	0:9b334a45a8ff	2256
bogdanm	0:9b334a45a8ff	2257
bogdanm	0:9b334a45a8ff	2258	/* Process unlocked */
bogdanm	0:9b334a45a8ff	2259	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261	/* Return function status */
bogdanm	0:9b334a45a8ff	2262	return tmp_status;
bogdanm	0:9b334a45a8ff	2263	}
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265
bogdanm	0:9b334a45a8ff	2266
bogdanm	0:9b334a45a8ff	2267	/**
bogdanm	0:9b334a45a8ff	2268	* @brief Enable Injected Queue
bogdanm	0:9b334a45a8ff	2269	* @note This function resets CFGR register JQDIS bit in order to enable the
bogdanm	0:9b334a45a8ff	2270	* Injected Queue. JQDIS can be written only when ADSTART and JDSTART
bogdanm	0:9b334a45a8ff	2271	* are both equal to 0 to ensure that no regular nor injected
bogdanm	0:9b334a45a8ff	2272	* conversion is ongoing.
bogdanm	0:9b334a45a8ff	2273	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2274	* @retval HAL status
bogdanm	0:9b334a45a8ff	2275	*/
bogdanm	0:9b334a45a8ff	2276	HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2277	{
bogdanm	0:9b334a45a8ff	2278
bogdanm	0:9b334a45a8ff	2279	/* Parameter can be set only if no conversion is on-going */
bogdanm	0:9b334a45a8ff	2280	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2281	{
bogdanm	0:9b334a45a8ff	2282	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
bogdanm	0:9b334a45a8ff	2283
bogdanm	0:9b334a45a8ff	2284	/* Update state, clear previous result related to injected queue overflow */
bogdanm	0:9b334a45a8ff	2285	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
bogdanm	0:9b334a45a8ff	2286
bogdanm	0:9b334a45a8ff	2287	return HAL_OK;
bogdanm	0:9b334a45a8ff	2288	}
bogdanm	0:9b334a45a8ff	2289	else
bogdanm	0:9b334a45a8ff	2290	{
bogdanm	0:9b334a45a8ff	2291	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2292	}
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	}
bogdanm	0:9b334a45a8ff	2295
bogdanm	0:9b334a45a8ff	2296	/**
bogdanm	0:9b334a45a8ff	2297	* @brief Disable Injected Queue
bogdanm	0:9b334a45a8ff	2298	* @note This function sets CFGR register JQDIS bit in order to disable the
bogdanm	0:9b334a45a8ff	2299	* Injected Queue. JQDIS can be written only when ADSTART and JDSTART
bogdanm	0:9b334a45a8ff	2300	* are both equal to 0 to ensure that no regular nor injected
bogdanm	0:9b334a45a8ff	2301	* conversion is ongoing.
bogdanm	0:9b334a45a8ff	2302	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2303	* @retval HAL status
bogdanm	0:9b334a45a8ff	2304	*/
bogdanm	0:9b334a45a8ff	2305	HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2306	{
bogdanm	0:9b334a45a8ff	2307
bogdanm	0:9b334a45a8ff	2308	/* Parameter can be set only if no conversion is on-going */
bogdanm	0:9b334a45a8ff	2309	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2310	{
bogdanm	0:9b334a45a8ff	2311	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
bogdanm	0:9b334a45a8ff	2312	return HAL_OK;
bogdanm	0:9b334a45a8ff	2313	}
bogdanm	0:9b334a45a8ff	2314	else
bogdanm	0:9b334a45a8ff	2315	{
bogdanm	0:9b334a45a8ff	2316	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2317	}
bogdanm	0:9b334a45a8ff	2318
bogdanm	0:9b334a45a8ff	2319	}
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321
bogdanm	0:9b334a45a8ff	2322	/**
bogdanm	0:9b334a45a8ff	2323	* @brief Disable ADC voltage regulator.
bogdanm	0:9b334a45a8ff	2324	* @note Disabling voltage regulator allows to save power. This operation can
bogdanm	0:9b334a45a8ff	2325	* be carried out only when ADC is disabled.
bogdanm	0:9b334a45a8ff	2326	* @note To enable again the voltage regulator, the user is expected to
bogdanm	0:9b334a45a8ff	2327	* resort to HAL_ADC_Init() API.
bogdanm	0:9b334a45a8ff	2328	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2329	* @retval HAL status
bogdanm	0:9b334a45a8ff	2330	*/
bogdanm	0:9b334a45a8ff	2331	HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2332	{
bogdanm	0:9b334a45a8ff	2333
bogdanm	0:9b334a45a8ff	2334	/* ADVREGEN can be written only when the ADC is disabled */
bogdanm	0:9b334a45a8ff	2335	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2336	{
bogdanm	0:9b334a45a8ff	2337	CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
bogdanm	0:9b334a45a8ff	2338	return HAL_OK;
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340	else
bogdanm	0:9b334a45a8ff	2341	{
bogdanm	0:9b334a45a8ff	2342	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2343	}
bogdanm	0:9b334a45a8ff	2344	}
bogdanm	0:9b334a45a8ff	2345
bogdanm	0:9b334a45a8ff	2346	/**
bogdanm	0:9b334a45a8ff	2347	* @brief Enter ADC deep-power-down mode
bogdanm	0:9b334a45a8ff	2348	* @note This mode is achieved in setting DEEPPWD bit and allows to save power
bogdanm	0:9b334a45a8ff	2349	* in reducing leakage currents. It is particularly interesting before
bogdanm	0:9b334a45a8ff	2350	* entering STOP1 or STOP2 modes.
bogdanm	0:9b334a45a8ff	2351	* @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
bogdanm	0:9b334a45a8ff	2352	* ADC voltage regulator. This means that this API encompasses
bogdanm	0:9b334a45a8ff	2353	* HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
bogdanm	0:9b334a45a8ff	2354	* calibration is lost.
bogdanm	0:9b334a45a8ff	2355	* @note To exit the ADC deep-power-down mode, the user is expected to
bogdanm	0:9b334a45a8ff	2356	* resort to HAL_ADC_Init() API as well as to relaunch a calibration
bogdanm	0:9b334a45a8ff	2357	* with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
bogdanm	0:9b334a45a8ff	2358	* saved calibration factor.
bogdanm	0:9b334a45a8ff	2359	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2360	* @retval HAL status
bogdanm	0:9b334a45a8ff	2361	*/
bogdanm	0:9b334a45a8ff	2362	HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2363	{
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/* DEEPPWD can be written only when the ADC is disabled */
bogdanm	0:9b334a45a8ff	2366	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2367	{
bogdanm	0:9b334a45a8ff	2368	SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
bogdanm	0:9b334a45a8ff	2369	return HAL_OK;
bogdanm	0:9b334a45a8ff	2370	}
bogdanm	0:9b334a45a8ff	2371	else
bogdanm	0:9b334a45a8ff	2372	{
bogdanm	0:9b334a45a8ff	2373	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2374	}
bogdanm	0:9b334a45a8ff	2375	}
bogdanm	0:9b334a45a8ff	2376
bogdanm	0:9b334a45a8ff	2377	/**
bogdanm	0:9b334a45a8ff	2378	* @}
bogdanm	0:9b334a45a8ff	2379	*/
bogdanm	0:9b334a45a8ff	2380
bogdanm	0:9b334a45a8ff	2381	/**
bogdanm	0:9b334a45a8ff	2382	* @}
bogdanm	0:9b334a45a8ff	2383	*/
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385
bogdanm	0:9b334a45a8ff	2386
bogdanm	0:9b334a45a8ff	2387	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2388	/**
bogdanm	0:9b334a45a8ff	2389	* @}
bogdanm	0:9b334a45a8ff	2390	*/
bogdanm	0:9b334a45a8ff	2391
bogdanm	0:9b334a45a8ff	2392	/**
bogdanm	0:9b334a45a8ff	2393	* @}
bogdanm	0:9b334a45a8ff	2394	*/
bogdanm	0:9b334a45a8ff	2395
bogdanm	0:9b334a45a8ff	2396	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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