mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/stm32l476xx.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l476xx.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file contains:
bogdanm	0:9b334a45a8ff	10	* - Data structures and the address mapping for all peripherals
bogdanm	0:9b334a45a8ff	11	* - Peripheral's registers declarations and bits definition
bogdanm	0:9b334a45a8ff	12	* - Macros to access peripherals registers hardware
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	******************************************************************************
bogdanm	0:9b334a45a8ff	15	* @attention
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	20	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	21	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	22	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	24	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	25	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	27	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	28	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	29	*
bogdanm	0:9b334a45a8ff	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	40	*
bogdanm	0:9b334a45a8ff	41	******************************************************************************
bogdanm	0:9b334a45a8ff	42	*/
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	/** @addtogroup CMSIS_Device
bogdanm	0:9b334a45a8ff	45	* @{
bogdanm	0:9b334a45a8ff	46	*/
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	/** @addtogroup stm32l476xx
bogdanm	0:9b334a45a8ff	49	* @{
bogdanm	0:9b334a45a8ff	50	*/
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	#ifndef __STM32L476xx_H
bogdanm	0:9b334a45a8ff	53	#define __STM32L476xx_H
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	56	extern "C" {
bogdanm	0:9b334a45a8ff	57	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	0:9b334a45a8ff	60	* @{
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	/**
bogdanm	0:9b334a45a8ff	64	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm	0:9b334a45a8ff	65	*/
bogdanm	0:9b334a45a8ff	66	#define __CM4_REV 0x0001 /!< Cortex-M4 revision r0p1 /
bogdanm	0:9b334a45a8ff	67	#define __MPU_PRESENT 1 /!< STM32L4XX provides an MPU /
bogdanm	0:9b334a45a8ff	68	#define __NVIC_PRIO_BITS 4 /!< STM32L4XX uses 4 Bits for the Priority Levels /
bogdanm	0:9b334a45a8ff	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	70	#define __FPU_PRESENT 1 /!< FPU present /
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	/**
bogdanm	0:9b334a45a8ff	73	* @}
bogdanm	0:9b334a45a8ff	74	*/
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	/** @addtogroup Peripheral_interrupt_number_definition
bogdanm	0:9b334a45a8ff	77	* @{
bogdanm	0:9b334a45a8ff	78	*/
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	/**
bogdanm	0:9b334a45a8ff	81	* @brief STM32L4XX Interrupt Number Definition, according to the selected device
bogdanm	0:9b334a45a8ff	82	* in @ref Library_configuration_section
bogdanm	0:9b334a45a8ff	83	*/
bogdanm	0:9b334a45a8ff	84	typedef enum
bogdanm	0:9b334a45a8ff	85	{
bogdanm	0:9b334a45a8ff	86	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
bogdanm	0:9b334a45a8ff	87	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	0:9b334a45a8ff	88	HardFault_IRQn = -13, /!< 4 Cortex-M4 Memory Management Interrupt /
bogdanm	0:9b334a45a8ff	89	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
bogdanm	0:9b334a45a8ff	90	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
bogdanm	0:9b334a45a8ff	91	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
bogdanm	0:9b334a45a8ff	92	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
bogdanm	0:9b334a45a8ff	93	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
bogdanm	0:9b334a45a8ff	94	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
bogdanm	0:9b334a45a8ff	95	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
bogdanm	0:9b334a45a8ff	96	/**** STM32 specific Interrupt Numbers ********************************************************************/
bogdanm	0:9b334a45a8ff	97	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	98	PVD_PVM_IRQn = 1, /!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts /
bogdanm	0:9b334a45a8ff	99	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
bogdanm	0:9b334a45a8ff	100	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
bogdanm	0:9b334a45a8ff	101	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	102	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	103	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	0:9b334a45a8ff	104	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	0:9b334a45a8ff	105	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
bogdanm	0:9b334a45a8ff	106	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	0:9b334a45a8ff	107	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	0:9b334a45a8ff	108	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
bogdanm	0:9b334a45a8ff	109	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
bogdanm	0:9b334a45a8ff	110	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
bogdanm	0:9b334a45a8ff	111	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
bogdanm	0:9b334a45a8ff	112	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
bogdanm	0:9b334a45a8ff	113	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
bogdanm	0:9b334a45a8ff	114	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
bogdanm	0:9b334a45a8ff	115	ADC1_2_IRQn = 18, /!< ADC1, ADC2 SAR global Interrupts /
bogdanm	0:9b334a45a8ff	116	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
bogdanm	0:9b334a45a8ff	117	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
bogdanm	0:9b334a45a8ff	118	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
bogdanm	0:9b334a45a8ff	119	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
bogdanm	0:9b334a45a8ff	120	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	0:9b334a45a8ff	121	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break interrupt and TIM15 global interrupt /
bogdanm	0:9b334a45a8ff	122	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update Interrupt and TIM16 global interrupt /
bogdanm	0:9b334a45a8ff	123	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt /
bogdanm	0:9b334a45a8ff	124	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	125	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	126	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
bogdanm	0:9b334a45a8ff	127	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
bogdanm	0:9b334a45a8ff	128	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	0:9b334a45a8ff	129	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	0:9b334a45a8ff	130	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
bogdanm	0:9b334a45a8ff	131	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
bogdanm	0:9b334a45a8ff	132	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
bogdanm	0:9b334a45a8ff	133	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
bogdanm	0:9b334a45a8ff	134	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	0:9b334a45a8ff	135	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	0:9b334a45a8ff	136	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	0:9b334a45a8ff	137	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	0:9b334a45a8ff	138	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
bogdanm	0:9b334a45a8ff	139	DFSDM3_IRQn = 42, /!< SD Filter 3 global Interrupt /
bogdanm	0:9b334a45a8ff	140	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
bogdanm	0:9b334a45a8ff	141	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
bogdanm	0:9b334a45a8ff	142	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
bogdanm	0:9b334a45a8ff	143	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	144	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
bogdanm	0:9b334a45a8ff	145	FMC_IRQn = 48, /!< FMC global Interrupt /
bogdanm	0:9b334a45a8ff	146	SDMMC1_IRQn = 49, /!< SDMMC1 global Interrupt /
bogdanm	0:9b334a45a8ff	147	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
bogdanm	0:9b334a45a8ff	148	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
bogdanm	0:9b334a45a8ff	149	UART4_IRQn = 52, /!< UART4 global Interrupt /
bogdanm	0:9b334a45a8ff	150	UART5_IRQn = 53, /!< UART5 global Interrupt /
bogdanm	0:9b334a45a8ff	151	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
bogdanm	0:9b334a45a8ff	152	TIM7_IRQn = 55, /!< TIM7 global interrupt /
bogdanm	0:9b334a45a8ff	153	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
bogdanm	0:9b334a45a8ff	154	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
bogdanm	0:9b334a45a8ff	155	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
bogdanm	0:9b334a45a8ff	156	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
bogdanm	0:9b334a45a8ff	157	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
bogdanm	0:9b334a45a8ff	158	DFSDM0_IRQn = 61, /!< SD Filter 0 global Interrupt /
bogdanm	0:9b334a45a8ff	159	DFSDM1_IRQn = 62, /!< SD Filter 1 global Interrupt /
bogdanm	0:9b334a45a8ff	160	DFSDM2_IRQn = 63, /!< SD Filter 2 global Interrupt /
bogdanm	0:9b334a45a8ff	161	COMP_IRQn = 64, /!< COMP1 and COMP2 Interrupts /
bogdanm	0:9b334a45a8ff	162	LPTIM1_IRQn = 65, /!< LP TIM1 interrupt /
bogdanm	0:9b334a45a8ff	163	LPTIM2_IRQn = 66, /!< LP TIM2 interrupt /
bogdanm	0:9b334a45a8ff	164	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
bogdanm	0:9b334a45a8ff	165	DMA2_Channel6_IRQn = 68, /!< DMA2 Channel 6 global interrupt /
bogdanm	0:9b334a45a8ff	166	DMA2_Channel7_IRQn = 69, /!< DMA2 Channel 7 global interrupt /
bogdanm	0:9b334a45a8ff	167	LPUART1_IRQn = 70, /!< LP UART1 interrupt /
bogdanm	0:9b334a45a8ff	168	QUADSPI_IRQn = 71, /!< Quad SPI global interrupt /
bogdanm	0:9b334a45a8ff	169	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
bogdanm	0:9b334a45a8ff	170	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
bogdanm	0:9b334a45a8ff	171	SAI1_IRQn = 74, /!< Serial Audio Interface 1 global interrupt /
bogdanm	0:9b334a45a8ff	172	SAI2_IRQn = 75, /!< Serial Audio Interface 2 global interrupt /
bogdanm	0:9b334a45a8ff	173	SWPMI1_IRQn = 76, /!< Serial Wire Interface 1 global interrupt /
bogdanm	0:9b334a45a8ff	174	TSC_IRQn = 77, /!< Touch Sense Controller global interrupt /
bogdanm	0:9b334a45a8ff	175	LCD_IRQn = 78, /!< LCD global interrupt /
bogdanm	0:9b334a45a8ff	176	RNG_IRQn = 80, /!< RNG global interrupt /
bogdanm	0:9b334a45a8ff	177	FPU_IRQn = 81 /!< FPU global interrupt /
bogdanm	0:9b334a45a8ff	178	} IRQn_Type;
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/**
bogdanm	0:9b334a45a8ff	181	* @}
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm	0:9b334a45a8ff	185	#include "system_stm32l4xx.h"
bogdanm	0:9b334a45a8ff	186	#include <stdint.h>
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	/** @addtogroup Peripheral_registers_structures
bogdanm	0:9b334a45a8ff	189	* @{
bogdanm	0:9b334a45a8ff	190	*/
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	/**
bogdanm	0:9b334a45a8ff	193	* @brief Analog to Digital Converter
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	typedef struct
bogdanm	0:9b334a45a8ff	197	{
bogdanm	0:9b334a45a8ff	198	__IO uint32_t ISR; /!< ADC Interrupt and Status Register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	199	__IO uint32_t IER; /!< ADC Interrupt Enable Register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	200	__IO uint32_t CR; /!< ADC control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	201	__IO uint32_t CFGR; /!< ADC Configuration register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	202	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	203	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	204	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	205	uint32_t RESERVED1; /!< Reserved, 0x01C /
bogdanm	0:9b334a45a8ff	206	__IO uint32_t TR1; /!< ADC watchdog threshold register 1, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	207	__IO uint32_t TR2; /!< ADC watchdog threshold register 2, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	208	__IO uint32_t TR3; /!< ADC watchdog threshold register 3, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	209	uint32_t RESERVED2; /!< Reserved, 0x02C /
bogdanm	0:9b334a45a8ff	210	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	211	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	212	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	213	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	214	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	215	uint32_t RESERVED3; /!< Reserved, 0x044 /
bogdanm	0:9b334a45a8ff	216	uint32_t RESERVED4; /!< Reserved, 0x048 /
bogdanm	0:9b334a45a8ff	217	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	218	uint32_t RESERVED5[4]; /!< Reserved, 0x050 - 0x05C /
bogdanm	0:9b334a45a8ff	219	__IO uint32_t OFR1; /!< ADC offset register 1, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	220	__IO uint32_t OFR2; /!< ADC offset register 2, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	221	__IO uint32_t OFR3; /!< ADC offset register 3, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	222	__IO uint32_t OFR4; /!< ADC offset register 4, Address offset: 0x6C /
bogdanm	0:9b334a45a8ff	223	uint32_t RESERVED6[4]; /!< Reserved, 0x070 - 0x07C /
bogdanm	0:9b334a45a8ff	224	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	225	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	226	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	227	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	228	uint32_t RESERVED7[4]; /!< Reserved, 0x090 - 0x09C /
bogdanm	0:9b334a45a8ff	229	__IO uint32_t AWD2CR; /!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 /
bogdanm	0:9b334a45a8ff	230	__IO uint32_t AWD3CR; /!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 /
bogdanm	0:9b334a45a8ff	231	uint32_t RESERVED8; /!< Reserved, 0x0A8 /
bogdanm	0:9b334a45a8ff	232	uint32_t RESERVED9; /!< Reserved, 0x0AC /
bogdanm	0:9b334a45a8ff	233	__IO uint32_t DIFSEL; /!< ADC Differential Mode Selection Register, Address offset: 0xB0 /
bogdanm	0:9b334a45a8ff	234	__IO uint32_t CALFACT; /!< ADC Calibration Factors, Address offset: 0xB4 /
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	} ADC_TypeDef;
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	typedef struct
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
bogdanm	0:9b334a45a8ff	241	uint32_t RESERVED; /!< Reserved, ADC1 base address + 0x304 /
bogdanm	0:9b334a45a8ff	242	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x308 /
bogdanm	0:9b334a45a8ff	243	__IO uint32_t CDR; /!< ADC common regular data register for dual Address offset: ADC1 base address + 0x30C /
bogdanm	0:9b334a45a8ff	244	} ADC_Common_TypeDef;
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/**
bogdanm	0:9b334a45a8ff	248	* @brief Controller Area Network TxMailBox
bogdanm	0:9b334a45a8ff	249	*/
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	typedef struct
bogdanm	0:9b334a45a8ff	252	{
bogdanm	0:9b334a45a8ff	253	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
bogdanm	0:9b334a45a8ff	254	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
bogdanm	0:9b334a45a8ff	255	__IO uint32_t TDLR; /!< CAN mailbox data low register /
bogdanm	0:9b334a45a8ff	256	__IO uint32_t TDHR; /!< CAN mailbox data high register /
bogdanm	0:9b334a45a8ff	257	} CAN_TxMailBox_TypeDef;
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/**
bogdanm	0:9b334a45a8ff	260	* @brief Controller Area Network FIFOMailBox
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	typedef struct
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
bogdanm	0:9b334a45a8ff	266	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
bogdanm	0:9b334a45a8ff	267	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
bogdanm	0:9b334a45a8ff	268	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
bogdanm	0:9b334a45a8ff	269	} CAN_FIFOMailBox_TypeDef;
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	/**
bogdanm	0:9b334a45a8ff	272	* @brief Controller Area Network FilterRegister
bogdanm	0:9b334a45a8ff	273	*/
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	typedef struct
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
bogdanm	0:9b334a45a8ff	278	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
bogdanm	0:9b334a45a8ff	279	} CAN_FilterRegister_TypeDef;
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/**
bogdanm	0:9b334a45a8ff	282	* @brief Controller Area Network
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	typedef struct
bogdanm	0:9b334a45a8ff	286	{
bogdanm	0:9b334a45a8ff	287	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	288	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	289	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	290	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	291	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	292	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	293	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	294	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	295	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
bogdanm	0:9b334a45a8ff	296	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
bogdanm	0:9b334a45a8ff	297	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
bogdanm	0:9b334a45a8ff	298	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
bogdanm	0:9b334a45a8ff	299	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
bogdanm	0:9b334a45a8ff	300	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
bogdanm	0:9b334a45a8ff	301	uint32_t RESERVED2; /!< Reserved, 0x208 /
bogdanm	0:9b334a45a8ff	302	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
bogdanm	0:9b334a45a8ff	303	uint32_t RESERVED3; /!< Reserved, 0x210 /
bogdanm	0:9b334a45a8ff	304	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
bogdanm	0:9b334a45a8ff	305	uint32_t RESERVED4; /!< Reserved, 0x218 /
bogdanm	0:9b334a45a8ff	306	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
bogdanm	0:9b334a45a8ff	307	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
bogdanm	0:9b334a45a8ff	308	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
bogdanm	0:9b334a45a8ff	309	} CAN_TypeDef;
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/**
bogdanm	0:9b334a45a8ff	313	* @brief Comparator
bogdanm	0:9b334a45a8ff	314	*/
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	typedef struct
bogdanm	0:9b334a45a8ff	317	{
bogdanm	0:9b334a45a8ff	318	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	319	} COMP_TypeDef;
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/**
bogdanm	0:9b334a45a8ff	323	* @brief CRC calculation unit
bogdanm	0:9b334a45a8ff	324	*/
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	typedef struct
bogdanm	0:9b334a45a8ff	327	{
bogdanm	0:9b334a45a8ff	328	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	329	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	330	uint8_t RESERVED0; /!< Reserved, 0x05 /
bogdanm	0:9b334a45a8ff	331	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	332	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	333	uint32_t RESERVED2; /!< Reserved, 0x0C /
bogdanm	0:9b334a45a8ff	334	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	335	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	336	} CRC_TypeDef;
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/**
bogdanm	0:9b334a45a8ff	339	* @brief Digital to Analog Converter
bogdanm	0:9b334a45a8ff	340	*/
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	typedef struct
bogdanm	0:9b334a45a8ff	343	{
bogdanm	0:9b334a45a8ff	344	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	345	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	346	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	347	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	348	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	349	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	350	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	351	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	352	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	353	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	354	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	355	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	356	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	357	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	358	__IO uint32_t CCR; /!< DAC calibration control register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	359	__IO uint32_t MCR; /!< DAC mode control register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	360	__IO uint32_t SHSR1; /!< DAC Sample and Hold sample time register 1, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	361	__IO uint32_t SHSR2; /!< DAC Sample and Hold sample time register 2, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	362	__IO uint32_t SHHR; /!< DAC Sample and Hold hold time register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	363	__IO uint32_t SHRR; /!< DAC Sample and Hold refresh time register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	364	} DAC_TypeDef;
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	/**
bogdanm	0:9b334a45a8ff	367	* @brief DFSDM module registers
bogdanm	0:9b334a45a8ff	368	*/
bogdanm	0:9b334a45a8ff	369	typedef struct
bogdanm	0:9b334a45a8ff	370	{
bogdanm	0:9b334a45a8ff	371	__IO uint32_t CR1; /!< DFSDM control register1, Address offset: 0x100 /
bogdanm	0:9b334a45a8ff	372	__IO uint32_t CR2; /!< DFSDM control register2, Address offset: 0x104 /
bogdanm	0:9b334a45a8ff	373	__IO uint32_t ISR; /!< DFSDM interrupt and status register, Address offset: 0x108 /
bogdanm	0:9b334a45a8ff	374	__IO uint32_t ICR; /!< DFSDM interrupt flag clear register, Address offset: 0x10C /
bogdanm	0:9b334a45a8ff	375	__IO uint32_t JCHGR; /!< DFSDM injected channel group selection register, Address offset: 0x110 /
bogdanm	0:9b334a45a8ff	376	__IO uint32_t FCR; /!< DFSDM filter control register, Address offset: 0x114 /
bogdanm	0:9b334a45a8ff	377	__IO uint32_t JDATAR; /!< DFSDM data register for injected group, Address offset: 0x118 /
bogdanm	0:9b334a45a8ff	378	__IO uint32_t RDATAR; /!< DFSDM data register for regular group, Address offset: 0x11C /
bogdanm	0:9b334a45a8ff	379	__IO uint32_t AWHTR; /!< DFSDM analog watchdog high threshold register, Address offset: 0x120 /
bogdanm	0:9b334a45a8ff	380	__IO uint32_t AWLTR; /!< DFSDM analog watchdog low threshold register, Address offset: 0x124 /
bogdanm	0:9b334a45a8ff	381	__IO uint32_t AWSR; /!< DFSDM analog watchdog status register Address offset: 0x128 /
bogdanm	0:9b334a45a8ff	382	__IO uint32_t AWCFR; /!< DFSDM analog watchdog clear flag register Address offset: 0x12C /
bogdanm	0:9b334a45a8ff	383	__IO uint32_t EXMAX; /!< DFSDM extreme detector maximum register, Address offset: 0x130 /
bogdanm	0:9b334a45a8ff	384	__IO uint32_t EXMIN; /!< DFSDM extreme detector minimum register Address offset: 0x134 /
bogdanm	0:9b334a45a8ff	385	__IO uint32_t CNVTIMR; /!< DFSDM conversion timer, Address offset: 0x138 /
bogdanm	0:9b334a45a8ff	386	} DFSDM_Filter_TypeDef;
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	/**
bogdanm	0:9b334a45a8ff	389	* @brief DFSDM channel configuration registers
bogdanm	0:9b334a45a8ff	390	*/
bogdanm	0:9b334a45a8ff	391	typedef struct
bogdanm	0:9b334a45a8ff	392	{
bogdanm	0:9b334a45a8ff	393	__IO uint32_t CHCFGR1; /!< DFSDM channel configuration register1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	394	__IO uint32_t CHCFGR2; /!< DFSDM channel configuration register2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	395	__IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and
bogdanm	0:9b334a45a8ff	396	short circuit detector register, Address offset: 0x08 */
bogdanm	0:9b334a45a8ff	397	__IO uint32_t CHWDATAR; /!< DFSDM channel watchdog filter data register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	398	__IO uint32_t CHDATINR; /!< DFSDM channel data input register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	399	} DFSDM_Channel_TypeDef;
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	/**
bogdanm	0:9b334a45a8ff	402	* @brief Debug MCU
bogdanm	0:9b334a45a8ff	403	*/
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	typedef struct
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	408	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	409	__IO uint32_t APB1FZR1; /!< Debug MCU APB1 freeze register 1, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	410	__IO uint32_t APB1FZR2; /!< Debug MCU APB1 freeze register 2, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	411	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	412	} DBGMCU_TypeDef;
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @brief DMA Controller
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	typedef struct
bogdanm	0:9b334a45a8ff	420	{
bogdanm	0:9b334a45a8ff	421	__IO uint32_t CCR; /!< DMA channel x configuration register /
bogdanm	0:9b334a45a8ff	422	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
bogdanm	0:9b334a45a8ff	423	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
bogdanm	0:9b334a45a8ff	424	__IO uint32_t CMAR; /!< DMA channel x memory address register /
bogdanm	0:9b334a45a8ff	425	} DMA_Channel_TypeDef;
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	typedef struct
bogdanm	0:9b334a45a8ff	428	{
bogdanm	0:9b334a45a8ff	429	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	430	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	431	} DMA_TypeDef;
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	typedef struct
bogdanm	0:9b334a45a8ff	434	{
bogdanm	0:9b334a45a8ff	435	__IO uint32_t CSELR; /!< DMA option register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	436	} DMA_request_TypeDef;
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/**
bogdanm	0:9b334a45a8ff	440	* @brief External Interrupt/Event Controller
bogdanm	0:9b334a45a8ff	441	*/
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	typedef struct
bogdanm	0:9b334a45a8ff	444	{
bogdanm	0:9b334a45a8ff	445	__IO uint32_t IMR1; /!< EXTI Interrupt mask register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	446	__IO uint32_t EMR1; /!< EXTI Event mask register 1, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	447	__IO uint32_t RTSR1; /!< EXTI Rising trigger selection register 1, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	448	__IO uint32_t FTSR1; /!< EXTI Falling trigger selection register 1, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	449	__IO uint32_t SWIER1; /!< EXTI Software interrupt event register 1, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	450	__IO uint32_t PR1; /!< EXTI Pending register 1, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	451	uint32_t RESERVED1; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	452	uint32_t RESERVED2; /!< Reserved, 0x1C /
bogdanm	0:9b334a45a8ff	453	__IO uint32_t IMR2; /!< EXTI Interrupt mask register 2, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	454	__IO uint32_t EMR2; /!< EXTI Event mask register 2, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	455	__IO uint32_t RTSR2; /!< EXTI Rising trigger selection register 2, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	456	__IO uint32_t FTSR2; /!< EXTI Falling trigger selection register 2, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	457	__IO uint32_t SWIER2; /!< EXTI Software interrupt event register 2, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	458	__IO uint32_t PR2; /!< EXTI Pending register 2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	459	} EXTI_TypeDef;
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	/**
bogdanm	0:9b334a45a8ff	463	* @brief Firewall
bogdanm	0:9b334a45a8ff	464	*/
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	typedef struct
bogdanm	0:9b334a45a8ff	467	{
bogdanm	0:9b334a45a8ff	468	__IO uint32_t CSSA; /!< Code Segment Start Address register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	469	__IO uint32_t CSL; /!< Code Segment Length register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	470	__IO uint32_t NVDSSA; /!< NON volatile data Segment Start Address register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	471	__IO uint32_t NVDSL; /!< NON volatile data Segment Length register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	472	__IO uint32_t VDSSA ; /!< Volatile data Segment Start Address register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	473	__IO uint32_t VDSL ; /!< Volatile data Segment Length register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	474	uint32_t RESERVED1; /!< Reserved1, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	475	uint32_t RESERVED2; /!< Reserved2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	476	__IO uint32_t CR ; /!< Configuration register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	477	} FIREWALL_TypeDef;
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/**
bogdanm	0:9b334a45a8ff	481	* @brief FLASH Registers
bogdanm	0:9b334a45a8ff	482	*/
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	typedef struct
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	487	__IO uint32_t PDKEYR; /!< FLASH power down key register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	488	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	489	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	490	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	491	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	492	__IO uint32_t ECCR; /!< FLASH ECC register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	493	__IO uint32_t RESERVED1; /!< Reserved1, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	494	__IO uint32_t OPTR; /!< FLASH option register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	495	__IO uint32_t PCROP1SR; /!< FLASH bank1 PCROP start address register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	496	__IO uint32_t PCROP1ER; /!< FLASH bank1 PCROP end address register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	497	__IO uint32_t WRP1AR; /!< FLASH bank1 WRP area A address register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	498	__IO uint32_t WRP1BR; /!< FLASH bank1 WRP area B address register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	499	uint32_t RESERVED2[4]; /!< Reserved2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	500	__IO uint32_t PCROP2SR; /!< FLASH bank2 PCROP start address register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	501	__IO uint32_t PCROP2ER; /!< FLASH bank2 PCROP end address register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	502	__IO uint32_t WRP2AR; /!< FLASH bank2 WRP area A address register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	503	__IO uint32_t WRP2BR; /!< FLASH bank2 WRP area B address register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	504	} FLASH_TypeDef;
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @brief Flexible Memory Controller
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	typedef struct
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
bogdanm	0:9b334a45a8ff	514	} FMC_Bank1_TypeDef;
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/**
bogdanm	0:9b334a45a8ff	517	* @brief Flexible Memory Controller Bank1E
bogdanm	0:9b334a45a8ff	518	*/
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	typedef struct
bogdanm	0:9b334a45a8ff	521	{
bogdanm	0:9b334a45a8ff	522	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
bogdanm	0:9b334a45a8ff	523	} FMC_Bank1E_TypeDef;
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/**
bogdanm	0:9b334a45a8ff	526	* @brief Flexible Memory Controller Bank3
bogdanm	0:9b334a45a8ff	527	*/
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	typedef struct
bogdanm	0:9b334a45a8ff	530	{
bogdanm	0:9b334a45a8ff	531	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	532	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	533	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	534	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	535	uint32_t RESERVED0; /!< Reserved, 0x90 /
bogdanm	0:9b334a45a8ff	536	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
bogdanm	0:9b334a45a8ff	537	} FMC_Bank3_TypeDef;
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/**
bogdanm	0:9b334a45a8ff	540	* @brief General Purpose I/O
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	typedef struct
bogdanm	0:9b334a45a8ff	544	{
bogdanm	0:9b334a45a8ff	545	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	546	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	547	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	548	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	549	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	550	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	551	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	552	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	553	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
bogdanm	0:9b334a45a8ff	554	__IO uint32_t BRR; /!< GPIO Bit Reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	555	__IO uint32_t ASCR; /!< GPIO analog switch control register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	} GPIO_TypeDef;
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/**
bogdanm	0:9b334a45a8ff	561	* @brief Inter-integrated Circuit Interface
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	typedef struct
bogdanm	0:9b334a45a8ff	565	{
bogdanm	0:9b334a45a8ff	566	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	567	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	568	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	569	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	570	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	571	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	572	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	573	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	574	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	575	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	576	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	577	} I2C_TypeDef;
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/**
bogdanm	0:9b334a45a8ff	580	* @brief Independent WATCHDOG
bogdanm	0:9b334a45a8ff	581	*/
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	typedef struct
bogdanm	0:9b334a45a8ff	584	{
bogdanm	0:9b334a45a8ff	585	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	586	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	587	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	588	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	589	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	590	} IWDG_TypeDef;
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/**
bogdanm	0:9b334a45a8ff	593	* @brief LCD
bogdanm	0:9b334a45a8ff	594	*/
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	typedef struct
bogdanm	0:9b334a45a8ff	597	{
bogdanm	0:9b334a45a8ff	598	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	599	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	600	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	601	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	602	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	603	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
bogdanm	0:9b334a45a8ff	604	} LCD_TypeDef;
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/**
bogdanm	0:9b334a45a8ff	607	* @brief LPTIMER
bogdanm	0:9b334a45a8ff	608	*/
bogdanm	0:9b334a45a8ff	609	typedef struct
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	612	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	613	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	614	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	615	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	616	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	617	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	618	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	619	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	620	} LPTIM_TypeDef;
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	/**
bogdanm	0:9b334a45a8ff	624	* @brief Operational Amplifier (OPAMP)
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	typedef struct
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	__IO uint32_t CSR; /!< OPAMP control/status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	630	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	631	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	632	} OPAMP_TypeDef;
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/**
bogdanm	0:9b334a45a8ff	636	* @brief Power Control
bogdanm	0:9b334a45a8ff	637	*/
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	typedef struct
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	__IO uint32_t CR1; /!< PWR power control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	642	__IO uint32_t CR2; /!< PWR power control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	643	__IO uint32_t CR3; /!< PWR power control register 3, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	644	__IO uint32_t CR4; /!< PWR power control register 4, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	645	__IO uint32_t SR1; /!< PWR power status register 1, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	646	__IO uint32_t SR2; /!< PWR power status register 2, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	647	__IO uint32_t SCR; /!< PWR power status reset register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	648	uint32_t RESERVED; /!< Reserved, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	649	__IO uint32_t PUCRA; /!< Pull_up control register of portA, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	650	__IO uint32_t PDCRA; /!< Pull_Down control register of portA, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	651	__IO uint32_t PUCRB; /!< Pull_up control register of portB, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	652	__IO uint32_t PDCRB; /!< Pull_Down control register of portB, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	653	__IO uint32_t PUCRC; /!< Pull_up control register of portC, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	654	__IO uint32_t PDCRC; /!< Pull_Down control register of portC, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	655	__IO uint32_t PUCRD; /!< Pull_up control register of portD, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	656	__IO uint32_t PDCRD; /!< Pull_Down control register of portD, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	657	__IO uint32_t PUCRE; /!< Pull_up control register of portE, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	658	__IO uint32_t PDCRE; /!< Pull_Down control register of portE, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	659	__IO uint32_t PUCRF; /!< Pull_up control register of portF, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	660	__IO uint32_t PDCRF; /!< Pull_Down control register of portF, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	661	__IO uint32_t PUCRG; /!< Pull_up control register of portG, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	662	__IO uint32_t PDCRG; /!< Pull_Down control register of portG, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	663	__IO uint32_t PUCRH; /!< Pull_up control register of portH, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	664	__IO uint32_t PDCRH; /!< Pull_Down control register of portH, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	665	} PWR_TypeDef;
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/**
bogdanm	0:9b334a45a8ff	669	* @brief QUAD Serial Peripheral Interface
bogdanm	0:9b334a45a8ff	670	*/
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	typedef struct
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	675	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	676	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	677	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	678	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	679	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	680	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	681	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	682	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	683	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	684	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	685	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	686	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	687	} QUADSPI_TypeDef;
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/**
bogdanm	0:9b334a45a8ff	691	* @brief Reset and Clock Control
bogdanm	0:9b334a45a8ff	692	*/
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	typedef struct
bogdanm	0:9b334a45a8ff	695	{
bogdanm	0:9b334a45a8ff	696	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	697	__IO uint32_t ICSCR; /!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	698	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	699	__IO uint32_t PLLCFGR; /!< RCC System PLL configuration register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	700	__IO uint32_t PLLSAI1CFGR; /!< RCC PLL SAI1 Configuration Register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	701	__IO uint32_t PLLSAI2CFGR; /!< RCC PLL SAI2 Configuration Register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	702	__IO uint32_t CIER; /!< RCC Clock Interrupt Enable Register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	703	__IO uint32_t CIFR; /!< RCC Clock Interrupt Flag Register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	704	__IO uint32_t CICR; /!< RCC Clock Interrupt Clear Register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	705	uint32_t RESERVED0; /!< Reserved, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	706	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	707	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	708	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	709	uint32_t RESERVED1; /!< Reserved, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	710	__IO uint32_t APB1RSTR1; /!< RCC LowSpeed APB1 macrocells resets Low Word, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	711	__IO uint32_t APB1RSTR2; /!< RCC LowSpeed APB1 macrocells resets High Word, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	712	__IO uint32_t APB2RSTR; /!< RCC High Speed APB macrocells resets, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	713	uint32_t RESERVED2; /!< Reserved, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	714	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock enable register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	715	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock enable register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	716	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock enable register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	717	uint32_t RESERVED3; /!< Reserved, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	718	__IO uint32_t APB1ENR1; /!< RCC LowSpeed APB1 macrocells clock enables Low Word, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	719	__IO uint32_t APB1ENR2; /!< RCC LowSpeed APB1 macrocells clock enables High Word, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	720	__IO uint32_t APB2ENR; /!< RCC High Speed APB macrocells clock enabled, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	721	uint32_t RESERVED4; /!< Reserved, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	722	__IO uint32_t AHB1SMENR; /!< RCC AHB1 macrocells clocks enables in sleep mode, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	723	__IO uint32_t AHB2SMENR; /!< RCC AHB2 macrocells clock enables in sleep mode, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	724	__IO uint32_t AHB3SMENR; /!< RCC AHB3 macrocells clock enables in sleep mode, Address offset: 0x70 /
bogdanm	0:9b334a45a8ff	725	uint32_t RESERVED5; /!< Reserved, Address offset: 0x74 /
bogdanm	0:9b334a45a8ff	726	__IO uint32_t APB1SMENR1; /!< RCC LowSpeed APB1 macrocells clock enables in sleep mode Low Word, Address offset: 0x78 /
bogdanm	0:9b334a45a8ff	727	__IO uint32_t APB1SMENR2; /!< RCC LowSpeed APB1 macrocells clock enables in sleep mode High Word, Address offset: 0x7C /
bogdanm	0:9b334a45a8ff	728	__IO uint32_t APB2SMENR; /!< RCC High Speed APB macrocells clock enabled in sleep mode, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	729	uint32_t RESERVED6; /!< Reserved, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	730	__IO uint32_t CCIPR; /!< RCC IPs Clocks Configuration Register, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	731	__IO uint32_t RESERVED7; /!< Reserved, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	732	__IO uint32_t BDCR; /!< RCC Vswitch Backup Domain Control Register, Address offset: 0x90 /
bogdanm	0:9b334a45a8ff	733	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x94 /
bogdanm	0:9b334a45a8ff	734	} RCC_TypeDef;
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/**
bogdanm	0:9b334a45a8ff	737	* @brief Real-Time Clock
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	typedef struct
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	743	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	744	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	745	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	746	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	747	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	748	uint32_t reserved; /!< Reserved /
bogdanm	0:9b334a45a8ff	749	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	750	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	751	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	752	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	753	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	754	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	755	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	756	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	757	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	758	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	759	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	760	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	761	__IO uint32_t OR; /!< RTC option register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	762	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	763	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	764	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	765	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	766	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	767	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	768	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	769	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
bogdanm	0:9b334a45a8ff	770	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
bogdanm	0:9b334a45a8ff	771	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
bogdanm	0:9b334a45a8ff	772	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
bogdanm	0:9b334a45a8ff	773	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
bogdanm	0:9b334a45a8ff	774	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	775	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	776	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	777	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	778	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
bogdanm	0:9b334a45a8ff	779	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
bogdanm	0:9b334a45a8ff	780	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
bogdanm	0:9b334a45a8ff	781	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
bogdanm	0:9b334a45a8ff	782	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
bogdanm	0:9b334a45a8ff	783	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
bogdanm	0:9b334a45a8ff	784	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
bogdanm	0:9b334a45a8ff	785	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
bogdanm	0:9b334a45a8ff	786	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
bogdanm	0:9b334a45a8ff	787	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
bogdanm	0:9b334a45a8ff	788	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
bogdanm	0:9b334a45a8ff	789	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
bogdanm	0:9b334a45a8ff	790	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
bogdanm	0:9b334a45a8ff	791	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
bogdanm	0:9b334a45a8ff	792	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
bogdanm	0:9b334a45a8ff	793	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
bogdanm	0:9b334a45a8ff	794	} RTC_TypeDef;
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/**
bogdanm	0:9b334a45a8ff	798	* @brief Serial Audio Interface
bogdanm	0:9b334a45a8ff	799	*/
bogdanm	0:9b334a45a8ff	800
bogdanm	0:9b334a45a8ff	801	typedef struct
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	804	} SAI_TypeDef;
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	typedef struct
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	809	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	810	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	811	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	812	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	813	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	814	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	815	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	816	} SAI_Block_TypeDef;
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	/**
bogdanm	0:9b334a45a8ff	820	* @brief Secure digital input/output Interface
bogdanm	0:9b334a45a8ff	821	*/
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	typedef struct
bogdanm	0:9b334a45a8ff	824	{
bogdanm	0:9b334a45a8ff	825	__IO uint32_t POWER; /!< SDMMC power control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	826	__IO uint32_t CLKCR; /!< SDMMC clock control register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	827	__IO uint32_t ARG; /!< SDMMC argument register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	828	__IO uint32_t CMD; /!< SDMMC command register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	829	__I uint32_t RESPCMD; /!< SDMMC command response register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	830	__I uint32_t RESP1; /!< SDMMC response 1 register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	831	__I uint32_t RESP2; /!< SDMMC response 2 register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	832	__I uint32_t RESP3; /!< SDMMC response 3 register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	833	__I uint32_t RESP4; /!< SDMMC response 4 register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	834	__IO uint32_t DTIMER; /!< SDMMC data timer register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	835	__IO uint32_t DLEN; /!< SDMMC data length register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	836	__IO uint32_t DCTRL; /!< SDMMC data control register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	837	__I uint32_t DCOUNT; /!< SDMMC data counter register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	838	__I uint32_t STA; /!< SDMMC status register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	839	__IO uint32_t ICR; /!< SDMMC interrupt clear register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	840	__IO uint32_t MASK; /!< SDMMC mask register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	841	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
bogdanm	0:9b334a45a8ff	842	__I uint32_t FIFOCNT; /!< SDMMC FIFO counter register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	843	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
bogdanm	0:9b334a45a8ff	844	__IO uint32_t FIFO; /!< SDMMC data FIFO register, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	845	} SDMMC_TypeDef;
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	/**
bogdanm	0:9b334a45a8ff	849	* @brief Serial Peripheral Interface
bogdanm	0:9b334a45a8ff	850	*/
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	typedef struct
bogdanm	0:9b334a45a8ff	853	{
bogdanm	0:9b334a45a8ff	854	__IO uint32_t CR1; /!< SPI Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	855	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	856	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	857	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	858	__IO uint32_t CRCPR; /!< SPI CRC polynomial register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	859	__IO uint32_t RXCRCR; /!< SPI Rx CRC register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	860	__IO uint32_t TXCRCR; /!< SPI Tx CRC register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	861	uint32_t RESERVED1; /!< Reserved, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	862	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	863	} SPI_TypeDef;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	/**
bogdanm	0:9b334a45a8ff	867	* @brief Single Wire Protocol Master Interface SPWMI
bogdanm	0:9b334a45a8ff	868	*/
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	typedef struct
bogdanm	0:9b334a45a8ff	871	{
bogdanm	0:9b334a45a8ff	872	__IO uint32_t CR; /!< SWPMI Configuration/Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	873	__IO uint32_t BRR; /!< SWPMI bitrate register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	874	uint32_t RESERVED1; /!< Reserved, 0x08 /
bogdanm	0:9b334a45a8ff	875	__IO uint32_t ISR; /!< SWPMI Interrupt and Status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	876	__IO uint32_t ICR; /!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	877	__IO uint32_t IER; /!< SWPMI Interrupt Enable register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	878	__IO uint32_t RFL; /!< SWPMI Receive Frame Length register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	879	__IO uint32_t TDR; /!< SWPMI Transmit data register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	880	__IO uint32_t RDR; /!< SWPMI Receive data register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	881	__IO uint32_t OR; /!< SWPMI Option register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	882	} SWPMI_TypeDef;
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/**
bogdanm	0:9b334a45a8ff	886	* @brief System configuration controller
bogdanm	0:9b334a45a8ff	887	*/
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	typedef struct
bogdanm	0:9b334a45a8ff	890	{
bogdanm	0:9b334a45a8ff	891	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	892	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	893	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
bogdanm	0:9b334a45a8ff	894	__IO uint32_t SCSR; /!< SYSCFG SRAM2 control and status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	895	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	896	__IO uint32_t SWPR; /!< SYSCFG SRAM2 write protection register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	897	__IO uint32_t SKR; /!< SYSCFG SRAM2 key register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	898	} SYSCFG_TypeDef;
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/**
bogdanm	0:9b334a45a8ff	902	* @brief TIM
bogdanm	0:9b334a45a8ff	903	*/
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	typedef struct
bogdanm	0:9b334a45a8ff	906	{
bogdanm	0:9b334a45a8ff	907	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	908	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	909	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	910	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	911	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	912	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	913	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	914	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	915	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	916	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	917	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	918	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	919	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	920	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	921	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	922	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	923	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	924	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	925	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	926	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	927	__IO uint32_t OR1; /!< TIM option register 1, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	928	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	929	__IO uint32_t CCR5; /!< TIM capture/compare register5, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	930	__IO uint32_t CCR6; /!< TIM capture/compare register6, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	931	__IO uint32_t OR2; /!< TIM option register 2, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	932	__IO uint32_t OR3; /!< TIM option register 3, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	933	} TIM_TypeDef;
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/**
bogdanm	0:9b334a45a8ff	937	* @brief Touch Sensing Controller (TSC)
bogdanm	0:9b334a45a8ff	938	*/
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	typedef struct
bogdanm	0:9b334a45a8ff	941	{
bogdanm	0:9b334a45a8ff	942	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	943	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	944	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	945	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	946	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	947	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	948	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	949	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	950	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	951	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	952	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	953	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	954	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	955	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
bogdanm	0:9b334a45a8ff	956	} TSC_TypeDef;
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/**
bogdanm	0:9b334a45a8ff	960	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	0:9b334a45a8ff	961	*/
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	typedef struct
bogdanm	0:9b334a45a8ff	964	{
bogdanm	0:9b334a45a8ff	965	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	966	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	967	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	968	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	969	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	970	uint16_t RESERVED2; /!< Reserved, 0x12 /
bogdanm	0:9b334a45a8ff	971	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	972	__IO uint16_t RQR; /!< USART Request register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	973	uint16_t RESERVED3; /!< Reserved, 0x1A /
bogdanm	0:9b334a45a8ff	974	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	975	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	976	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	977	uint16_t RESERVED4; /!< Reserved, 0x26 /
bogdanm	0:9b334a45a8ff	978	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	979	uint16_t RESERVED5; /!< Reserved, 0x2A /
bogdanm	0:9b334a45a8ff	980	} USART_TypeDef;
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/**
bogdanm	0:9b334a45a8ff	984	* @brief VREFBUF
bogdanm	0:9b334a45a8ff	985	*/
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	typedef struct
bogdanm	0:9b334a45a8ff	988	{
bogdanm	0:9b334a45a8ff	989	__IO uint32_t CSR; /!< VREFBUF control and status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	990	__IO uint32_t CCR; /!< VREFBUF calibration and control register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	991	} VREFBUF_TypeDef;
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/**
bogdanm	0:9b334a45a8ff	994	* @brief Window WATCHDOG
bogdanm	0:9b334a45a8ff	995	*/
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	typedef struct
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	1000	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	1001	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	1002	} WWDG_TypeDef;
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	/**
bogdanm	0:9b334a45a8ff	1007	* @brief RNG
bogdanm	0:9b334a45a8ff	1008	*/
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	typedef struct
bogdanm	0:9b334a45a8ff	1011	{
bogdanm	0:9b334a45a8ff	1012	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	1013	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	1014	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	1015	} RNG_TypeDef;
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/**
bogdanm	0:9b334a45a8ff	1018	* @brief USB_OTG_Core_register
bogdanm	0:9b334a45a8ff	1019	*/
bogdanm	0:9b334a45a8ff	1020	typedef struct
bogdanm	0:9b334a45a8ff	1021	{
bogdanm	0:9b334a45a8ff	1022	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h/
bogdanm	0:9b334a45a8ff	1023	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h/
bogdanm	0:9b334a45a8ff	1024	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h/
bogdanm	0:9b334a45a8ff	1025	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch/
bogdanm	0:9b334a45a8ff	1026	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h/
bogdanm	0:9b334a45a8ff	1027	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h/
bogdanm	0:9b334a45a8ff	1028	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h/
bogdanm	0:9b334a45a8ff	1029	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch/
bogdanm	0:9b334a45a8ff	1030	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h/
bogdanm	0:9b334a45a8ff	1031	__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
bogdanm	0:9b334a45a8ff	1032	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h/
bogdanm	0:9b334a45a8ff	1033	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch/
bogdanm	0:9b334a45a8ff	1034	uint32_t Reserved30[2]; /* Reserved 030h*/
bogdanm	0:9b334a45a8ff	1035	__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
bogdanm	0:9b334a45a8ff	1036	__IO uint32_t CID; /* User ID Register 03Ch*/
bogdanm	0:9b334a45a8ff	1037	uint32_t Reserved5[3]; /* Reserved 040h-048h*/
bogdanm	0:9b334a45a8ff	1038	__IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
bogdanm	0:9b334a45a8ff	1039	uint32_t Reserved6; /* Reserved 050h*/
bogdanm	0:9b334a45a8ff	1040	__IO uint32_t GLPMCFG; /* LPM Register 054h*/
bogdanm	0:9b334a45a8ff	1041	__IO uint32_t GPWRDN; /* Power Down Register 058h*/
bogdanm	0:9b334a45a8ff	1042	__IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
bogdanm	0:9b334a45a8ff	1043	__IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
bogdanm	0:9b334a45a8ff	1044	uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
bogdanm	0:9b334a45a8ff	1045	__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
bogdanm	0:9b334a45a8ff	1046	__IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
bogdanm	0:9b334a45a8ff	1047	} USB_OTG_GlobalTypeDef;
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/**
bogdanm	0:9b334a45a8ff	1050	* @brief USB_OTG_device_Registers
bogdanm	0:9b334a45a8ff	1051	*/
bogdanm	0:9b334a45a8ff	1052	typedef struct
bogdanm	0:9b334a45a8ff	1053	{
bogdanm	0:9b334a45a8ff	1054	__IO uint32_t DCFG; /* dev Configuration Register 800h*/
bogdanm	0:9b334a45a8ff	1055	__IO uint32_t DCTL; /* dev Control Register 804h*/
bogdanm	0:9b334a45a8ff	1056	__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
bogdanm	0:9b334a45a8ff	1057	uint32_t Reserved0C; /* Reserved 80Ch*/
bogdanm	0:9b334a45a8ff	1058	__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
bogdanm	0:9b334a45a8ff	1059	__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
bogdanm	0:9b334a45a8ff	1060	__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
bogdanm	0:9b334a45a8ff	1061	__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
bogdanm	0:9b334a45a8ff	1062	uint32_t Reserved20; /* Reserved 820h*/
bogdanm	0:9b334a45a8ff	1063	uint32_t Reserved9; /* Reserved 824h*/
bogdanm	0:9b334a45a8ff	1064	__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
bogdanm	0:9b334a45a8ff	1065	__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
bogdanm	0:9b334a45a8ff	1066	__IO uint32_t DTHRCTL; /* dev thr 830h*/
bogdanm	0:9b334a45a8ff	1067	__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
bogdanm	0:9b334a45a8ff	1068	__IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
bogdanm	0:9b334a45a8ff	1069	__IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
bogdanm	0:9b334a45a8ff	1070	uint32_t Reserved40; /* dedicated EP mask 840h*/
bogdanm	0:9b334a45a8ff	1071	__IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
bogdanm	0:9b334a45a8ff	1072	uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
bogdanm	0:9b334a45a8ff	1073	__IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
bogdanm	0:9b334a45a8ff	1074	} USB_OTG_DeviceTypeDef;
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/**
bogdanm	0:9b334a45a8ff	1077	* @brief USB_OTG_IN_Endpoint-Specific_Register
bogdanm	0:9b334a45a8ff	1078	*/
bogdanm	0:9b334a45a8ff	1079	typedef struct
bogdanm	0:9b334a45a8ff	1080	{
bogdanm	0:9b334a45a8ff	1081	__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
bogdanm	0:9b334a45a8ff	1082	uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
bogdanm	0:9b334a45a8ff	1083	__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
bogdanm	0:9b334a45a8ff	1084	uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
bogdanm	0:9b334a45a8ff	1085	__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
bogdanm	0:9b334a45a8ff	1086	__IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
bogdanm	0:9b334a45a8ff	1087	__IO uint32_t DTXFSTS; /IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h*/
bogdanm	0:9b334a45a8ff	1088	uint32_t Reserved18; /* Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num 20h) + 1Ch*/
bogdanm	0:9b334a45a8ff	1089	} USB_OTG_INEndpointTypeDef;
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/**
bogdanm	0:9b334a45a8ff	1092	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
bogdanm	0:9b334a45a8ff	1093	*/
bogdanm	0:9b334a45a8ff	1094	typedef struct
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
bogdanm	0:9b334a45a8ff	1097	uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
bogdanm	0:9b334a45a8ff	1098	__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
bogdanm	0:9b334a45a8ff	1099	uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
bogdanm	0:9b334a45a8ff	1100	__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
bogdanm	0:9b334a45a8ff	1101	__IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
bogdanm	0:9b334a45a8ff	1102	uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
bogdanm	0:9b334a45a8ff	1103	} USB_OTG_OUTEndpointTypeDef;
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief USB_OTG_Host_Mode_Register_Structures
bogdanm	0:9b334a45a8ff	1107	*/
bogdanm	0:9b334a45a8ff	1108	typedef struct
bogdanm	0:9b334a45a8ff	1109	{
bogdanm	0:9b334a45a8ff	1110	__IO uint32_t HCFG; /* Host Configuration Register 400h*/
bogdanm	0:9b334a45a8ff	1111	__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
bogdanm	0:9b334a45a8ff	1112	__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
bogdanm	0:9b334a45a8ff	1113	uint32_t Reserved40C; /* Reserved 40Ch*/
bogdanm	0:9b334a45a8ff	1114	__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
bogdanm	0:9b334a45a8ff	1115	__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
bogdanm	0:9b334a45a8ff	1116	__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
bogdanm	0:9b334a45a8ff	1117	} USB_OTG_HostTypeDef;
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/**
bogdanm	0:9b334a45a8ff	1120	* @brief USB_OTG_Host_Channel_Specific_Registers
bogdanm	0:9b334a45a8ff	1121	*/
bogdanm	0:9b334a45a8ff	1122	typedef struct
bogdanm	0:9b334a45a8ff	1123	{
bogdanm	0:9b334a45a8ff	1124	__IO uint32_t HCCHAR;
bogdanm	0:9b334a45a8ff	1125	__IO uint32_t HCSPLT;
bogdanm	0:9b334a45a8ff	1126	__IO uint32_t HCINT;
bogdanm	0:9b334a45a8ff	1127	__IO uint32_t HCINTMSK;
bogdanm	0:9b334a45a8ff	1128	__IO uint32_t HCTSIZ;
bogdanm	0:9b334a45a8ff	1129	__IO uint32_t HCDMA;
bogdanm	0:9b334a45a8ff	1130	uint32_t Reserved[2];
bogdanm	0:9b334a45a8ff	1131	} USB_OTG_HostChannelTypeDef;
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/**
bogdanm	0:9b334a45a8ff	1134	* @}
bogdanm	0:9b334a45a8ff	1135	*/
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/** @addtogroup Peripheral_memory_map
bogdanm	0:9b334a45a8ff	1138	* @{
bogdanm	0:9b334a45a8ff	1139	*/
bogdanm	0:9b334a45a8ff	1140	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH(up to 1 MB) base address /
bogdanm	0:9b334a45a8ff	1141	#define SRAM1_BASE ((uint32_t)0x20000000) /!< SRAM1(96 KB) base address/
bogdanm	0:9b334a45a8ff	1142	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address /
bogdanm	0:9b334a45a8ff	1143	#define FMC_BASE ((uint32_t)0x60000000) /!< FMC base address /
bogdanm	0:9b334a45a8ff	1144	#define SRAM2_BASE ((uint32_t)0x10000000) /!< SRAM2(32 KB) base address/
bogdanm	0:9b334a45a8ff	1145	#define FMC_R_BASE ((uint32_t)0xA0000000) /!< FMC control registers base address /
bogdanm	0:9b334a45a8ff	1146	#define QSPI_R_BASE ((uint32_t)0xA0001000) /!< QUADSPI control registers base address /
bogdanm	0:9b334a45a8ff	1147	#define SRAM1_BB_BASE ((uint32_t)0x22000000) /!< SRAM1(96 KB) base address in the bit-band region /
bogdanm	0:9b334a45a8ff	1148	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
bogdanm	0:9b334a45a8ff	1149	#define SRAM2_BB_BASE ((uint32_t)0x12000000) /!< SRAM2(32 KB) base address in the bit-band region /
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Legacy defines */
bogdanm	0:9b334a45a8ff	1152	#define SRAM_BASE SRAM1_BASE
bogdanm	0:9b334a45a8ff	1153	#define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	#define SRAM1_SIZE_MAX ((uint32_t)0x00018000) /!< maximum SRAM1 size (up to 96 KBytes) /
bogdanm	0:9b334a45a8ff	1156	#define SRAM2_SIZE ((uint32_t)0x00008000) /!< SRAM2 size (32 KBytes) /
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	/!< Peripheral memory map /
bogdanm	0:9b334a45a8ff	1159	#define APB1PERIPH_BASE PERIPH_BASE
bogdanm	0:9b334a45a8ff	1160	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm	0:9b334a45a8ff	1161	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm	0:9b334a45a8ff	1162	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	#define FMC_BANK1 FMC_BASE
bogdanm	0:9b334a45a8ff	1165	#define FMC_BANK1_1 FMC_BANK1
bogdanm	0:9b334a45a8ff	1166	#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000)
bogdanm	0:9b334a45a8ff	1167	#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000)
bogdanm	0:9b334a45a8ff	1168	#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000)
bogdanm	0:9b334a45a8ff	1169	#define FMC_BANK3 (FMC_BASE + 0x20000000)
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/!< APB1 peripherals /
bogdanm	0:9b334a45a8ff	1172	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1173	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1174	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm	0:9b334a45a8ff	1175	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm	0:9b334a45a8ff	1176	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	1177	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm	0:9b334a45a8ff	1178	#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
bogdanm	0:9b334a45a8ff	1179	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm	0:9b334a45a8ff	1180	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm	0:9b334a45a8ff	1181	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	1182	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm	0:9b334a45a8ff	1183	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm	0:9b334a45a8ff	1184	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm	0:9b334a45a8ff	1185	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm	0:9b334a45a8ff	1186	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm	0:9b334a45a8ff	1187	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm	0:9b334a45a8ff	1188	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm	0:9b334a45a8ff	1189	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm	0:9b334a45a8ff	1190	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm	0:9b334a45a8ff	1191	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm	0:9b334a45a8ff	1192	#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00)
bogdanm	0:9b334a45a8ff	1193	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm	0:9b334a45a8ff	1194	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm	0:9b334a45a8ff	1195	#define DAC1_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm	0:9b334a45a8ff	1196	#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm	0:9b334a45a8ff	1197	#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm	0:9b334a45a8ff	1198	#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810)
bogdanm	0:9b334a45a8ff	1199	#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000)
bogdanm	0:9b334a45a8ff	1200	#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800)
bogdanm	0:9b334a45a8ff	1201	#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400)
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203
bogdanm	0:9b334a45a8ff	1204	/!< APB2 peripherals /
bogdanm	0:9b334a45a8ff	1205	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1206	#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030)
bogdanm	0:9b334a45a8ff	1207	#define COMP1_BASE (APB2PERIPH_BASE + 0x0200)
bogdanm	0:9b334a45a8ff	1208	#define COMP2_BASE (APB2PERIPH_BASE + 0x0204)
bogdanm	0:9b334a45a8ff	1209	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1210	#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00)
bogdanm	0:9b334a45a8ff	1211	#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800)
bogdanm	0:9b334a45a8ff	1212	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm	0:9b334a45a8ff	1213	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	1214	#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
bogdanm	0:9b334a45a8ff	1215	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm	0:9b334a45a8ff	1216	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm	0:9b334a45a8ff	1217	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm	0:9b334a45a8ff	1218	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm	0:9b334a45a8ff	1219	#define SAI1_BASE (APB2PERIPH_BASE + 0x5400)
bogdanm	0:9b334a45a8ff	1220	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
bogdanm	0:9b334a45a8ff	1221	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
bogdanm	0:9b334a45a8ff	1222	#define SAI2_BASE (APB2PERIPH_BASE + 0x5800)
bogdanm	0:9b334a45a8ff	1223	#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
bogdanm	0:9b334a45a8ff	1224	#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
bogdanm	0:9b334a45a8ff	1225	#define DFSDM_BASE (APB2PERIPH_BASE + 0x6000)
bogdanm	0:9b334a45a8ff	1226	#define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00)
bogdanm	0:9b334a45a8ff	1227	#define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20)
bogdanm	0:9b334a45a8ff	1228	#define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40)
bogdanm	0:9b334a45a8ff	1229	#define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60)
bogdanm	0:9b334a45a8ff	1230	#define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80)
bogdanm	0:9b334a45a8ff	1231	#define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0)
bogdanm	0:9b334a45a8ff	1232	#define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0)
bogdanm	0:9b334a45a8ff	1233	#define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0)
bogdanm	0:9b334a45a8ff	1234	#define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100)
bogdanm	0:9b334a45a8ff	1235	#define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180)
bogdanm	0:9b334a45a8ff	1236	#define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200)
bogdanm	0:9b334a45a8ff	1237	#define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280)
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	/!< AHB1 peripherals /
bogdanm	0:9b334a45a8ff	1240	#define DMA1_BASE (AHB1PERIPH_BASE)
bogdanm	0:9b334a45a8ff	1241	#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1242	#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	1243	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000)
bogdanm	0:9b334a45a8ff	1244	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	1245	#define TSC_BASE (AHB1PERIPH_BASE + 0x4000)
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
bogdanm	0:9b334a45a8ff	1249	#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
bogdanm	0:9b334a45a8ff	1250	#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
bogdanm	0:9b334a45a8ff	1251	#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
bogdanm	0:9b334a45a8ff	1252	#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
bogdanm	0:9b334a45a8ff	1253	#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
bogdanm	0:9b334a45a8ff	1254	#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
bogdanm	0:9b334a45a8ff	1255	#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8)
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
bogdanm	0:9b334a45a8ff	1259	#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
bogdanm	0:9b334a45a8ff	1260	#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
bogdanm	0:9b334a45a8ff	1261	#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
bogdanm	0:9b334a45a8ff	1262	#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
bogdanm	0:9b334a45a8ff	1263	#define DMA2_Channel6_BASE (DMA2_BASE + 0x006C)
bogdanm	0:9b334a45a8ff	1264	#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080)
bogdanm	0:9b334a45a8ff	1265	#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8)
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/!< AHB2 peripherals /
bogdanm	0:9b334a45a8ff	1269	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1270	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1271	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
bogdanm	0:9b334a45a8ff	1272	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
bogdanm	0:9b334a45a8ff	1273	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	1274	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
bogdanm	0:9b334a45a8ff	1275	#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800)
bogdanm	0:9b334a45a8ff	1276	#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00)
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000)
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000)
bogdanm	0:9b334a45a8ff	1281	#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100)
bogdanm	0:9b334a45a8ff	1282	#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200)
bogdanm	0:9b334a45a8ff	1283	#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300)
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800)
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/!< FMC Banks registers base address /
bogdanm	0:9b334a45a8ff	1288	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1289	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
bogdanm	0:9b334a45a8ff	1290	#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
bogdanm	0:9b334a45a8ff	1291	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
bogdanm	0:9b334a45a8ff	1292	#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	/* Debug MCU registers base address */
bogdanm	0:9b334a45a8ff	1295	#define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	/!< USB registers base address /
bogdanm	0:9b334a45a8ff	1298	#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
bogdanm	0:9b334a45a8ff	1301	#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
bogdanm	0:9b334a45a8ff	1302	#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
bogdanm	0:9b334a45a8ff	1303	#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
bogdanm	0:9b334a45a8ff	1304	#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
bogdanm	0:9b334a45a8ff	1305	#define USB_OTG_HOST_BASE ((uint32_t )0x400)
bogdanm	0:9b334a45a8ff	1306	#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
bogdanm	0:9b334a45a8ff	1307	#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
bogdanm	0:9b334a45a8ff	1308	#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
bogdanm	0:9b334a45a8ff	1309	#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
bogdanm	0:9b334a45a8ff	1310	#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
bogdanm	0:9b334a45a8ff	1311	#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	/**
bogdanm	0:9b334a45a8ff	1314	* @}
bogdanm	0:9b334a45a8ff	1315	*/
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/** @addtogroup Peripheral_declaration
bogdanm	0:9b334a45a8ff	1318	* @{
bogdanm	0:9b334a45a8ff	1319	*/
bogdanm	0:9b334a45a8ff	1320	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	0:9b334a45a8ff	1321	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	0:9b334a45a8ff	1322	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm	0:9b334a45a8ff	1323	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm	0:9b334a45a8ff	1324	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm	0:9b334a45a8ff	1325	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm	0:9b334a45a8ff	1326	#define LCD ((LCD_TypeDef *) LCD_BASE)
bogdanm	0:9b334a45a8ff	1327	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	0:9b334a45a8ff	1328	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	0:9b334a45a8ff	1329	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	0:9b334a45a8ff	1330	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm	0:9b334a45a8ff	1331	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm	0:9b334a45a8ff	1332	#define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm	0:9b334a45a8ff	1333	#define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm	0:9b334a45a8ff	1334	#define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm	0:9b334a45a8ff	1335	#define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm	0:9b334a45a8ff	1336	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	0:9b334a45a8ff	1337	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm	0:9b334a45a8ff	1338	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm	0:9b334a45a8ff	1339	#define CAN ((CAN_TypeDef *) CAN1_BASE)
bogdanm	0:9b334a45a8ff	1340	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm	0:9b334a45a8ff	1341	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
bogdanm	0:9b334a45a8ff	1342	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	0:9b334a45a8ff	1343	#define DAC ((DAC_TypeDef *) DAC1_BASE)
bogdanm	0:9b334a45a8ff	1344	#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
bogdanm	0:9b334a45a8ff	1345	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
bogdanm	0:9b334a45a8ff	1346	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
bogdanm	0:9b334a45a8ff	1347	#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
bogdanm	0:9b334a45a8ff	1348	#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
bogdanm	0:9b334a45a8ff	1349	#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
bogdanm	0:9b334a45a8ff	1350	#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm	0:9b334a45a8ff	1353	#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
bogdanm	0:9b334a45a8ff	1354	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
bogdanm	0:9b334a45a8ff	1355	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm	0:9b334a45a8ff	1356	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	0:9b334a45a8ff	1357	#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
bogdanm	0:9b334a45a8ff	1358	#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
bogdanm	0:9b334a45a8ff	1359	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	0:9b334a45a8ff	1360	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	0:9b334a45a8ff	1361	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm	0:9b334a45a8ff	1362	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	0:9b334a45a8ff	1363	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm	0:9b334a45a8ff	1364	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm	0:9b334a45a8ff	1365	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm	0:9b334a45a8ff	1366	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
bogdanm	0:9b334a45a8ff	1367	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
bogdanm	0:9b334a45a8ff	1368	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
bogdanm	0:9b334a45a8ff	1369	#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
bogdanm	0:9b334a45a8ff	1370	#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
bogdanm	0:9b334a45a8ff	1371	#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
bogdanm	0:9b334a45a8ff	1372	#define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
bogdanm	0:9b334a45a8ff	1373	#define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
bogdanm	0:9b334a45a8ff	1374	#define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
bogdanm	0:9b334a45a8ff	1375	#define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
bogdanm	0:9b334a45a8ff	1376	#define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
bogdanm	0:9b334a45a8ff	1377	#define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
bogdanm	0:9b334a45a8ff	1378	#define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
bogdanm	0:9b334a45a8ff	1379	#define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
bogdanm	0:9b334a45a8ff	1380	#define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
bogdanm	0:9b334a45a8ff	1381	#define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
bogdanm	0:9b334a45a8ff	1382	#define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
bogdanm	0:9b334a45a8ff	1383	#define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
bogdanm	0:9b334a45a8ff	1384	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	0:9b334a45a8ff	1385	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm	0:9b334a45a8ff	1386	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	0:9b334a45a8ff	1387	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	0:9b334a45a8ff	1388	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	0:9b334a45a8ff	1389	#define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm	0:9b334a45a8ff	1390
bogdanm	0:9b334a45a8ff	1391	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	0:9b334a45a8ff	1392	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	0:9b334a45a8ff	1393	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	0:9b334a45a8ff	1394	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm	0:9b334a45a8ff	1395	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm	0:9b334a45a8ff	1396	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm	0:9b334a45a8ff	1397	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm	0:9b334a45a8ff	1398	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm	0:9b334a45a8ff	1399	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	0:9b334a45a8ff	1400	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm	0:9b334a45a8ff	1401	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm	0:9b334a45a8ff	1402	#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
bogdanm	0:9b334a45a8ff	1403	#define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm	0:9b334a45a8ff	1407	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm	0:9b334a45a8ff	1408	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm	0:9b334a45a8ff	1409	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm	0:9b334a45a8ff	1410	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm	0:9b334a45a8ff	1411	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm	0:9b334a45a8ff	1412	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm	0:9b334a45a8ff	1413	#define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
bogdanm	0:9b334a45a8ff	1417	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
bogdanm	0:9b334a45a8ff	1418	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
bogdanm	0:9b334a45a8ff	1419	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
bogdanm	0:9b334a45a8ff	1420	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
bogdanm	0:9b334a45a8ff	1421	#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
bogdanm	0:9b334a45a8ff	1422	#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
bogdanm	0:9b334a45a8ff	1423	#define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
bogdanm	0:9b334a45a8ff	1427	#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
bogdanm	0:9b334a45a8ff	1428	#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
bogdanm	0:9b334a45a8ff	1435	/**
bogdanm	0:9b334a45a8ff	1436	* @}
bogdanm	0:9b334a45a8ff	1437	*/
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/** @addtogroup Exported_constants
bogdanm	0:9b334a45a8ff	1440	* @{
bogdanm	0:9b334a45a8ff	1441	*/
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	0:9b334a45a8ff	1444	* @{
bogdanm	0:9b334a45a8ff	1445	*/
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1448	/* Peripheral Registers_Bits_Definition */
bogdanm	0:9b334a45a8ff	1449	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1452	/* */
bogdanm	0:9b334a45a8ff	1453	/* Analog to Digital Converter */
bogdanm	0:9b334a45a8ff	1454	/* */
bogdanm	0:9b334a45a8ff	1455	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1456	/****************** Bit definition for ADC_ISR register ******************/
bogdanm	0:9b334a45a8ff	1457	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) flag /
bogdanm	0:9b334a45a8ff	1458	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling flag /
bogdanm	0:9b334a45a8ff	1459	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion flag /
bogdanm	0:9b334a45a8ff	1460	#define ADC_ISR_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	1461	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< ADC overrun flag /
bogdanm	0:9b334a45a8ff	1462	#define ADC_ISR_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion flag /
bogdanm	0:9b334a45a8ff	1463	#define ADC_ISR_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	1464	#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 flag /
bogdanm	0:9b334a45a8ff	1465	#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 flag /
bogdanm	0:9b334a45a8ff	1466	#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 flag /
bogdanm	0:9b334a45a8ff	1467	#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow flag /
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	/****************** Bit definition for ADC_IER register ******************/
bogdanm	0:9b334a45a8ff	1470	#define ADC_IER_ADRDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) interrupt source /
bogdanm	0:9b334a45a8ff	1471	#define ADC_IER_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling interrupt source /
bogdanm	0:9b334a45a8ff	1472	#define ADC_IER_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion interrupt source /
bogdanm	0:9b334a45a8ff	1473	#define ADC_IER_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions interrupt source /
bogdanm	0:9b334a45a8ff	1474	#define ADC_IER_OVR ((uint32_t)0x00000010) /!< ADC overrun interrupt source /
bogdanm	0:9b334a45a8ff	1475	#define ADC_IER_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion interrupt source /
bogdanm	0:9b334a45a8ff	1476	#define ADC_IER_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions interrupt source /
bogdanm	0:9b334a45a8ff	1477	#define ADC_IER_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 interrupt source /
bogdanm	0:9b334a45a8ff	1478	#define ADC_IER_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 interrupt source /
bogdanm	0:9b334a45a8ff	1479	#define ADC_IER_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 interrupt source /
bogdanm	0:9b334a45a8ff	1480	#define ADC_IER_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow interrupt source /
bogdanm	0:9b334a45a8ff	1481
bogdanm	0:9b334a45a8ff	1482	/****************** Bit definition for ADC_CR register ******************/
bogdanm	0:9b334a45a8ff	1483	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC Enable control /
bogdanm	0:9b334a45a8ff	1484	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC Disable command /
bogdanm	0:9b334a45a8ff	1485	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC Start of Regular conversion /
bogdanm	0:9b334a45a8ff	1486	#define ADC_CR_JADSTART ((uint32_t)0x00000008) /!< ADC Start of injected conversion /
bogdanm	0:9b334a45a8ff	1487	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC Stop of Regular conversion /
bogdanm	0:9b334a45a8ff	1488	#define ADC_CR_JADSTP ((uint32_t)0x00000020) /!< ADC Stop of injected conversion /
bogdanm	0:9b334a45a8ff	1489	#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /!< ADC Voltage regulator Enable /
bogdanm	0:9b334a45a8ff	1490	#define ADC_CR_DEEPPWD ((uint32_t)0x20000000) /!< ADC Deep power down Enable /
bogdanm	0:9b334a45a8ff	1491	#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /!< ADC Differential Mode for calibration /
bogdanm	0:9b334a45a8ff	1492	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC Calibration /
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/****************** Bit definition for ADC_CFGR register ******************/
bogdanm	0:9b334a45a8ff	1495	#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /!< ADC DMA Enable /
bogdanm	0:9b334a45a8ff	1496	#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /!< ADC DMA configuration /
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	#define ADC_CFGR_RES ((uint32_t)0x00000018) /!< ADC Data resolution /
bogdanm	0:9b334a45a8ff	1499	#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /!< ADC RES bit 0 /
bogdanm	0:9b334a45a8ff	1500	#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /!< ADC RES bit 1 /
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /!< ADC Data Alignement /
bogdanm	0:9b334a45a8ff	1503
bogdanm	0:9b334a45a8ff	1504	#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /!< ADC External trigger selection for regular group /
bogdanm	0:9b334a45a8ff	1505	#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /!< ADC EXTSEL bit 0 /
bogdanm	0:9b334a45a8ff	1506	#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /!< ADC EXTSEL bit 1 /
bogdanm	0:9b334a45a8ff	1507	#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /!< ADC EXTSEL bit 2 /
bogdanm	0:9b334a45a8ff	1508	#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /!< ADC EXTSEL bit 3 /
bogdanm	0:9b334a45a8ff	1509
bogdanm	0:9b334a45a8ff	1510	#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /!< ADC External trigger enable and polarity selection for regular channels /
bogdanm	0:9b334a45a8ff	1511	#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /!< ADC EXTEN bit 0 /
bogdanm	0:9b334a45a8ff	1512	#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /!< ADC EXTEN bit 1 /
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /!< ADC overrun mode /
bogdanm	0:9b334a45a8ff	1515	#define ADC_CFGR_CONT ((uint32_t)0x00002000) /!< ADC Single/continuous conversion mode for regular conversion /
bogdanm	0:9b334a45a8ff	1516	#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /!< ADC Delayed conversion mode /
bogdanm	0:9b334a45a8ff	1517
bogdanm	0:9b334a45a8ff	1518	#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /!< ADC Discontinuous mode for regular channels /
bogdanm	0:9b334a45a8ff	1519
bogdanm	0:9b334a45a8ff	1520	#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /!< ADC Discontinuous mode channel count /
bogdanm	0:9b334a45a8ff	1521	#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /!< ADC DISCNUM bit 0 /
bogdanm	0:9b334a45a8ff	1522	#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /!< ADC DISCNUM bit 1 /
bogdanm	0:9b334a45a8ff	1523	#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /!< ADC DISCNUM bit 2 /
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /!< ADC Discontinuous mode on injected channels /
bogdanm	0:9b334a45a8ff	1526	#define ADC_CFGR_JQM ((uint32_t)0x00200000) /!< ADC JSQR Queue mode /
bogdanm	0:9b334a45a8ff	1527	#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /!< Enable the watchdog 1 on a single channel or on all channels /
bogdanm	0:9b334a45a8ff	1528	#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /!< ADC Analog watchdog 1 enable on regular Channels /
bogdanm	0:9b334a45a8ff	1529	#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /!< ADC Analog watchdog 1 enable on injected Channels /
bogdanm	0:9b334a45a8ff	1530	#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /!< ADC Automatic injected group conversion /
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /!< ADC Analog watchdog 1 Channel selection /
bogdanm	0:9b334a45a8ff	1533	#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /!< ADC AWD1CH bit 0 /
bogdanm	0:9b334a45a8ff	1534	#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /!< ADC AWD1CH bit 1 /
bogdanm	0:9b334a45a8ff	1535	#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /!< ADC AWD1CH bit 2 /
bogdanm	0:9b334a45a8ff	1536	#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /!< ADC AWD1CH bit 3 /
bogdanm	0:9b334a45a8ff	1537	#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /!< ADC AWD1CH bit 4 /
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	#define ADC_CFGR_JQDIS ((uint32_t)0x80000000) /!< ADC Injected queue disable /
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/****************** Bit definition for ADC_CFGR2 register ******************/
bogdanm	0:9b334a45a8ff	1542	#define ADC_CFGR2_ROVSE ((uint32_t)0x00000001) /!< ADC Regular group oversampler enable /
bogdanm	0:9b334a45a8ff	1543	#define ADC_CFGR2_JOVSE ((uint32_t)0x00000002) /!< ADC Injected group oversampler enable /
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /!< ADC Regular group oversampler enable /
bogdanm	0:9b334a45a8ff	1546	#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /!< ADC OVSR bit 0 /
bogdanm	0:9b334a45a8ff	1547	#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /!< ADC OVSR bit 1 /
bogdanm	0:9b334a45a8ff	1548	#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /!< ADC OVSR bit 2 /
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /!< ADC Regular Oversampling shift /
bogdanm	0:9b334a45a8ff	1551	#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /!< ADC OVSS bit 0 /
bogdanm	0:9b334a45a8ff	1552	#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /!< ADC OVSS bit 1 /
bogdanm	0:9b334a45a8ff	1553	#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /!< ADC OVSS bit 2 /
bogdanm	0:9b334a45a8ff	1554	#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /!< ADC OVSS bit 3 /
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	#define ADC_CFGR2_TROVS ((uint32_t)0x00000200) /!< ADC Triggered regular Oversampling /
bogdanm	0:9b334a45a8ff	1557	#define ADC_CFGR2_ROVSM ((uint32_t)0x00000400) /!< ADC Regular oversampling mode /
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	/****************** Bit definition for ADC_SMPR1 register ******************/
bogdanm	0:9b334a45a8ff	1560	#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /!< ADC Channel 0 Sampling time selection /
bogdanm	0:9b334a45a8ff	1561	#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /!< ADC SMP0 bit 0 /
bogdanm	0:9b334a45a8ff	1562	#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /!< ADC SMP0 bit 1 /
bogdanm	0:9b334a45a8ff	1563	#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /!< ADC SMP0 bit 2 /
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565	#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /!< ADC Channel 1 Sampling time selection /
bogdanm	0:9b334a45a8ff	1566	#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /!< ADC SMP1 bit 0 /
bogdanm	0:9b334a45a8ff	1567	#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /!< ADC SMP1 bit 1 /
bogdanm	0:9b334a45a8ff	1568	#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /!< ADC SMP1 bit 2 /
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /!< ADC Channel 2 Sampling time selection /
bogdanm	0:9b334a45a8ff	1571	#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /!< ADC SMP2 bit 0 /
bogdanm	0:9b334a45a8ff	1572	#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /!< ADC SMP2 bit 1 /
bogdanm	0:9b334a45a8ff	1573	#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /!< ADC SMP2 bit 2 /
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /!< ADC Channel 3 Sampling time selection /
bogdanm	0:9b334a45a8ff	1576	#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /!< ADC SMP3 bit 0 /
bogdanm	0:9b334a45a8ff	1577	#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /!< ADC SMP3 bit 1 /
bogdanm	0:9b334a45a8ff	1578	#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /!< ADC SMP3 bit 2 /
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /!< ADC Channel 4 Sampling time selection /
bogdanm	0:9b334a45a8ff	1581	#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /!< ADC SMP4 bit 0 /
bogdanm	0:9b334a45a8ff	1582	#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /!< ADC SMP4 bit 1 /
bogdanm	0:9b334a45a8ff	1583	#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /!< ADC SMP4 bit 2 /
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585	#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /!< ADC Channel 5 Sampling time selection /
bogdanm	0:9b334a45a8ff	1586	#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /!< ADC SMP5 bit 0 /
bogdanm	0:9b334a45a8ff	1587	#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /!< ADC SMP5 bit 1 /
bogdanm	0:9b334a45a8ff	1588	#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /!< ADC SMP5 bit 2 /
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /!< ADC Channel 6 Sampling time selection /
bogdanm	0:9b334a45a8ff	1591	#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /!< ADC SMP6 bit 0 /
bogdanm	0:9b334a45a8ff	1592	#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /!< ADC SMP6 bit 1 /
bogdanm	0:9b334a45a8ff	1593	#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /!< ADC SMP6 bit 2 /
bogdanm	0:9b334a45a8ff	1594
bogdanm	0:9b334a45a8ff	1595	#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /!< ADC Channel 7 Sampling time selection /
bogdanm	0:9b334a45a8ff	1596	#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /!< ADC SMP7 bit 0 /
bogdanm	0:9b334a45a8ff	1597	#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /!< ADC SMP7 bit 1 /
bogdanm	0:9b334a45a8ff	1598	#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /!< ADC SMP7 bit 2 /
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /!< ADC Channel 8 Sampling time selection /
bogdanm	0:9b334a45a8ff	1601	#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /!< ADC SMP8 bit 0 /
bogdanm	0:9b334a45a8ff	1602	#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /!< ADC SMP8 bit 1 /
bogdanm	0:9b334a45a8ff	1603	#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /!< ADC SMP8 bit 2 /
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /!< ADC Channel 9 Sampling time selection /
bogdanm	0:9b334a45a8ff	1606	#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /!< ADC SMP9 bit 0 /
bogdanm	0:9b334a45a8ff	1607	#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /!< ADC SMP9 bit 1 /
bogdanm	0:9b334a45a8ff	1608	#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /!< ADC SMP9 bit 2 /
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	/****************** Bit definition for ADC_SMPR2 register ******************/
bogdanm	0:9b334a45a8ff	1611	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< ADC Channel 10 Sampling time selection /
bogdanm	0:9b334a45a8ff	1612	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< ADC SMP10 bit 0 /
bogdanm	0:9b334a45a8ff	1613	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< ADC SMP10 bit 1 /
bogdanm	0:9b334a45a8ff	1614	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< ADC SMP10 bit 2 /
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< ADC Channel 11 Sampling time selection /
bogdanm	0:9b334a45a8ff	1617	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< ADC SMP11 bit 0 /
bogdanm	0:9b334a45a8ff	1618	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< ADC SMP11 bit 1 /
bogdanm	0:9b334a45a8ff	1619	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< ADC SMP11 bit 2 /
bogdanm	0:9b334a45a8ff	1620
bogdanm	0:9b334a45a8ff	1621	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< ADC Channel 12 Sampling time selection /
bogdanm	0:9b334a45a8ff	1622	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< ADC SMP12 bit 0 /
bogdanm	0:9b334a45a8ff	1623	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< ADC SMP12 bit 1 /
bogdanm	0:9b334a45a8ff	1624	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< ADC SMP12 bit 2 /
bogdanm	0:9b334a45a8ff	1625
bogdanm	0:9b334a45a8ff	1626	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< ADC Channel 13 Sampling time selection /
bogdanm	0:9b334a45a8ff	1627	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< ADC SMP13 bit 0 /
bogdanm	0:9b334a45a8ff	1628	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< ADC SMP13 bit 1 /
bogdanm	0:9b334a45a8ff	1629	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< ADC SMP13 bit 2 /
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< ADC Channel 14 Sampling time selection /
bogdanm	0:9b334a45a8ff	1632	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< ADC SMP14 bit 0 /
bogdanm	0:9b334a45a8ff	1633	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< ADC SMP14 bit 1 /
bogdanm	0:9b334a45a8ff	1634	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< ADC SMP14 bit 2 /
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< ADC Channel 15 Sampling time selection /
bogdanm	0:9b334a45a8ff	1637	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< ADC SMP15 bit 0 /
bogdanm	0:9b334a45a8ff	1638	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< ADC SMP15 bit 1 /
bogdanm	0:9b334a45a8ff	1639	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< ADC SMP15 bit 2 /
bogdanm	0:9b334a45a8ff	1640
bogdanm	0:9b334a45a8ff	1641	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< ADC Channel 16 Sampling time selection /
bogdanm	0:9b334a45a8ff	1642	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< ADC SMP16 bit 0 /
bogdanm	0:9b334a45a8ff	1643	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< ADC SMP16 bit 1 /
bogdanm	0:9b334a45a8ff	1644	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< ADC SMP16 bit 2 /
bogdanm	0:9b334a45a8ff	1645
bogdanm	0:9b334a45a8ff	1646	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< ADC Channel 17 Sampling time selection /
bogdanm	0:9b334a45a8ff	1647	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< ADC SMP17 bit 0 /
bogdanm	0:9b334a45a8ff	1648	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< ADC SMP17 bit 1 /
bogdanm	0:9b334a45a8ff	1649	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< ADC SMP17 bit 2 /
bogdanm	0:9b334a45a8ff	1650
bogdanm	0:9b334a45a8ff	1651	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< ADC Channel 18 Sampling time selection /
bogdanm	0:9b334a45a8ff	1652	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< ADC SMP18 bit 0 /
bogdanm	0:9b334a45a8ff	1653	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< ADC SMP18 bit 1 /
bogdanm	0:9b334a45a8ff	1654	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< ADC SMP18 bit 2 /
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/****************** Bit definition for ADC_TR1 register ******************/
bogdanm	0:9b334a45a8ff	1657	#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /!< ADC Analog watchdog 1 lower threshold /
bogdanm	0:9b334a45a8ff	1658	#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /!< ADC LT1 bit 0 /
bogdanm	0:9b334a45a8ff	1659	#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /!< ADC LT1 bit 1 /
bogdanm	0:9b334a45a8ff	1660	#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /!< ADC LT1 bit 2 /
bogdanm	0:9b334a45a8ff	1661	#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /!< ADC LT1 bit 3 /
bogdanm	0:9b334a45a8ff	1662	#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /!< ADC LT1 bit 4 /
bogdanm	0:9b334a45a8ff	1663	#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /!< ADC LT1 bit 5 /
bogdanm	0:9b334a45a8ff	1664	#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /!< ADC LT1 bit 6 /
bogdanm	0:9b334a45a8ff	1665	#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /!< ADC LT1 bit 7 /
bogdanm	0:9b334a45a8ff	1666	#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /!< ADC LT1 bit 8 /
bogdanm	0:9b334a45a8ff	1667	#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /!< ADC LT1 bit 9 /
bogdanm	0:9b334a45a8ff	1668	#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /!< ADC LT1 bit 10 /
bogdanm	0:9b334a45a8ff	1669	#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /!< ADC LT1 bit 11 /
bogdanm	0:9b334a45a8ff	1670
bogdanm	0:9b334a45a8ff	1671	#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /!< ADC Analog watchdog 1 higher threshold /
bogdanm	0:9b334a45a8ff	1672	#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /!< ADC HT1 bit 0 /
bogdanm	0:9b334a45a8ff	1673	#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /!< ADC HT1 bit 1 /
bogdanm	0:9b334a45a8ff	1674	#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /!< ADC HT1 bit 2 /
bogdanm	0:9b334a45a8ff	1675	#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /!< ADC HT1 bit 3 /
bogdanm	0:9b334a45a8ff	1676	#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /!< ADC HT1 bit 4 /
bogdanm	0:9b334a45a8ff	1677	#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /!< ADC HT1 bit 5 /
bogdanm	0:9b334a45a8ff	1678	#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /!< ADC HT1 bit 6 /
bogdanm	0:9b334a45a8ff	1679	#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /!< ADC HT1 bit 7 /
bogdanm	0:9b334a45a8ff	1680	#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /!< ADC HT1 bit 8 /
bogdanm	0:9b334a45a8ff	1681	#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /!< ADC HT1 bit 9 /
bogdanm	0:9b334a45a8ff	1682	#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /!< ADC HT1 bit 10 /
bogdanm	0:9b334a45a8ff	1683	#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /!< ADC HT1 bit 11 /
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/****************** Bit definition for ADC_TR2 register ******************/
bogdanm	0:9b334a45a8ff	1686	#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 2 lower threshold /
bogdanm	0:9b334a45a8ff	1687	#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /!< ADC LT2 bit 0 /
bogdanm	0:9b334a45a8ff	1688	#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /!< ADC LT2 bit 1 /
bogdanm	0:9b334a45a8ff	1689	#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /!< ADC LT2 bit 2 /
bogdanm	0:9b334a45a8ff	1690	#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /!< ADC LT2 bit 3 /
bogdanm	0:9b334a45a8ff	1691	#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /!< ADC LT2 bit 4 /
bogdanm	0:9b334a45a8ff	1692	#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /!< ADC LT2 bit 5 /
bogdanm	0:9b334a45a8ff	1693	#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /!< ADC LT2 bit 6 /
bogdanm	0:9b334a45a8ff	1694	#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /!< ADC LT2 bit 7 /
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 2 higher threshold /
bogdanm	0:9b334a45a8ff	1697	#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /!< ADC HT2 bit 0 /
bogdanm	0:9b334a45a8ff	1698	#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /!< ADC HT2 bit 1 /
bogdanm	0:9b334a45a8ff	1699	#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /!< ADC HT2 bit 2 /
bogdanm	0:9b334a45a8ff	1700	#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /!< ADC HT2 bit 3 /
bogdanm	0:9b334a45a8ff	1701	#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /!< ADC HT2 bit 4 /
bogdanm	0:9b334a45a8ff	1702	#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /!< ADC HT2 bit 5 /
bogdanm	0:9b334a45a8ff	1703	#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /!< ADC HT2 bit 6 /
bogdanm	0:9b334a45a8ff	1704	#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /!< ADC HT2 bit 7 /
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	/****************** Bit definition for ADC_TR3 register ******************/
bogdanm	0:9b334a45a8ff	1707	#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 3 lower threshold /
bogdanm	0:9b334a45a8ff	1708	#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /!< ADC LT3 bit 0 /
bogdanm	0:9b334a45a8ff	1709	#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /!< ADC LT3 bit 1 /
bogdanm	0:9b334a45a8ff	1710	#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /!< ADC LT3 bit 2 /
bogdanm	0:9b334a45a8ff	1711	#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /!< ADC LT3 bit 3 /
bogdanm	0:9b334a45a8ff	1712	#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /!< ADC LT3 bit 4 /
bogdanm	0:9b334a45a8ff	1713	#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /!< ADC LT3 bit 5 /
bogdanm	0:9b334a45a8ff	1714	#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /!< ADC LT3 bit 6 /
bogdanm	0:9b334a45a8ff	1715	#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /!< ADC LT3 bit 7 /
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 3 higher threshold /
bogdanm	0:9b334a45a8ff	1718	#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /!< ADC HT3 bit 0 /
bogdanm	0:9b334a45a8ff	1719	#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /!< ADC HT3 bit 1 /
bogdanm	0:9b334a45a8ff	1720	#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /!< ADC HT3 bit 2 /
bogdanm	0:9b334a45a8ff	1721	#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /!< ADC HT3 bit 3 /
bogdanm	0:9b334a45a8ff	1722	#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /!< ADC HT3 bit 4 /
bogdanm	0:9b334a45a8ff	1723	#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /!< ADC HT3 bit 5 /
bogdanm	0:9b334a45a8ff	1724	#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /!< ADC HT3 bit 6 /
bogdanm	0:9b334a45a8ff	1725	#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /!< ADC HT3 bit 7 /
bogdanm	0:9b334a45a8ff	1726
bogdanm	0:9b334a45a8ff	1727	/****************** Bit definition for ADC_SQR1 register ******************/
bogdanm	0:9b334a45a8ff	1728	#define ADC_SQR1_L ((uint32_t)0x0000000F) /!< ADC regular channel sequence lenght /
bogdanm	0:9b334a45a8ff	1729	#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /!< ADC L bit 0 /
bogdanm	0:9b334a45a8ff	1730	#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /!< ADC L bit 1 /
bogdanm	0:9b334a45a8ff	1731	#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /!< ADC L bit 2 /
bogdanm	0:9b334a45a8ff	1732	#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /!< ADC L bit 3 /
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /!< ADC 1st conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1735	#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /!< ADC SQ1 bit 0 /
bogdanm	0:9b334a45a8ff	1736	#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /!< ADC SQ1 bit 1 /
bogdanm	0:9b334a45a8ff	1737	#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /!< ADC SQ1 bit 2 /
bogdanm	0:9b334a45a8ff	1738	#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /!< ADC SQ1 bit 3 /
bogdanm	0:9b334a45a8ff	1739	#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /!< ADC SQ1 bit 4 /
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /!< ADC 2nd conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1742	#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /!< ADC SQ2 bit 0 /
bogdanm	0:9b334a45a8ff	1743	#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /!< ADC SQ2 bit 1 /
bogdanm	0:9b334a45a8ff	1744	#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /!< ADC SQ2 bit 2 /
bogdanm	0:9b334a45a8ff	1745	#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /!< ADC SQ2 bit 3 /
bogdanm	0:9b334a45a8ff	1746	#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /!< ADC SQ2 bit 4 /
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /!< ADC 3rd conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1749	#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /!< ADC SQ3 bit 0 /
bogdanm	0:9b334a45a8ff	1750	#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /!< ADC SQ3 bit 1 /
bogdanm	0:9b334a45a8ff	1751	#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /!< ADC SQ3 bit 2 /
bogdanm	0:9b334a45a8ff	1752	#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /!< ADC SQ3 bit 3 /
bogdanm	0:9b334a45a8ff	1753	#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /!< ADC SQ3 bit 4 /
bogdanm	0:9b334a45a8ff	1754
bogdanm	0:9b334a45a8ff	1755	#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /!< ADC 4th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1756	#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /!< ADC SQ4 bit 0 /
bogdanm	0:9b334a45a8ff	1757	#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /!< ADC SQ4 bit 1 /
bogdanm	0:9b334a45a8ff	1758	#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /!< ADC SQ4 bit 2 /
bogdanm	0:9b334a45a8ff	1759	#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /!< ADC SQ4 bit 3 /
bogdanm	0:9b334a45a8ff	1760	#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /!< ADC SQ4 bit 4 /
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762	/****************** Bit definition for ADC_SQR2 register ******************/
bogdanm	0:9b334a45a8ff	1763	#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /!< ADC 5th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1764	#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /!< ADC SQ5 bit 0 /
bogdanm	0:9b334a45a8ff	1765	#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /!< ADC SQ5 bit 1 /
bogdanm	0:9b334a45a8ff	1766	#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /!< ADC SQ5 bit 2 /
bogdanm	0:9b334a45a8ff	1767	#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /!< ADC SQ5 bit 3 /
bogdanm	0:9b334a45a8ff	1768	#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /!< ADC SQ5 bit 4 /
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /!< ADC 6th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1771	#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /!< ADC SQ6 bit 0 /
bogdanm	0:9b334a45a8ff	1772	#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /!< ADC SQ6 bit 1 /
bogdanm	0:9b334a45a8ff	1773	#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /!< ADC SQ6 bit 2 /
bogdanm	0:9b334a45a8ff	1774	#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /!< ADC SQ6 bit 3 /
bogdanm	0:9b334a45a8ff	1775	#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /!< ADC SQ6 bit 4 /
bogdanm	0:9b334a45a8ff	1776
bogdanm	0:9b334a45a8ff	1777	#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /!< ADC 7th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1778	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /!< ADC SQ7 bit 0 /
bogdanm	0:9b334a45a8ff	1779	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /!< ADC SQ7 bit 1 /
bogdanm	0:9b334a45a8ff	1780	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /!< ADC SQ7 bit 2 /
bogdanm	0:9b334a45a8ff	1781	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /!< ADC SQ7 bit 3 /
bogdanm	0:9b334a45a8ff	1782	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /!< ADC SQ7 bit 4 /
bogdanm	0:9b334a45a8ff	1783
bogdanm	0:9b334a45a8ff	1784	#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /!< ADC 8th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1785	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /!< ADC SQ8 bit 0 /
bogdanm	0:9b334a45a8ff	1786	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /!< ADC SQ8 bit 1 /
bogdanm	0:9b334a45a8ff	1787	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /!< ADC SQ8 bit 2 /
bogdanm	0:9b334a45a8ff	1788	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /!< ADC SQ8 bit 3 /
bogdanm	0:9b334a45a8ff	1789	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /!< ADC SQ8 bit 4 /
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /!< ADC 9th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1792	#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /!< ADC SQ9 bit 0 /
bogdanm	0:9b334a45a8ff	1793	#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /!< ADC SQ9 bit 1 /
bogdanm	0:9b334a45a8ff	1794	#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /!< ADC SQ9 bit 2 /
bogdanm	0:9b334a45a8ff	1795	#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /!< ADC SQ9 bit 3 /
bogdanm	0:9b334a45a8ff	1796	#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /!< ADC SQ9 bit 4 /
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	/****************** Bit definition for ADC_SQR3 register ******************/
bogdanm	0:9b334a45a8ff	1799	#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /!< ADC 10th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1800	#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /!< ADC SQ10 bit 0 /
bogdanm	0:9b334a45a8ff	1801	#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /!< ADC SQ10 bit 1 /
bogdanm	0:9b334a45a8ff	1802	#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /!< ADC SQ10 bit 2 /
bogdanm	0:9b334a45a8ff	1803	#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /!< ADC SQ10 bit 3 /
bogdanm	0:9b334a45a8ff	1804	#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /!< ADC SQ10 bit 4 /
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /!< ADC 11th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1807	#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /!< ADC SQ11 bit 0 /
bogdanm	0:9b334a45a8ff	1808	#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /!< ADC SQ11 bit 1 /
bogdanm	0:9b334a45a8ff	1809	#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /!< ADC SQ11 bit 2 /
bogdanm	0:9b334a45a8ff	1810	#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /!< ADC SQ11 bit 3 /
bogdanm	0:9b334a45a8ff	1811	#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /!< ADC SQ11 bit 4 /
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /!< ADC 12th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1814	#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /!< ADC SQ12 bit 0 /
bogdanm	0:9b334a45a8ff	1815	#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /!< ADC SQ12 bit 1 /
bogdanm	0:9b334a45a8ff	1816	#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /!< ADC SQ12 bit 2 /
bogdanm	0:9b334a45a8ff	1817	#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /!< ADC SQ12 bit 3 /
bogdanm	0:9b334a45a8ff	1818	#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /!< ADC SQ12 bit 4 /
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /!< ADC 13th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1821	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /!< ADC SQ13 bit 0 /
bogdanm	0:9b334a45a8ff	1822	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /!< ADC SQ13 bit 1 /
bogdanm	0:9b334a45a8ff	1823	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /!< ADC SQ13 bit 2 /
bogdanm	0:9b334a45a8ff	1824	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /!< ADC SQ13 bit 3 /
bogdanm	0:9b334a45a8ff	1825	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /!< ADC SQ13 bit 4 /
bogdanm	0:9b334a45a8ff	1826
bogdanm	0:9b334a45a8ff	1827	#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /!< ADC 14th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1828	#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /!< ADC SQ14 bit 0 /
bogdanm	0:9b334a45a8ff	1829	#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /!< ADC SQ14 bit 1 /
bogdanm	0:9b334a45a8ff	1830	#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /!< ADC SQ14 bit 2 /
bogdanm	0:9b334a45a8ff	1831	#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /!< ADC SQ14 bit 3 /
bogdanm	0:9b334a45a8ff	1832	#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /!< ADC SQ14 bit 4 /
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/****************** Bit definition for ADC_SQR4 register ******************/
bogdanm	0:9b334a45a8ff	1835	#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /!< ADC 15th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1836	#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /!< ADC SQ15 bit 0 /
bogdanm	0:9b334a45a8ff	1837	#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /!< ADC SQ15 bit 1 /
bogdanm	0:9b334a45a8ff	1838	#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /!< ADC SQ15 bit 2 /
bogdanm	0:9b334a45a8ff	1839	#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /!< ADC SQ15 bit 3 /
bogdanm	0:9b334a45a8ff	1840	#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /!< ADC SQ105 bit 4 /
bogdanm	0:9b334a45a8ff	1841
bogdanm	0:9b334a45a8ff	1842	#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /!< ADC 16th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	1843	#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /!< ADC SQ16 bit 0 /
bogdanm	0:9b334a45a8ff	1844	#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /!< ADC SQ16 bit 1 /
bogdanm	0:9b334a45a8ff	1845	#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /!< ADC SQ16 bit 2 /
bogdanm	0:9b334a45a8ff	1846	#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /!< ADC SQ16 bit 3 /
bogdanm	0:9b334a45a8ff	1847	#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /!< ADC SQ16 bit 4 /
bogdanm	0:9b334a45a8ff	1848
bogdanm	0:9b334a45a8ff	1849	/****************** Bit definition for ADC_DR register ******************/
bogdanm	0:9b334a45a8ff	1850	#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /!< ADC regular Data converted /
bogdanm	0:9b334a45a8ff	1851	#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /!< ADC RDATA bit 0 /
bogdanm	0:9b334a45a8ff	1852	#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /!< ADC RDATA bit 1 /
bogdanm	0:9b334a45a8ff	1853	#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /!< ADC RDATA bit 2 /
bogdanm	0:9b334a45a8ff	1854	#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /!< ADC RDATA bit 3 /
bogdanm	0:9b334a45a8ff	1855	#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /!< ADC RDATA bit 4 /
bogdanm	0:9b334a45a8ff	1856	#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /!< ADC RDATA bit 5 /
bogdanm	0:9b334a45a8ff	1857	#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /!< ADC RDATA bit 6 /
bogdanm	0:9b334a45a8ff	1858	#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /!< ADC RDATA bit 7 /
bogdanm	0:9b334a45a8ff	1859	#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /!< ADC RDATA bit 8 /
bogdanm	0:9b334a45a8ff	1860	#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /!< ADC RDATA bit 9 /
bogdanm	0:9b334a45a8ff	1861	#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /!< ADC RDATA bit 10 /
bogdanm	0:9b334a45a8ff	1862	#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /!< ADC RDATA bit 11 /
bogdanm	0:9b334a45a8ff	1863	#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /!< ADC RDATA bit 12 /
bogdanm	0:9b334a45a8ff	1864	#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /!< ADC RDATA bit 13 /
bogdanm	0:9b334a45a8ff	1865	#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /!< ADC RDATA bit 14 /
bogdanm	0:9b334a45a8ff	1866	#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /!< ADC RDATA bit 15 /
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/****************** Bit definition for ADC_JSQR register ******************/
bogdanm	0:9b334a45a8ff	1869	#define ADC_JSQR_JL ((uint32_t)0x00000003) /!< ADC injected channel sequence length /
bogdanm	0:9b334a45a8ff	1870	#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /!< ADC JL bit 0 /
bogdanm	0:9b334a45a8ff	1871	#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /!< ADC JL bit 1 /
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /!< ADC external trigger selection for injected group /
bogdanm	0:9b334a45a8ff	1874	#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /!< ADC JEXTSEL bit 0 /
bogdanm	0:9b334a45a8ff	1875	#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /!< ADC JEXTSEL bit 1 /
bogdanm	0:9b334a45a8ff	1876	#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /!< ADC JEXTSEL bit 2 /
bogdanm	0:9b334a45a8ff	1877	#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /!< ADC JEXTSEL bit 3 /
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /!< ADC external trigger enable and polarity selection for injected channels /
bogdanm	0:9b334a45a8ff	1880	#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /!< ADC JEXTEN bit 0 /
bogdanm	0:9b334a45a8ff	1881	#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /!< ADC JEXTEN bit 1 /
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /!< ADC 1st conversion in injected sequence /
bogdanm	0:9b334a45a8ff	1884	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /!< ADC JSQ1 bit 0 /
bogdanm	0:9b334a45a8ff	1885	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /!< ADC JSQ1 bit 1 /
bogdanm	0:9b334a45a8ff	1886	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /!< ADC JSQ1 bit 2 /
bogdanm	0:9b334a45a8ff	1887	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /!< ADC JSQ1 bit 3 /
bogdanm	0:9b334a45a8ff	1888	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /!< ADC JSQ1 bit 4 /
bogdanm	0:9b334a45a8ff	1889
bogdanm	0:9b334a45a8ff	1890	#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /!< ADC 2nd conversion in injected sequence /
bogdanm	0:9b334a45a8ff	1891	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /!< ADC JSQ2 bit 0 /
bogdanm	0:9b334a45a8ff	1892	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /!< ADC JSQ2 bit 1 /
bogdanm	0:9b334a45a8ff	1893	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /!< ADC JSQ2 bit 2 /
bogdanm	0:9b334a45a8ff	1894	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /!< ADC JSQ2 bit 3 /
bogdanm	0:9b334a45a8ff	1895	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /!< ADC JSQ2 bit 4 /
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /!< ADC 3rd conversion in injected sequence /
bogdanm	0:9b334a45a8ff	1898	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /!< ADC JSQ3 bit 0 /
bogdanm	0:9b334a45a8ff	1899	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /!< ADC JSQ3 bit 1 /
bogdanm	0:9b334a45a8ff	1900	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /!< ADC JSQ3 bit 2 /
bogdanm	0:9b334a45a8ff	1901	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /!< ADC JSQ3 bit 3 /
bogdanm	0:9b334a45a8ff	1902	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /!< ADC JSQ3 bit 4 /
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /!< ADC 4th conversion in injected sequence /
bogdanm	0:9b334a45a8ff	1905	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /!< ADC JSQ4 bit 0 /
bogdanm	0:9b334a45a8ff	1906	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /!< ADC JSQ4 bit 1 /
bogdanm	0:9b334a45a8ff	1907	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /!< ADC JSQ4 bit 2 /
bogdanm	0:9b334a45a8ff	1908	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /!< ADC JSQ4 bit 3 /
bogdanm	0:9b334a45a8ff	1909	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /!< ADC JSQ4 bit 4 /
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	/****************** Bit definition for ADC_OFR1 register ******************/
bogdanm	0:9b334a45a8ff	1913	#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] /
bogdanm	0:9b334a45a8ff	1914	#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /!< ADC OFFSET1 bit 0 /
bogdanm	0:9b334a45a8ff	1915	#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /!< ADC OFFSET1 bit 1 /
bogdanm	0:9b334a45a8ff	1916	#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /!< ADC OFFSET1 bit 2 /
bogdanm	0:9b334a45a8ff	1917	#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /!< ADC OFFSET1 bit 3 /
bogdanm	0:9b334a45a8ff	1918	#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /!< ADC OFFSET1 bit 4 /
bogdanm	0:9b334a45a8ff	1919	#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /!< ADC OFFSET1 bit 5 /
bogdanm	0:9b334a45a8ff	1920	#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /!< ADC OFFSET1 bit 6 /
bogdanm	0:9b334a45a8ff	1921	#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /!< ADC OFFSET1 bit 7 /
bogdanm	0:9b334a45a8ff	1922	#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /!< ADC OFFSET1 bit 8 /
bogdanm	0:9b334a45a8ff	1923	#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /!< ADC OFFSET1 bit 9 /
bogdanm	0:9b334a45a8ff	1924	#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /!< ADC OFFSET1 bit 10 /
bogdanm	0:9b334a45a8ff	1925	#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /!< ADC OFFSET1 bit 11 /
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 1 /
bogdanm	0:9b334a45a8ff	1928	#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET1_CH bit 0 /
bogdanm	0:9b334a45a8ff	1929	#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET1_CH bit 1 /
bogdanm	0:9b334a45a8ff	1930	#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET1_CH bit 2 /
bogdanm	0:9b334a45a8ff	1931	#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET1_CH bit 3 /
bogdanm	0:9b334a45a8ff	1932	#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET1_CH bit 4 /
bogdanm	0:9b334a45a8ff	1933
bogdanm	0:9b334a45a8ff	1934	#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /!< ADC offset 1 enable /
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	/****************** Bit definition for ADC_OFR2 register ******************/
bogdanm	0:9b334a45a8ff	1937	#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] /
bogdanm	0:9b334a45a8ff	1938	#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /!< ADC OFFSET2 bit 0 /
bogdanm	0:9b334a45a8ff	1939	#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /!< ADC OFFSET2 bit 1 /
bogdanm	0:9b334a45a8ff	1940	#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /!< ADC OFFSET2 bit 2 /
bogdanm	0:9b334a45a8ff	1941	#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /!< ADC OFFSET2 bit 3 /
bogdanm	0:9b334a45a8ff	1942	#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /!< ADC OFFSET2 bit 4 /
bogdanm	0:9b334a45a8ff	1943	#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /!< ADC OFFSET2 bit 5 /
bogdanm	0:9b334a45a8ff	1944	#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /!< ADC OFFSET2 bit 6 /
bogdanm	0:9b334a45a8ff	1945	#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /!< ADC OFFSET2 bit 7 /
bogdanm	0:9b334a45a8ff	1946	#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /!< ADC OFFSET2 bit 8 /
bogdanm	0:9b334a45a8ff	1947	#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /!< ADC OFFSET2 bit 9 /
bogdanm	0:9b334a45a8ff	1948	#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /!< ADC OFFSET2 bit 10 /
bogdanm	0:9b334a45a8ff	1949	#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /!< ADC OFFSET2 bit 11 /
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 2 /
bogdanm	0:9b334a45a8ff	1952	#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET2_CH bit 0 /
bogdanm	0:9b334a45a8ff	1953	#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET2_CH bit 1 /
bogdanm	0:9b334a45a8ff	1954	#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET2_CH bit 2 /
bogdanm	0:9b334a45a8ff	1955	#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET2_CH bit 3 /
bogdanm	0:9b334a45a8ff	1956	#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET2_CH bit 4 /
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /!< ADC offset 2 enable /
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	/****************** Bit definition for ADC_OFR3 register ******************/
bogdanm	0:9b334a45a8ff	1961	#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] /
bogdanm	0:9b334a45a8ff	1962	#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /!< ADC OFFSET3 bit 0 /
bogdanm	0:9b334a45a8ff	1963	#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /!< ADC OFFSET3 bit 1 /
bogdanm	0:9b334a45a8ff	1964	#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /!< ADC OFFSET3 bit 2 /
bogdanm	0:9b334a45a8ff	1965	#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /!< ADC OFFSET3 bit 3 /
bogdanm	0:9b334a45a8ff	1966	#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /!< ADC OFFSET3 bit 4 /
bogdanm	0:9b334a45a8ff	1967	#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /!< ADC OFFSET3 bit 5 /
bogdanm	0:9b334a45a8ff	1968	#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /!< ADC OFFSET3 bit 6 /
bogdanm	0:9b334a45a8ff	1969	#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /!< ADC OFFSET3 bit 7 /
bogdanm	0:9b334a45a8ff	1970	#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /!< ADC OFFSET3 bit 8 /
bogdanm	0:9b334a45a8ff	1971	#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /!< ADC OFFSET3 bit 9 /
bogdanm	0:9b334a45a8ff	1972	#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /!< ADC OFFSET3 bit 10 /
bogdanm	0:9b334a45a8ff	1973	#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /!< ADC OFFSET3 bit 11 /
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 3 /
bogdanm	0:9b334a45a8ff	1976	#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET3_CH bit 0 /
bogdanm	0:9b334a45a8ff	1977	#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET3_CH bit 1 /
bogdanm	0:9b334a45a8ff	1978	#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET3_CH bit 2 /
bogdanm	0:9b334a45a8ff	1979	#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET3_CH bit 3 /
bogdanm	0:9b334a45a8ff	1980	#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET3_CH bit 4 /
bogdanm	0:9b334a45a8ff	1981
bogdanm	0:9b334a45a8ff	1982	#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /!< ADC offset 3 enable /
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/****************** Bit definition for ADC_OFR4 register ******************/
bogdanm	0:9b334a45a8ff	1985	#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] /
bogdanm	0:9b334a45a8ff	1986	#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /!< ADC OFFSET4 bit 0 /
bogdanm	0:9b334a45a8ff	1987	#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /!< ADC OFFSET4 bit 1 /
bogdanm	0:9b334a45a8ff	1988	#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /!< ADC OFFSET4 bit 2 /
bogdanm	0:9b334a45a8ff	1989	#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /!< ADC OFFSET4 bit 3 /
bogdanm	0:9b334a45a8ff	1990	#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /!< ADC OFFSET4 bit 4 /
bogdanm	0:9b334a45a8ff	1991	#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /!< ADC OFFSET4 bit 5 /
bogdanm	0:9b334a45a8ff	1992	#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /!< ADC OFFSET4 bit 6 /
bogdanm	0:9b334a45a8ff	1993	#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /!< ADC OFFSET4 bit 7 /
bogdanm	0:9b334a45a8ff	1994	#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /!< ADC OFFSET4 bit 8 /
bogdanm	0:9b334a45a8ff	1995	#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /!< ADC OFFSET4 bit 9 /
bogdanm	0:9b334a45a8ff	1996	#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /!< ADC OFFSET4 bit 10 /
bogdanm	0:9b334a45a8ff	1997	#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /!< ADC OFFSET4 bit 11 /
bogdanm	0:9b334a45a8ff	1998
bogdanm	0:9b334a45a8ff	1999	#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 4 /
bogdanm	0:9b334a45a8ff	2000	#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET4_CH bit 0 /
bogdanm	0:9b334a45a8ff	2001	#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET4_CH bit 1 /
bogdanm	0:9b334a45a8ff	2002	#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET4_CH bit 2 /
bogdanm	0:9b334a45a8ff	2003	#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET4_CH bit 3 /
bogdanm	0:9b334a45a8ff	2004	#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET4_CH bit 4 /
bogdanm	0:9b334a45a8ff	2005
bogdanm	0:9b334a45a8ff	2006	#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /!< ADC offset 4 enable /
bogdanm	0:9b334a45a8ff	2007
bogdanm	0:9b334a45a8ff	2008	/****************** Bit definition for ADC_JDR1 register ******************/
bogdanm	0:9b334a45a8ff	2009	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	2010	#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	2011	#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	2012	#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	2013	#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	2014	#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	2015	#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	2016	#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	2017	#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	2018	#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	2019	#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	2020	#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	2021	#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	2022	#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	2023	#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	2024	#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	2025	#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	2026
bogdanm	0:9b334a45a8ff	2027	/****************** Bit definition for ADC_JDR2 register ******************/
bogdanm	0:9b334a45a8ff	2028	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	2029	#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	2030	#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	2031	#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	2032	#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	2033	#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	2034	#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	2035	#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	2036	#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	2037	#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	2038	#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	2039	#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	2040	#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	2041	#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	2042	#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	2043	#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	2044	#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	2045
bogdanm	0:9b334a45a8ff	2046	/****************** Bit definition for ADC_JDR3 register ******************/
bogdanm	0:9b334a45a8ff	2047	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	2048	#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	2049	#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	2050	#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	2051	#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	2052	#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	2053	#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	2054	#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	2055	#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	2056	#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	2057	#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	2058	#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	2059	#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	2060	#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	2061	#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	2062	#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	2063	#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	2064
bogdanm	0:9b334a45a8ff	2065	/****************** Bit definition for ADC_JDR4 register ******************/
bogdanm	0:9b334a45a8ff	2066	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	2067	#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	2068	#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	2069	#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	2070	#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	2071	#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	2072	#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	2073	#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	2074	#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	2075	#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	2076	#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	2077	#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	2078	#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	2079	#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	2080	#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	2081	#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	2082	#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	/****************** Bit definition for ADC_AWD2CR register ******************/
bogdanm	0:9b334a45a8ff	2085	#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFF) /!< ADC Analog watchdog 2 channel selection /
bogdanm	0:9b334a45a8ff	2086	#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001) /!< ADC AWD2CH bit 0 /
bogdanm	0:9b334a45a8ff	2087	#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002) /!< ADC AWD2CH bit 1 /
bogdanm	0:9b334a45a8ff	2088	#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004) /!< ADC AWD2CH bit 2 /
bogdanm	0:9b334a45a8ff	2089	#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008) /!< ADC AWD2CH bit 3 /
bogdanm	0:9b334a45a8ff	2090	#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010) /!< ADC AWD2CH bit 4 /
bogdanm	0:9b334a45a8ff	2091	#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020) /!< ADC AWD2CH bit 5 /
bogdanm	0:9b334a45a8ff	2092	#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040) /!< ADC AWD2CH bit 6 /
bogdanm	0:9b334a45a8ff	2093	#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080) /!< ADC AWD2CH bit 7 /
bogdanm	0:9b334a45a8ff	2094	#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100) /!< ADC AWD2CH bit 8 /
bogdanm	0:9b334a45a8ff	2095	#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200) /!< ADC AWD2CH bit 9 /
bogdanm	0:9b334a45a8ff	2096	#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400) /!< ADC AWD2CH bit 10 /
bogdanm	0:9b334a45a8ff	2097	#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800) /!< ADC AWD2CH bit 11 /
bogdanm	0:9b334a45a8ff	2098	#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000) /!< ADC AWD2CH bit 12 /
bogdanm	0:9b334a45a8ff	2099	#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000) /!< ADC AWD2CH bit 13 /
bogdanm	0:9b334a45a8ff	2100	#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000) /!< ADC AWD2CH bit 14 /
bogdanm	0:9b334a45a8ff	2101	#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000) /!< ADC AWD2CH bit 15 /
bogdanm	0:9b334a45a8ff	2102	#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000) /!< ADC AWD2CH bit 16 /
bogdanm	0:9b334a45a8ff	2103	#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000) /!< ADC AWD2CH bit 17 /
bogdanm	0:9b334a45a8ff	2104	#define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000) /!< ADC AWD2CH bit 18 /
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	/****************** Bit definition for ADC_AWD3CR register ******************/
bogdanm	0:9b334a45a8ff	2107	#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFF) /!< ADC Analog watchdog 3 channel selection /
bogdanm	0:9b334a45a8ff	2108	#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001) /!< ADC AWD3CH bit 0 /
bogdanm	0:9b334a45a8ff	2109	#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002) /!< ADC AWD3CH bit 1 /
bogdanm	0:9b334a45a8ff	2110	#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004) /!< ADC AWD3CH bit 2 /
bogdanm	0:9b334a45a8ff	2111	#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008) /!< ADC AWD3CH bit 3 /
bogdanm	0:9b334a45a8ff	2112	#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010) /!< ADC AWD3CH bit 4 /
bogdanm	0:9b334a45a8ff	2113	#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020) /!< ADC AWD3CH bit 5 /
bogdanm	0:9b334a45a8ff	2114	#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040) /!< ADC AWD3CH bit 6 /
bogdanm	0:9b334a45a8ff	2115	#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080) /!< ADC AWD3CH bit 7 /
bogdanm	0:9b334a45a8ff	2116	#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100) /!< ADC AWD3CH bit 8 /
bogdanm	0:9b334a45a8ff	2117	#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200) /!< ADC AWD3CH bit 9 /
bogdanm	0:9b334a45a8ff	2118	#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400) /!< ADC AWD3CH bit 10 /
bogdanm	0:9b334a45a8ff	2119	#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800) /!< ADC AWD3CH bit 11 /
bogdanm	0:9b334a45a8ff	2120	#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000) /!< ADC AWD3CH bit 12 /
bogdanm	0:9b334a45a8ff	2121	#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000) /!< ADC AWD3CH bit 13 /
bogdanm	0:9b334a45a8ff	2122	#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000) /!< ADC AWD3CH bit 14 /
bogdanm	0:9b334a45a8ff	2123	#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000) /!< ADC AWD3CH bit 15 /
bogdanm	0:9b334a45a8ff	2124	#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000) /!< ADC AWD3CH bit 16 /
bogdanm	0:9b334a45a8ff	2125	#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000) /!< ADC AWD3CH bit 17 /
bogdanm	0:9b334a45a8ff	2126	#define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000) /!< ADC AWD3CH bit 18 /
bogdanm	0:9b334a45a8ff	2127
bogdanm	0:9b334a45a8ff	2128	/****************** Bit definition for ADC_DIFSEL register ******************/
bogdanm	0:9b334a45a8ff	2129	#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFF) /!< ADC differential modes for channels 1 to 18 /
bogdanm	0:9b334a45a8ff	2130	#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001) /!< ADC DIFSEL bit 0 /
bogdanm	0:9b334a45a8ff	2131	#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002) /!< ADC DIFSEL bit 1 /
bogdanm	0:9b334a45a8ff	2132	#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004) /!< ADC DIFSEL bit 2 /
bogdanm	0:9b334a45a8ff	2133	#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008) /!< ADC DIFSEL bit 3 /
bogdanm	0:9b334a45a8ff	2134	#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010) /!< ADC DIFSEL bit 4 /
bogdanm	0:9b334a45a8ff	2135	#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020) /!< ADC DIFSEL bit 5 /
bogdanm	0:9b334a45a8ff	2136	#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040) /!< ADC DIFSEL bit 6 /
bogdanm	0:9b334a45a8ff	2137	#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080) /!< ADC DIFSEL bit 7 /
bogdanm	0:9b334a45a8ff	2138	#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100) /!< ADC DIFSEL bit 8 /
bogdanm	0:9b334a45a8ff	2139	#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200) /!< ADC DIFSEL bit 9 /
bogdanm	0:9b334a45a8ff	2140	#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400) /!< ADC DIFSEL bit 10 /
bogdanm	0:9b334a45a8ff	2141	#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800) /!< ADC DIFSEL bit 11 /
bogdanm	0:9b334a45a8ff	2142	#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000) /!< ADC DIFSEL bit 12 /
bogdanm	0:9b334a45a8ff	2143	#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000) /!< ADC DIFSEL bit 13 /
bogdanm	0:9b334a45a8ff	2144	#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000) /!< ADC DIFSEL bit 14 /
bogdanm	0:9b334a45a8ff	2145	#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000) /!< ADC DIFSEL bit 15 /
bogdanm	0:9b334a45a8ff	2146	#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000) /!< ADC DIFSEL bit 16 /
bogdanm	0:9b334a45a8ff	2147	#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000) /!< ADC DIFSEL bit 17 /
bogdanm	0:9b334a45a8ff	2148	#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000) /!< ADC DIFSEL bit 18 /
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	/****************** Bit definition for ADC_CALFACT register ******************/
bogdanm	0:9b334a45a8ff	2151	#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /!< ADC calibration factors in single-ended mode /
bogdanm	0:9b334a45a8ff	2152	#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /!< ADC CALFACT_S bit 0 /
bogdanm	0:9b334a45a8ff	2153	#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /!< ADC CALFACT_S bit 1 /
bogdanm	0:9b334a45a8ff	2154	#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /!< ADC CALFACT_S bit 2 /
bogdanm	0:9b334a45a8ff	2155	#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /!< ADC CALFACT_S bit 3 /
bogdanm	0:9b334a45a8ff	2156	#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /!< ADC CALFACT_S bit 4 /
bogdanm	0:9b334a45a8ff	2157	#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /!< ADC CALFACT_S bit 5 /
bogdanm	0:9b334a45a8ff	2158	#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /!< ADC CALFACT_S bit 6 /
bogdanm	0:9b334a45a8ff	2159
bogdanm	0:9b334a45a8ff	2160	#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /!< ADC calibration factors in differential mode /
bogdanm	0:9b334a45a8ff	2161	#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /!< ADC CALFACT_D bit 0 /
bogdanm	0:9b334a45a8ff	2162	#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /!< ADC CALFACT_D bit 1 /
bogdanm	0:9b334a45a8ff	2163	#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /!< ADC CALFACT_D bit 2 /
bogdanm	0:9b334a45a8ff	2164	#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /!< ADC CALFACT_D bit 3 /
bogdanm	0:9b334a45a8ff	2165	#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /!< ADC CALFACT_D bit 4 /
bogdanm	0:9b334a45a8ff	2166	#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /!< ADC CALFACT_D bit 5 /
bogdanm	0:9b334a45a8ff	2167	#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /!< ADC CALFACT_D bit 6 /
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	/*********************** ADC Common registers ***************************/
bogdanm	0:9b334a45a8ff	2170	/****************** Bit definition for ADC_CSR register ******************/
bogdanm	0:9b334a45a8ff	2171	#define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
bogdanm	0:9b334a45a8ff	2172	#define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
bogdanm	0:9b334a45a8ff	2173	#define ADC_CSR_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
bogdanm	0:9b334a45a8ff	2174	#define ADC_CSR_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	2175	#define ADC_CSR_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
bogdanm	0:9b334a45a8ff	2176	#define ADC_CSR_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
bogdanm	0:9b334a45a8ff	2177	#define ADC_CSR_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	2178	#define ADC_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
bogdanm	0:9b334a45a8ff	2179	#define ADC_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
bogdanm	0:9b334a45a8ff	2180	#define ADC_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
bogdanm	0:9b334a45a8ff	2181	#define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	#define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
bogdanm	0:9b334a45a8ff	2184	#define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2185	#define ADC_CSR_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	2186	#define ADC_CSR_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2187	#define ADC_CSR_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2188	#define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	2189	#define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2190	#define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2191	#define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2192	#define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2193	#define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
bogdanm	0:9b334a45a8ff	2194
bogdanm	0:9b334a45a8ff	2195	/****************** Bit definition for ADC_CCR register ******************/
bogdanm	0:9b334a45a8ff	2196	#define ADC_CCR_DUAL ((uint32_t)0x0000001F) /!< Dual ADC mode selection /
bogdanm	0:9b334a45a8ff	2197	#define ADC_CCR_DUAL_0 ((uint32_t)0x00000001) /!< Dual bit 0 /
bogdanm	0:9b334a45a8ff	2198	#define ADC_CCR_DUAL_1 ((uint32_t)0x00000002) /!< Dual bit 1 /
bogdanm	0:9b334a45a8ff	2199	#define ADC_CCR_DUAL_2 ((uint32_t)0x00000004) /!< Dual bit 2 /
bogdanm	0:9b334a45a8ff	2200	#define ADC_CCR_DUAL_3 ((uint32_t)0x00000008) /!< Dual bit 3 /
bogdanm	0:9b334a45a8ff	2201	#define ADC_CCR_DUAL_4 ((uint32_t)0x00000010) /!< Dual bit 4 /
bogdanm	0:9b334a45a8ff	2202
bogdanm	0:9b334a45a8ff	2203	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
bogdanm	0:9b334a45a8ff	2204	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
bogdanm	0:9b334a45a8ff	2205	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
bogdanm	0:9b334a45a8ff	2206	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
bogdanm	0:9b334a45a8ff	2207	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	#define ADC_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
bogdanm	0:9b334a45a8ff	2210
bogdanm	0:9b334a45a8ff	2211	#define ADC_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
bogdanm	0:9b334a45a8ff	2212	#define ADC_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
bogdanm	0:9b334a45a8ff	2213	#define ADC_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
bogdanm	0:9b334a45a8ff	2214
bogdanm	0:9b334a45a8ff	2215	#define ADC_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
bogdanm	0:9b334a45a8ff	2216	#define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
bogdanm	0:9b334a45a8ff	2217	#define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
bogdanm	0:9b334a45a8ff	2218
bogdanm	0:9b334a45a8ff	2219	#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /!< ADC prescaler /
bogdanm	0:9b334a45a8ff	2220	#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /!< ADC prescaler bit 0 /
bogdanm	0:9b334a45a8ff	2221	#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /!< ADC prescaler bit 1 /
bogdanm	0:9b334a45a8ff	2222	#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /!< ADC prescaler bit 2 /
bogdanm	0:9b334a45a8ff	2223	#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /!< ADC prescaler bit 3 /
bogdanm	0:9b334a45a8ff	2224
bogdanm	0:9b334a45a8ff	2225	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
bogdanm	0:9b334a45a8ff	2226	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Temperature sensor enable /
bogdanm	0:9b334a45a8ff	2227	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< VBAT enable /
bogdanm	0:9b334a45a8ff	2228
bogdanm	0:9b334a45a8ff	2229	/****************** Bit definition for ADC_CDR register ******************/
bogdanm	0:9b334a45a8ff	2230	#define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	2231	#define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
bogdanm	0:9b334a45a8ff	2232	#define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
bogdanm	0:9b334a45a8ff	2233	#define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
bogdanm	0:9b334a45a8ff	2234	#define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
bogdanm	0:9b334a45a8ff	2235	#define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
bogdanm	0:9b334a45a8ff	2236	#define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
bogdanm	0:9b334a45a8ff	2237	#define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
bogdanm	0:9b334a45a8ff	2238	#define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
bogdanm	0:9b334a45a8ff	2239	#define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
bogdanm	0:9b334a45a8ff	2240	#define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
bogdanm	0:9b334a45a8ff	2241	#define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
bogdanm	0:9b334a45a8ff	2242	#define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
bogdanm	0:9b334a45a8ff	2243	#define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
bogdanm	0:9b334a45a8ff	2244	#define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
bogdanm	0:9b334a45a8ff	2245	#define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
bogdanm	0:9b334a45a8ff	2246	#define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
bogdanm	0:9b334a45a8ff	2247
bogdanm	0:9b334a45a8ff	2248	#define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	2249	#define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
bogdanm	0:9b334a45a8ff	2250	#define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
bogdanm	0:9b334a45a8ff	2251	#define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
bogdanm	0:9b334a45a8ff	2252	#define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
bogdanm	0:9b334a45a8ff	2253	#define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
bogdanm	0:9b334a45a8ff	2254	#define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
bogdanm	0:9b334a45a8ff	2255	#define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
bogdanm	0:9b334a45a8ff	2256	#define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
bogdanm	0:9b334a45a8ff	2257	#define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
bogdanm	0:9b334a45a8ff	2258	#define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
bogdanm	0:9b334a45a8ff	2259	#define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
bogdanm	0:9b334a45a8ff	2260	#define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
bogdanm	0:9b334a45a8ff	2261	#define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
bogdanm	0:9b334a45a8ff	2262	#define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
bogdanm	0:9b334a45a8ff	2263	#define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
bogdanm	0:9b334a45a8ff	2264	#define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
bogdanm	0:9b334a45a8ff	2265
bogdanm	0:9b334a45a8ff	2266	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2267	/* */
bogdanm	0:9b334a45a8ff	2268	/* Controller Area Network */
bogdanm	0:9b334a45a8ff	2269	/* */
bogdanm	0:9b334a45a8ff	2270	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2271	/!<CAN control and status registers /
bogdanm	0:9b334a45a8ff	2272	/***************** Bit definition for CAN_MCR register ******************/
bogdanm	0:9b334a45a8ff	2273	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
bogdanm	0:9b334a45a8ff	2274	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
bogdanm	0:9b334a45a8ff	2275	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
bogdanm	0:9b334a45a8ff	2276	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
bogdanm	0:9b334a45a8ff	2277	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
bogdanm	0:9b334a45a8ff	2278	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
bogdanm	0:9b334a45a8ff	2279	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
bogdanm	0:9b334a45a8ff	2280	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
bogdanm	0:9b334a45a8ff	2281	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
bogdanm	0:9b334a45a8ff	2282
bogdanm	0:9b334a45a8ff	2283	/***************** Bit definition for CAN_MSR register ******************/
bogdanm	0:9b334a45a8ff	2284	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
bogdanm	0:9b334a45a8ff	2285	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
bogdanm	0:9b334a45a8ff	2286	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
bogdanm	0:9b334a45a8ff	2287	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	2288	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
bogdanm	0:9b334a45a8ff	2289	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
bogdanm	0:9b334a45a8ff	2290	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
bogdanm	0:9b334a45a8ff	2291	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
bogdanm	0:9b334a45a8ff	2292	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	/***************** Bit definition for CAN_TSR register ******************/
bogdanm	0:9b334a45a8ff	2295	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
bogdanm	0:9b334a45a8ff	2296	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
bogdanm	0:9b334a45a8ff	2297	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
bogdanm	0:9b334a45a8ff	2298	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
bogdanm	0:9b334a45a8ff	2299	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
bogdanm	0:9b334a45a8ff	2300	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
bogdanm	0:9b334a45a8ff	2301	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
bogdanm	0:9b334a45a8ff	2302	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
bogdanm	0:9b334a45a8ff	2303	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
bogdanm	0:9b334a45a8ff	2304	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
bogdanm	0:9b334a45a8ff	2305	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
bogdanm	0:9b334a45a8ff	2306	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
bogdanm	0:9b334a45a8ff	2307	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
bogdanm	0:9b334a45a8ff	2308	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
bogdanm	0:9b334a45a8ff	2309	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
bogdanm	0:9b334a45a8ff	2310	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
bogdanm	0:9b334a45a8ff	2311
bogdanm	0:9b334a45a8ff	2312	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
bogdanm	0:9b334a45a8ff	2313	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
bogdanm	0:9b334a45a8ff	2314	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
bogdanm	0:9b334a45a8ff	2315	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
bogdanm	0:9b334a45a8ff	2316
bogdanm	0:9b334a45a8ff	2317	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
bogdanm	0:9b334a45a8ff	2318	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
bogdanm	0:9b334a45a8ff	2319	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
bogdanm	0:9b334a45a8ff	2320	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
bogdanm	0:9b334a45a8ff	2321
bogdanm	0:9b334a45a8ff	2322	/***************** Bit definition for CAN_RF0R register *****************/
bogdanm	0:9b334a45a8ff	2323	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
bogdanm	0:9b334a45a8ff	2324	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
bogdanm	0:9b334a45a8ff	2325	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
bogdanm	0:9b334a45a8ff	2326	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
bogdanm	0:9b334a45a8ff	2327
bogdanm	0:9b334a45a8ff	2328	/***************** Bit definition for CAN_RF1R register *****************/
bogdanm	0:9b334a45a8ff	2329	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
bogdanm	0:9b334a45a8ff	2330	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
bogdanm	0:9b334a45a8ff	2331	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
bogdanm	0:9b334a45a8ff	2332	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
bogdanm	0:9b334a45a8ff	2333
bogdanm	0:9b334a45a8ff	2334	/****************** Bit definition for CAN_IER register *****************/
bogdanm	0:9b334a45a8ff	2335	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	2336	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
bogdanm	0:9b334a45a8ff	2337	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
bogdanm	0:9b334a45a8ff	2338	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
bogdanm	0:9b334a45a8ff	2339	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
bogdanm	0:9b334a45a8ff	2340	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
bogdanm	0:9b334a45a8ff	2341	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
bogdanm	0:9b334a45a8ff	2342	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
bogdanm	0:9b334a45a8ff	2343	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
bogdanm	0:9b334a45a8ff	2344	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
bogdanm	0:9b334a45a8ff	2345	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
bogdanm	0:9b334a45a8ff	2346	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	2347	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
bogdanm	0:9b334a45a8ff	2348	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
bogdanm	0:9b334a45a8ff	2349
bogdanm	0:9b334a45a8ff	2350	/****************** Bit definition for CAN_ESR register *****************/
bogdanm	0:9b334a45a8ff	2351	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
bogdanm	0:9b334a45a8ff	2352	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
bogdanm	0:9b334a45a8ff	2353	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
bogdanm	0:9b334a45a8ff	2354
bogdanm	0:9b334a45a8ff	2355	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
bogdanm	0:9b334a45a8ff	2356	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2357	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2358	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2359
bogdanm	0:9b334a45a8ff	2360	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
bogdanm	0:9b334a45a8ff	2361	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	/***************** Bit definition for CAN_BTR register ******************/
bogdanm	0:9b334a45a8ff	2364	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
bogdanm	0:9b334a45a8ff	2365	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
bogdanm	0:9b334a45a8ff	2366	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
bogdanm	0:9b334a45a8ff	2367	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
bogdanm	0:9b334a45a8ff	2368	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
bogdanm	0:9b334a45a8ff	2369	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
bogdanm	0:9b334a45a8ff	2370	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
bogdanm	0:9b334a45a8ff	2371	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
bogdanm	0:9b334a45a8ff	2372	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
bogdanm	0:9b334a45a8ff	2373	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
bogdanm	0:9b334a45a8ff	2374	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
bogdanm	0:9b334a45a8ff	2375	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
bogdanm	0:9b334a45a8ff	2376	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
bogdanm	0:9b334a45a8ff	2377	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
bogdanm	0:9b334a45a8ff	2378	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
bogdanm	0:9b334a45a8ff	2379
bogdanm	0:9b334a45a8ff	2380	/!<Mailbox registers /
bogdanm	0:9b334a45a8ff	2381	/**************** Bit definition for CAN_TI0R register ******************/
bogdanm	0:9b334a45a8ff	2382	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	2383	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	2384	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	2385	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	2386	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	2387
bogdanm	0:9b334a45a8ff	2388	/**************** Bit definition for CAN_TDT0R register *****************/
bogdanm	0:9b334a45a8ff	2389	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	2390	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	2391	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	2392
bogdanm	0:9b334a45a8ff	2393	/**************** Bit definition for CAN_TDL0R register *****************/
bogdanm	0:9b334a45a8ff	2394	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	2395	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	2396	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	2397	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	2398
bogdanm	0:9b334a45a8ff	2399	/**************** Bit definition for CAN_TDH0R register *****************/
bogdanm	0:9b334a45a8ff	2400	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	2401	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	2402	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	2403	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	2404
bogdanm	0:9b334a45a8ff	2405	/***************** Bit definition for CAN_TI1R register *****************/
bogdanm	0:9b334a45a8ff	2406	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	2407	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	2408	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	2409	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	2410	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	2411
bogdanm	0:9b334a45a8ff	2412	/***************** Bit definition for CAN_TDT1R register ****************/
bogdanm	0:9b334a45a8ff	2413	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	2414	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	2415	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	2416
bogdanm	0:9b334a45a8ff	2417	/***************** Bit definition for CAN_TDL1R register ****************/
bogdanm	0:9b334a45a8ff	2418	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	2419	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	2420	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	2421	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	2422
bogdanm	0:9b334a45a8ff	2423	/***************** Bit definition for CAN_TDH1R register ****************/
bogdanm	0:9b334a45a8ff	2424	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	2425	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	2426	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	2427	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	2428
bogdanm	0:9b334a45a8ff	2429	/***************** Bit definition for CAN_TI2R register *****************/
bogdanm	0:9b334a45a8ff	2430	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	2431	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	2432	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	2433	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	0:9b334a45a8ff	2434	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	/***************** Bit definition for CAN_TDT2R register ****************/
bogdanm	0:9b334a45a8ff	2437	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	2438	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	2439	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	2440
bogdanm	0:9b334a45a8ff	2441	/***************** Bit definition for CAN_TDL2R register ****************/
bogdanm	0:9b334a45a8ff	2442	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	2443	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	2444	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	2445	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	2446
bogdanm	0:9b334a45a8ff	2447	/***************** Bit definition for CAN_TDH2R register ****************/
bogdanm	0:9b334a45a8ff	2448	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	2449	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	2450	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	2451	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	2452
bogdanm	0:9b334a45a8ff	2453	/***************** Bit definition for CAN_RI0R register *****************/
bogdanm	0:9b334a45a8ff	2454	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	2455	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	2456	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	2457	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	2458
bogdanm	0:9b334a45a8ff	2459	/***************** Bit definition for CAN_RDT0R register ****************/
bogdanm	0:9b334a45a8ff	2460	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	2461	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	0:9b334a45a8ff	2462	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	2463
bogdanm	0:9b334a45a8ff	2464	/***************** Bit definition for CAN_RDL0R register ****************/
bogdanm	0:9b334a45a8ff	2465	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	2466	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	2467	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	2468	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	2469
bogdanm	0:9b334a45a8ff	2470	/***************** Bit definition for CAN_RDH0R register ****************/
bogdanm	0:9b334a45a8ff	2471	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	2472	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	2473	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	2474	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	2475
bogdanm	0:9b334a45a8ff	2476	/***************** Bit definition for CAN_RI1R register *****************/
bogdanm	0:9b334a45a8ff	2477	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	2478	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	2479	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	0:9b334a45a8ff	2480	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/***************** Bit definition for CAN_RDT1R register ****************/
bogdanm	0:9b334a45a8ff	2483	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	2484	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	0:9b334a45a8ff	2485	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	2486
bogdanm	0:9b334a45a8ff	2487	/***************** Bit definition for CAN_RDL1R register ****************/
bogdanm	0:9b334a45a8ff	2488	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	2489	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	2490	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	2491	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	2492
bogdanm	0:9b334a45a8ff	2493	/***************** Bit definition for CAN_RDH1R register ****************/
bogdanm	0:9b334a45a8ff	2494	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	2495	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	2496	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	2497	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	2498
bogdanm	0:9b334a45a8ff	2499	/!<CAN filter registers /
bogdanm	0:9b334a45a8ff	2500	/***************** Bit definition for CAN_FMR register ******************/
bogdanm	0:9b334a45a8ff	2501	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
bogdanm	0:9b334a45a8ff	2502
bogdanm	0:9b334a45a8ff	2503	/***************** Bit definition for CAN_FM1R register *****************/
bogdanm	0:9b334a45a8ff	2504	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
bogdanm	0:9b334a45a8ff	2505	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
bogdanm	0:9b334a45a8ff	2506	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
bogdanm	0:9b334a45a8ff	2507	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
bogdanm	0:9b334a45a8ff	2508	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
bogdanm	0:9b334a45a8ff	2509	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
bogdanm	0:9b334a45a8ff	2510	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
bogdanm	0:9b334a45a8ff	2511	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
bogdanm	0:9b334a45a8ff	2512	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
bogdanm	0:9b334a45a8ff	2513	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
bogdanm	0:9b334a45a8ff	2514	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
bogdanm	0:9b334a45a8ff	2515	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
bogdanm	0:9b334a45a8ff	2516	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
bogdanm	0:9b334a45a8ff	2517	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
bogdanm	0:9b334a45a8ff	2518	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
bogdanm	0:9b334a45a8ff	2519
bogdanm	0:9b334a45a8ff	2520	/***************** Bit definition for CAN_FS1R register *****************/
bogdanm	0:9b334a45a8ff	2521	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
bogdanm	0:9b334a45a8ff	2522	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
bogdanm	0:9b334a45a8ff	2523	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
bogdanm	0:9b334a45a8ff	2524	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
bogdanm	0:9b334a45a8ff	2525	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
bogdanm	0:9b334a45a8ff	2526	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
bogdanm	0:9b334a45a8ff	2527	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
bogdanm	0:9b334a45a8ff	2528	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
bogdanm	0:9b334a45a8ff	2529	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
bogdanm	0:9b334a45a8ff	2530	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
bogdanm	0:9b334a45a8ff	2531	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
bogdanm	0:9b334a45a8ff	2532	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
bogdanm	0:9b334a45a8ff	2533	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
bogdanm	0:9b334a45a8ff	2534	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
bogdanm	0:9b334a45a8ff	2535	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
bogdanm	0:9b334a45a8ff	2536
bogdanm	0:9b334a45a8ff	2537	/**************** Bit definition for CAN_FFA1R register *****************/
bogdanm	0:9b334a45a8ff	2538	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
bogdanm	0:9b334a45a8ff	2539	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
bogdanm	0:9b334a45a8ff	2540	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
bogdanm	0:9b334a45a8ff	2541	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
bogdanm	0:9b334a45a8ff	2542	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
bogdanm	0:9b334a45a8ff	2543	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
bogdanm	0:9b334a45a8ff	2544	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
bogdanm	0:9b334a45a8ff	2545	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
bogdanm	0:9b334a45a8ff	2546	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
bogdanm	0:9b334a45a8ff	2547	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
bogdanm	0:9b334a45a8ff	2548	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
bogdanm	0:9b334a45a8ff	2549	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
bogdanm	0:9b334a45a8ff	2550	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
bogdanm	0:9b334a45a8ff	2551	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
bogdanm	0:9b334a45a8ff	2552	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
bogdanm	0:9b334a45a8ff	2553
bogdanm	0:9b334a45a8ff	2554	/***************** Bit definition for CAN_FA1R register *****************/
bogdanm	0:9b334a45a8ff	2555	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
bogdanm	0:9b334a45a8ff	2556	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
bogdanm	0:9b334a45a8ff	2557	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
bogdanm	0:9b334a45a8ff	2558	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
bogdanm	0:9b334a45a8ff	2559	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
bogdanm	0:9b334a45a8ff	2560	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
bogdanm	0:9b334a45a8ff	2561	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
bogdanm	0:9b334a45a8ff	2562	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
bogdanm	0:9b334a45a8ff	2563	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
bogdanm	0:9b334a45a8ff	2564	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
bogdanm	0:9b334a45a8ff	2565	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
bogdanm	0:9b334a45a8ff	2566	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
bogdanm	0:9b334a45a8ff	2567	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
bogdanm	0:9b334a45a8ff	2568	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
bogdanm	0:9b334a45a8ff	2569	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	/***************** Bit definition for CAN_F0R1 register *****************/
bogdanm	0:9b334a45a8ff	2572	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2573	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2574	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2575	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2576	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2577	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2578	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2579	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2580	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2581	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2582	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2583	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2584	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2585	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2586	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2587	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2588	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2589	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2590	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2591	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2592	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2593	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2594	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2595	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2596	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2597	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2598	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2599	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2600	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2601	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2602	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2603	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2604
bogdanm	0:9b334a45a8ff	2605	/***************** Bit definition for CAN_F1R1 register *****************/
bogdanm	0:9b334a45a8ff	2606	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2607	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2608	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2609	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2610	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2611	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2612	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2613	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2614	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2615	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2616	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2617	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2618	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2619	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2620	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2621	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2622	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2623	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2624	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2625	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2626	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2627	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2628	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2629	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2630	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2631	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2632	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2633	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2634	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2635	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2636	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2637	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2638
bogdanm	0:9b334a45a8ff	2639	/***************** Bit definition for CAN_F2R1 register *****************/
bogdanm	0:9b334a45a8ff	2640	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2641	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2642	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2643	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2644	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2645	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2646	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2647	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2648	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2649	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2650	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2651	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2652	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2653	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2654	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2655	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2656	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2657	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2658	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2659	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2660	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2661	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2662	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2663	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2664	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2665	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2666	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2667	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2668	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2669	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2670	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2671	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2672
bogdanm	0:9b334a45a8ff	2673	/***************** Bit definition for CAN_F3R1 register *****************/
bogdanm	0:9b334a45a8ff	2674	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2675	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2676	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2677	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2678	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2679	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2680	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2681	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2682	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2683	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2684	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2685	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2686	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2687	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2688	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2689	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2690	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2691	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2692	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2693	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2694	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2695	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2696	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2697	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2698	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2699	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2700	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2701	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2702	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2703	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2704	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2705	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2706
bogdanm	0:9b334a45a8ff	2707	/***************** Bit definition for CAN_F4R1 register *****************/
bogdanm	0:9b334a45a8ff	2708	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2709	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2710	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2711	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2712	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2713	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2714	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2715	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2716	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2717	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2718	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2719	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2720	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2721	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2722	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2723	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2724	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2725	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2726	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2727	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2728	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2729	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2730	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2731	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2732	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2733	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2734	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2735	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2736	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2737	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2738	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2739	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2740
bogdanm	0:9b334a45a8ff	2741	/***************** Bit definition for CAN_F5R1 register *****************/
bogdanm	0:9b334a45a8ff	2742	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2743	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2744	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2745	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2746	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2747	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2748	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2749	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2750	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2751	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2752	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2753	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2754	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2755	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2756	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2757	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2758	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2759	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2760	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2761	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2762	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2763	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2764	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2765	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2766	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2767	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2768	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2769	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2770	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2771	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2772	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2773	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2774
bogdanm	0:9b334a45a8ff	2775	/***************** Bit definition for CAN_F6R1 register *****************/
bogdanm	0:9b334a45a8ff	2776	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2777	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2778	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2779	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2780	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2781	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2782	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2783	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2784	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2785	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2786	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2787	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2788	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2789	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2790	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2791	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2792	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2793	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2794	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2795	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2796	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2797	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2798	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2799	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2800	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2801	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2802	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2803	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2804	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2805	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2806	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2807	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2808
bogdanm	0:9b334a45a8ff	2809	/***************** Bit definition for CAN_F7R1 register *****************/
bogdanm	0:9b334a45a8ff	2810	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2811	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2812	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2813	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2814	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2815	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2816	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2817	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2818	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2819	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2820	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2821	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2822	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2823	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2824	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2825	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2826	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2827	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2828	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2829	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2830	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2831	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2832	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2833	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2834	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2835	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2836	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2837	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2838	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2839	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2840	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2841	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2842
bogdanm	0:9b334a45a8ff	2843	/***************** Bit definition for CAN_F8R1 register *****************/
bogdanm	0:9b334a45a8ff	2844	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2845	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2846	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2847	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2848	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2849	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2850	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2851	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2852	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2853	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2854	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2855	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2856	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2857	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2858	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2859	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2860	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2861	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2862	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2863	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2864	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2865	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2866	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2867	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2868	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2869	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2870	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2871	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2872	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2873	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2874	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2875	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2876
bogdanm	0:9b334a45a8ff	2877	/***************** Bit definition for CAN_F9R1 register *****************/
bogdanm	0:9b334a45a8ff	2878	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2879	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2880	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2881	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2882	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2883	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2884	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2885	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2886	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2887	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2888	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2889	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2890	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2891	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2892	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2893	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2894	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2895	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2896	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2897	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2898	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2899	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2900	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2901	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2902	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2903	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2904	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2905	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2906	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2907	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2908	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2909	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2910
bogdanm	0:9b334a45a8ff	2911	/***************** Bit definition for CAN_F10R1 register ****************/
bogdanm	0:9b334a45a8ff	2912	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2913	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2914	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2915	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2916	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2917	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2918	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2919	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2920	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2921	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2922	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2923	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2924	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2925	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2926	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2927	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2928	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2929	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2930	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2931	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2932	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2933	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2934	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2935	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2936	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2937	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2938	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2939	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2940	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2941	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2942	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2943	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	/***************** Bit definition for CAN_F11R1 register ****************/
bogdanm	0:9b334a45a8ff	2946	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2947	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2948	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2949	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2950	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2951	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2952	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2953	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2954	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2955	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2956	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2957	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2958	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2959	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2960	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2961	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2962	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2963	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2964	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2965	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	2966	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	2967	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	2968	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	2969	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	2970	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	2971	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	2972	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	2973	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	2974	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	2975	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	2976	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	2977	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	2978
bogdanm	0:9b334a45a8ff	2979	/***************** Bit definition for CAN_F12R1 register ****************/
bogdanm	0:9b334a45a8ff	2980	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	2981	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	2982	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	2983	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	2984	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	2985	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	2986	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	2987	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	2988	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	2989	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	2990	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	2991	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	2992	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	2993	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	2994	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	2995	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	2996	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	2997	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	2998	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	2999	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3000	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3001	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3002	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3003	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3004	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3005	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3006	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3007	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3008	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3009	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3010	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3011	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3012
bogdanm	0:9b334a45a8ff	3013	/***************** Bit definition for CAN_F13R1 register ****************/
bogdanm	0:9b334a45a8ff	3014	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3015	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3016	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3017	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3018	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3019	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3020	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3021	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3022	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3023	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3024	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3025	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3026	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3027	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3028	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3029	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3030	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3031	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3032	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3033	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3034	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3035	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3036	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3037	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3038	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3039	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3040	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3041	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3042	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3043	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3044	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3045	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3046
bogdanm	0:9b334a45a8ff	3047	/***************** Bit definition for CAN_F0R2 register *****************/
bogdanm	0:9b334a45a8ff	3048	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3049	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3050	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3051	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3052	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3053	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3054	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3055	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3056	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3057	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3058	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3059	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3060	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3061	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3062	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3063	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3064	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3065	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3066	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3067	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3068	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3069	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3070	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3071	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3072	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3073	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3074	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3075	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3076	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3077	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3078	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3079	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3080
bogdanm	0:9b334a45a8ff	3081	/***************** Bit definition for CAN_F1R2 register *****************/
bogdanm	0:9b334a45a8ff	3082	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3083	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3084	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3085	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3086	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3087	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3088	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3089	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3090	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3091	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3092	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3093	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3094	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3095	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3096	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3097	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3098	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3099	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3100	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3101	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3102	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3103	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3104	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3105	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3106	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3107	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3108	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3109	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3110	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3111	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3112	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3113	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3114
bogdanm	0:9b334a45a8ff	3115	/***************** Bit definition for CAN_F2R2 register *****************/
bogdanm	0:9b334a45a8ff	3116	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3117	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3118	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3119	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3120	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3121	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3122	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3123	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3124	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3125	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3126	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3127	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3128	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3129	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3130	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3131	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3132	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3133	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3134	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3135	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3136	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3137	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3138	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3139	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3140	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3141	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3142	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3143	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3144	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3145	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3146	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3147	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3148
bogdanm	0:9b334a45a8ff	3149	/***************** Bit definition for CAN_F3R2 register *****************/
bogdanm	0:9b334a45a8ff	3150	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3151	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3152	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3153	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3154	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3155	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3156	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3157	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3158	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3159	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3160	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3161	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3162	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3163	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3164	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3165	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3166	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3167	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3168	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3169	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3170	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3171	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3172	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3173	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3174	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3175	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3176	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3177	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3178	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3179	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3180	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3181	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3182
bogdanm	0:9b334a45a8ff	3183	/***************** Bit definition for CAN_F4R2 register *****************/
bogdanm	0:9b334a45a8ff	3184	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3185	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3186	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3187	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3188	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3189	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3190	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3191	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3192	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3193	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3194	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3195	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3196	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3197	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3198	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3199	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3200	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3201	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3202	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3203	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3204	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3205	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3206	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3207	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3208	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3209	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3210	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3211	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3212	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3213	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3214	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3215	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3216
bogdanm	0:9b334a45a8ff	3217	/***************** Bit definition for CAN_F5R2 register *****************/
bogdanm	0:9b334a45a8ff	3218	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3219	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3220	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3221	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3222	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3223	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3224	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3225	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3226	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3227	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3228	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3229	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3230	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3231	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3232	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3233	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3234	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3235	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3236	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3237	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3238	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3239	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3240	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3241	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3242	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3243	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3244	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3245	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3246	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3247	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3248	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3249	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3250
bogdanm	0:9b334a45a8ff	3251	/***************** Bit definition for CAN_F6R2 register *****************/
bogdanm	0:9b334a45a8ff	3252	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3253	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3254	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3255	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3256	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3257	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3258	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3259	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3260	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3261	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3262	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3263	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3264	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3265	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3266	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3267	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3268	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3269	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3270	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3271	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3272	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3273	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3274	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3275	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3276	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3277	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3278	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3279	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3280	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3281	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3282	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3283	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3284
bogdanm	0:9b334a45a8ff	3285	/***************** Bit definition for CAN_F7R2 register *****************/
bogdanm	0:9b334a45a8ff	3286	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3287	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3288	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3289	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3290	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3291	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3292	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3293	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3294	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3295	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3296	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3297	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3298	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3299	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3300	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3301	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3302	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3303	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3304	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3305	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3306	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3307	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3308	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3309	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3310	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3311	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3312	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3313	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3314	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3315	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3316	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3317	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3318
bogdanm	0:9b334a45a8ff	3319	/***************** Bit definition for CAN_F8R2 register *****************/
bogdanm	0:9b334a45a8ff	3320	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3321	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3322	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3323	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3324	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3325	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3326	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3327	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3328	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3329	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3330	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3331	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3332	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3333	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3334	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3335	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3336	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3337	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3338	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3339	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3340	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3341	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3342	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3343	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3344	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3345	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3346	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3347	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3348	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3349	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3350	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3351	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3352
bogdanm	0:9b334a45a8ff	3353	/***************** Bit definition for CAN_F9R2 register *****************/
bogdanm	0:9b334a45a8ff	3354	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3355	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3356	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3357	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3358	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3359	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3360	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3361	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3362	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3363	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3364	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3365	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3366	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3367	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3368	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3369	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3370	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3371	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3372	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3373	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3374	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3375	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3376	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3377	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3378	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3379	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3380	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3381	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3382	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3383	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3384	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3385	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3386
bogdanm	0:9b334a45a8ff	3387	/***************** Bit definition for CAN_F10R2 register ****************/
bogdanm	0:9b334a45a8ff	3388	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3389	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3390	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3391	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3392	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3393	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3394	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3395	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3396	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3397	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3398	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3399	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3400	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3401	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3402	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3403	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3404	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3405	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3406	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3407	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3408	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3409	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3410	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3411	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3412	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3413	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3414	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3415	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3416	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3417	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3418	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3419	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3420
bogdanm	0:9b334a45a8ff	3421	/***************** Bit definition for CAN_F11R2 register ****************/
bogdanm	0:9b334a45a8ff	3422	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3423	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3424	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3425	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3426	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3427	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3428	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3429	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3430	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3431	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3432	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3433	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3434	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3435	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3436	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3437	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3438	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3439	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3440	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3441	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3442	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3443	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3444	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3445	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3446	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3447	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3448	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3449	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3450	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3451	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3452	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3453	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3454
bogdanm	0:9b334a45a8ff	3455	/***************** Bit definition for CAN_F12R2 register ****************/
bogdanm	0:9b334a45a8ff	3456	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3457	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3458	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3459	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3460	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3461	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3462	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3463	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3464	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3465	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3466	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3467	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3468	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3469	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3470	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3471	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3472	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3473	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3474	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3475	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3476	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3477	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3478	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3479	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3480	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3481	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3482	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3483	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3484	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3485	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3486	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3487	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3488
bogdanm	0:9b334a45a8ff	3489	/***************** Bit definition for CAN_F13R2 register ****************/
bogdanm	0:9b334a45a8ff	3490	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	3491	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	3492	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	3493	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	3494	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	3495	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	3496	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	3497	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	3498	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	3499	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	3500	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	3501	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	3502	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	3503	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	3504	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	3505	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	3506	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	3507	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	3508	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	3509	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	3510	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	3511	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	3512	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	3513	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	3514	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	3515	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	3516	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	3517	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	3518	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	3519	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	3520	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	3521	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	3522
bogdanm	0:9b334a45a8ff	3523	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3524	/* */
bogdanm	0:9b334a45a8ff	3525	/* CRC calculation unit */
bogdanm	0:9b334a45a8ff	3526	/* */
bogdanm	0:9b334a45a8ff	3527	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3528	/***************** Bit definition for CRC_DR register *******************/
bogdanm	0:9b334a45a8ff	3529	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	0:9b334a45a8ff	3530
bogdanm	0:9b334a45a8ff	3531	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	0:9b334a45a8ff	3532	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
bogdanm	0:9b334a45a8ff	3533
bogdanm	0:9b334a45a8ff	3534	/****************** Bit definition for CRC_CR register ******************/
bogdanm	0:9b334a45a8ff	3535	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
bogdanm	0:9b334a45a8ff	3536	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
bogdanm	0:9b334a45a8ff	3537	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
bogdanm	0:9b334a45a8ff	3538	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
bogdanm	0:9b334a45a8ff	3539	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
bogdanm	0:9b334a45a8ff	3540	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3541	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3542	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
bogdanm	0:9b334a45a8ff	3543
bogdanm	0:9b334a45a8ff	3544	/***************** Bit definition for CRC_INIT register *****************/
bogdanm	0:9b334a45a8ff	3545	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
bogdanm	0:9b334a45a8ff	3546
bogdanm	0:9b334a45a8ff	3547	/***************** Bit definition for CRC_POL register ******************/
bogdanm	0:9b334a45a8ff	3548	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
bogdanm	0:9b334a45a8ff	3549
bogdanm	0:9b334a45a8ff	3550	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3551	/* */
bogdanm	0:9b334a45a8ff	3552	/* Digital to Analog Converter */
bogdanm	0:9b334a45a8ff	3553	/* */
bogdanm	0:9b334a45a8ff	3554	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3555	/****************** Bit definition for DAC_CR register ******************/
bogdanm	0:9b334a45a8ff	3556	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
bogdanm	0:9b334a45a8ff	3557	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
bogdanm	0:9b334a45a8ff	3558
bogdanm	0:9b334a45a8ff	3559	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
bogdanm	0:9b334a45a8ff	3560	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3561	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3562	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3563
bogdanm	0:9b334a45a8ff	3564	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	3565	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3566	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3567
bogdanm	0:9b334a45a8ff	3568	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	3569	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3570	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3571	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3572	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	3573
bogdanm	0:9b334a45a8ff	3574	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
bogdanm	0:9b334a45a8ff	3575	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel 1 DMA underrun interrupt enable >/
bogdanm	0:9b334a45a8ff	3576	#define DAC_CR_CEN1 ((uint32_t)0x00004000) /!<DAC channel 1 calibration enable >/
bogdanm	0:9b334a45a8ff	3577
bogdanm	0:9b334a45a8ff	3578	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
bogdanm	0:9b334a45a8ff	3579	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
bogdanm	0:9b334a45a8ff	3580
bogdanm	0:9b334a45a8ff	3581	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
bogdanm	0:9b334a45a8ff	3582	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3583	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3584	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3585
bogdanm	0:9b334a45a8ff	3586	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	3587	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3588	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3589
bogdanm	0:9b334a45a8ff	3590	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	3591	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3592	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3593	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3594	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	3595
bogdanm	0:9b334a45a8ff	3596	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
bogdanm	0:9b334a45a8ff	3597	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun interrupt enable >/
bogdanm	0:9b334a45a8ff	3598	#define DAC_CR_CEN2 ((uint32_t)0x40000000) /!<DAC channel2 calibration enable >/
bogdanm	0:9b334a45a8ff	3599
bogdanm	0:9b334a45a8ff	3600	/*************** Bit definition for DAC_SWTRIGR register ****************/
bogdanm	0:9b334a45a8ff	3601	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!<DAC channel1 software trigger /
bogdanm	0:9b334a45a8ff	3602	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!<DAC channel2 software trigger /
bogdanm	0:9b334a45a8ff	3603
bogdanm	0:9b334a45a8ff	3604	/*************** Bit definition for DAC_DHR12R1 register ****************/
bogdanm	0:9b334a45a8ff	3605	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3606
bogdanm	0:9b334a45a8ff	3607	/*************** Bit definition for DAC_DHR12L1 register ****************/
bogdanm	0:9b334a45a8ff	3608	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	3609
bogdanm	0:9b334a45a8ff	3610	/**************** Bit definition for DAC_DHR8R1 register ****************/
bogdanm	0:9b334a45a8ff	3611	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3612
bogdanm	0:9b334a45a8ff	3613	/*************** Bit definition for DAC_DHR12R2 register ****************/
bogdanm	0:9b334a45a8ff	3614	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!<DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3615
bogdanm	0:9b334a45a8ff	3616	/*************** Bit definition for DAC_DHR12L2 register ****************/
bogdanm	0:9b334a45a8ff	3617	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!<DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	3618
bogdanm	0:9b334a45a8ff	3619	/**************** Bit definition for DAC_DHR8R2 register ****************/
bogdanm	0:9b334a45a8ff	3620	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!<DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3621
bogdanm	0:9b334a45a8ff	3622	/*************** Bit definition for DAC_DHR12RD register ****************/
bogdanm	0:9b334a45a8ff	3623	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3624	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3625
bogdanm	0:9b334a45a8ff	3626	/*************** Bit definition for DAC_DHR12LD register ****************/
bogdanm	0:9b334a45a8ff	3627	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	3628	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	3629
bogdanm	0:9b334a45a8ff	3630	/**************** Bit definition for DAC_DHR8RD register ****************/
bogdanm	0:9b334a45a8ff	3631	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3632	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!<DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	3633
bogdanm	0:9b334a45a8ff	3634	/***************** Bit definition for DAC_DOR1 register *****************/
bogdanm	0:9b334a45a8ff	3635	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!<DAC channel1 data output /
bogdanm	0:9b334a45a8ff	3636
bogdanm	0:9b334a45a8ff	3637	/***************** Bit definition for DAC_DOR2 register *****************/
bogdanm	0:9b334a45a8ff	3638	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!<DAC channel2 data output /
bogdanm	0:9b334a45a8ff	3639
bogdanm	0:9b334a45a8ff	3640	/****************** Bit definition for DAC_SR register ******************/
bogdanm	0:9b334a45a8ff	3641	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
bogdanm	0:9b334a45a8ff	3642	#define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000) /!<DAC channel1 calibration offset status /
bogdanm	0:9b334a45a8ff	3643	#define DAC_SR_BWST1 ((uint32_t)0x20008000) /!<DAC channel1 busy writing sample time flag /
bogdanm	0:9b334a45a8ff	3644
bogdanm	0:9b334a45a8ff	3645	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
bogdanm	0:9b334a45a8ff	3646	#define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000) /!<DAC channel2 calibration offset status /
bogdanm	0:9b334a45a8ff	3647	#define DAC_SR_BWST2 ((uint32_t)0x80000000) /!<DAC channel2 busy writing sample time flag /
bogdanm	0:9b334a45a8ff	3648
bogdanm	0:9b334a45a8ff	3649	/***************** Bit definition for DAC_CCR register ******************/
bogdanm	0:9b334a45a8ff	3650	#define DAC_CCR_OTRIM1 ((uint32_t)0x0000001F) /!<DAC channel1 offset trimming value /
bogdanm	0:9b334a45a8ff	3651	#define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000) /!<DAC channel2 offset trimming value /
bogdanm	0:9b334a45a8ff	3652
bogdanm	0:9b334a45a8ff	3653	/***************** Bit definition for DAC_MCR register *****************/
bogdanm	0:9b334a45a8ff	3654	#define DAC_MCR_MODE1 ((uint32_t)0x00000007) /!<MODE1[2:0] (DAC channel1 mode) /
bogdanm	0:9b334a45a8ff	3655	#define DAC_MCR_MODE1_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3656	#define DAC_MCR_MODE1_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3657	#define DAC_MCR_MODE1_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3658
bogdanm	0:9b334a45a8ff	3659	#define DAC_MCR_MODE2 ((uint32_t)0x00070000) /!<MODE2[2:0] (DAC channel2 mode) /
bogdanm	0:9b334a45a8ff	3660	#define DAC_MCR_MODE2_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3661	#define DAC_MCR_MODE2_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3662	#define DAC_MCR_MODE2_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3663
bogdanm	0:9b334a45a8ff	3664	/**************** Bit definition for DAC_SHSR1 register ****************/
bogdanm	0:9b334a45a8ff	3665	#define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FF) /!<DAC channel1 sample time /
bogdanm	0:9b334a45a8ff	3666
bogdanm	0:9b334a45a8ff	3667	/**************** Bit definition for DAC_SHSR2 register ****************/
bogdanm	0:9b334a45a8ff	3668	#define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FF) /!<DAC channel2 sample time /
bogdanm	0:9b334a45a8ff	3669
bogdanm	0:9b334a45a8ff	3670	/**************** Bit definition for DAC_SHHR register ****************/
bogdanm	0:9b334a45a8ff	3671	#define DAC_SHHR_THOLD1 ((uint32_t)0x000003FF) /!<DAC channel1 hold time /
bogdanm	0:9b334a45a8ff	3672	#define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000) /!<DAC channel2 hold time /
bogdanm	0:9b334a45a8ff	3673
bogdanm	0:9b334a45a8ff	3674	/**************** Bit definition for DAC_SHRR register ****************/
bogdanm	0:9b334a45a8ff	3675	#define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FF) /!<DAC channel1 refresh time /
bogdanm	0:9b334a45a8ff	3676	#define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000) /!<DAC channel2 refresh time /
bogdanm	0:9b334a45a8ff	3677
bogdanm	0:9b334a45a8ff	3678
bogdanm	0:9b334a45a8ff	3679	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3680	/* */
bogdanm	0:9b334a45a8ff	3681	/* Digital Filter for Sigma Delta Modulators */
bogdanm	0:9b334a45a8ff	3682	/* */
bogdanm	0:9b334a45a8ff	3683	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3684
bogdanm	0:9b334a45a8ff	3685	/************** DFSDM channel configuration registers ******************/
bogdanm	0:9b334a45a8ff	3686
bogdanm	0:9b334a45a8ff	3687	/************* Bit definition for DFSDM_CHCFGR1 register ****************/
bogdanm	0:9b334a45a8ff	3688	#define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000) /!< Global enable for DFSDM interface /
bogdanm	0:9b334a45a8ff	3689	#define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000) /!< Output serial clock source selection /
bogdanm	0:9b334a45a8ff	3690	#define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000) /!< CKOUTDIV[7:0] output serial clock divider /
bogdanm	0:9b334a45a8ff	3691	#define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000) /!< DATPACK[1:0] Data packing mode /
bogdanm	0:9b334a45a8ff	3692	#define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000) /!< Data packing mode, Bit 1 /
bogdanm	0:9b334a45a8ff	3693	#define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000) /!< Data packing mode, Bit 0 /
bogdanm	0:9b334a45a8ff	3694	#define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000) /!< DATMPX[1:0] Input data multiplexer for channel y /
bogdanm	0:9b334a45a8ff	3695	#define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000) /!< Input data multiplexer for channel y, Bit 1 /
bogdanm	0:9b334a45a8ff	3696	#define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000) /!< Input data multiplexer for channel y, Bit 0 /
bogdanm	0:9b334a45a8ff	3697	#define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100) /!< Serial inputs selection for channel y /
bogdanm	0:9b334a45a8ff	3698	#define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080) /!< Channel y enable /
bogdanm	0:9b334a45a8ff	3699	#define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040) /!< Clock absence detector enable on channel y /
bogdanm	0:9b334a45a8ff	3700	#define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020) /!< Short circuit detector enable on channel y /
bogdanm	0:9b334a45a8ff	3701	#define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000C) /!< SPICKSEL[1:0] SPI clock select for channel y /
bogdanm	0:9b334a45a8ff	3702	#define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008) /!< SPI clock select for channel y, Bit 1 /
bogdanm	0:9b334a45a8ff	3703	#define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004) /!< SPI clock select for channel y, Bit 0 /
bogdanm	0:9b334a45a8ff	3704	#define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003) /!< SITP[1:0] Serial interface type for channel y /
bogdanm	0:9b334a45a8ff	3705	#define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002) /!< Serial interface type for channel y, Bit 1 /
bogdanm	0:9b334a45a8ff	3706	#define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001) /!< Serial interface type for channel y, Bit 0 /
bogdanm	0:9b334a45a8ff	3707
bogdanm	0:9b334a45a8ff	3708	/************* Bit definition for DFSDM_CHCFGR2 register ****************/
bogdanm	0:9b334a45a8ff	3709	#define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00) /!< OFFSET[23:0] 24-bit calibration offset for channel y /
bogdanm	0:9b334a45a8ff	3710	#define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8) /!< DTRBS[4:0] Data right bit-shift for channel y /
bogdanm	0:9b334a45a8ff	3711
bogdanm	0:9b334a45a8ff	3712	/**************** Bit definition for DFSDM_AWSCDR register ***************/
bogdanm	0:9b334a45a8ff	3713	#define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000) /!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y /
bogdanm	0:9b334a45a8ff	3714	#define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000) /!< Analog watchdog Sinc filter order on channel y, Bit 1 /
bogdanm	0:9b334a45a8ff	3715	#define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000) /!< Analog watchdog Sinc filter order on channel y, Bit 0 /
bogdanm	0:9b334a45a8ff	3716	#define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000) /!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y /
bogdanm	0:9b334a45a8ff	3717	#define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000) /!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y /
bogdanm	0:9b334a45a8ff	3718	#define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FF) /!< SCDT[7:0] Short circuit detector threshold for channel y /
bogdanm	0:9b334a45a8ff	3719
bogdanm	0:9b334a45a8ff	3720	/************** Bit definition for DFSDM_CHWDATR register *****************/
bogdanm	0:9b334a45a8ff	3721	#define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFF) /!< WDATA[15:0] Input channel y watchdog data /
bogdanm	0:9b334a45a8ff	3722
bogdanm	0:9b334a45a8ff	3723	/************** Bit definition for DFSDM_CHDATINR register ***************/
bogdanm	0:9b334a45a8ff	3724	#define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFF) /!< INDAT0[31:16] Input data for channel y or channel (y+1) /
bogdanm	0:9b334a45a8ff	3725	#define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000) /!< INDAT0[15:0] Input data for channel y /
bogdanm	0:9b334a45a8ff	3726
bogdanm	0:9b334a45a8ff	3727	/********************** DFSDM module registers **************************/
bogdanm	0:9b334a45a8ff	3728
bogdanm	0:9b334a45a8ff	3729	/****************** Bit definition for DFSDM_CR1 register *****************/
bogdanm	0:9b334a45a8ff	3730	#define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000) /!< Analog watchdog fast mode select /
bogdanm	0:9b334a45a8ff	3731	#define DFSDM_CR1_FAST ((uint32_t)0x20000000) /!< Fast conversion mode selection /
bogdanm	0:9b334a45a8ff	3732	#define DFSDM_CR1_RCH ((uint32_t)0x07000000) /!< RCH[2:0] Regular channel selection /
bogdanm	0:9b334a45a8ff	3733	#define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000) /!< DMA channel enabled to read data for the regular conversion /
bogdanm	0:9b334a45a8ff	3734	#define DFSDM_CR1_RSYNC ((uint32_t)0x00080000) /!< Launch regular conversion synchronously with DFSDMx /
bogdanm	0:9b334a45a8ff	3735	#define DFSDM_CR1_RCONT ((uint32_t)0x00040000) /!< Continuous mode selection for regular conversions /
bogdanm	0:9b334a45a8ff	3736	#define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000) /!< Software start of a conversion on the regular channel /
bogdanm	0:9b334a45a8ff	3737	#define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000) /!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions /
bogdanm	0:9b334a45a8ff	3738	#define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000) /!< Trigger enable and trigger edge selection for injected conversions, Bit 1 /
bogdanm	0:9b334a45a8ff	3739	#define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000) /!< Trigger enable and trigger edge selection for injected conversions, Bit 0 /
bogdanm	0:9b334a45a8ff	3740	#define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700) /!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions /
bogdanm	0:9b334a45a8ff	3741	#define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400) /!< Trigger signal selection for launching injected conversions, Bit 2 /
bogdanm	0:9b334a45a8ff	3742	#define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200) /!< Trigger signal selection for launching injected conversions, Bit 1 /
bogdanm	0:9b334a45a8ff	3743	#define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100) /!< Trigger signal selection for launching injected conversions, Bit 0 /
bogdanm	0:9b334a45a8ff	3744	#define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020) /!< DMA channel enabled to read data for the injected channel group /
bogdanm	0:9b334a45a8ff	3745	#define DFSDM_CR1_JSCAN ((uint32_t)0x00000010) /!< Scanning conversion in continuous mode selection for injected conversions /
bogdanm	0:9b334a45a8ff	3746	#define DFSDM_CR1_JSYNC ((uint32_t)0x00000008) /!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger /
bogdanm	0:9b334a45a8ff	3747	#define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002) /!< Start the conversion of the injected group of channels /
bogdanm	0:9b334a45a8ff	3748	#define DFSDM_CR1_DFEN ((uint32_t)0x00000001) /!< DFSDM enable /
bogdanm	0:9b334a45a8ff	3749
bogdanm	0:9b334a45a8ff	3750	/****************** Bit definition for DFSDM_CR2 register *****************/
bogdanm	0:9b334a45a8ff	3751	#define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000) /!< AWDCH[7:0] Analog watchdog channel selection /
bogdanm	0:9b334a45a8ff	3752	#define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00) /!< EXCH[7:0] Extreme detector channel selection /
bogdanm	0:9b334a45a8ff	3753	#define DFSDM_CR2_CKABIE ((uint32_t)0x00000040) /!< Clock absence interrupt enable /
bogdanm	0:9b334a45a8ff	3754	#define DFSDM_CR2_SCDIE ((uint32_t)0x00000020) /!< Short circuit detector interrupt enable /
bogdanm	0:9b334a45a8ff	3755	#define DFSDM_CR2_AWDIE ((uint32_t)0x00000010) /!< Analog watchdog interrupt enable /
bogdanm	0:9b334a45a8ff	3756	#define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008) /!< Regular data overrun interrupt enable /
bogdanm	0:9b334a45a8ff	3757	#define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004) /!< Injected data overrun interrupt enable /
bogdanm	0:9b334a45a8ff	3758	#define DFSDM_CR2_REOCIE ((uint32_t)0x00000002) /!< Regular end of conversion interrupt enable /
bogdanm	0:9b334a45a8ff	3759	#define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001) /!< Injected end of conversion interrupt enable /
bogdanm	0:9b334a45a8ff	3760
bogdanm	0:9b334a45a8ff	3761	/****************** Bit definition for DFSDM_ISR register *****************/
bogdanm	0:9b334a45a8ff	3762	#define DFSDM_ISR_SCDF ((uint32_t)0xFF000000) /!< SCDF[7:0] Short circuit detector flag /
bogdanm	0:9b334a45a8ff	3763	#define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000) /!< CKABF[7:0] Clock absence flag /
bogdanm	0:9b334a45a8ff	3764	#define DFSDM_ISR_RCIP ((uint32_t)0x00004000) /!< Regular conversion in progress status /
bogdanm	0:9b334a45a8ff	3765	#define DFSDM_ISR_JCIP ((uint32_t)0x00002000) /!< Injected conversion in progress status /
bogdanm	0:9b334a45a8ff	3766	#define DFSDM_ISR_AWDF ((uint32_t)0x00000010) /!< Analog watchdog /
bogdanm	0:9b334a45a8ff	3767	#define DFSDM_ISR_ROVRF ((uint32_t)0x00000008) /!< Regular conversion overrun flag /
bogdanm	0:9b334a45a8ff	3768	#define DFSDM_ISR_JOVRF ((uint32_t)0x00000004) /!< Injected conversion overrun flag /
bogdanm	0:9b334a45a8ff	3769	#define DFSDM_ISR_REOCF ((uint32_t)0x00000002) /!< End of regular conversion flag /
bogdanm	0:9b334a45a8ff	3770	#define DFSDM_ISR_JEOCF ((uint32_t)0x00000001) /!< End of injected conversion flag /
bogdanm	0:9b334a45a8ff	3771
bogdanm	0:9b334a45a8ff	3772	/****************** Bit definition for DFSDM_ICR register *****************/
bogdanm	0:9b334a45a8ff	3773	#define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000) /!< CLRSCSDF[7:0] Clear the short circuit detector flag /
bogdanm	0:9b334a45a8ff	3774	#define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000) /!< CLRCKABF[7:0] Clear the clock absence flag /
bogdanm	0:9b334a45a8ff	3775	#define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008) /!< Clear the regular conversion overrun flag /
bogdanm	0:9b334a45a8ff	3776	#define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004) /!< Clear the injected conversion overrun flag /
bogdanm	0:9b334a45a8ff	3777
bogdanm	0:9b334a45a8ff	3778	/***************** Bit definition for DFSDM_JCHGR register ****************/
bogdanm	0:9b334a45a8ff	3779	#define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FF) /!< JCHG[7:0] Injected channel group selection /
bogdanm	0:9b334a45a8ff	3780
bogdanm	0:9b334a45a8ff	3781	/****************** Bit definition for DFSDM_FCR register *****************/
bogdanm	0:9b334a45a8ff	3782	#define DFSDM_FCR_FORD ((uint32_t)0xE0000000) /!< FORD[2:0] Sinc filter order /
bogdanm	0:9b334a45a8ff	3783	#define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000) /!< Sinc filter order, Bit 2 /
bogdanm	0:9b334a45a8ff	3784	#define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000) /!< Sinc filter order, Bit 1 /
bogdanm	0:9b334a45a8ff	3785	#define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000) /!< Sinc filter order, Bit 0 /
bogdanm	0:9b334a45a8ff	3786	#define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000) /!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) /
bogdanm	0:9b334a45a8ff	3787	#define DFSDM_FCR_IOSR ((uint32_t)0x000000FF) /!< IOSR[7:0] Integrator oversampling ratio (averaging length) /
bogdanm	0:9b334a45a8ff	3788
bogdanm	0:9b334a45a8ff	3789	/**************** Bit definition for DFSDM_JDATAR register ***************/
bogdanm	0:9b334a45a8ff	3790	#define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00) /!< JDATA[23:0] Injected group conversion data /
bogdanm	0:9b334a45a8ff	3791	#define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007) /!< JDATACH[2:0] Injected channel most recently converted /
bogdanm	0:9b334a45a8ff	3792
bogdanm	0:9b334a45a8ff	3793	/**************** Bit definition for DFSDM_RDATAR register ***************/
bogdanm	0:9b334a45a8ff	3794	#define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00) /!< RDATA[23:0] Regular channel conversion data /
bogdanm	0:9b334a45a8ff	3795	#define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010) /!< RPEND Regular channel pending data /
bogdanm	0:9b334a45a8ff	3796	#define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007) /!< RDATACH[2:0] Regular channel most recently converted /
bogdanm	0:9b334a45a8ff	3797
bogdanm	0:9b334a45a8ff	3798	/**************** Bit definition for DFSDM_AWHTR register ****************/
bogdanm	0:9b334a45a8ff	3799	#define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00) /!< AWHT[23:0] Analog watchdog high threshold /
bogdanm	0:9b334a45a8ff	3800	#define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000F) /!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event /
bogdanm	0:9b334a45a8ff	3801
bogdanm	0:9b334a45a8ff	3802	/**************** Bit definition for DFSDM_AWLTR register ****************/
bogdanm	0:9b334a45a8ff	3803	#define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00) /!< AWHT[23:0] Analog watchdog low threshold /
bogdanm	0:9b334a45a8ff	3804	#define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000F) /!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event /
bogdanm	0:9b334a45a8ff	3805
bogdanm	0:9b334a45a8ff	3806	/**************** Bit definition for DFSDM_AWSR register ****************/
bogdanm	0:9b334a45a8ff	3807	#define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00) /!< AWHTF[15:8] Analog watchdog high threshold error on given channels /
bogdanm	0:9b334a45a8ff	3808	#define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FF) /!< AWLTF[7:0] Analog watchdog low threshold error on given channels /
bogdanm	0:9b334a45a8ff	3809
bogdanm	0:9b334a45a8ff	3810	/**************** Bit definition for DFSDM_AWCFR) register ***************/
bogdanm	0:9b334a45a8ff	3811	#define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00) /!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag /
bogdanm	0:9b334a45a8ff	3812	#define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FF) /!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag /
bogdanm	0:9b334a45a8ff	3813
bogdanm	0:9b334a45a8ff	3814	/**************** Bit definition for DFSDM_EXMAX register ****************/
bogdanm	0:9b334a45a8ff	3815	#define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00) /!< EXMAX[23:0] Extreme detector maximum value /
bogdanm	0:9b334a45a8ff	3816	#define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007) /!< EXMAXCH[2:0] Extreme detector maximum data channel /
bogdanm	0:9b334a45a8ff	3817
bogdanm	0:9b334a45a8ff	3818	/**************** Bit definition for DFSDM_EXMIN register ****************/
bogdanm	0:9b334a45a8ff	3819	#define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00) /!< EXMIN[23:0] Extreme detector minimum value /
bogdanm	0:9b334a45a8ff	3820	#define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007) /!< EXMINCH[2:0] Extreme detector minimum data channel /
bogdanm	0:9b334a45a8ff	3821
bogdanm	0:9b334a45a8ff	3822	/**************** Bit definition for DFSDM_EXMIN register ****************/
bogdanm	0:9b334a45a8ff	3823	#define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0) /!< CNVCNT[27:0]: 28-bit timer counting conversion time /
bogdanm	0:9b334a45a8ff	3824
bogdanm	0:9b334a45a8ff	3825	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3826	/* */
bogdanm	0:9b334a45a8ff	3827	/* DMA Controller (DMA) */
bogdanm	0:9b334a45a8ff	3828	/* */
bogdanm	0:9b334a45a8ff	3829	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3830
bogdanm	0:9b334a45a8ff	3831	/***************** Bit definition for DMA_ISR register ******************/
bogdanm	0:9b334a45a8ff	3832	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3833	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3834	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3835	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3836	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3837	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3838	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3839	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3840	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3841	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3842	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3843	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3844	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3845	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3846	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3847	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3848	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3849	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3850	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3851	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3852	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3853	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3854	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3855	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3856	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
bogdanm	0:9b334a45a8ff	3857	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	3858	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
bogdanm	0:9b334a45a8ff	3859	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
bogdanm	0:9b334a45a8ff	3860
bogdanm	0:9b334a45a8ff	3861	/***************** Bit definition for DMA_IFCR register *****************/
bogdanm	0:9b334a45a8ff	3862	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clearr /
bogdanm	0:9b334a45a8ff	3863	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3864	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3865	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3866	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3867	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3868	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3869	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3870	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3871	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3872	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3873	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3874	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3875	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3876	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3877	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3878	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3879	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3880	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3881	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3882	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3883	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3884	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3885	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3886	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
bogdanm	0:9b334a45a8ff	3887	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	3888	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
bogdanm	0:9b334a45a8ff	3889	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
bogdanm	0:9b334a45a8ff	3890
bogdanm	0:9b334a45a8ff	3891	/***************** Bit definition for DMA_CCR register ******************/
bogdanm	0:9b334a45a8ff	3892	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
bogdanm	0:9b334a45a8ff	3893	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	3894	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
bogdanm	0:9b334a45a8ff	3895	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
bogdanm	0:9b334a45a8ff	3896	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
bogdanm	0:9b334a45a8ff	3897	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
bogdanm	0:9b334a45a8ff	3898	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
bogdanm	0:9b334a45a8ff	3899	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
bogdanm	0:9b334a45a8ff	3900
bogdanm	0:9b334a45a8ff	3901	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
bogdanm	0:9b334a45a8ff	3902	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3903	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3904
bogdanm	0:9b334a45a8ff	3905	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
bogdanm	0:9b334a45a8ff	3906	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3907	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3908
bogdanm	0:9b334a45a8ff	3909	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
bogdanm	0:9b334a45a8ff	3910	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3911	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3912
bogdanm	0:9b334a45a8ff	3913	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
bogdanm	0:9b334a45a8ff	3914
bogdanm	0:9b334a45a8ff	3915	/**************** Bit definition for DMA_CNDTR register *****************/
bogdanm	0:9b334a45a8ff	3916	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
bogdanm	0:9b334a45a8ff	3917
bogdanm	0:9b334a45a8ff	3918	/**************** Bit definition for DMA_CPAR register ******************/
bogdanm	0:9b334a45a8ff	3919	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
bogdanm	0:9b334a45a8ff	3920
bogdanm	0:9b334a45a8ff	3921	/**************** Bit definition for DMA_CMAR register ******************/
bogdanm	0:9b334a45a8ff	3922	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
bogdanm	0:9b334a45a8ff	3923
bogdanm	0:9b334a45a8ff	3924
bogdanm	0:9b334a45a8ff	3925	/***************** Bit definition for DMA_CSELR register *****************/
bogdanm	0:9b334a45a8ff	3926	#define DMA_CSELR_C1S ((uint32_t)0x0000000F) /!< Channel 1 Selection /
bogdanm	0:9b334a45a8ff	3927	#define DMA_CSELR_C2S ((uint32_t)0x000000F0) /!< Channel 2 Selection /
bogdanm	0:9b334a45a8ff	3928	#define DMA_CSELR_C3S ((uint32_t)0x00000F00) /!< Channel 3 Selection /
bogdanm	0:9b334a45a8ff	3929	#define DMA_CSELR_C4S ((uint32_t)0x0000F000) /!< Channel 4 Selection /
bogdanm	0:9b334a45a8ff	3930	#define DMA_CSELR_C5S ((uint32_t)0x000F0000) /!< Channel 5 Selection /
bogdanm	0:9b334a45a8ff	3931	#define DMA_CSELR_C6S ((uint32_t)0x00F00000) /!< Channel 6 Selection /
bogdanm	0:9b334a45a8ff	3932	#define DMA_CSELR_C7S ((uint32_t)0x0F000000) /!< Channel 7 Selection /
bogdanm	0:9b334a45a8ff	3933
bogdanm	0:9b334a45a8ff	3934
bogdanm	0:9b334a45a8ff	3935	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3936	/* */
bogdanm	0:9b334a45a8ff	3937	/* External Interrupt/Event Controller */
bogdanm	0:9b334a45a8ff	3938	/* */
bogdanm	0:9b334a45a8ff	3939	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3940	/***************** Bit definition for EXTI_IMR1 register ****************/
bogdanm	0:9b334a45a8ff	3941	#define EXTI_IMR1_IM0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	0:9b334a45a8ff	3942	#define EXTI_IMR1_IM1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	0:9b334a45a8ff	3943	#define EXTI_IMR1_IM2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	0:9b334a45a8ff	3944	#define EXTI_IMR1_IM3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	0:9b334a45a8ff	3945	#define EXTI_IMR1_IM4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	0:9b334a45a8ff	3946	#define EXTI_IMR1_IM5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	0:9b334a45a8ff	3947	#define EXTI_IMR1_IM6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	0:9b334a45a8ff	3948	#define EXTI_IMR1_IM7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	0:9b334a45a8ff	3949	#define EXTI_IMR1_IM8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	0:9b334a45a8ff	3950	#define EXTI_IMR1_IM9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	0:9b334a45a8ff	3951	#define EXTI_IMR1_IM10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	0:9b334a45a8ff	3952	#define EXTI_IMR1_IM11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	0:9b334a45a8ff	3953	#define EXTI_IMR1_IM12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	0:9b334a45a8ff	3954	#define EXTI_IMR1_IM13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	0:9b334a45a8ff	3955	#define EXTI_IMR1_IM14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	0:9b334a45a8ff	3956	#define EXTI_IMR1_IM15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	0:9b334a45a8ff	3957	#define EXTI_IMR1_IM16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	0:9b334a45a8ff	3958	#define EXTI_IMR1_IM17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	0:9b334a45a8ff	3959	#define EXTI_IMR1_IM18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
bogdanm	0:9b334a45a8ff	3960	#define EXTI_IMR1_IM19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	0:9b334a45a8ff	3961	#define EXTI_IMR1_IM20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
bogdanm	0:9b334a45a8ff	3962	#define EXTI_IMR1_IM21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
bogdanm	0:9b334a45a8ff	3963	#define EXTI_IMR1_IM22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
bogdanm	0:9b334a45a8ff	3964	#define EXTI_IMR1_IM23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
bogdanm	0:9b334a45a8ff	3965	#define EXTI_IMR1_IM24 ((uint32_t)0x01000000) /!< Interrupt Mask on line 24 /
bogdanm	0:9b334a45a8ff	3966	#define EXTI_IMR1_IM25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
bogdanm	0:9b334a45a8ff	3967	#define EXTI_IMR1_IM26 ((uint32_t)0x04000000) /!< Interrupt Mask on line 26 /
bogdanm	0:9b334a45a8ff	3968	#define EXTI_IMR1_IM27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
bogdanm	0:9b334a45a8ff	3969	#define EXTI_IMR1_IM28 ((uint32_t)0x10000000) /!< Interrupt Mask on line 28 /
bogdanm	0:9b334a45a8ff	3970	#define EXTI_IMR1_IM29 ((uint32_t)0x20000000) /!< Interrupt Mask on line 29 /
bogdanm	0:9b334a45a8ff	3971	#define EXTI_IMR1_IM30 ((uint32_t)0x40000000) /!< Interrupt Mask on line 30 /
bogdanm	0:9b334a45a8ff	3972	#define EXTI_IMR1_IM31 ((uint32_t)0x80000000) /!< Interrupt Mask on line 31 /
bogdanm	0:9b334a45a8ff	3973
bogdanm	0:9b334a45a8ff	3974	/***************** Bit definition for EXTI_EMR1 register ****************/
bogdanm	0:9b334a45a8ff	3975	#define EXTI_EMR1_EM0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	0:9b334a45a8ff	3976	#define EXTI_EMR1_EM1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	0:9b334a45a8ff	3977	#define EXTI_EMR1_EM2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	0:9b334a45a8ff	3978	#define EXTI_EMR1_EM3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	0:9b334a45a8ff	3979	#define EXTI_EMR1_EM4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	0:9b334a45a8ff	3980	#define EXTI_EMR1_EM5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	0:9b334a45a8ff	3981	#define EXTI_EMR1_EM6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	0:9b334a45a8ff	3982	#define EXTI_EMR1_EM7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	0:9b334a45a8ff	3983	#define EXTI_EMR1_EM8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	0:9b334a45a8ff	3984	#define EXTI_EMR1_EM9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	0:9b334a45a8ff	3985	#define EXTI_EMR1_EM10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	0:9b334a45a8ff	3986	#define EXTI_EMR1_EM11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	0:9b334a45a8ff	3987	#define EXTI_EMR1_EM12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	0:9b334a45a8ff	3988	#define EXTI_EMR1_EM13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	0:9b334a45a8ff	3989	#define EXTI_EMR1_EM14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	0:9b334a45a8ff	3990	#define EXTI_EMR1_EM15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	0:9b334a45a8ff	3991	#define EXTI_EMR1_EM16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	0:9b334a45a8ff	3992	#define EXTI_EMR1_EM17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	0:9b334a45a8ff	3993	#define EXTI_EMR1_EM18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
bogdanm	0:9b334a45a8ff	3994	#define EXTI_EMR1_EM19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	0:9b334a45a8ff	3995	#define EXTI_EMR1_EM20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
bogdanm	0:9b334a45a8ff	3996	#define EXTI_EMR1_EM21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
bogdanm	0:9b334a45a8ff	3997	#define EXTI_EMR1_EM22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
bogdanm	0:9b334a45a8ff	3998	#define EXTI_EMR1_EM23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
bogdanm	0:9b334a45a8ff	3999	#define EXTI_EMR1_EM24 ((uint32_t)0x01000000) /!< Event Mask on line 24 /
bogdanm	0:9b334a45a8ff	4000	#define EXTI_EMR1_EM25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
bogdanm	0:9b334a45a8ff	4001	#define EXTI_EMR1_EM26 ((uint32_t)0x04000000) /!< Event Mask on line 26 /
bogdanm	0:9b334a45a8ff	4002	#define EXTI_EMR1_EM27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
bogdanm	0:9b334a45a8ff	4003	#define EXTI_EMR1_EM28 ((uint32_t)0x10000000) /!< Event Mask on line 28 /
bogdanm	0:9b334a45a8ff	4004	#define EXTI_EMR1_EM29 ((uint32_t)0x20000000) /!< Event Mask on line 29 /
bogdanm	0:9b334a45a8ff	4005	#define EXTI_EMR1_EM30 ((uint32_t)0x40000000) /!< Event Mask on line 30 /
bogdanm	0:9b334a45a8ff	4006	#define EXTI_EMR1_EM31 ((uint32_t)0x80000000) /!< Event Mask on line 31 /
bogdanm	0:9b334a45a8ff	4007
bogdanm	0:9b334a45a8ff	4008	/**************** Bit definition for EXTI_RTSR1 register ****************/
bogdanm	0:9b334a45a8ff	4009	#define EXTI_RTSR1_RT0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	4010	#define EXTI_RTSR1_RT1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	4011	#define EXTI_RTSR1_RT2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	4012	#define EXTI_RTSR1_RT3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	4013	#define EXTI_RTSR1_RT4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	4014	#define EXTI_RTSR1_RT5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	4015	#define EXTI_RTSR1_RT6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	4016	#define EXTI_RTSR1_RT7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	4017	#define EXTI_RTSR1_RT8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	4018	#define EXTI_RTSR1_RT9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	4019	#define EXTI_RTSR1_RT10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	4020	#define EXTI_RTSR1_RT11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	4021	#define EXTI_RTSR1_RT12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	4022	#define EXTI_RTSR1_RT13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	4023	#define EXTI_RTSR1_RT14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	4024	#define EXTI_RTSR1_RT15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	4025	#define EXTI_RTSR1_RT16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	4026	#define EXTI_RTSR1_RT18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	4027	#define EXTI_RTSR1_RT19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	4028	#define EXTI_RTSR1_RT20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
bogdanm	0:9b334a45a8ff	4029	#define EXTI_RTSR1_RT21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
bogdanm	0:9b334a45a8ff	4030	#define EXTI_RTSR1_RT22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
bogdanm	0:9b334a45a8ff	4031
bogdanm	0:9b334a45a8ff	4032	/**************** Bit definition for EXTI_FTSR1 register ****************/
bogdanm	0:9b334a45a8ff	4033	#define EXTI_FTSR1_FT0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	4034	#define EXTI_FTSR1_FT1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	4035	#define EXTI_FTSR1_FT2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	4036	#define EXTI_FTSR1_FT3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	4037	#define EXTI_FTSR1_FT4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	4038	#define EXTI_FTSR1_FT5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	4039	#define EXTI_FTSR1_FT6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	4040	#define EXTI_FTSR1_FT7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	4041	#define EXTI_FTSR1_FT8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	4042	#define EXTI_FTSR1_FT9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	4043	#define EXTI_FTSR1_FT10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	4044	#define EXTI_FTSR1_FT11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	4045	#define EXTI_FTSR1_FT12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	4046	#define EXTI_FTSR1_FT13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	4047	#define EXTI_FTSR1_FT14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	4048	#define EXTI_FTSR1_FT15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	4049	#define EXTI_FTSR1_FT16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	4050	#define EXTI_FTSR1_FT18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	4051	#define EXTI_FTSR1_FT19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	4052	#define EXTI_FTSR1_FT20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
bogdanm	0:9b334a45a8ff	4053	#define EXTI_FTSR1_FT21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
bogdanm	0:9b334a45a8ff	4054	#define EXTI_FTSR1_FT22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
bogdanm	0:9b334a45a8ff	4055
bogdanm	0:9b334a45a8ff	4056	/**************** Bit definition for EXTI_SWIER1 register ***************/
bogdanm	0:9b334a45a8ff	4057	#define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	0:9b334a45a8ff	4058	#define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	0:9b334a45a8ff	4059	#define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	0:9b334a45a8ff	4060	#define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	0:9b334a45a8ff	4061	#define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	0:9b334a45a8ff	4062	#define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	0:9b334a45a8ff	4063	#define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	0:9b334a45a8ff	4064	#define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	0:9b334a45a8ff	4065	#define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	0:9b334a45a8ff	4066	#define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	0:9b334a45a8ff	4067	#define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	0:9b334a45a8ff	4068	#define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	0:9b334a45a8ff	4069	#define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	0:9b334a45a8ff	4070	#define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	0:9b334a45a8ff	4071	#define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	0:9b334a45a8ff	4072	#define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	0:9b334a45a8ff	4073	#define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	0:9b334a45a8ff	4074	#define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
bogdanm	0:9b334a45a8ff	4075	#define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	0:9b334a45a8ff	4076	#define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
bogdanm	0:9b334a45a8ff	4077	#define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
bogdanm	0:9b334a45a8ff	4078	#define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
bogdanm	0:9b334a45a8ff	4079
bogdanm	0:9b334a45a8ff	4080	/***************** Bit definition for EXTI_PR1 register *****************/
bogdanm	0:9b334a45a8ff	4081	#define EXTI_PR1_PIF0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
bogdanm	0:9b334a45a8ff	4082	#define EXTI_PR1_PIF1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
bogdanm	0:9b334a45a8ff	4083	#define EXTI_PR1_PIF2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
bogdanm	0:9b334a45a8ff	4084	#define EXTI_PR1_PIF3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
bogdanm	0:9b334a45a8ff	4085	#define EXTI_PR1_PIF4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
bogdanm	0:9b334a45a8ff	4086	#define EXTI_PR1_PIF5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
bogdanm	0:9b334a45a8ff	4087	#define EXTI_PR1_PIF6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
bogdanm	0:9b334a45a8ff	4088	#define EXTI_PR1_PIF7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
bogdanm	0:9b334a45a8ff	4089	#define EXTI_PR1_PIF8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
bogdanm	0:9b334a45a8ff	4090	#define EXTI_PR1_PIF9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
bogdanm	0:9b334a45a8ff	4091	#define EXTI_PR1_PIF10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
bogdanm	0:9b334a45a8ff	4092	#define EXTI_PR1_PIF11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
bogdanm	0:9b334a45a8ff	4093	#define EXTI_PR1_PIF12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
bogdanm	0:9b334a45a8ff	4094	#define EXTI_PR1_PIF13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
bogdanm	0:9b334a45a8ff	4095	#define EXTI_PR1_PIF14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
bogdanm	0:9b334a45a8ff	4096	#define EXTI_PR1_PIF15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
bogdanm	0:9b334a45a8ff	4097	#define EXTI_PR1_PIF16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
bogdanm	0:9b334a45a8ff	4098	#define EXTI_PR1_PIF18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
bogdanm	0:9b334a45a8ff	4099	#define EXTI_PR1_PIF19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
bogdanm	0:9b334a45a8ff	4100	#define EXTI_PR1_PIF20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
bogdanm	0:9b334a45a8ff	4101	#define EXTI_PR1_PIF21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
bogdanm	0:9b334a45a8ff	4102	#define EXTI_PR1_PIF22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
bogdanm	0:9b334a45a8ff	4103
bogdanm	0:9b334a45a8ff	4104	/***************** Bit definition for EXTI_IMR2 register ****************/
bogdanm	0:9b334a45a8ff	4105	#define EXTI_IMR2_IM32 ((uint32_t)0x00000001) /!< Interrupt Mask on line 32 /
bogdanm	0:9b334a45a8ff	4106	#define EXTI_IMR2_IM33 ((uint32_t)0x00000002) /!< Interrupt Mask on line 33 /
bogdanm	0:9b334a45a8ff	4107	#define EXTI_IMR2_IM34 ((uint32_t)0x00000004) /!< Interrupt Mask on line 34 /
bogdanm	0:9b334a45a8ff	4108	#define EXTI_IMR2_IM35 ((uint32_t)0x00000008) /!< Interrupt Mask on line 35 /
bogdanm	0:9b334a45a8ff	4109	#define EXTI_IMR2_IM36 ((uint32_t)0x00000010) /!< Interrupt Mask on line 36 /
bogdanm	0:9b334a45a8ff	4110	#define EXTI_IMR2_IM37 ((uint32_t)0x00000020) /!< Interrupt Mask on line 37 /
bogdanm	0:9b334a45a8ff	4111	#define EXTI_IMR2_IM38 ((uint32_t)0x00000040) /!< Interrupt Mask on line 38 /
bogdanm	0:9b334a45a8ff	4112	#define EXTI_IMR2_IM39 ((uint32_t)0x00000080) /!< Interrupt Mask on line 39 /
bogdanm	0:9b334a45a8ff	4113
bogdanm	0:9b334a45a8ff	4114	/***************** Bit definition for EXTI_EMR2 register ****************/
bogdanm	0:9b334a45a8ff	4115	#define EXTI_EMR2_EM32 ((uint32_t)0x00000001) /!< Event Mask on line 32 /
bogdanm	0:9b334a45a8ff	4116	#define EXTI_EMR2_EM33 ((uint32_t)0x00000002) /!< Event Mask on line 33 /
bogdanm	0:9b334a45a8ff	4117	#define EXTI_EMR2_EM34 ((uint32_t)0x00000004) /!< Event Mask on line 34 /
bogdanm	0:9b334a45a8ff	4118	#define EXTI_EMR2_EM35 ((uint32_t)0x00000008) /!< Event Mask on line 35 /
bogdanm	0:9b334a45a8ff	4119	#define EXTI_EMR2_EM36 ((uint32_t)0x00000010) /!< Event Mask on line 36 /
bogdanm	0:9b334a45a8ff	4120	#define EXTI_EMR2_EM37 ((uint32_t)0x00000020) /!< Event Mask on line 37 /
bogdanm	0:9b334a45a8ff	4121	#define EXTI_EMR2_EM38 ((uint32_t)0x00000040) /!< Event Mask on line 38 /
bogdanm	0:9b334a45a8ff	4122	#define EXTI_EMR2_EM39 ((uint32_t)0x00000080) /!< Event Mask on line 39 /
bogdanm	0:9b334a45a8ff	4123
bogdanm	0:9b334a45a8ff	4124	/**************** Bit definition for EXTI_RTSR2 register ****************/
bogdanm	0:9b334a45a8ff	4125	#define EXTI_RTSR2_RT35 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 35 /
bogdanm	0:9b334a45a8ff	4126	#define EXTI_RTSR2_RT36 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 36 /
bogdanm	0:9b334a45a8ff	4127	#define EXTI_RTSR2_RT37 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 37 /
bogdanm	0:9b334a45a8ff	4128	#define EXTI_RTSR2_RT38 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 38 /
bogdanm	0:9b334a45a8ff	4129
bogdanm	0:9b334a45a8ff	4130	/**************** Bit definition for EXTI_FTSR2 register ****************/
bogdanm	0:9b334a45a8ff	4131	#define EXTI_FTSR2_FT35 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 35 /
bogdanm	0:9b334a45a8ff	4132	#define EXTI_FTSR2_FT36 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 36 /
bogdanm	0:9b334a45a8ff	4133	#define EXTI_FTSR2_FT37 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 37 /
bogdanm	0:9b334a45a8ff	4134	#define EXTI_FTSR2_FT38 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 38 /
bogdanm	0:9b334a45a8ff	4135
bogdanm	0:9b334a45a8ff	4136	/**************** Bit definition for EXTI_SWIER2 register ***************/
bogdanm	0:9b334a45a8ff	4137	#define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008) /!< Software Interrupt on line 35 /
bogdanm	0:9b334a45a8ff	4138	#define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010) /!< Software Interrupt on line 36 /
bogdanm	0:9b334a45a8ff	4139	#define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020) /!< Software Interrupt on line 37 /
bogdanm	0:9b334a45a8ff	4140	#define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040) /!< Software Interrupt on line 38 /
bogdanm	0:9b334a45a8ff	4141
bogdanm	0:9b334a45a8ff	4142	/***************** Bit definition for EXTI_PR2 register *****************/
bogdanm	0:9b334a45a8ff	4143	#define EXTI_PR2_PIF35 ((uint32_t)0x00000008) /!< Pending bit for line 35 /
bogdanm	0:9b334a45a8ff	4144	#define EXTI_PR2_PIF36 ((uint32_t)0x00000010) /!< Pending bit for line 36 /
bogdanm	0:9b334a45a8ff	4145	#define EXTI_PR2_PIF37 ((uint32_t)0x00000020) /!< Pending bit for line 37 /
bogdanm	0:9b334a45a8ff	4146	#define EXTI_PR2_PIF38 ((uint32_t)0x00000040) /!< Pending bit for line 38 /
bogdanm	0:9b334a45a8ff	4147
bogdanm	0:9b334a45a8ff	4148
bogdanm	0:9b334a45a8ff	4149	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4150	/* */
bogdanm	0:9b334a45a8ff	4151	/* FLASH */
bogdanm	0:9b334a45a8ff	4152	/* */
bogdanm	0:9b334a45a8ff	4153	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4154	/***************** Bits definition for FLASH_ACR register ***************/
bogdanm	0:9b334a45a8ff	4155	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
bogdanm	0:9b334a45a8ff	4156	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	4157	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4158	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4159	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	4160	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4161	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4162	#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4163	#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4164	#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4165	#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4166	#define FLASH_ACR_RUN_PD ((uint32_t)0x00002000) /!< Flash power down mode during run /
bogdanm	0:9b334a45a8ff	4167	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000) /!< Flash power down mode during sleep /
bogdanm	0:9b334a45a8ff	4168
bogdanm	0:9b334a45a8ff	4169	/***************** Bits definition for FLASH_SR register ****************/
bogdanm	0:9b334a45a8ff	4170	#define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4171	#define FLASH_SR_OPERR ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4172	#define FLASH_SR_PROGERR ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4173	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4174	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4175	#define FLASH_SR_SIZERR ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4176	#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4177	#define FLASH_SR_MISERR ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4178	#define FLASH_SR_FASTERR ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4179	#define FLASH_SR_RDERR ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4180	#define FLASH_SR_OPTVERR ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4181	#define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4182
bogdanm	0:9b334a45a8ff	4183	/***************** Bits definition for FLASH_CR register ****************/
bogdanm	0:9b334a45a8ff	4184	#define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4185	#define FLASH_CR_PER ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4186	#define FLASH_CR_MER1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4187	#define FLASH_CR_PNB ((uint32_t)0x000007F8)
bogdanm	0:9b334a45a8ff	4188	/*#define FLASH_CR_PNB_0 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4189	#define FLASH_CR_PNB_1 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4190	#define FLASH_CR_PNB_2 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4191	#define FLASH_CR_PNB_3 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4192	#define FLASH_CR_PNB_4 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4193	#define FLASH_CR_PNB_5 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4194	#define FLASH_CR_PNB_6 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4195	#define FLASH_CR_PNB_7 ((uint32_t)0x00000400)*/
bogdanm	0:9b334a45a8ff	4196	#define FLASH_CR_BKER ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4197	#define FLASH_CR_MER2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4198	#define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4199	#define FLASH_CR_OPTSTRT ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4200	#define FLASH_CR_FSTPG ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4201	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4202	#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4203	#define FLASH_CR_RDERRIE ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	4204	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	4205	#define FLASH_CR_OPTLOCK ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4206	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4207
bogdanm	0:9b334a45a8ff	4208	/***************** Bits definition for FLASH_ECCR register *************/
bogdanm	0:9b334a45a8ff	4209	#define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFF)
bogdanm	0:9b334a45a8ff	4210	/*#define FLASH_ECCR_ADDR_ECC_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4211	#define FLASH_ECCR_ADDR_ECC_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4212	#define FLASH_ECCR_ADDR_ECC_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4213	#define FLASH_ECCR_ADDR_ECC_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4214	#define FLASH_ECCR_ADDR_ECC_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4215	#define FLASH_ECCR_ADDR_ECC_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4216	#define FLASH_ECCR_ADDR_ECC_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4217	#define FLASH_ECCR_ADDR_ECC_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4218	#define FLASH_ECCR_ADDR_ECC_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4219	#define FLASH_ECCR_ADDR_ECC_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4220	#define FLASH_ECCR_ADDR_ECC_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4221	#define FLASH_ECCR_ADDR_ECC_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4222	#define FLASH_ECCR_ADDR_ECC_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4223	#define FLASH_ECCR_ADDR_ECC_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4224	#define FLASH_ECCR_ADDR_ECC_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4225	#define FLASH_ECCR_ADDR_ECC_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4226	#define FLASH_ECCR_ADDR_ECC_16 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4227	#define FLASH_ECCR_ADDR_ECC_17 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4228	#define FLASH_ECCR_ADDR_ECC_18 ((uint32_t)0x00040000)*/
bogdanm	0:9b334a45a8ff	4229	#define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4230	#define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4231	#define FLASH_ECCR_ECCIE ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4232	#define FLASH_ECCR_ECCC ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4233	#define FLASH_ECCR_ECCD ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4234
bogdanm	0:9b334a45a8ff	4235	/***************** Bits definition for FLASH_OPTR register *************/
bogdanm	0:9b334a45a8ff	4236	#define FLASH_OPTR_RDP ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	4237	/*#define FLASH_OPTR_RDP_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4238	#define FLASH_OPTR_RDP_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4239	#define FLASH_OPTR_RDP_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4240	#define FLASH_OPTR_RDP_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4241	#define FLASH_OPTR_RDP_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4242	#define FLASH_OPTR_RDP_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4243	#define FLASH_OPTR_RDP_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4244	#define FLASH_OPTR_RDP_7 ((uint32_t)0x00000080)*/
bogdanm	0:9b334a45a8ff	4245	#define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700)
bogdanm	0:9b334a45a8ff	4246	#define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	4247	#define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4248	#define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4249	#define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	4250	#define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4251	#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4252	#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4253	#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4254	#define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4255	#define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4256	#define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4257	#define FLASH_OPTR_BFB2 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4258	#define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	4259	#define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	4260	#define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4261	#define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4262
bogdanm	0:9b334a45a8ff	4263	/**************** Bits definition for FLASH_PCROP1SR register ********/
bogdanm	0:9b334a45a8ff	4264	#define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	4265
bogdanm	0:9b334a45a8ff	4266	/**************** Bits definition for FLASH_PCROP1ER register *********/
bogdanm	0:9b334a45a8ff	4267	#define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	4268	#define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4269
bogdanm	0:9b334a45a8ff	4270	/**************** Bits definition for FLASH_WRP1AR register *************/
bogdanm	0:9b334a45a8ff	4271	#define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	4272	#define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000)
bogdanm	0:9b334a45a8ff	4273
bogdanm	0:9b334a45a8ff	4274	/**************** Bits definition for FLASH_WRPB1R register *************/
bogdanm	0:9b334a45a8ff	4275	#define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	4276	#define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000)
bogdanm	0:9b334a45a8ff	4277
bogdanm	0:9b334a45a8ff	4278	/**************** Bits definition for FLASH_PCROP2SR register ********/
bogdanm	0:9b334a45a8ff	4279	#define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	4280
bogdanm	0:9b334a45a8ff	4281	/**************** Bits definition for FLASH_PCROP2ER register *********/
bogdanm	0:9b334a45a8ff	4282	#define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	4283
bogdanm	0:9b334a45a8ff	4284	/**************** Bits definition for FLASH_WRP2AR register *************/
bogdanm	0:9b334a45a8ff	4285	#define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	4286	#define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000)
bogdanm	0:9b334a45a8ff	4287
bogdanm	0:9b334a45a8ff	4288	/**************** Bits definition for FLASH_WRP2BR register *************/
bogdanm	0:9b334a45a8ff	4289	#define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	4290	#define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000)
bogdanm	0:9b334a45a8ff	4291
bogdanm	0:9b334a45a8ff	4292
bogdanm	0:9b334a45a8ff	4293	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4294	/* */
bogdanm	0:9b334a45a8ff	4295	/* Flexible Memory Controller */
bogdanm	0:9b334a45a8ff	4296	/* */
bogdanm	0:9b334a45a8ff	4297	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4298	/**************** Bit definition for FMC_BCR1 register *****************/
bogdanm	0:9b334a45a8ff	4299	#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /!<Continous clock enable /
bogdanm	0:9b334a45a8ff	4300	#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /!<Write FIFO Disable /
bogdanm	0:9b334a45a8ff	4301
bogdanm	0:9b334a45a8ff	4302	/**************** Bit definition for FMC_BCRx registers (x=1..4) *******/
bogdanm	0:9b334a45a8ff	4303	#define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
bogdanm	0:9b334a45a8ff	4304	#define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
bogdanm	0:9b334a45a8ff	4305
bogdanm	0:9b334a45a8ff	4306	#define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
bogdanm	0:9b334a45a8ff	4307	#define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4308	#define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4309
bogdanm	0:9b334a45a8ff	4310	#define FMC_BCRx_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
bogdanm	0:9b334a45a8ff	4311	#define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4312	#define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4313
bogdanm	0:9b334a45a8ff	4314	#define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
bogdanm	0:9b334a45a8ff	4315	#define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
bogdanm	0:9b334a45a8ff	4316	#define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
bogdanm	0:9b334a45a8ff	4317	#define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
bogdanm	0:9b334a45a8ff	4318	#define FMC_BCRx_WREN ((uint32_t)0x00001000) /!<Write enable bit /
bogdanm	0:9b334a45a8ff	4319	#define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
bogdanm	0:9b334a45a8ff	4320	#define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
bogdanm	0:9b334a45a8ff	4321	#define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
bogdanm	0:9b334a45a8ff	4322
bogdanm	0:9b334a45a8ff	4323	#define FMC_BCRx_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
bogdanm	0:9b334a45a8ff	4324	#define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4325	#define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4326	#define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4327
bogdanm	0:9b334a45a8ff	4328	#define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
bogdanm	0:9b334a45a8ff	4329
bogdanm	0:9b334a45a8ff	4330	/**************** Bit definition for FMC_BTRx registers (x=1..4) *******/
bogdanm	0:9b334a45a8ff	4331	#define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	0:9b334a45a8ff	4332	#define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4333	#define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4334	#define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4335	#define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4336
bogdanm	0:9b334a45a8ff	4337	#define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	0:9b334a45a8ff	4338	#define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4339	#define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4340	#define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4341	#define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4342
bogdanm	0:9b334a45a8ff	4343	#define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	0:9b334a45a8ff	4344	#define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4345	#define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4346	#define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4347	#define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4348	#define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4349	#define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4350	#define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4351	#define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4352
bogdanm	0:9b334a45a8ff	4353	#define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
bogdanm	0:9b334a45a8ff	4354	#define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4355	#define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4356	#define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4357	#define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4358
bogdanm	0:9b334a45a8ff	4359	#define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	0:9b334a45a8ff	4360	#define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4361	#define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4362	#define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4363	#define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4364
bogdanm	0:9b334a45a8ff	4365	#define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	0:9b334a45a8ff	4366	#define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4367	#define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4368	#define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4369	#define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4370
bogdanm	0:9b334a45a8ff	4371	#define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	0:9b334a45a8ff	4372	#define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4373	#define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4374
bogdanm	0:9b334a45a8ff	4375	/**************** Bit definition for FMC_BWTRx registers (x=1..4) *******/
bogdanm	0:9b334a45a8ff	4376	#define FMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	0:9b334a45a8ff	4377	#define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4378	#define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4379	#define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4380	#define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4381
bogdanm	0:9b334a45a8ff	4382	#define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	0:9b334a45a8ff	4383	#define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4384	#define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4385	#define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4386	#define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4387
bogdanm	0:9b334a45a8ff	4388	#define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	0:9b334a45a8ff	4389	#define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4390	#define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4391	#define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4392	#define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4393	#define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4394	#define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4395	#define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4396	#define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4397
bogdanm	0:9b334a45a8ff	4398	#define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	0:9b334a45a8ff	4399	#define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4400	#define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4401
bogdanm	0:9b334a45a8ff	4402	/**************** Bit definition for FMC_PCR register ******************/
bogdanm	0:9b334a45a8ff	4403	#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
bogdanm	0:9b334a45a8ff	4404	#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /!<NAND Flash memory bank enable bit /
bogdanm	0:9b334a45a8ff	4405	#define FMC_PCR_PTYP ((uint32_t)0x00000008) /!<Memory type /
bogdanm	0:9b334a45a8ff	4406
bogdanm	0:9b334a45a8ff	4407	#define FMC_PCR_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
bogdanm	0:9b334a45a8ff	4408	#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4409	#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4410
bogdanm	0:9b334a45a8ff	4411	#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
bogdanm	0:9b334a45a8ff	4412
bogdanm	0:9b334a45a8ff	4413	#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
bogdanm	0:9b334a45a8ff	4414	#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4415	#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4416	#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4417	#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4418
bogdanm	0:9b334a45a8ff	4419	#define FMC_PCR_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
bogdanm	0:9b334a45a8ff	4420	#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4421	#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4422	#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4423	#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4424
bogdanm	0:9b334a45a8ff	4425	#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[1:0] bits (ECC page size) /
bogdanm	0:9b334a45a8ff	4426	#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4427	#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4428	#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4429
bogdanm	0:9b334a45a8ff	4430	/***************** Bit definition for FMC_SR register ******************/
bogdanm	0:9b334a45a8ff	4431	#define FMC_SR_IRS ((uint32_t)0x00000001) /!<Interrupt Rising Edge status /
bogdanm	0:9b334a45a8ff	4432	#define FMC_SR_ILS ((uint32_t)0x00000002) /!<Interrupt Level status /
bogdanm	0:9b334a45a8ff	4433	#define FMC_SR_IFS ((uint32_t)0x00000004) /!<Interrupt Falling Edge status /
bogdanm	0:9b334a45a8ff	4434	#define FMC_SR_IREN ((uint32_t)0x00000008) /!<Interrupt Rising Edge detection Enable bit /
bogdanm	0:9b334a45a8ff	4435	#define FMC_SR_ILEN ((uint32_t)0x00000010) /!<Interrupt Level detection Enable bit /
bogdanm	0:9b334a45a8ff	4436	#define FMC_SR_IFEN ((uint32_t)0x00000020) /!<Interrupt Falling Edge detection Enable bit /
bogdanm	0:9b334a45a8ff	4437	#define FMC_SR_FEMPT ((uint32_t)0x00000040) /!<FIFO empty /
bogdanm	0:9b334a45a8ff	4438
bogdanm	0:9b334a45a8ff	4439	/**************** Bit definition for FMC_PMEM register ****************/
bogdanm	0:9b334a45a8ff	4440	#define FMC_PMEM_MEMSET ((uint32_t)0x000000FF) /!<MEMSET[7:0] bits (Common memory setup time) /
bogdanm	0:9b334a45a8ff	4441	#define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4442	#define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4443	#define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4444	#define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4445	#define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4446	#define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4447	#define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4448	#define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4449
bogdanm	0:9b334a45a8ff	4450	#define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00) /!<MEMWAIT[7:0] bits (Common memory wait time) /
bogdanm	0:9b334a45a8ff	4451	#define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4452	#define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4453	#define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4454	#define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4455	#define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4456	#define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4457	#define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4458	#define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4459
bogdanm	0:9b334a45a8ff	4460	#define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000) /!<MEMHOLD[7:0] bits (Common memory hold time) /
bogdanm	0:9b334a45a8ff	4461	#define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4462	#define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4463	#define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4464	#define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4465	#define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4466	#define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4467	#define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4468	#define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4469
bogdanm	0:9b334a45a8ff	4470	#define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000) /!<MEMHIZ[7:0] bits (Common memory databus HiZ time) /
bogdanm	0:9b334a45a8ff	4471	#define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4472	#define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4473	#define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4474	#define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4475	#define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4476	#define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4477	#define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4478	#define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4479
bogdanm	0:9b334a45a8ff	4480	/**************** Bit definition for FMC_PATT register *****************/
bogdanm	0:9b334a45a8ff	4481	#define FMC_PATT_ATTSET ((uint32_t)0x000000FF) /!<ATTSET[7:0] bits (Attribute memory setup time) /
bogdanm	0:9b334a45a8ff	4482	#define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4483	#define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4484	#define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4485	#define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4486	#define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4487	#define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4488	#define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4489	#define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4490
bogdanm	0:9b334a45a8ff	4491	#define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00) /!<ATTWAIT[7:0] bits (Attribute memory wait time) /
bogdanm	0:9b334a45a8ff	4492	#define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4493	#define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4494	#define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4495	#define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4496	#define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4497	#define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4498	#define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4499	#define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4500
bogdanm	0:9b334a45a8ff	4501	#define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000) /!<ATTHOLD[7:0] bits (Attribute memory hold time) /
bogdanm	0:9b334a45a8ff	4502	#define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4503	#define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4504	#define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4505	#define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4506	#define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4507	#define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4508	#define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4509	#define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4510
bogdanm	0:9b334a45a8ff	4511	#define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000) /!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) /
bogdanm	0:9b334a45a8ff	4512	#define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	4513	#define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	4514	#define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	4515	#define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	4516	#define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	4517	#define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	4518	#define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	4519	#define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	4520
bogdanm	0:9b334a45a8ff	4521	/**************** Bit definition for FMC_ECCR register *****************/
bogdanm	0:9b334a45a8ff	4522	#define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFF) /!<ECC result /
bogdanm	0:9b334a45a8ff	4523
bogdanm	0:9b334a45a8ff	4524	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4525	/* */
bogdanm	0:9b334a45a8ff	4526	/* General Purpose I/O */
bogdanm	0:9b334a45a8ff	4527	/* */
bogdanm	0:9b334a45a8ff	4528	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4529	/**************** Bits definition for GPIO_MODER register ***************/
bogdanm	0:9b334a45a8ff	4530	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	4531	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4532	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4533	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	4534	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4535	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4536	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	4537	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4538	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4539	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	4540	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4541	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4542	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	4543	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4544	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4545	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	4546	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4547	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4548	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	4549	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4550	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4551	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	4552	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4553	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4554	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	4555	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4556	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4557	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	4558	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4559	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4560	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	4561	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4562	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	4563	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	4564	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	4565	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	4566	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	4567	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4568	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4569	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	4570	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	4571	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	4572	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	4573	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	4574	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	4575	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	4576	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4577	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4578
bogdanm	0:9b334a45a8ff	4579	/**************** Bits definition for GPIO_OTYPER register **************/
bogdanm	0:9b334a45a8ff	4580	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4581	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4582	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4583	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4584	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4585	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4586	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4587	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4588	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4589	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4590	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4591	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4592	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4593	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4594	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4595	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4596
bogdanm	0:9b334a45a8ff	4597	/**************** Bits definition for GPIO_OSPEEDR register *************/
bogdanm	0:9b334a45a8ff	4598	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	4599	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4600	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4601	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	4602	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4603	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4604	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	4605	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4606	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4607	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	4608	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4609	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4610	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	4611	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4612	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4613	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	4614	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4615	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4616	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	4617	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4618	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4619	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	4620	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4621	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4622	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	4623	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4624	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4625	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	4626	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4627	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4628	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	4629	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4630	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	4631	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	4632	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	4633	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	4634	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	4635	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4636	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4637	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	4638	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	4639	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	4640	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	4641	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	4642	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	4643	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	4644	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4645	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4646
bogdanm	0:9b334a45a8ff	4647	/**************** Bits definition for GPIO_PUPDR register ***************/
bogdanm	0:9b334a45a8ff	4648	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	4649	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4650	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4651	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	4652	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4653	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4654	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	4655	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4656	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4657	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	4658	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4659	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4660	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	4661	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4662	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4663	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	4664	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4665	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4666	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	4667	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4668	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4669	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	4670	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4671	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4672	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	4673	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4674	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4675	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	4676	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4677	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4678	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	4679	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4680	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	4681	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	4682	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	4683	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	4684	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	4685	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4686	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4687	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	4688	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	4689	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	4690	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	4691	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	4692	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	4693	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	4694	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4695	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4696
bogdanm	0:9b334a45a8ff	4697	/**************** Bits definition for GPIO_IDR register *****************/
bogdanm	0:9b334a45a8ff	4698	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4699	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4700	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4701	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4702	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4703	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4704	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4705	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4706	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4707	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4708	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4709	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4710	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4711	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4712	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4713	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4714
bogdanm	0:9b334a45a8ff	4715	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	4716	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm	0:9b334a45a8ff	4717	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm	0:9b334a45a8ff	4718	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm	0:9b334a45a8ff	4719	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm	0:9b334a45a8ff	4720	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm	0:9b334a45a8ff	4721	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm	0:9b334a45a8ff	4722	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm	0:9b334a45a8ff	4723	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm	0:9b334a45a8ff	4724	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm	0:9b334a45a8ff	4725	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm	0:9b334a45a8ff	4726	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm	0:9b334a45a8ff	4727	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm	0:9b334a45a8ff	4728	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm	0:9b334a45a8ff	4729	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm	0:9b334a45a8ff	4730	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm	0:9b334a45a8ff	4731	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm	0:9b334a45a8ff	4732
bogdanm	0:9b334a45a8ff	4733	/**************** Bits definition for GPIO_ODR register *****************/
bogdanm	0:9b334a45a8ff	4734	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4735	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4736	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4737	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4738	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4739	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4740	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4741	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4742	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4743	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4744	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4745	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4746	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4747	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4748	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4749	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4750
bogdanm	0:9b334a45a8ff	4751	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	4752	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm	0:9b334a45a8ff	4753	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm	0:9b334a45a8ff	4754	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm	0:9b334a45a8ff	4755	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm	0:9b334a45a8ff	4756	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm	0:9b334a45a8ff	4757	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm	0:9b334a45a8ff	4758	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm	0:9b334a45a8ff	4759	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm	0:9b334a45a8ff	4760	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm	0:9b334a45a8ff	4761	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm	0:9b334a45a8ff	4762	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm	0:9b334a45a8ff	4763	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm	0:9b334a45a8ff	4764	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm	0:9b334a45a8ff	4765	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm	0:9b334a45a8ff	4766	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm	0:9b334a45a8ff	4767	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm	0:9b334a45a8ff	4768
bogdanm	0:9b334a45a8ff	4769	/**************** Bits definition for GPIO_BSRR register ****************/
bogdanm	0:9b334a45a8ff	4770	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4771	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4772	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4773	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4774	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4775	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4776	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4777	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4778	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4779	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4780	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4781	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4782	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4783	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4784	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4785	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4786	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4787	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	4788	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	4789	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	4790	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	4791	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	4792	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	4793	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	4794	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	4795	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	4796	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	4797	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	4798	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	4799	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	4800	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	4801	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	4802
bogdanm	0:9b334a45a8ff	4803	/**************** Bits definition for GPIO_BRR register ****************/
bogdanm	0:9b334a45a8ff	4804	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4805	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4806	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4807	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4808	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4809	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4810	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4811	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4812	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4813	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4814	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4815	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4816	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4817	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4818	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4819	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4820
bogdanm	0:9b334a45a8ff	4821	/**************** Bit definition for GPIO_LCKR register *******************/
bogdanm	0:9b334a45a8ff	4822	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4823	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4824	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4825	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4826	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4827	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4828	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4829	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4830	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4831	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4832	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4833	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4834	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4835	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4836	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4837	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4838	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	4839
bogdanm	0:9b334a45a8ff	4840	/**************** Bit definition for GPIO_AFRL register ******************/
bogdanm	0:9b334a45a8ff	4841	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	4842	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	4843	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	4844	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	4845	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	4846	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	4847	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	4848	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	4849
bogdanm	0:9b334a45a8ff	4850	/**************** Bit definition for GPIO_AFRH register ******************/
bogdanm	0:9b334a45a8ff	4851	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	4852	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	4853	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	4854	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	4855	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	4856	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	4857	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	4858	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	4859
bogdanm	0:9b334a45a8ff	4860	/**************** Bits definition for GPIO_ASCR register *****************/
bogdanm	0:9b334a45a8ff	4861	#define GPIO_ASCR_EN_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	4862	#define GPIO_ASCR_EN_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	4863	#define GPIO_ASCR_EN_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	4864	#define GPIO_ASCR_EN_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	4865	#define GPIO_ASCR_EN_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	4866	#define GPIO_ASCR_EN_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	4867	#define GPIO_ASCR_EN_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	4868	#define GPIO_ASCR_EN_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	4869	#define GPIO_ASCR_EN_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	4870	#define GPIO_ASCR_EN_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	4871	#define GPIO_ASCR_EN_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	4872	#define GPIO_ASCR_EN_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	4873	#define GPIO_ASCR_EN_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	4874	#define GPIO_ASCR_EN_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	4875	#define GPIO_ASCR_EN_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	4876	#define GPIO_ASCR_EN_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	4877
bogdanm	0:9b334a45a8ff	4878	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4879	/* */
bogdanm	0:9b334a45a8ff	4880	/* Inter-integrated Circuit Interface (I2C) */
bogdanm	0:9b334a45a8ff	4881	/* */
bogdanm	0:9b334a45a8ff	4882	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4883	/***************** Bit definition for I2C_CR1 register *****************/
bogdanm	0:9b334a45a8ff	4884	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
bogdanm	0:9b334a45a8ff	4885	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
bogdanm	0:9b334a45a8ff	4886	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
bogdanm	0:9b334a45a8ff	4887	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
bogdanm	0:9b334a45a8ff	4888	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
bogdanm	0:9b334a45a8ff	4889	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
bogdanm	0:9b334a45a8ff	4890	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	4891	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
bogdanm	0:9b334a45a8ff	4892	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
bogdanm	0:9b334a45a8ff	4893	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
bogdanm	0:9b334a45a8ff	4894	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
bogdanm	0:9b334a45a8ff	4895	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
bogdanm	0:9b334a45a8ff	4896	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
bogdanm	0:9b334a45a8ff	4897	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
bogdanm	0:9b334a45a8ff	4898	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
bogdanm	0:9b334a45a8ff	4899	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
bogdanm	0:9b334a45a8ff	4900	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
bogdanm	0:9b334a45a8ff	4901	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
bogdanm	0:9b334a45a8ff	4902	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
bogdanm	0:9b334a45a8ff	4903	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
bogdanm	0:9b334a45a8ff	4904	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
bogdanm	0:9b334a45a8ff	4905
bogdanm	0:9b334a45a8ff	4906	/**************** Bit definition for I2C_CR2 register ******************/
bogdanm	0:9b334a45a8ff	4907	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
bogdanm	0:9b334a45a8ff	4908	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
bogdanm	0:9b334a45a8ff	4909	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
bogdanm	0:9b334a45a8ff	4910	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
bogdanm	0:9b334a45a8ff	4911	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
bogdanm	0:9b334a45a8ff	4912	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
bogdanm	0:9b334a45a8ff	4913	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
bogdanm	0:9b334a45a8ff	4914	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
bogdanm	0:9b334a45a8ff	4915	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
bogdanm	0:9b334a45a8ff	4916	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
bogdanm	0:9b334a45a8ff	4917	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
bogdanm	0:9b334a45a8ff	4918
bogdanm	0:9b334a45a8ff	4919	/***************** Bit definition for I2C_OAR1 register ****************/
bogdanm	0:9b334a45a8ff	4920	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
bogdanm	0:9b334a45a8ff	4921	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
bogdanm	0:9b334a45a8ff	4922	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
bogdanm	0:9b334a45a8ff	4923
bogdanm	0:9b334a45a8ff	4924	/***************** Bit definition for I2C_OAR2 register ****************/
bogdanm	0:9b334a45a8ff	4925	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
bogdanm	0:9b334a45a8ff	4926	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
bogdanm	0:9b334a45a8ff	4927	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /!< No mask /
bogdanm	0:9b334a45a8ff	4928	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /!< OA2[1] is masked, Only OA2[7:2] are compared /
bogdanm	0:9b334a45a8ff	4929	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
bogdanm	0:9b334a45a8ff	4930	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
bogdanm	0:9b334a45a8ff	4931	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
bogdanm	0:9b334a45a8ff	4932	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
bogdanm	0:9b334a45a8ff	4933	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /!< OA2[6:1] is masked, Only OA2[7] are compared /
bogdanm	0:9b334a45a8ff	4934	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /!< OA2[7:1] is masked, No comparison is done /
bogdanm	0:9b334a45a8ff	4935	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
bogdanm	0:9b334a45a8ff	4936
bogdanm	0:9b334a45a8ff	4937	/***************** Bit definition for I2C_TIMINGR register *****************/
bogdanm	0:9b334a45a8ff	4938	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
bogdanm	0:9b334a45a8ff	4939	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
bogdanm	0:9b334a45a8ff	4940	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
bogdanm	0:9b334a45a8ff	4941	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
bogdanm	0:9b334a45a8ff	4942	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
bogdanm	0:9b334a45a8ff	4943
bogdanm	0:9b334a45a8ff	4944	/***************** Bit definition for I2C_TIMEOUTR register *****************/
bogdanm	0:9b334a45a8ff	4945	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
bogdanm	0:9b334a45a8ff	4946	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
bogdanm	0:9b334a45a8ff	4947	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
bogdanm	0:9b334a45a8ff	4948	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B /
bogdanm	0:9b334a45a8ff	4949	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
bogdanm	0:9b334a45a8ff	4950
bogdanm	0:9b334a45a8ff	4951	/**************** Bit definition for I2C_ISR register *******************/
bogdanm	0:9b334a45a8ff	4952	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
bogdanm	0:9b334a45a8ff	4953	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
bogdanm	0:9b334a45a8ff	4954	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
bogdanm	0:9b334a45a8ff	4955	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode) /
bogdanm	0:9b334a45a8ff	4956	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
bogdanm	0:9b334a45a8ff	4957	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
bogdanm	0:9b334a45a8ff	4958	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
bogdanm	0:9b334a45a8ff	4959	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
bogdanm	0:9b334a45a8ff	4960	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
bogdanm	0:9b334a45a8ff	4961	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
bogdanm	0:9b334a45a8ff	4962	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
bogdanm	0:9b334a45a8ff	4963	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
bogdanm	0:9b334a45a8ff	4964	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
bogdanm	0:9b334a45a8ff	4965	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
bogdanm	0:9b334a45a8ff	4966	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
bogdanm	0:9b334a45a8ff	4967	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
bogdanm	0:9b334a45a8ff	4968	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
bogdanm	0:9b334a45a8ff	4969
bogdanm	0:9b334a45a8ff	4970	/**************** Bit definition for I2C_ICR register *******************/
bogdanm	0:9b334a45a8ff	4971	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
bogdanm	0:9b334a45a8ff	4972	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
bogdanm	0:9b334a45a8ff	4973	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
bogdanm	0:9b334a45a8ff	4974	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
bogdanm	0:9b334a45a8ff	4975	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
bogdanm	0:9b334a45a8ff	4976	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
bogdanm	0:9b334a45a8ff	4977	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
bogdanm	0:9b334a45a8ff	4978	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
bogdanm	0:9b334a45a8ff	4979	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
bogdanm	0:9b334a45a8ff	4980
bogdanm	0:9b334a45a8ff	4981	/**************** Bit definition for I2C_PECR register *******************/
bogdanm	0:9b334a45a8ff	4982	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
bogdanm	0:9b334a45a8ff	4983
bogdanm	0:9b334a45a8ff	4984	/**************** Bit definition for I2C_RXDR register *******************/
bogdanm	0:9b334a45a8ff	4985	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
bogdanm	0:9b334a45a8ff	4986
bogdanm	0:9b334a45a8ff	4987	/**************** Bit definition for I2C_TXDR register *******************/
bogdanm	0:9b334a45a8ff	4988	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
bogdanm	0:9b334a45a8ff	4989
bogdanm	0:9b334a45a8ff	4990	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4991	/* */
bogdanm	0:9b334a45a8ff	4992	/* Independent WATCHDOG */
bogdanm	0:9b334a45a8ff	4993	/* */
bogdanm	0:9b334a45a8ff	4994	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4995	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	0:9b334a45a8ff	4996	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!<Key value (write only, read 0000h) /
bogdanm	0:9b334a45a8ff	4997
bogdanm	0:9b334a45a8ff	4998	/***************** Bit definition for IWDG_PR register ******************/
bogdanm	0:9b334a45a8ff	4999	#define IWDG_PR_PR ((uint32_t)0x00000007) /!<PR[2:0] (Prescaler divider) /
bogdanm	0:9b334a45a8ff	5000	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5001	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5002	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5003
bogdanm	0:9b334a45a8ff	5004	/***************** Bit definition for IWDG_RLR register *****************/
bogdanm	0:9b334a45a8ff	5005	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!<Watchdog counter reload value /
bogdanm	0:9b334a45a8ff	5006
bogdanm	0:9b334a45a8ff	5007	/***************** Bit definition for IWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	5008	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
bogdanm	0:9b334a45a8ff	5009	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
bogdanm	0:9b334a45a8ff	5010	#define IWDG_SR_WVU ((uint32_t)0x00000004) /!< Watchdog counter window value update /
bogdanm	0:9b334a45a8ff	5011
bogdanm	0:9b334a45a8ff	5012	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	0:9b334a45a8ff	5013	#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /!< Watchdog counter window value /
bogdanm	0:9b334a45a8ff	5014
bogdanm	0:9b334a45a8ff	5015	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5016	/* */
bogdanm	0:9b334a45a8ff	5017	/* Firewall */
bogdanm	0:9b334a45a8ff	5018	/* */
bogdanm	0:9b334a45a8ff	5019	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5020
bogdanm	0:9b334a45a8ff	5021	/******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register /
bogdanm	0:9b334a45a8ff	5022	#define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /!< Code Segment Start Address /
bogdanm	0:9b334a45a8ff	5023	#define FW_CSL_LENG ((uint32_t)0x003FFF00) /!< Code Segment Length /
bogdanm	0:9b334a45a8ff	5024	#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /!< Non Volatile Dat Segment Start Address /
bogdanm	0:9b334a45a8ff	5025	#define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /!< Non Volatile Data Segment Length /
bogdanm	0:9b334a45a8ff	5026	#define FW_VDSSA_ADD ((uint32_t)0x0001FFC0) /!< Volatile Data Segment Start Address /
bogdanm	0:9b334a45a8ff	5027	#define FW_VDSL_LENG ((uint32_t)0x0001FFC0) /!< Volatile Data Segment Length /
bogdanm	0:9b334a45a8ff	5028	#define FW_LSSA_ADD ((uint32_t)0x0007FF80) /!< Library Segment Start Address/
bogdanm	0:9b334a45a8ff	5029	#define FW_LSL_LENG ((uint32_t)0x0007FF80) /!< Library Segment Length/
bogdanm	0:9b334a45a8ff	5030
bogdanm	0:9b334a45a8ff	5031	/************************Bit definition for CR register *******************/
bogdanm	0:9b334a45a8ff	5032	#define FW_CR_FPA ((uint32_t)0x00000001) /!< Firewall Pre Arm/
bogdanm	0:9b334a45a8ff	5033	#define FW_CR_VDS ((uint32_t)0x00000002) /!< Volatile Data Sharing/
bogdanm	0:9b334a45a8ff	5034	#define FW_CR_VDE ((uint32_t)0x00000004) /!< Volatile Data Execution/
bogdanm	0:9b334a45a8ff	5035
bogdanm	0:9b334a45a8ff	5036	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5037	/* */
bogdanm	0:9b334a45a8ff	5038	/* Power Control */
bogdanm	0:9b334a45a8ff	5039	/* */
bogdanm	0:9b334a45a8ff	5040	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5041
bogdanm	0:9b334a45a8ff	5042	/****************** Bit definition for PWR_CR1 register ******************/
bogdanm	0:9b334a45a8ff	5043
bogdanm	0:9b334a45a8ff	5044	#define PWR_CR1_LPR ((uint32_t)0x00004000) /!< Regulator low-power mode /
bogdanm	0:9b334a45a8ff	5045	#define PWR_CR1_VOS ((uint32_t)0x00000600) /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
bogdanm	0:9b334a45a8ff	5046	#define PWR_CR1_VOS_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5047	#define PWR_CR1_VOS_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5048	#define PWR_CR1_DBP ((uint32_t)0x00000100) /!< Disable Back-up domain Protection /
bogdanm	0:9b334a45a8ff	5049	#define PWR_CR1_LPMS ((uint32_t)0x00000007) /!< Low-power mode selection field /
bogdanm	0:9b334a45a8ff	5050	#define PWR_CR1_LPMS_STOP1MR ((uint32_t)0x00000000) /!< Stop 1 mode with Main Regulator /
bogdanm	0:9b334a45a8ff	5051	#define PWR_CR1_LPMS_STOP1LPR ((uint32_t)0x00000001) /!< Stop 1 mode with Low-Power Regulator /
bogdanm	0:9b334a45a8ff	5052	#define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002) /!< Stop 2 mode /
bogdanm	0:9b334a45a8ff	5053	#define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003) /!< Stand-by mode /
bogdanm	0:9b334a45a8ff	5054	#define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004) /!< Shut-down mode /
bogdanm	0:9b334a45a8ff	5055
bogdanm	0:9b334a45a8ff	5056
bogdanm	0:9b334a45a8ff	5057	/****************** Bit definition for PWR_CR2 register ******************/
bogdanm	0:9b334a45a8ff	5058	#define PWR_CR2_USV ((uint32_t)0x00000400) /!< VDD USB Supply Valid /
bogdanm	0:9b334a45a8ff	5059	#define PWR_CR2_IOSV ((uint32_t)0x00000200) /!< VDD IO2 independent I/Os Supply Valid /
bogdanm	0:9b334a45a8ff	5060	/!< PVME Peripheral Voltage Monitor Enable /
bogdanm	0:9b334a45a8ff	5061	#define PWR_CR2_PVME ((uint32_t)0x000000F0) /!< PVM bits field /
bogdanm	0:9b334a45a8ff	5062	#define PWR_CR2_PVME4 ((uint32_t)0x00000080) /!< PVM 4 Enable /
bogdanm	0:9b334a45a8ff	5063	#define PWR_CR2_PVME3 ((uint32_t)0x00000040) /!< PVM 3 Enable /
bogdanm	0:9b334a45a8ff	5064	#define PWR_CR2_PVME2 ((uint32_t)0x00000020) /!< PVM 2 Enable /
bogdanm	0:9b334a45a8ff	5065	#define PWR_CR2_PVME1 ((uint32_t)0x00000010) /!< PVM 1 Enable /
bogdanm	0:9b334a45a8ff	5066	/!< PVD level configuration /
bogdanm	0:9b334a45a8ff	5067	#define PWR_CR2_PLS ((uint32_t)0x0000000E) /!< PVD level selection /
bogdanm	0:9b334a45a8ff	5068	#define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
bogdanm	0:9b334a45a8ff	5069	#define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002) /!< PVD level 1 /
bogdanm	0:9b334a45a8ff	5070	#define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004) /!< PVD level 2 /
bogdanm	0:9b334a45a8ff	5071	#define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006) /!< PVD level 3 /
bogdanm	0:9b334a45a8ff	5072	#define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008) /!< PVD level 4 /
bogdanm	0:9b334a45a8ff	5073	#define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000A) /!< PVD level 5 /
bogdanm	0:9b334a45a8ff	5074	#define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000C) /!< PVD level 6 /
bogdanm	0:9b334a45a8ff	5075	#define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000E) /!< PVD level 7 /
bogdanm	0:9b334a45a8ff	5076	#define PWR_CR2_PVDE ((uint32_t)0x00000001) /!< Power Voltage Detector Enable /
bogdanm	0:9b334a45a8ff	5077
bogdanm	0:9b334a45a8ff	5078	/****************** Bit definition for PWR_CR3 register ******************/
bogdanm	0:9b334a45a8ff	5079	#define PWR_CR3_EIWF ((uint32_t)0x00008000) /!< Enable Internal Wake-up line /
bogdanm	0:9b334a45a8ff	5080	#define PWR_CR3_APC ((uint32_t)0x00000400) /!< Apply pull-up and pull-down configuration /
bogdanm	0:9b334a45a8ff	5081	#define PWR_CR3_RRS ((uint32_t)0x00000100) /!< SRAM2 Retention in Stand-by mode /
bogdanm	0:9b334a45a8ff	5082	#define PWR_CR3_EWUP5 ((uint32_t)0x00000010) /!< Enable Wake-Up Pin 5 /
bogdanm	0:9b334a45a8ff	5083	#define PWR_CR3_EWUP4 ((uint32_t)0x00000008) /!< Enable Wake-Up Pin 4 /
bogdanm	0:9b334a45a8ff	5084	#define PWR_CR3_EWUP3 ((uint32_t)0x00000004) /!< Enable Wake-Up Pin 3 /
bogdanm	0:9b334a45a8ff	5085	#define PWR_CR3_EWUP2 ((uint32_t)0x00000002) /!< Enable Wake-Up Pin 2 /
bogdanm	0:9b334a45a8ff	5086	#define PWR_CR3_EWUP1 ((uint32_t)0x00000001) /!< Enable Wake-Up Pin 1 /
bogdanm	0:9b334a45a8ff	5087	#define PWR_CR3_EWUP ((uint32_t)0x0000001F) /!< Enable Wake-Up Pins /
bogdanm	0:9b334a45a8ff	5088
bogdanm	0:9b334a45a8ff	5089	/****************** Bit definition for PWR_CR4 register ******************/
bogdanm	0:9b334a45a8ff	5090	#define PWR_CR4_VBRS ((uint32_t)0x00000200) /!< VBAT Battery charging Resistor Selection /
bogdanm	0:9b334a45a8ff	5091	#define PWR_CR4_VBE ((uint32_t)0x00000100) /!< VBAT Battery charging Enable /
bogdanm	0:9b334a45a8ff	5092	#define PWR_CR4_WP5 ((uint32_t)0x00000010) /!< Wake-Up Pin 5 polarity /
bogdanm	0:9b334a45a8ff	5093	#define PWR_CR4_WP4 ((uint32_t)0x00000008) /!< Wake-Up Pin 4 polarity /
bogdanm	0:9b334a45a8ff	5094	#define PWR_CR4_WP3 ((uint32_t)0x00000004) /!< Wake-Up Pin 3 polarity /
bogdanm	0:9b334a45a8ff	5095	#define PWR_CR4_WP2 ((uint32_t)0x00000002) /!< Wake-Up Pin 2 polarity /
bogdanm	0:9b334a45a8ff	5096	#define PWR_CR4_WP1 ((uint32_t)0x00000001) /!< Wake-Up Pin 1 polarity /
bogdanm	0:9b334a45a8ff	5097
bogdanm	0:9b334a45a8ff	5098	/****************** Bit definition for PWR_SR1 register ******************/
bogdanm	0:9b334a45a8ff	5099	#define PWR_SR1_WUFI ((uint32_t)0x00008000) /!< Wake-Up Flag Internal /
bogdanm	0:9b334a45a8ff	5100	#define PWR_SR1_SBF ((uint32_t)0x00000100) /!< Stand-By Flag /
bogdanm	0:9b334a45a8ff	5101	#define PWR_SR1_WUF ((uint32_t)0x0000001F) /!< Wake-up Flags /
bogdanm	0:9b334a45a8ff	5102	#define PWR_SR1_WUF5 ((uint32_t)0x00000010) /!< Wake-up Flag 5 /
bogdanm	0:9b334a45a8ff	5103	#define PWR_SR1_WUF4 ((uint32_t)0x00000008) /!< Wake-up Flag 4 /
bogdanm	0:9b334a45a8ff	5104	#define PWR_SR1_WUF3 ((uint32_t)0x00000004) /!< Wake-up Flag 3 /
bogdanm	0:9b334a45a8ff	5105	#define PWR_SR1_WUF2 ((uint32_t)0x00000002) /!< Wake-up Flag 2 /
bogdanm	0:9b334a45a8ff	5106	#define PWR_SR1_WUF1 ((uint32_t)0x00000001) /!< Wake-up Flag 1 /
bogdanm	0:9b334a45a8ff	5107
bogdanm	0:9b334a45a8ff	5108	/****************** Bit definition for PWR_SR2 register ******************/
bogdanm	0:9b334a45a8ff	5109	#define PWR_SR2_PVMO4 ((uint32_t)0x00008000) /!< Peripheral Voltage Monitoring Output 4 /
bogdanm	0:9b334a45a8ff	5110	#define PWR_SR2_PVMO3 ((uint32_t)0x00004000) /!< Peripheral Voltage Monitoring Output 3 /
bogdanm	0:9b334a45a8ff	5111	#define PWR_SR2_PVMO2 ((uint32_t)0x00002000) /!< Peripheral Voltage Monitoring Output 2 /
bogdanm	0:9b334a45a8ff	5112	#define PWR_SR2_PVMO1 ((uint32_t)0x00001000) /!< Peripheral Voltage Monitoring Output 1 /
bogdanm	0:9b334a45a8ff	5113	#define PWR_SR2_PVDO ((uint32_t)0x00000800) /!< Power Voltage Detector Output /
bogdanm	0:9b334a45a8ff	5114	#define PWR_SR2_VOSF ((uint32_t)0x00000400) /!< Voltage Scaling Flag /
bogdanm	0:9b334a45a8ff	5115	#define PWR_SR2_REGLPF ((uint32_t)0x00000200) /!< Low-power Regulator Flag /
bogdanm	0:9b334a45a8ff	5116	#define PWR_SR2_REGLPS ((uint32_t)0x00000100) /!< Low-power Regulator Started /
bogdanm	0:9b334a45a8ff	5117
bogdanm	0:9b334a45a8ff	5118	/****************** Bit definition for PWR_SCR register ******************/
bogdanm	0:9b334a45a8ff	5119	#define PWR_SCR_CSBF ((uint32_t)0x00000100) /!< Clear Stand-By Flag /
bogdanm	0:9b334a45a8ff	5120	#define PWR_SCR_CWUF ((uint32_t)0x0000001F) /!< Clear Wake-up Flags /
bogdanm	0:9b334a45a8ff	5121	#define PWR_SCR_CWUF5 ((uint32_t)0x00000010) /!< Clear Wake-up Flag 5 /
bogdanm	0:9b334a45a8ff	5122	#define PWR_SCR_CWUF4 ((uint32_t)0x00000008) /!< Clear Wake-up Flag 4 /
bogdanm	0:9b334a45a8ff	5123	#define PWR_SCR_CWUF3 ((uint32_t)0x00000004) /!< Clear Wake-up Flag 3 /
bogdanm	0:9b334a45a8ff	5124	#define PWR_SCR_CWUF2 ((uint32_t)0x00000002) /!< Clear Wake-up Flag 2 /
bogdanm	0:9b334a45a8ff	5125	#define PWR_SCR_CWUF1 ((uint32_t)0x00000001) /!< Clear Wake-up Flag 1 /
bogdanm	0:9b334a45a8ff	5126
bogdanm	0:9b334a45a8ff	5127	/****************** Bit definition for PWR_PUCRA register ******************/
bogdanm	0:9b334a45a8ff	5128	#define PWR_PUCRA_PA15 ((uint32_t)0x00008000) /!< Port PA15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5129	#define PWR_PUCRA_PA13 ((uint32_t)0x00002000) /!< Port PA13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5130	#define PWR_PUCRA_PA12 ((uint32_t)0x00001000) /!< Port PA12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5131	#define PWR_PUCRA_PA11 ((uint32_t)0x00000800) /!< Port PA11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5132	#define PWR_PUCRA_PA10 ((uint32_t)0x00000400) /!< Port PA10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5133	#define PWR_PUCRA_PA9 ((uint32_t)0x00000200) /!< Port PA9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5134	#define PWR_PUCRA_PA8 ((uint32_t)0x00000100) /!< Port PA8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5135	#define PWR_PUCRA_PA7 ((uint32_t)0x00000080) /!< Port PA7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5136	#define PWR_PUCRA_PA6 ((uint32_t)0x00000040) /!< Port PA6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5137	#define PWR_PUCRA_PA5 ((uint32_t)0x00000020) /!< Port PA5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5138	#define PWR_PUCRA_PA4 ((uint32_t)0x00000010) /!< Port PA4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5139	#define PWR_PUCRA_PA3 ((uint32_t)0x00000008) /!< Port PA3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5140	#define PWR_PUCRA_PA2 ((uint32_t)0x00000004) /!< Port PA2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5141	#define PWR_PUCRA_PA1 ((uint32_t)0x00000002) /!< Port PA1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5142	#define PWR_PUCRA_PA0 ((uint32_t)0x00000001) /!< Port PA0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5143
bogdanm	0:9b334a45a8ff	5144	/****************** Bit definition for PWR_PDCRA register ******************/
bogdanm	0:9b334a45a8ff	5145	#define PWR_PDCRA_PA14 ((uint32_t)0x00004000) /!< Port PA14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5146	#define PWR_PDCRA_PA12 ((uint32_t)0x00001000) /!< Port PA12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5147	#define PWR_PDCRA_PA11 ((uint32_t)0x00000800) /!< Port PA11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5148	#define PWR_PDCRA_PA10 ((uint32_t)0x00000400) /!< Port PA10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5149	#define PWR_PDCRA_PA9 ((uint32_t)0x00000200) /!< Port PA9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5150	#define PWR_PDCRA_PA8 ((uint32_t)0x00000100) /!< Port PA8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5151	#define PWR_PDCRA_PA7 ((uint32_t)0x00000080) /!< Port PA7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5152	#define PWR_PDCRA_PA6 ((uint32_t)0x00000040) /!< Port PA6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5153	#define PWR_PDCRA_PA5 ((uint32_t)0x00000020) /!< Port PA5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5154	#define PWR_PDCRA_PA4 ((uint32_t)0x00000010) /!< Port PA4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5155	#define PWR_PDCRA_PA3 ((uint32_t)0x00000008) /!< Port PA3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5156	#define PWR_PDCRA_PA2 ((uint32_t)0x00000004) /!< Port PA2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5157	#define PWR_PDCRA_PA1 ((uint32_t)0x00000002) /!< Port PA1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5158	#define PWR_PDCRA_PA0 ((uint32_t)0x00000001) /!< Port PA0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5159
bogdanm	0:9b334a45a8ff	5160	/****************** Bit definition for PWR_PUCRB register ******************/
bogdanm	0:9b334a45a8ff	5161	#define PWR_PUCRB_PB15 ((uint32_t)0x00008000) /!< Port PB15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5162	#define PWR_PUCRB_PB14 ((uint32_t)0x00004000) /!< Port PB14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5163	#define PWR_PUCRB_PB13 ((uint32_t)0x00002000) /!< Port PB13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5164	#define PWR_PUCRB_PB12 ((uint32_t)0x00001000) /!< Port PB12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5165	#define PWR_PUCRB_PB11 ((uint32_t)0x00000800) /!< Port PB11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5166	#define PWR_PUCRB_PB10 ((uint32_t)0x00000400) /!< Port PB10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5167	#define PWR_PUCRB_PB9 ((uint32_t)0x00000200) /!< Port PB9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5168	#define PWR_PUCRB_PB8 ((uint32_t)0x00000100) /!< Port PB8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5169	#define PWR_PUCRB_PB7 ((uint32_t)0x00000080) /!< Port PB7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5170	#define PWR_PUCRB_PB6 ((uint32_t)0x00000040) /!< Port PB6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5171	#define PWR_PUCRB_PB5 ((uint32_t)0x00000020) /!< Port PB5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5172	#define PWR_PUCRB_PB4 ((uint32_t)0x00000010) /!< Port PB4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5173	#define PWR_PUCRB_PB3 ((uint32_t)0x00000008) /!< Port PB3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5174	#define PWR_PUCRB_PB2 ((uint32_t)0x00000004) /!< Port PB2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5175	#define PWR_PUCRB_PB1 ((uint32_t)0x00000002) /!< Port PB1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5176	#define PWR_PUCRB_PB0 ((uint32_t)0x00000001) /!< Port PB0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5177
bogdanm	0:9b334a45a8ff	5178	/****************** Bit definition for PWR_PDCRB register ******************/
bogdanm	0:9b334a45a8ff	5179	#define PWR_PDCRB_PB15 ((uint32_t)0x00008000) /!< Port PB15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5180	#define PWR_PDCRB_PB14 ((uint32_t)0x00004000) /!< Port PB14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5181	#define PWR_PDCRB_PB13 ((uint32_t)0x00002000) /!< Port PB13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5182	#define PWR_PDCRB_PB12 ((uint32_t)0x00001000) /!< Port PB12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5183	#define PWR_PDCRB_PB11 ((uint32_t)0x00000800) /!< Port PB11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5184	#define PWR_PDCRB_PB10 ((uint32_t)0x00000400) /!< Port PB10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5185	#define PWR_PDCRB_PB9 ((uint32_t)0x00000200) /!< Port PB9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5186	#define PWR_PDCRB_PB8 ((uint32_t)0x00000100) /!< Port PB8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5187	#define PWR_PDCRB_PB7 ((uint32_t)0x00000080) /!< Port PB7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5188	#define PWR_PDCRB_PB6 ((uint32_t)0x00000040) /!< Port PB6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5189	#define PWR_PDCRB_PB5 ((uint32_t)0x00000020) /!< Port PB5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5190	#define PWR_PDCRB_PB3 ((uint32_t)0x00000008) /!< Port PB3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5191	#define PWR_PDCRB_PB2 ((uint32_t)0x00000004) /!< Port PB2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5192	#define PWR_PDCRB_PB1 ((uint32_t)0x00000002) /!< Port PB1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5193	#define PWR_PDCRB_PB0 ((uint32_t)0x00000001) /!< Port PB0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5194
bogdanm	0:9b334a45a8ff	5195	/****************** Bit definition for PWR_PUCRC register ******************/
bogdanm	0:9b334a45a8ff	5196	#define PWR_PUCRC_PC15 ((uint32_t)0x00008000) /!< Port PC15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5197	#define PWR_PUCRC_PC14 ((uint32_t)0x00004000) /!< Port PC14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5198	#define PWR_PUCRC_PC13 ((uint32_t)0x00002000) /!< Port PC13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5199	#define PWR_PUCRC_PC12 ((uint32_t)0x00001000) /!< Port PC12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5200	#define PWR_PUCRC_PC11 ((uint32_t)0x00000800) /!< Port PC11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5201	#define PWR_PUCRC_PC10 ((uint32_t)0x00000400) /!< Port PC10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5202	#define PWR_PUCRC_PC9 ((uint32_t)0x00000200) /!< Port PC9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5203	#define PWR_PUCRC_PC8 ((uint32_t)0x00000100) /!< Port PC8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5204	#define PWR_PUCRC_PC7 ((uint32_t)0x00000080) /!< Port PC7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5205	#define PWR_PUCRC_PC6 ((uint32_t)0x00000040) /!< Port PC6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5206	#define PWR_PUCRC_PC5 ((uint32_t)0x00000020) /!< Port PC5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5207	#define PWR_PUCRC_PC4 ((uint32_t)0x00000010) /!< Port PC4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5208	#define PWR_PUCRC_PC3 ((uint32_t)0x00000008) /!< Port PC3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5209	#define PWR_PUCRC_PC2 ((uint32_t)0x00000004) /!< Port PC2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5210	#define PWR_PUCRC_PC1 ((uint32_t)0x00000002) /!< Port PC1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5211	#define PWR_PUCRC_PC0 ((uint32_t)0x00000001) /!< Port PC0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5212
bogdanm	0:9b334a45a8ff	5213	/****************** Bit definition for PWR_PDCRC register ******************/
bogdanm	0:9b334a45a8ff	5214	#define PWR_PDCRC_PC15 ((uint32_t)0x00008000) /!< Port PC15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5215	#define PWR_PDCRC_PC14 ((uint32_t)0x00004000) /!< Port PC14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5216	#define PWR_PDCRC_PC13 ((uint32_t)0x00002000) /!< Port PC13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5217	#define PWR_PDCRC_PC12 ((uint32_t)0x00001000) /!< Port PC12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5218	#define PWR_PDCRC_PC11 ((uint32_t)0x00000800) /!< Port PC11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5219	#define PWR_PDCRC_PC10 ((uint32_t)0x00000400) /!< Port PC10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5220	#define PWR_PDCRC_PC9 ((uint32_t)0x00000200) /!< Port PC9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5221	#define PWR_PDCRC_PC8 ((uint32_t)0x00000100) /!< Port PC8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5222	#define PWR_PDCRC_PC7 ((uint32_t)0x00000080) /!< Port PC7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5223	#define PWR_PDCRC_PC6 ((uint32_t)0x00000040) /!< Port PC6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5224	#define PWR_PDCRC_PC5 ((uint32_t)0x00000020) /!< Port PC5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5225	#define PWR_PDCRC_PC4 ((uint32_t)0x00000010) /!< Port PC4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5226	#define PWR_PDCRC_PC3 ((uint32_t)0x00000008) /!< Port PC3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5227	#define PWR_PDCRC_PC2 ((uint32_t)0x00000004) /!< Port PC2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5228	#define PWR_PDCRC_PC1 ((uint32_t)0x00000002) /!< Port PC1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5229	#define PWR_PDCRC_PC0 ((uint32_t)0x00000001) /!< Port PC0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5230
bogdanm	0:9b334a45a8ff	5231	/****************** Bit definition for PWR_PUCRD register ******************/
bogdanm	0:9b334a45a8ff	5232	#define PWR_PUCRD_PD15 ((uint32_t)0x00008000) /!< Port PD15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5233	#define PWR_PUCRD_PD14 ((uint32_t)0x00004000) /!< Port PD14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5234	#define PWR_PUCRD_PD13 ((uint32_t)0x00002000) /!< Port PD13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5235	#define PWR_PUCRD_PD12 ((uint32_t)0x00001000) /!< Port PD12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5236	#define PWR_PUCRD_PD11 ((uint32_t)0x00000800) /!< Port PD11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5237	#define PWR_PUCRD_PD10 ((uint32_t)0x00000400) /!< Port PD10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5238	#define PWR_PUCRD_PD9 ((uint32_t)0x00000200) /!< Port PD9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5239	#define PWR_PUCRD_PD8 ((uint32_t)0x00000100) /!< Port PD8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5240	#define PWR_PUCRD_PD7 ((uint32_t)0x00000080) /!< Port PD7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5241	#define PWR_PUCRD_PD6 ((uint32_t)0x00000040) /!< Port PD6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5242	#define PWR_PUCRD_PD5 ((uint32_t)0x00000020) /!< Port PD5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5243	#define PWR_PUCRD_PD4 ((uint32_t)0x00000010) /!< Port PD4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5244	#define PWR_PUCRD_PD3 ((uint32_t)0x00000008) /!< Port PD3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5245	#define PWR_PUCRD_PD2 ((uint32_t)0x00000004) /!< Port PD2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5246	#define PWR_PUCRD_PD1 ((uint32_t)0x00000002) /!< Port PD1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5247	#define PWR_PUCRD_PD0 ((uint32_t)0x00000001) /!< Port PD0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5248
bogdanm	0:9b334a45a8ff	5249	/****************** Bit definition for PWR_PDCRD register ******************/
bogdanm	0:9b334a45a8ff	5250	#define PWR_PDCRD_PD15 ((uint32_t)0x00008000) /!< Port PD15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5251	#define PWR_PDCRD_PD14 ((uint32_t)0x00004000) /!< Port PD14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5252	#define PWR_PDCRD_PD13 ((uint32_t)0x00002000) /!< Port PD13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5253	#define PWR_PDCRD_PD12 ((uint32_t)0x00001000) /!< Port PD12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5254	#define PWR_PDCRD_PD11 ((uint32_t)0x00000800) /!< Port PD11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5255	#define PWR_PDCRD_PD10 ((uint32_t)0x00000400) /!< Port PD10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5256	#define PWR_PDCRD_PD9 ((uint32_t)0x00000200) /!< Port PD9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5257	#define PWR_PDCRD_PD8 ((uint32_t)0x00000100) /!< Port PD8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5258	#define PWR_PDCRD_PD7 ((uint32_t)0x00000080) /!< Port PD7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5259	#define PWR_PDCRD_PD6 ((uint32_t)0x00000040) /!< Port PD6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5260	#define PWR_PDCRD_PD5 ((uint32_t)0x00000020) /!< Port PD5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5261	#define PWR_PDCRD_PD4 ((uint32_t)0x00000010) /!< Port PD4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5262	#define PWR_PDCRD_PD3 ((uint32_t)0x00000008) /!< Port PD3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5263	#define PWR_PDCRD_PD2 ((uint32_t)0x00000004) /!< Port PD2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5264	#define PWR_PDCRD_PD1 ((uint32_t)0x00000002) /!< Port PD1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5265	#define PWR_PDCRD_PD0 ((uint32_t)0x00000001) /!< Port PD0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5266
bogdanm	0:9b334a45a8ff	5267	/****************** Bit definition for PWR_PUCRE register ******************/
bogdanm	0:9b334a45a8ff	5268	#define PWR_PUCRE_PE15 ((uint32_t)0x00008000) /!< Port PE15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5269	#define PWR_PUCRE_PE14 ((uint32_t)0x00004000) /!< Port PE14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5270	#define PWR_PUCRE_PE13 ((uint32_t)0x00002000) /!< Port PE13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5271	#define PWR_PUCRE_PE12 ((uint32_t)0x00001000) /!< Port PE12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5272	#define PWR_PUCRE_PE11 ((uint32_t)0x00000800) /!< Port PE11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5273	#define PWR_PUCRE_PE10 ((uint32_t)0x00000400) /!< Port PE10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5274	#define PWR_PUCRE_PE9 ((uint32_t)0x00000200) /!< Port PE9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5275	#define PWR_PUCRE_PE8 ((uint32_t)0x00000100) /!< Port PE8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5276	#define PWR_PUCRE_PE7 ((uint32_t)0x00000080) /!< Port PE7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5277	#define PWR_PUCRE_PE6 ((uint32_t)0x00000040) /!< Port PE6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5278	#define PWR_PUCRE_PE5 ((uint32_t)0x00000020) /!< Port PE5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5279	#define PWR_PUCRE_PE4 ((uint32_t)0x00000010) /!< Port PE4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5280	#define PWR_PUCRE_PE3 ((uint32_t)0x00000008) /!< Port PE3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5281	#define PWR_PUCRE_PE2 ((uint32_t)0x00000004) /!< Port PE2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5282	#define PWR_PUCRE_PE1 ((uint32_t)0x00000002) /!< Port PE1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5283	#define PWR_PUCRE_PE0 ((uint32_t)0x00000001) /!< Port PE0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5284
bogdanm	0:9b334a45a8ff	5285	/****************** Bit definition for PWR_PDCRE register ******************/
bogdanm	0:9b334a45a8ff	5286	#define PWR_PDCRE_PE15 ((uint32_t)0x00008000) /!< Port PE15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5287	#define PWR_PDCRE_PE14 ((uint32_t)0x00004000) /!< Port PE14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5288	#define PWR_PDCRE_PE13 ((uint32_t)0x00002000) /!< Port PE13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5289	#define PWR_PDCRE_PE12 ((uint32_t)0x00001000) /!< Port PE12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5290	#define PWR_PDCRE_PE11 ((uint32_t)0x00000800) /!< Port PE11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5291	#define PWR_PDCRE_PE10 ((uint32_t)0x00000400) /!< Port PE10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5292	#define PWR_PDCRE_PE9 ((uint32_t)0x00000200) /!< Port PE9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5293	#define PWR_PDCRE_PE8 ((uint32_t)0x00000100) /!< Port PE8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5294	#define PWR_PDCRE_PE7 ((uint32_t)0x00000080) /!< Port PE7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5295	#define PWR_PDCRE_PE6 ((uint32_t)0x00000040) /!< Port PE6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5296	#define PWR_PDCRE_PE5 ((uint32_t)0x00000020) /!< Port PE5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5297	#define PWR_PDCRE_PE4 ((uint32_t)0x00000010) /!< Port PE4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5298	#define PWR_PDCRE_PE3 ((uint32_t)0x00000008) /!< Port PE3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5299	#define PWR_PDCRE_PE2 ((uint32_t)0x00000004) /!< Port PE2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5300	#define PWR_PDCRE_PE1 ((uint32_t)0x00000002) /!< Port PE1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5301	#define PWR_PDCRE_PE0 ((uint32_t)0x00000001) /!< Port PE0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5302
bogdanm	0:9b334a45a8ff	5303	/****************** Bit definition for PWR_PUCRF register ******************/
bogdanm	0:9b334a45a8ff	5304	#define PWR_PUCRF_PF15 ((uint32_t)0x00008000) /!< Port PF15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5305	#define PWR_PUCRF_PF14 ((uint32_t)0x00004000) /!< Port PF14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5306	#define PWR_PUCRF_PF13 ((uint32_t)0x00002000) /!< Port PF13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5307	#define PWR_PUCRF_PF12 ((uint32_t)0x00001000) /!< Port PF12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5308	#define PWR_PUCRF_PF11 ((uint32_t)0x00000800) /!< Port PF11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5309	#define PWR_PUCRF_PF10 ((uint32_t)0x00000400) /!< Port PF10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5310	#define PWR_PUCRF_PF9 ((uint32_t)0x00000200) /!< Port PF9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5311	#define PWR_PUCRF_PF8 ((uint32_t)0x00000100) /!< Port PF8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5312	#define PWR_PUCRF_PF7 ((uint32_t)0x00000080) /!< Port PF7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5313	#define PWR_PUCRF_PF6 ((uint32_t)0x00000040) /!< Port PF6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5314	#define PWR_PUCRF_PF5 ((uint32_t)0x00000020) /!< Port PF5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5315	#define PWR_PUCRF_PF4 ((uint32_t)0x00000010) /!< Port PF4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5316	#define PWR_PUCRF_PF3 ((uint32_t)0x00000008) /!< Port PF3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5317	#define PWR_PUCRF_PF2 ((uint32_t)0x00000004) /!< Port PF2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5318	#define PWR_PUCRF_PF1 ((uint32_t)0x00000002) /!< Port PF1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5319	#define PWR_PUCRF_PF0 ((uint32_t)0x00000001) /!< Port PF0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5320
bogdanm	0:9b334a45a8ff	5321	/****************** Bit definition for PWR_PDCRF register ******************/
bogdanm	0:9b334a45a8ff	5322	#define PWR_PDCRF_PF15 ((uint32_t)0x00008000) /!< Port PF15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5323	#define PWR_PDCRF_PF14 ((uint32_t)0x00004000) /!< Port PF14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5324	#define PWR_PDCRF_PF13 ((uint32_t)0x00002000) /!< Port PF13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5325	#define PWR_PDCRF_PF12 ((uint32_t)0x00001000) /!< Port PF12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5326	#define PWR_PDCRF_PF11 ((uint32_t)0x00000800) /!< Port PF11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5327	#define PWR_PDCRF_PF10 ((uint32_t)0x00000400) /!< Port PF10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5328	#define PWR_PDCRF_PF9 ((uint32_t)0x00000200) /!< Port PF9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5329	#define PWR_PDCRF_PF8 ((uint32_t)0x00000100) /!< Port PF8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5330	#define PWR_PDCRF_PF7 ((uint32_t)0x00000080) /!< Port PF7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5331	#define PWR_PDCRF_PF6 ((uint32_t)0x00000040) /!< Port PF6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5332	#define PWR_PDCRF_PF5 ((uint32_t)0x00000020) /!< Port PF5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5333	#define PWR_PDCRF_PF4 ((uint32_t)0x00000010) /!< Port PF4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5334	#define PWR_PDCRF_PF3 ((uint32_t)0x00000008) /!< Port PF3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5335	#define PWR_PDCRF_PF2 ((uint32_t)0x00000004) /!< Port PF2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5336	#define PWR_PDCRF_PF1 ((uint32_t)0x00000002) /!< Port PF1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5337	#define PWR_PDCRF_PF0 ((uint32_t)0x00000001) /!< Port PF0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5338
bogdanm	0:9b334a45a8ff	5339	/****************** Bit definition for PWR_PUCRG register ******************/
bogdanm	0:9b334a45a8ff	5340	#define PWR_PUCRG_PG15 ((uint32_t)0x00008000) /!< Port PG15 Pull-Up set /
bogdanm	0:9b334a45a8ff	5341	#define PWR_PUCRG_PG14 ((uint32_t)0x00004000) /!< Port PG14 Pull-Up set /
bogdanm	0:9b334a45a8ff	5342	#define PWR_PUCRG_PG13 ((uint32_t)0x00002000) /!< Port PG13 Pull-Up set /
bogdanm	0:9b334a45a8ff	5343	#define PWR_PUCRG_PG12 ((uint32_t)0x00001000) /!< Port PG12 Pull-Up set /
bogdanm	0:9b334a45a8ff	5344	#define PWR_PUCRG_PG11 ((uint32_t)0x00000800) /!< Port PG11 Pull-Up set /
bogdanm	0:9b334a45a8ff	5345	#define PWR_PUCRG_PG10 ((uint32_t)0x00000400) /!< Port PG10 Pull-Up set /
bogdanm	0:9b334a45a8ff	5346	#define PWR_PUCRG_PG9 ((uint32_t)0x00000200) /!< Port PG9 Pull-Up set /
bogdanm	0:9b334a45a8ff	5347	#define PWR_PUCRG_PG8 ((uint32_t)0x00000100) /!< Port PG8 Pull-Up set /
bogdanm	0:9b334a45a8ff	5348	#define PWR_PUCRG_PG7 ((uint32_t)0x00000080) /!< Port PG7 Pull-Up set /
bogdanm	0:9b334a45a8ff	5349	#define PWR_PUCRG_PG6 ((uint32_t)0x00000040) /!< Port PG6 Pull-Up set /
bogdanm	0:9b334a45a8ff	5350	#define PWR_PUCRG_PG5 ((uint32_t)0x00000020) /!< Port PG5 Pull-Up set /
bogdanm	0:9b334a45a8ff	5351	#define PWR_PUCRG_PG4 ((uint32_t)0x00000010) /!< Port PG4 Pull-Up set /
bogdanm	0:9b334a45a8ff	5352	#define PWR_PUCRG_PG3 ((uint32_t)0x00000008) /!< Port PG3 Pull-Up set /
bogdanm	0:9b334a45a8ff	5353	#define PWR_PUCRG_PG2 ((uint32_t)0x00000004) /!< Port PG2 Pull-Up set /
bogdanm	0:9b334a45a8ff	5354	#define PWR_PUCRG_PG1 ((uint32_t)0x00000002) /!< Port PG1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5355	#define PWR_PUCRG_PG0 ((uint32_t)0x00000001) /!< Port PG0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5356
bogdanm	0:9b334a45a8ff	5357	/****************** Bit definition for PWR_PDCRG register ******************/
bogdanm	0:9b334a45a8ff	5358	#define PWR_PDCRG_PG15 ((uint32_t)0x00008000) /!< Port PG15 Pull-Down set /
bogdanm	0:9b334a45a8ff	5359	#define PWR_PDCRG_PG14 ((uint32_t)0x00004000) /!< Port PG14 Pull-Down set /
bogdanm	0:9b334a45a8ff	5360	#define PWR_PDCRG_PG13 ((uint32_t)0x00002000) /!< Port PG13 Pull-Down set /
bogdanm	0:9b334a45a8ff	5361	#define PWR_PDCRG_PG12 ((uint32_t)0x00001000) /!< Port PG12 Pull-Down set /
bogdanm	0:9b334a45a8ff	5362	#define PWR_PDCRG_PG11 ((uint32_t)0x00000800) /!< Port PG11 Pull-Down set /
bogdanm	0:9b334a45a8ff	5363	#define PWR_PDCRG_PG10 ((uint32_t)0x00000400) /!< Port PG10 Pull-Down set /
bogdanm	0:9b334a45a8ff	5364	#define PWR_PDCRG_PG9 ((uint32_t)0x00000200) /!< Port PG9 Pull-Down set /
bogdanm	0:9b334a45a8ff	5365	#define PWR_PDCRG_PG8 ((uint32_t)0x00000100) /!< Port PG8 Pull-Down set /
bogdanm	0:9b334a45a8ff	5366	#define PWR_PDCRG_PG7 ((uint32_t)0x00000080) /!< Port PG7 Pull-Down set /
bogdanm	0:9b334a45a8ff	5367	#define PWR_PDCRG_PG6 ((uint32_t)0x00000040) /!< Port PG6 Pull-Down set /
bogdanm	0:9b334a45a8ff	5368	#define PWR_PDCRG_PG5 ((uint32_t)0x00000020) /!< Port PG5 Pull-Down set /
bogdanm	0:9b334a45a8ff	5369	#define PWR_PDCRG_PG4 ((uint32_t)0x00000010) /!< Port PG4 Pull-Down set /
bogdanm	0:9b334a45a8ff	5370	#define PWR_PDCRG_PG3 ((uint32_t)0x00000008) /!< Port PG3 Pull-Down set /
bogdanm	0:9b334a45a8ff	5371	#define PWR_PDCRG_PG2 ((uint32_t)0x00000004) /!< Port PG2 Pull-Down set /
bogdanm	0:9b334a45a8ff	5372	#define PWR_PDCRG_PG1 ((uint32_t)0x00000002) /!< Port PG1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5373	#define PWR_PDCRG_PG0 ((uint32_t)0x00000001) /!< Port PG0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5374
bogdanm	0:9b334a45a8ff	5375	/****************** Bit definition for PWR_PUCRH register ******************/
bogdanm	0:9b334a45a8ff	5376	#define PWR_PUCRH_PH1 ((uint32_t)0x00000002) /!< Port PH1 Pull-Up set /
bogdanm	0:9b334a45a8ff	5377	#define PWR_PUCRH_PH0 ((uint32_t)0x00000001) /!< Port PH0 Pull-Up set /
bogdanm	0:9b334a45a8ff	5378
bogdanm	0:9b334a45a8ff	5379	/****************** Bit definition for PWR_PDCRH register ******************/
bogdanm	0:9b334a45a8ff	5380	#define PWR_PDCRH_PH1 ((uint32_t)0x00000002) /!< Port PH1 Pull-Down set /
bogdanm	0:9b334a45a8ff	5381	#define PWR_PDCRH_PH0 ((uint32_t)0x00000001) /!< Port PH0 Pull-Down set /
bogdanm	0:9b334a45a8ff	5382
bogdanm	0:9b334a45a8ff	5383
bogdanm	0:9b334a45a8ff	5384	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5385	/* */
bogdanm	0:9b334a45a8ff	5386	/* Reset and Clock Control */
bogdanm	0:9b334a45a8ff	5387	/* */
bogdanm	0:9b334a45a8ff	5388	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5389	/****************** Bit definition for RCC_CR register ******************/
bogdanm	0:9b334a45a8ff	5390	#define RCC_CR_MSION ((uint32_t)0x00000001) /!< Internal Multi Speed clock enable /
bogdanm	0:9b334a45a8ff	5391	#define RCC_CR_MSIRDY ((uint32_t)0x00000002) /!< Internal Multi Speed clock ready flag /
bogdanm	0:9b334a45a8ff	5392	#define RCC_CR_MSIPLLEN ((uint32_t)0x00000004) /!< Internal Multi Speed PLL enable /
bogdanm	0:9b334a45a8ff	5393	#define RCC_CR_MSIRGSEL ((uint32_t)0x00000008) /!< Internal Multi Speed range selection /
bogdanm	0:9b334a45a8ff	5394
bogdanm	0:9b334a45a8ff	5395	/!< MSIRANGE configuration : 12 frequency ranges available /
bogdanm	0:9b334a45a8ff	5396	#define RCC_CR_MSIRANGE ((uint32_t)0x000000F0) /!< Internal Multi Speed clock Range /
bogdanm	0:9b334a45a8ff	5397	#define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000) /!< Internal Multi Speed clock Range 100 KHz /
bogdanm	0:9b334a45a8ff	5398	#define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010) /!< Internal Multi Speed clock Range 200 KHz /
bogdanm	0:9b334a45a8ff	5399	#define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020) /!< Internal Multi Speed clock Range 400 KHz /
bogdanm	0:9b334a45a8ff	5400	#define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030) /!< Internal Multi Speed clock Range 800 KHz /
bogdanm	0:9b334a45a8ff	5401	#define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040) /!< Internal Multi Speed clock Range 1 MHz /
bogdanm	0:9b334a45a8ff	5402	#define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050) /!< Internal Multi Speed clock Range 2 MHz /
bogdanm	0:9b334a45a8ff	5403	#define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060) /!< Internal Multi Speed clock Range 4 MHz /
bogdanm	0:9b334a45a8ff	5404	#define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070) /!< Internal Multi Speed clock Range 8 KHz /
bogdanm	0:9b334a45a8ff	5405	#define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080) /!< Internal Multi Speed clock Range 16 MHz /
bogdanm	0:9b334a45a8ff	5406	#define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090) /!< Internal Multi Speed clock Range 24 MHz /
bogdanm	0:9b334a45a8ff	5407	#define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0) /!< Internal Multi Speed clock Range 32 MHz /
bogdanm	0:9b334a45a8ff	5408	#define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0) /!< Internal Multi Speed clock Range 48 MHz /
bogdanm	0:9b334a45a8ff	5409
bogdanm	0:9b334a45a8ff	5410	#define RCC_CR_HSION ((uint32_t)0x00000100) /!< Internal High Speed clock enable /
bogdanm	0:9b334a45a8ff	5411	#define RCC_CR_HSIKERON ((uint32_t)0x00000200) /!< Internal High Speed clock enable for some IPs Kernel /
bogdanm	0:9b334a45a8ff	5412	#define RCC_CR_HSIRDY ((uint32_t)0x00000400) /!< Internal High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	5413	#define RCC_CR_HSIASFS ((uint32_t)0x00000800) /!< HSI Automatic Start from Stop /
bogdanm	0:9b334a45a8ff	5414
bogdanm	0:9b334a45a8ff	5415	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
bogdanm	0:9b334a45a8ff	5416	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready /
bogdanm	0:9b334a45a8ff	5417	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
bogdanm	0:9b334a45a8ff	5418	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< HSE Clock Security System enable /
bogdanm	0:9b334a45a8ff	5419
bogdanm	0:9b334a45a8ff	5420	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< System PLL clock enable /
bogdanm	0:9b334a45a8ff	5421	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< System PLL clock ready /
bogdanm	0:9b334a45a8ff	5422	#define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000) /!< SAI1 PLL enable /
bogdanm	0:9b334a45a8ff	5423	#define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000) /!< SAI1 PLL ready /
bogdanm	0:9b334a45a8ff	5424	#define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000) /!< SAI2 PLL enable /
bogdanm	0:9b334a45a8ff	5425	#define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000) /!< SAI2 PLL ready /
bogdanm	0:9b334a45a8ff	5426
bogdanm	0:9b334a45a8ff	5427	/****************** Bit definition for RCC_ICSCR register *************/
bogdanm	0:9b334a45a8ff	5428	/!< MSICAL configuration /
bogdanm	0:9b334a45a8ff	5429	#define RCC_ICSCR_MSICAL ((uint32_t)0x000000FF) /!< MSICAL[7:0] bits /
bogdanm	0:9b334a45a8ff	5430	#define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5431	#define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5432	#define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5433	#define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	5434	#define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	5435	#define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	5436	#define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	5437	#define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	5438
bogdanm	0:9b334a45a8ff	5439	/!< MSITRIM configuration /
bogdanm	0:9b334a45a8ff	5440	#define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00) /!< MSITRIM[7:0] bits /
bogdanm	0:9b334a45a8ff	5441	#define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5442	#define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5443	#define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5444	#define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	5445	#define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	5446	#define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	5447	#define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	5448	#define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	5449
bogdanm	0:9b334a45a8ff	5450	/!< HSICAL configuration /
bogdanm	0:9b334a45a8ff	5451	#define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000) /!< HSICAL[7:0] bits /
bogdanm	0:9b334a45a8ff	5452	#define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5453	#define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5454	#define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5455	#define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	5456	#define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	5457	#define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	5458	#define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	5459	#define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	5460
bogdanm	0:9b334a45a8ff	5461	/!< HSITRIM configuration /
bogdanm	0:9b334a45a8ff	5462	#define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000) /!< HSITRIM[7:0] bits /
bogdanm	0:9b334a45a8ff	5463	#define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5464	#define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5465	#define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5466	#define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	5467	#define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	5468
bogdanm	0:9b334a45a8ff	5469	/****************** Bit definition for RCC_PLLCFGR register *************/
bogdanm	0:9b334a45a8ff	5470	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	5471
bogdanm	0:9b334a45a8ff	5472	#define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001) /!< MSI source clock selected /
bogdanm	0:9b334a45a8ff	5473	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002) /!< HSI source clock selected /
bogdanm	0:9b334a45a8ff	5474	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003) /!< HSE source clock selected /
bogdanm	0:9b334a45a8ff	5475
bogdanm	0:9b334a45a8ff	5476	#define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	5477	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5478	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5479	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5480
bogdanm	0:9b334a45a8ff	5481	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00)
bogdanm	0:9b334a45a8ff	5482	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5483	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5484	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5485	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5486	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5487	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5488	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5489
bogdanm	0:9b334a45a8ff	5490	#define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5491	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5492	#define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5493
bogdanm	0:9b334a45a8ff	5494	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000)
bogdanm	0:9b334a45a8ff	5495	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5496	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5497
bogdanm	0:9b334a45a8ff	5498	#define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5499	#define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000)
bogdanm	0:9b334a45a8ff	5500	#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5501	#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5502
bogdanm	0:9b334a45a8ff	5503	/****************** Bit definition for RCC_CFGR register ****************/
bogdanm	0:9b334a45a8ff	5504	/!< SW configuration /
bogdanm	0:9b334a45a8ff	5505	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	0:9b334a45a8ff	5506	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5507	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5508
bogdanm	0:9b334a45a8ff	5509	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /!< MSI selection as system clock /
bogdanm	0:9b334a45a8ff	5510	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /!< HSI selection as system clock /
bogdanm	0:9b334a45a8ff	5511	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /!< HSE selection as system clock /
bogdanm	0:9b334a45a8ff	5512	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /!< PLL selection as system clock /
bogdanm	0:9b334a45a8ff	5513
bogdanm	0:9b334a45a8ff	5514	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /!< MSI used as system clock /
bogdanm	0:9b334a45a8ff	5515	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /!< HSI used as system clock /
bogdanm	0:9b334a45a8ff	5516	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /!< HSE used as system clock /
bogdanm	0:9b334a45a8ff	5517	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	5518
bogdanm	0:9b334a45a8ff	5519	/!< SWS configuration /
bogdanm	0:9b334a45a8ff	5520	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	0:9b334a45a8ff	5521	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5522	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5523
bogdanm	0:9b334a45a8ff	5524	/!< HPRE configuration /
bogdanm	0:9b334a45a8ff	5525	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	0:9b334a45a8ff	5526	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5527	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5528	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5529	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	5530
bogdanm	0:9b334a45a8ff	5531	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	5532	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	5533	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	5534	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	5535	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	5536	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	5537	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	5538	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	5539	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	5540
bogdanm	0:9b334a45a8ff	5541	/!< PPRE1 configuration /
bogdanm	0:9b334a45a8ff	5542	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB2 prescaler) /
bogdanm	0:9b334a45a8ff	5543	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5544	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5545	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5546
bogdanm	0:9b334a45a8ff	5547	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	5548	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	5549	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	5550	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	5551	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	5552
bogdanm	0:9b334a45a8ff	5553	/!< PPRE2 configuration /
bogdanm	0:9b334a45a8ff	5554	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
bogdanm	0:9b334a45a8ff	5555	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5556	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5557	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5558
bogdanm	0:9b334a45a8ff	5559	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	5560	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	5561	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	5562	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	5563	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	5564
bogdanm	0:9b334a45a8ff	5565	#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /!< Wake Up from stop and CSS backup clock selection /
bogdanm	0:9b334a45a8ff	5566
bogdanm	0:9b334a45a8ff	5567	/!< MCOSEL configuration /
bogdanm	0:9b334a45a8ff	5568	#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /!< MCOSEL [2:0] bits (Clock output selection) /
bogdanm	0:9b334a45a8ff	5569	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	5570	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	5571	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	5572
bogdanm	0:9b334a45a8ff	5573	#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /!< MCO prescaler /
bogdanm	0:9b334a45a8ff	5574	#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
bogdanm	0:9b334a45a8ff	5575	#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
bogdanm	0:9b334a45a8ff	5576	#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
bogdanm	0:9b334a45a8ff	5577	#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
bogdanm	0:9b334a45a8ff	5578	#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
bogdanm	0:9b334a45a8ff	5579
bogdanm	0:9b334a45a8ff	5580	/****************** Bit definition for RCC_CIER register ****************/
bogdanm	0:9b334a45a8ff	5581	#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5582	#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5583	#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5584	#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5585	#define RCC_CIER_HSERDYIE ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5586	#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5587	#define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5588	#define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5589	#define RCC_CIER_LSECSSIE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5590
bogdanm	0:9b334a45a8ff	5591	/****************** Bit definition for RCC_CIFR register ****************/
bogdanm	0:9b334a45a8ff	5592	#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5593	#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5594	#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5595	#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5596	#define RCC_CIFR_HSERDYF ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5597	#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5598	#define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5599	#define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5600	#define RCC_CIFR_CSSF ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5601	#define RCC_CIFR_LSECSSF ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5602
bogdanm	0:9b334a45a8ff	5603	/****************** Bit definition for RCC_CICR register ****************/
bogdanm	0:9b334a45a8ff	5604	#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5605	#define RCC_CICR_LSERDYC ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5606	#define RCC_CICR_MSIRDYC ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5607	#define RCC_CICR_HSIRDYC ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5608	#define RCC_CICR_HSERDYC ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5609	#define RCC_CICR_PLLRDYC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5610	#define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5611	#define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5612	#define RCC_CICR_CSSC ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5613	#define RCC_CICR_LSECSSC ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5614
bogdanm	0:9b334a45a8ff	5615	/****************** Bit definition for RCC_AHB1RSTR register ************/
bogdanm	0:9b334a45a8ff	5616	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5617	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5618	#define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5619	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5620	#define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5621
bogdanm	0:9b334a45a8ff	5622	/****************** Bit definition for RCC_AHB2RSTR register ************/
bogdanm	0:9b334a45a8ff	5623	#define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5624	#define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5625	#define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5626	#define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5627	#define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5628	#define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5629	#define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5630	#define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5631	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5632	#define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5633	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5634
bogdanm	0:9b334a45a8ff	5635	/****************** Bit definition for RCC_AHB3RSTR register ************/
bogdanm	0:9b334a45a8ff	5636	#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5637	#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5638
bogdanm	0:9b334a45a8ff	5639	/****************** Bit definition for RCC_APB1RSTR1 register ************/
bogdanm	0:9b334a45a8ff	5640	#define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5641	#define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5642	#define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5643	#define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5644	#define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5645	#define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5646	#define RCC_APB1RSTR1_LCDRST ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5647	#define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5648	#define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5649	#define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5650	#define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5651	#define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5652	#define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5653	#define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5654	#define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5655	#define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5656	#define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5657	#define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5658	#define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5659	#define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5660	#define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5661
bogdanm	0:9b334a45a8ff	5662	/****************** Bit definition for RCC_APB1RSTR2 register ************/
bogdanm	0:9b334a45a8ff	5663	#define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5664	#define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5665	#define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5666
bogdanm	0:9b334a45a8ff	5667	/****************** Bit definition for RCC_APB2RSTR register ************/
bogdanm	0:9b334a45a8ff	5668	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5669	#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5670	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5671	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5672	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5673	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5674	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5675	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5676	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5677	#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5678	#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5679	#define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5680
bogdanm	0:9b334a45a8ff	5681	/****************** Bit definition for RCC_AHB1ENR register *************/
bogdanm	0:9b334a45a8ff	5682	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5683	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5684	#define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5685	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5686	#define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5687
bogdanm	0:9b334a45a8ff	5688	/****************** Bit definition for RCC_AHB2ENR register *************/
bogdanm	0:9b334a45a8ff	5689	#define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5690	#define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5691	#define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5692	#define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5693	#define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5694	#define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5695	#define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5696	#define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5697	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5698	#define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5699	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5700
bogdanm	0:9b334a45a8ff	5701	/****************** Bit definition for RCC_AHB3ENR register *************/
bogdanm	0:9b334a45a8ff	5702	#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5703	#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5704
bogdanm	0:9b334a45a8ff	5705	/****************** Bit definition for RCC_APB1ENR1 register *************/
bogdanm	0:9b334a45a8ff	5706	#define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5707	#define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5708	#define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5709	#define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5710	#define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5711	#define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5712	#define RCC_APB1ENR1_LCDEN ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5713	#define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5714	#define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5715	#define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5716	#define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5717	#define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5718	#define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5719	#define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5720	#define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5721	#define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5722	#define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5723	#define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5724	#define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5725	#define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5726	#define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5727	#define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5728
bogdanm	0:9b334a45a8ff	5729	/****************** Bit definition for RCC_APB1RSTR2 register ************/
bogdanm	0:9b334a45a8ff	5730	#define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5731	#define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5732	#define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5733
bogdanm	0:9b334a45a8ff	5734	/****************** Bit definition for RCC_APB2ENR register *************/
bogdanm	0:9b334a45a8ff	5735	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5736	#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5737	#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5738	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5739	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5740	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5741	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5742	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5743	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5744	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5745	#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5746	#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5747	#define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5748
bogdanm	0:9b334a45a8ff	5749	/****************** Bit definition for RCC_AHB1SMENR register *************/
bogdanm	0:9b334a45a8ff	5750	#define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5751	#define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5752	#define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5753	#define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5754	#define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5755	#define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5756
bogdanm	0:9b334a45a8ff	5757	/****************** Bit definition for RCC_AHB2SMENR register ***********/
bogdanm	0:9b334a45a8ff	5758	#define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5759	#define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5760	#define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5761	#define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5762	#define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5763	#define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5764	#define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5765	#define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5766	#define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5767	#define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5768	#define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5769	#define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5770
bogdanm	0:9b334a45a8ff	5771	/****************** Bit definition for RCC_AHB3SMENR register ***********/
bogdanm	0:9b334a45a8ff	5772	#define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5773	#define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5774
bogdanm	0:9b334a45a8ff	5775	/****************** Bit definition for RCC_APB1SMENR1 register ***********/
bogdanm	0:9b334a45a8ff	5776	#define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5777	#define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5778	#define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5779	#define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5780	#define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5781	#define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5782	#define RCC_APB1SMENR1_LCDSMEN ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5783	#define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5784	#define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5785	#define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5786	#define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5787	#define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5788	#define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5789	#define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5790	#define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5791	#define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5792	#define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5793	#define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5794	#define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5795	#define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5796	#define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5797	#define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5798
bogdanm	0:9b334a45a8ff	5799	/****************** Bit definition for RCC_APB1SMENR2 register ***********/
bogdanm	0:9b334a45a8ff	5800	#define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5801	#define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5802	#define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5803
bogdanm	0:9b334a45a8ff	5804	/****************** Bit definition for RCC_APB2SMENR register ***********/
bogdanm	0:9b334a45a8ff	5805	#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5806	#define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5807	#define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5808	#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5809	#define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5810	#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5811	#define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5812	#define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5813	#define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5814	#define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5815	#define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5816	#define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5817
bogdanm	0:9b334a45a8ff	5818	/****************** Bit definition for RCC_CCIPR register ****************/
bogdanm	0:9b334a45a8ff	5819	#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	5820	#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5821	#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5822
bogdanm	0:9b334a45a8ff	5823	#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	5824	#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5825	#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5826
bogdanm	0:9b334a45a8ff	5827	#define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	5828	#define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5829	#define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5830
bogdanm	0:9b334a45a8ff	5831	#define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	5832	#define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5833	#define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5834
bogdanm	0:9b334a45a8ff	5835	#define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	5836	#define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5837	#define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5838
bogdanm	0:9b334a45a8ff	5839	#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	5840	#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5841	#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5842
bogdanm	0:9b334a45a8ff	5843	#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	5844	#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5845	#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5846
bogdanm	0:9b334a45a8ff	5847	#define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	5848	#define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5849	#define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5850
bogdanm	0:9b334a45a8ff	5851	#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	5852	#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5853	#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5854
bogdanm	0:9b334a45a8ff	5855	#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	5856	#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5857	#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5858
bogdanm	0:9b334a45a8ff	5859	#define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	5860	#define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5861	#define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5862
bogdanm	0:9b334a45a8ff	5863	#define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	5864	#define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5865	#define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5866
bogdanm	0:9b334a45a8ff	5867	#define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	5868	#define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5869	#define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5870
bogdanm	0:9b334a45a8ff	5871	#define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	5872	#define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5873	#define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5874
bogdanm	0:9b334a45a8ff	5875	#define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	5876	#define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5877	#define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5878
bogdanm	0:9b334a45a8ff	5879	#define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5880	#define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5881
bogdanm	0:9b334a45a8ff	5882	/****************** Bit definition for RCC_BDCR register ****************/
bogdanm	0:9b334a45a8ff	5883	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5884	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5885	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5886
bogdanm	0:9b334a45a8ff	5887	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
bogdanm	0:9b334a45a8ff	5888	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5889	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5890
bogdanm	0:9b334a45a8ff	5891	#define RCC_BDCR_LSECSSON ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5892	#define RCC_BDCR_LSECSSD ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5893
bogdanm	0:9b334a45a8ff	5894	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	5895	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5896	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5897
bogdanm	0:9b334a45a8ff	5898	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5899	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5900	#define RCC_BDCR_LSCOEN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5901	#define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5902
bogdanm	0:9b334a45a8ff	5903	/****************** Bit definition for RCC_CSR register *****************/
bogdanm	0:9b334a45a8ff	5904	#define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5905	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5906
bogdanm	0:9b334a45a8ff	5907	#define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	5908	#define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400) /!< MSI frequency 1MHZ /
bogdanm	0:9b334a45a8ff	5909	#define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500) /!< MSI frequency 2MHZ /
bogdanm	0:9b334a45a8ff	5910	#define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600) /!< The default frequency 4MHZ /
bogdanm	0:9b334a45a8ff	5911	#define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700) /!< MSI frequency 8MHZ /
bogdanm	0:9b334a45a8ff	5912
bogdanm	0:9b334a45a8ff	5913	#define RCC_CSR_RMVF ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5914	#define RCC_CSR_FWRSTF ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5915	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5916	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5917	#define RCC_CSR_BORRSTF ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5918	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5919	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5920	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5921	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5922
bogdanm	0:9b334a45a8ff	5923	/****************** Bit definition for RCC_PLLSAI1CFGR register **********/
bogdanm	0:9b334a45a8ff	5924	#define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00)
bogdanm	0:9b334a45a8ff	5925	#define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5926	#define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5927	#define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5928	#define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5929	#define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5930	#define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5931	#define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5932
bogdanm	0:9b334a45a8ff	5933	#define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5934	#define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5935	#define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5936	#define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000)
bogdanm	0:9b334a45a8ff	5937	#define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5938	#define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000)
bogdanm	0:9b334a45a8ff	5939
bogdanm	0:9b334a45a8ff	5940	/****************** Bit definition for RCC_PLLSAI2CFGR register **********/
bogdanm	0:9b334a45a8ff	5941	#define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00)
bogdanm	0:9b334a45a8ff	5942	#define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5943	#define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5944	#define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5945	#define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5946	#define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5947	#define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5948	#define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5949
bogdanm	0:9b334a45a8ff	5950	#define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5951	#define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5952	#define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5953	#define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000)
bogdanm	0:9b334a45a8ff	5954
bogdanm	0:9b334a45a8ff	5955
bogdanm	0:9b334a45a8ff	5956
bogdanm	0:9b334a45a8ff	5957	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5958	/* */
bogdanm	0:9b334a45a8ff	5959	/* RNG */
bogdanm	0:9b334a45a8ff	5960	/* */
bogdanm	0:9b334a45a8ff	5961	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5962	/****************** Bits definition for RNG_CR register *****************/
bogdanm	0:9b334a45a8ff	5963	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5964	#define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5965
bogdanm	0:9b334a45a8ff	5966	/****************** Bits definition for RNG_SR register *****************/
bogdanm	0:9b334a45a8ff	5967	#define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5968	#define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5969	#define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5970	#define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5971	#define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5972
bogdanm	0:9b334a45a8ff	5973	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5974	/* */
bogdanm	0:9b334a45a8ff	5975	/* Real-Time Clock (RTC) */
bogdanm	0:9b334a45a8ff	5976	/* */
bogdanm	0:9b334a45a8ff	5977	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5978	/****************** Bits definition for RTC_TR register *****************/
bogdanm	0:9b334a45a8ff	5979	#define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5980	#define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	5981	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5982	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5983	#define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	5984	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5985	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5986	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5987	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5988	#define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	5989	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5990	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5991	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5992	#define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	5993	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5994	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5995	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5996	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5997	#define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	5998	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5999	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6000	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6001	#define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6002	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6003	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6004	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6005	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6006
bogdanm	0:9b334a45a8ff	6007	/****************** Bits definition for RTC_DR register *****************/
bogdanm	0:9b334a45a8ff	6008	#define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	6009	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6010	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6011	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6012	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6013	#define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6014	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6015	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6016	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6017	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6018	#define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	6019	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6020	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6021	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6022	#define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6023	#define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6024	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6025	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6026	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6027	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6028	#define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	6029	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6030	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6031	#define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6032	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6033	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6034	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6035	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6036
bogdanm	0:9b334a45a8ff	6037	/****************** Bits definition for RTC_CR register *****************/
bogdanm	0:9b334a45a8ff	6038	#define RTC_CR_ITSE ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6039	#define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6040	#define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm	0:9b334a45a8ff	6041	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6042	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6043	#define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6044	#define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6045	#define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6046	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6047	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6048	#define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6049	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6050	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6051	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6052	#define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6053	#define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6054	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6055	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6056	#define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6057	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6058	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6059	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6060	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm	0:9b334a45a8ff	6061	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6062	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6063	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6064
bogdanm	0:9b334a45a8ff	6065	/****************** Bits definition for RTC_ISR register ****************/
bogdanm	0:9b334a45a8ff	6066	#define RTC_ISR_ITSF ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6067	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6068	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6069	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6070	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6071	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6072	#define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6073	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6074	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6075	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6076	#define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6077	#define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6078	#define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6079	#define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6080	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6081	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6082	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6083	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6084
bogdanm	0:9b334a45a8ff	6085	/****************** Bits definition for RTC_PRER register ***************/
bogdanm	0:9b334a45a8ff	6086	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm	0:9b334a45a8ff	6087	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6088
bogdanm	0:9b334a45a8ff	6089	/****************** Bits definition for RTC_WUTR register ***************/
bogdanm	0:9b334a45a8ff	6090	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6091
bogdanm	0:9b334a45a8ff	6092	/****************** Bits definition for RTC_ALRMAR register *************/
bogdanm	0:9b334a45a8ff	6093	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6094	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	6095	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	6096	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	6097	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	6098	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6099	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6100	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6101	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6102	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6103	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6104	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6105	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6106	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6107	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6108	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6109	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6110	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6111	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6112	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6113	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6114	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6115	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6116	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6117	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6118	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6119	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6120	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6121	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6122	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6123	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6124	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6125	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6126	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6127	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6128	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6129	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6130	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6131	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6132	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6133
bogdanm	0:9b334a45a8ff	6134	/****************** Bits definition for RTC_ALRMBR register *************/
bogdanm	0:9b334a45a8ff	6135	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6136	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	6137	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	6138	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	6139	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	6140	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6141	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6142	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6143	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6144	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6145	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6146	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6147	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6148	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6149	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6150	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6151	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6152	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6153	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6154	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6155	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6156	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6157	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6158	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6159	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6160	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6161	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6162	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6163	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6164	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6165	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6166	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6167	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6168	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6169	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6170	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6171	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6172	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6173	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6174	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6175
bogdanm	0:9b334a45a8ff	6176	/****************** Bits definition for RTC_WPR register ****************/
bogdanm	0:9b334a45a8ff	6177	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	6178
bogdanm	0:9b334a45a8ff	6179	/****************** Bits definition for RTC_SSR register ****************/
bogdanm	0:9b334a45a8ff	6180	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6181
bogdanm	0:9b334a45a8ff	6182	/****************** Bits definition for RTC_SHIFTR register *************/
bogdanm	0:9b334a45a8ff	6183	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6184	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6185
bogdanm	0:9b334a45a8ff	6186	/****************** Bits definition for RTC_TSTR register ***************/
bogdanm	0:9b334a45a8ff	6187	#define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6188	#define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6189	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6190	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6191	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6192	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6193	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6194	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6195	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6196	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6197	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6198	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6199	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6200	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6201	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6202	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6203	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6204	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6205	#define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6206	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6207	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6208	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6209	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6210	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6211	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6212	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6213	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6214
bogdanm	0:9b334a45a8ff	6215	/****************** Bits definition for RTC_TSDR register ***************/
bogdanm	0:9b334a45a8ff	6216	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	6217	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6218	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6219	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6220	#define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6221	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6222	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6223	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6224	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6225	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6226	#define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	6227	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6228	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6229	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6230	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6231	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6232	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6233	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6234
bogdanm	0:9b334a45a8ff	6235	/****************** Bits definition for RTC_TSSSR register **************/
bogdanm	0:9b334a45a8ff	6236	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6237
bogdanm	0:9b334a45a8ff	6238	/****************** Bits definition for RTC_CAL register ***************/
bogdanm	0:9b334a45a8ff	6239	#define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6240	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6241	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6242	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm	0:9b334a45a8ff	6243	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6244	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6245	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6246	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6247	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6248	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6249	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6250	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6251	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6252
bogdanm	0:9b334a45a8ff	6253	/****************** Bits definition for RTC_TAMPCR register *************/
bogdanm	0:9b334a45a8ff	6254	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6255	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6256	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6257	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6258	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6259	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6260	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6261	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6262	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6263	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6264	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm	0:9b334a45a8ff	6265	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6266	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6267	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm	0:9b334a45a8ff	6268	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6269	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6270	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm	0:9b334a45a8ff	6271	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6272	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6273	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6274	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6275	#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6276	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6277	#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6278	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6279	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6280	#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6281	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6282
bogdanm	0:9b334a45a8ff	6283	/****************** Bits definition for RTC_ALRMASSR register ***********/
bogdanm	0:9b334a45a8ff	6284	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6285	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6286	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6287	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6288	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6289	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6290
bogdanm	0:9b334a45a8ff	6291	/****************** Bits definition for RTC_ALRMBSSR register ***********/
bogdanm	0:9b334a45a8ff	6292	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6293	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6294	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6295	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6296	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6297	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6298
bogdanm	0:9b334a45a8ff	6299	/****************** Bits definition for RTC_0R register *****************/
bogdanm	0:9b334a45a8ff	6300	#define RTC_OR_OUT_RMP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6301	#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6302
bogdanm	0:9b334a45a8ff	6303
bogdanm	0:9b334a45a8ff	6304	/****************** Bits definition for RTC_BKP0R register **************/
bogdanm	0:9b334a45a8ff	6305	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6306
bogdanm	0:9b334a45a8ff	6307	/****************** Bits definition for RTC_BKP1R register **************/
bogdanm	0:9b334a45a8ff	6308	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6309
bogdanm	0:9b334a45a8ff	6310	/****************** Bits definition for RTC_BKP2R register **************/
bogdanm	0:9b334a45a8ff	6311	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6312
bogdanm	0:9b334a45a8ff	6313	/****************** Bits definition for RTC_BKP3R register **************/
bogdanm	0:9b334a45a8ff	6314	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6315
bogdanm	0:9b334a45a8ff	6316	/****************** Bits definition for RTC_BKP4R register **************/
bogdanm	0:9b334a45a8ff	6317	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6318
bogdanm	0:9b334a45a8ff	6319	/****************** Bits definition for RTC_BKP5R register **************/
bogdanm	0:9b334a45a8ff	6320	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6321
bogdanm	0:9b334a45a8ff	6322	/****************** Bits definition for RTC_BKP6R register **************/
bogdanm	0:9b334a45a8ff	6323	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6324
bogdanm	0:9b334a45a8ff	6325	/****************** Bits definition for RTC_BKP7R register **************/
bogdanm	0:9b334a45a8ff	6326	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6327
bogdanm	0:9b334a45a8ff	6328	/****************** Bits definition for RTC_BKP8R register **************/
bogdanm	0:9b334a45a8ff	6329	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6330
bogdanm	0:9b334a45a8ff	6331	/****************** Bits definition for RTC_BKP9R register **************/
bogdanm	0:9b334a45a8ff	6332	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6333
bogdanm	0:9b334a45a8ff	6334	/****************** Bits definition for RTC_BKP10R register *************/
bogdanm	0:9b334a45a8ff	6335	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6336
bogdanm	0:9b334a45a8ff	6337	/****************** Bits definition for RTC_BKP11R register *************/
bogdanm	0:9b334a45a8ff	6338	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6339
bogdanm	0:9b334a45a8ff	6340	/****************** Bits definition for RTC_BKP12R register *************/
bogdanm	0:9b334a45a8ff	6341	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6342
bogdanm	0:9b334a45a8ff	6343	/****************** Bits definition for RTC_BKP13R register *************/
bogdanm	0:9b334a45a8ff	6344	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6345
bogdanm	0:9b334a45a8ff	6346	/****************** Bits definition for RTC_BKP14R register *************/
bogdanm	0:9b334a45a8ff	6347	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6348
bogdanm	0:9b334a45a8ff	6349	/****************** Bits definition for RTC_BKP15R register *************/
bogdanm	0:9b334a45a8ff	6350	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6351
bogdanm	0:9b334a45a8ff	6352	/****************** Bits definition for RTC_BKP16R register *************/
bogdanm	0:9b334a45a8ff	6353	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6354
bogdanm	0:9b334a45a8ff	6355	/****************** Bits definition for RTC_BKP17R register *************/
bogdanm	0:9b334a45a8ff	6356	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6357
bogdanm	0:9b334a45a8ff	6358	/****************** Bits definition for RTC_BKP18R register *************/
bogdanm	0:9b334a45a8ff	6359	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6360
bogdanm	0:9b334a45a8ff	6361	/****************** Bits definition for RTC_BKP19R register *************/
bogdanm	0:9b334a45a8ff	6362	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6363
bogdanm	0:9b334a45a8ff	6364	/****************** Bits definition for RTC_BKP20R register *************/
bogdanm	0:9b334a45a8ff	6365	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6366
bogdanm	0:9b334a45a8ff	6367	/****************** Bits definition for RTC_BKP21R register *************/
bogdanm	0:9b334a45a8ff	6368	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6369
bogdanm	0:9b334a45a8ff	6370	/****************** Bits definition for RTC_BKP22R register *************/
bogdanm	0:9b334a45a8ff	6371	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6372
bogdanm	0:9b334a45a8ff	6373	/****************** Bits definition for RTC_BKP23R register *************/
bogdanm	0:9b334a45a8ff	6374	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6375
bogdanm	0:9b334a45a8ff	6376	/****************** Bits definition for RTC_BKP24R register *************/
bogdanm	0:9b334a45a8ff	6377	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6378
bogdanm	0:9b334a45a8ff	6379	/****************** Bits definition for RTC_BKP25R register *************/
bogdanm	0:9b334a45a8ff	6380	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6381
bogdanm	0:9b334a45a8ff	6382	/****************** Bits definition for RTC_BKP26R register *************/
bogdanm	0:9b334a45a8ff	6383	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6384
bogdanm	0:9b334a45a8ff	6385	/****************** Bits definition for RTC_BKP27R register *************/
bogdanm	0:9b334a45a8ff	6386	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6387
bogdanm	0:9b334a45a8ff	6388	/****************** Bits definition for RTC_BKP28R register *************/
bogdanm	0:9b334a45a8ff	6389	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6390
bogdanm	0:9b334a45a8ff	6391	/****************** Bits definition for RTC_BKP29R register *************/
bogdanm	0:9b334a45a8ff	6392	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6393
bogdanm	0:9b334a45a8ff	6394	/****************** Bits definition for RTC_BKP30R register *************/
bogdanm	0:9b334a45a8ff	6395	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6396
bogdanm	0:9b334a45a8ff	6397	/****************** Bits definition for RTC_BKP31R register *************/
bogdanm	0:9b334a45a8ff	6398	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6399
bogdanm	0:9b334a45a8ff	6400	/****************** Number of backup registers ****************************/
bogdanm	0:9b334a45a8ff	6401	#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6402
bogdanm	0:9b334a45a8ff	6403	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6404	/* */
bogdanm	0:9b334a45a8ff	6405	/* Serial Audio Interface */
bogdanm	0:9b334a45a8ff	6406	/* */
bogdanm	0:9b334a45a8ff	6407	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6408	/****************** Bit definition for SAI_GCR register *****************/
bogdanm	0:9b334a45a8ff	6409	#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /!<SYNCIN[1:0] bits (Synchronization Inputs) /
bogdanm	0:9b334a45a8ff	6410	#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6411	#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6412
bogdanm	0:9b334a45a8ff	6413	#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
bogdanm	0:9b334a45a8ff	6414	#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6415	#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6416
bogdanm	0:9b334a45a8ff	6417	/***************** Bit definition for SAI_xCR1 register *****************/
bogdanm	0:9b334a45a8ff	6418	#define SAI_xCR1_MODE ((uint32_t)0x00000003) /!<MODE[1:0] bits (Audio Block Mode) /
bogdanm	0:9b334a45a8ff	6419	#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6420	#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6421
bogdanm	0:9b334a45a8ff	6422	#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /!<PRTCFG[1:0] bits (Protocol Configuration) /
bogdanm	0:9b334a45a8ff	6423	#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6424	#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6425
bogdanm	0:9b334a45a8ff	6426	#define SAI_xCR1_DS ((uint32_t)0x000000E0) /!<DS[1:0] bits (Data Size) /
bogdanm	0:9b334a45a8ff	6427	#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6428	#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6429	#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6430
bogdanm	0:9b334a45a8ff	6431	#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /!<LSB First Configuration /
bogdanm	0:9b334a45a8ff	6432	#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /!<ClocK STRobing edge /
bogdanm	0:9b334a45a8ff	6433
bogdanm	0:9b334a45a8ff	6434	#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /!<SYNCEN[1:0](SYNChronization ENable) /
bogdanm	0:9b334a45a8ff	6435	#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6436	#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6437
bogdanm	0:9b334a45a8ff	6438	#define SAI_xCR1_MONO ((uint32_t)0x00001000) /!<Mono mode /
bogdanm	0:9b334a45a8ff	6439	#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /!<Output Drive /
bogdanm	0:9b334a45a8ff	6440	#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /!<Audio Block enable /
bogdanm	0:9b334a45a8ff	6441	#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /!<DMA enable /
bogdanm	0:9b334a45a8ff	6442	#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /!<No Divider Configuration /
bogdanm	0:9b334a45a8ff	6443
bogdanm	0:9b334a45a8ff	6444	#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /!<MCKDIV[3:0] (Master ClocK Divider) /
bogdanm	0:9b334a45a8ff	6445	#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6446	#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6447	#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6448	#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6449
bogdanm	0:9b334a45a8ff	6450	/***************** Bit definition for SAI_xCR2 register *****************/
bogdanm	0:9b334a45a8ff	6451	#define SAI_xCR2_FTH ((uint32_t)0x00000007) /!<FTH[2:0](Fifo THreshold) /
bogdanm	0:9b334a45a8ff	6452	#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6453	#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6454	#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6455
bogdanm	0:9b334a45a8ff	6456	#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /!<Fifo FLUSH /
bogdanm	0:9b334a45a8ff	6457	#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /!<TRIState Management on data line /
bogdanm	0:9b334a45a8ff	6458	#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /!<Mute mode /
bogdanm	0:9b334a45a8ff	6459	#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /!<Muate value /
bogdanm	0:9b334a45a8ff	6460
bogdanm	0:9b334a45a8ff	6461
bogdanm	0:9b334a45a8ff	6462	#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /!<MUTECNT[5:0] (MUTE counter) /
bogdanm	0:9b334a45a8ff	6463	#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6464	#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6465	#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6466	#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6467	#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	6468	#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	6469
bogdanm	0:9b334a45a8ff	6470	#define SAI_xCR2_CPL ((uint32_t)0x00002000) /!<CPL mode /
bogdanm	0:9b334a45a8ff	6471	#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /!<COMP[1:0] (Companding mode) /
bogdanm	0:9b334a45a8ff	6472	#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6473	#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6474
bogdanm	0:9b334a45a8ff	6475
bogdanm	0:9b334a45a8ff	6476	/**************** Bit definition for SAI_xFRCR register *****************/
bogdanm	0:9b334a45a8ff	6477	#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /!<FRL[7:0](Frame length) /
bogdanm	0:9b334a45a8ff	6478	#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6479	#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6480	#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6481	#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6482	#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	6483	#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	6484	#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	6485	#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	6486
bogdanm	0:9b334a45a8ff	6487	#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /!<FRL[6:0] (Frame synchronization active level length) /
bogdanm	0:9b334a45a8ff	6488	#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6489	#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6490	#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6491	#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6492	#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	6493	#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	6494	#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	6495
bogdanm	0:9b334a45a8ff	6496	#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /!< Frame Synchronization Definition /
bogdanm	0:9b334a45a8ff	6497	#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /!<Frame Synchronization POLarity /
bogdanm	0:9b334a45a8ff	6498	#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /!<Frame Synchronization OFFset /
bogdanm	0:9b334a45a8ff	6499
bogdanm	0:9b334a45a8ff	6500	/**************** Bit definition for SAI_xSLOTR register *****************/
bogdanm	0:9b334a45a8ff	6501	#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /!<FRL[4:0](First Bit Offset) /
bogdanm	0:9b334a45a8ff	6502	#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6503	#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6504	#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6505	#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6506	#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	6507
bogdanm	0:9b334a45a8ff	6508	#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /!<SLOTSZ[1:0] (Slot size) /
bogdanm	0:9b334a45a8ff	6509	#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6510	#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6511
bogdanm	0:9b334a45a8ff	6512	#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
bogdanm	0:9b334a45a8ff	6513	#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6514	#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6515	#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6516	#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6517
bogdanm	0:9b334a45a8ff	6518	#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /!<SLOTEN[15:0] (Slot Enable) /
bogdanm	0:9b334a45a8ff	6519
bogdanm	0:9b334a45a8ff	6520	/***************** Bit definition for SAI_xIMR register *****************/
bogdanm	0:9b334a45a8ff	6521	#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /!<Overrun underrun interrupt enable /
bogdanm	0:9b334a45a8ff	6522	#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /!<Mute detection interrupt enable /
bogdanm	0:9b334a45a8ff	6523	#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /!<Wrong Clock Configuration interrupt enable /
bogdanm	0:9b334a45a8ff	6524	#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /!<FIFO request interrupt enable /
bogdanm	0:9b334a45a8ff	6525	#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /!<Codec not ready interrupt enable /
bogdanm	0:9b334a45a8ff	6526	#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection interrupt enable /
bogdanm	0:9b334a45a8ff	6527	#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /!<Late frame synchronization detection interrupt enable /
bogdanm	0:9b334a45a8ff	6528
bogdanm	0:9b334a45a8ff	6529	/****************** Bit definition for SAI_xSR register *****************/
bogdanm	0:9b334a45a8ff	6530	#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /!<Overrun underrun /
bogdanm	0:9b334a45a8ff	6531	#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /!<Mute detection /
bogdanm	0:9b334a45a8ff	6532	#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /!<Wrong Clock Configuration /
bogdanm	0:9b334a45a8ff	6533	#define SAI_xSR_FREQ ((uint32_t)0x00000008) /!<FIFO request /
bogdanm	0:9b334a45a8ff	6534	#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /!<Codec not ready /
bogdanm	0:9b334a45a8ff	6535	#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection /
bogdanm	0:9b334a45a8ff	6536	#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /!<Late frame synchronization detection /
bogdanm	0:9b334a45a8ff	6537
bogdanm	0:9b334a45a8ff	6538	#define SAI_xSR_FLVL ((uint32_t)0x00070000) /!<FLVL[2:0] (FIFO Level Threshold) /
bogdanm	0:9b334a45a8ff	6539	#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6540	#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6541	#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6542
bogdanm	0:9b334a45a8ff	6543	/**************** Bit definition for SAI_xCLRFR register ****************/
bogdanm	0:9b334a45a8ff	6544	#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /!<Clear Overrun underrun /
bogdanm	0:9b334a45a8ff	6545	#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /!<Clear Mute detection /
bogdanm	0:9b334a45a8ff	6546	#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /!<Clear Wrong Clock Configuration /
bogdanm	0:9b334a45a8ff	6547	#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /!<Clear FIFO request /
bogdanm	0:9b334a45a8ff	6548	#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /!<Clear Codec not ready /
bogdanm	0:9b334a45a8ff	6549	#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /!<Clear Anticipated frame synchronization detection /
bogdanm	0:9b334a45a8ff	6550	#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /!<Clear Late frame synchronization detection /
bogdanm	0:9b334a45a8ff	6551
bogdanm	0:9b334a45a8ff	6552	/**************** Bit definition for SAI_xDR register ****************/
bogdanm	0:9b334a45a8ff	6553	#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6554
bogdanm	0:9b334a45a8ff	6555	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6556	/* */
bogdanm	0:9b334a45a8ff	6557	/* LCD Controller (LCD) */
bogdanm	0:9b334a45a8ff	6558	/* */
bogdanm	0:9b334a45a8ff	6559	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6560
bogdanm	0:9b334a45a8ff	6561	/***************** Bit definition for LCD_CR register *******************/
bogdanm	0:9b334a45a8ff	6562	#define LCD_CR_LCDEN ((uint32_t)0x00000001) /!< LCD Enable Bit /
bogdanm	0:9b334a45a8ff	6563	#define LCD_CR_VSEL ((uint32_t)0x00000002) /!< Voltage source selector Bit /
bogdanm	0:9b334a45a8ff	6564
bogdanm	0:9b334a45a8ff	6565	#define LCD_CR_DUTY ((uint32_t)0x0000001C) /!< DUTY[2:0] bits (Duty selector) /
bogdanm	0:9b334a45a8ff	6566	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /!< Duty selector Bit 0 /
bogdanm	0:9b334a45a8ff	6567	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /!< Duty selector Bit 1 /
bogdanm	0:9b334a45a8ff	6568	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /!< Duty selector Bit 2 /
bogdanm	0:9b334a45a8ff	6569
bogdanm	0:9b334a45a8ff	6570	#define LCD_CR_BIAS ((uint32_t)0x00000060) /!< BIAS[1:0] bits (Bias selector) /
bogdanm	0:9b334a45a8ff	6571	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /!< Bias selector Bit 0 /
bogdanm	0:9b334a45a8ff	6572	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /!< Bias selector Bit 1 /
bogdanm	0:9b334a45a8ff	6573
bogdanm	0:9b334a45a8ff	6574	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /!< Mux Segment Enable Bit /
bogdanm	0:9b334a45a8ff	6575	#define LCD_CR_BUFEN ((uint32_t)0x00000100) /!< Voltage output buffer enable /
bogdanm	0:9b334a45a8ff	6576
bogdanm	0:9b334a45a8ff	6577	/***************** Bit definition for LCD_FCR register ******************/
bogdanm	0:9b334a45a8ff	6578	#define LCD_FCR_HD ((uint32_t)0x00000001) /!< High Drive Enable Bit /
bogdanm	0:9b334a45a8ff	6579	#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /!< Start of Frame Interrupt Enable Bit /
bogdanm	0:9b334a45a8ff	6580	#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /!< Update Display Done Interrupt Enable Bit /
bogdanm	0:9b334a45a8ff	6581
bogdanm	0:9b334a45a8ff	6582	#define LCD_FCR_PON ((uint32_t)0x00000070) /!< PON[2:0] bits (Pulse ON Duration) /
bogdanm	0:9b334a45a8ff	6583	#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6584	#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6585	#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6586
bogdanm	0:9b334a45a8ff	6587	#define LCD_FCR_DEAD ((uint32_t)0x00000380) /!< DEAD[2:0] bits (DEAD Time) /
bogdanm	0:9b334a45a8ff	6588	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6589	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6590	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6591
bogdanm	0:9b334a45a8ff	6592	#define LCD_FCR_CC ((uint32_t)0x00001C00) /!< CC[2:0] bits (Contrast Control) /
bogdanm	0:9b334a45a8ff	6593	#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6594	#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6595	#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6596
bogdanm	0:9b334a45a8ff	6597	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /!< BLINKF[2:0] bits (Blink Frequency) /
bogdanm	0:9b334a45a8ff	6598	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6599	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6600	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6601
bogdanm	0:9b334a45a8ff	6602	#define LCD_FCR_BLINK ((uint32_t)0x00030000) /!< BLINK[1:0] bits (Blink Enable) /
bogdanm	0:9b334a45a8ff	6603	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6604	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6605
bogdanm	0:9b334a45a8ff	6606	#define LCD_FCR_DIV ((uint32_t)0x003C0000) /!< DIV[3:0] bits (Divider) /
bogdanm	0:9b334a45a8ff	6607	#define LCD_FCR_PS ((uint32_t)0x03C00000) /!< PS[3:0] bits (Prescaler) /
bogdanm	0:9b334a45a8ff	6608
bogdanm	0:9b334a45a8ff	6609	/***************** Bit definition for LCD_SR register *******************/
bogdanm	0:9b334a45a8ff	6610	#define LCD_SR_ENS ((uint32_t)0x00000001) /!< LCD Enabled Bit /
bogdanm	0:9b334a45a8ff	6611	#define LCD_SR_SOF ((uint32_t)0x00000002) /!< Start Of Frame Flag Bit /
bogdanm	0:9b334a45a8ff	6612	#define LCD_SR_UDR ((uint32_t)0x00000004) /!< Update Display Request Bit /
bogdanm	0:9b334a45a8ff	6613	#define LCD_SR_UDD ((uint32_t)0x00000008) /!< Update Display Done Flag Bit /
bogdanm	0:9b334a45a8ff	6614	#define LCD_SR_RDY ((uint32_t)0x00000010) /!< Ready Flag Bit /
bogdanm	0:9b334a45a8ff	6615	#define LCD_SR_FCRSR ((uint32_t)0x00000020) /!< LCD FCR Register Synchronization Flag Bit /
bogdanm	0:9b334a45a8ff	6616
bogdanm	0:9b334a45a8ff	6617	/***************** Bit definition for LCD_CLR register ******************/
bogdanm	0:9b334a45a8ff	6618	#define LCD_CLR_SOFC ((uint32_t)0x00000002) /!< Start Of Frame Flag Clear Bit /
bogdanm	0:9b334a45a8ff	6619	#define LCD_CLR_UDDC ((uint32_t)0x00000008) /!< Update Display Done Flag Clear Bit /
bogdanm	0:9b334a45a8ff	6620
bogdanm	0:9b334a45a8ff	6621	/***************** Bit definition for LCD_RAM register ******************/
bogdanm	0:9b334a45a8ff	6622	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /!< Segment Data Bits /
bogdanm	0:9b334a45a8ff	6623
bogdanm	0:9b334a45a8ff	6624	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6625	/* */
bogdanm	0:9b334a45a8ff	6626	/* SDMMC Interface */
bogdanm	0:9b334a45a8ff	6627	/* */
bogdanm	0:9b334a45a8ff	6628	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6629	/**************** Bit definition for SDMMC_POWER register ****************/
bogdanm	0:9b334a45a8ff	6630	#define SDMMC_POWER_PWRCTRL ((uint8_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
bogdanm	0:9b334a45a8ff	6631	#define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6632	#define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6633
bogdanm	0:9b334a45a8ff	6634	/**************** Bit definition for SDMMC_CLKCR register ****************/
bogdanm	0:9b334a45a8ff	6635	#define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FF) /!<Clock divide factor /
bogdanm	0:9b334a45a8ff	6636	#define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100) /!<Clock enable bit /
bogdanm	0:9b334a45a8ff	6637	#define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200) /!<Power saving configuration bit /
bogdanm	0:9b334a45a8ff	6638	#define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400) /!<Clock divider bypass enable bit /
bogdanm	0:9b334a45a8ff	6639
bogdanm	0:9b334a45a8ff	6640	#define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
bogdanm	0:9b334a45a8ff	6641	#define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6642	#define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6643
bogdanm	0:9b334a45a8ff	6644	#define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000) /!<SDMMC_CK dephasing selection bit /
bogdanm	0:9b334a45a8ff	6645	#define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000) /!<HW Flow Control enable /
bogdanm	0:9b334a45a8ff	6646
bogdanm	0:9b334a45a8ff	6647	/***************** Bit definition for SDMMC_ARG register *****************/
bogdanm	0:9b334a45a8ff	6648	#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
bogdanm	0:9b334a45a8ff	6649
bogdanm	0:9b334a45a8ff	6650	/***************** Bit definition for SDMMC_CMD register *****************/
bogdanm	0:9b334a45a8ff	6651	#define SDMMC_CMD_CMDINDEX ((uint16_t)0x003F) /!<Command Index /
bogdanm	0:9b334a45a8ff	6652
bogdanm	0:9b334a45a8ff	6653	#define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
bogdanm	0:9b334a45a8ff	6654	#define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6655	#define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6656
bogdanm	0:9b334a45a8ff	6657	#define SDMMC_CMD_WAITINT ((uint16_t)0x0100) /!<CPSM Waits for Interrupt Request /
bogdanm	0:9b334a45a8ff	6658	#define SDMMC_CMD_WAITPEND ((uint16_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
bogdanm	0:9b334a45a8ff	6659	#define SDMMC_CMD_CPSMEN ((uint16_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
bogdanm	0:9b334a45a8ff	6660	#define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!<SD I/O suspend command /
bogdanm	0:9b334a45a8ff	6661
bogdanm	0:9b334a45a8ff	6662	/*************** Bit definition for SDMMC_RESPCMD register ***************/
bogdanm	0:9b334a45a8ff	6663	#define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3F) /!<Response command index /
bogdanm	0:9b334a45a8ff	6664
bogdanm	0:9b334a45a8ff	6665	/**************** Bit definition for SDMMC_RESP0 register ****************/
bogdanm	0:9b334a45a8ff	6666	#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	0:9b334a45a8ff	6667
bogdanm	0:9b334a45a8ff	6668	/**************** Bit definition for SDMMC_RESP1 register ****************/
bogdanm	0:9b334a45a8ff	6669	#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	0:9b334a45a8ff	6670
bogdanm	0:9b334a45a8ff	6671	/**************** Bit definition for SDMMC_RESP2 register ****************/
bogdanm	0:9b334a45a8ff	6672	#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	0:9b334a45a8ff	6673
bogdanm	0:9b334a45a8ff	6674	/**************** Bit definition for SDMMC_RESP3 register ****************/
bogdanm	0:9b334a45a8ff	6675	#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	0:9b334a45a8ff	6676
bogdanm	0:9b334a45a8ff	6677	/**************** Bit definition for SDMMC_RESP4 register ****************/
bogdanm	0:9b334a45a8ff	6678	#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	0:9b334a45a8ff	6679
bogdanm	0:9b334a45a8ff	6680	/**************** Bit definition for SDMMC_DTIMER register ***************/
bogdanm	0:9b334a45a8ff	6681	#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
bogdanm	0:9b334a45a8ff	6682
bogdanm	0:9b334a45a8ff	6683	/**************** Bit definition for SDMMC_DLEN register *****************/
bogdanm	0:9b334a45a8ff	6684	#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
bogdanm	0:9b334a45a8ff	6685
bogdanm	0:9b334a45a8ff	6686	/**************** Bit definition for SDMMC_DCTRL register ****************/
bogdanm	0:9b334a45a8ff	6687	#define SDMMC_DCTRL_DTEN ((uint16_t)0x0001) /!<Data transfer enabled bit /
bogdanm	0:9b334a45a8ff	6688	#define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002) /!<Data transfer direction selection /
bogdanm	0:9b334a45a8ff	6689	#define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004) /!<Data transfer mode selection /
bogdanm	0:9b334a45a8ff	6690	#define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008) /!<DMA enabled bit /
bogdanm	0:9b334a45a8ff	6691
bogdanm	0:9b334a45a8ff	6692	#define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
bogdanm	0:9b334a45a8ff	6693	#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6694	#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6695	#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6696	#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	6697
bogdanm	0:9b334a45a8ff	6698	#define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100) /!<Read wait start /
bogdanm	0:9b334a45a8ff	6699	#define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200) /!<Read wait stop /
bogdanm	0:9b334a45a8ff	6700	#define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400) /!<Read wait mode /
bogdanm	0:9b334a45a8ff	6701	#define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800) /!<SD I/O enable functions /
bogdanm	0:9b334a45a8ff	6702
bogdanm	0:9b334a45a8ff	6703	/**************** Bit definition for SDMMC_DCOUNT register ***************/
bogdanm	0:9b334a45a8ff	6704	#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
bogdanm	0:9b334a45a8ff	6705
bogdanm	0:9b334a45a8ff	6706	/**************** Bit definition for SDMMC_STA register ******************/
bogdanm	0:9b334a45a8ff	6707	#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
bogdanm	0:9b334a45a8ff	6708	#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
bogdanm	0:9b334a45a8ff	6709	#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
bogdanm	0:9b334a45a8ff	6710	#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
bogdanm	0:9b334a45a8ff	6711	#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
bogdanm	0:9b334a45a8ff	6712	#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
bogdanm	0:9b334a45a8ff	6713	#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
bogdanm	0:9b334a45a8ff	6714	#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
bogdanm	0:9b334a45a8ff	6715	#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
bogdanm	0:9b334a45a8ff	6716	#define SDMMC_STA_STBITERR ((uint32_t)0x00000200) /!<Start bit not detected on all data signals in wide bus mode /
bogdanm	0:9b334a45a8ff	6717	#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
bogdanm	0:9b334a45a8ff	6718	#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
bogdanm	0:9b334a45a8ff	6719	#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
bogdanm	0:9b334a45a8ff	6720	#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
bogdanm	0:9b334a45a8ff	6721	#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
bogdanm	0:9b334a45a8ff	6722	#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
bogdanm	0:9b334a45a8ff	6723	#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
bogdanm	0:9b334a45a8ff	6724	#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
bogdanm	0:9b334a45a8ff	6725	#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
bogdanm	0:9b334a45a8ff	6726	#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
bogdanm	0:9b334a45a8ff	6727	#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
bogdanm	0:9b334a45a8ff	6728	#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
bogdanm	0:9b334a45a8ff	6729	#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /!<SDIO interrupt received /
bogdanm	0:9b334a45a8ff	6730
bogdanm	0:9b334a45a8ff	6731	/***************** Bit definition for SDMMC_ICR register *****************/
bogdanm	0:9b334a45a8ff	6732	#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
bogdanm	0:9b334a45a8ff	6733	#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
bogdanm	0:9b334a45a8ff	6734	#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
bogdanm	0:9b334a45a8ff	6735	#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
bogdanm	0:9b334a45a8ff	6736	#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
bogdanm	0:9b334a45a8ff	6737	#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
bogdanm	0:9b334a45a8ff	6738	#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
bogdanm	0:9b334a45a8ff	6739	#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
bogdanm	0:9b334a45a8ff	6740	#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
bogdanm	0:9b334a45a8ff	6741	#define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200) /!<STBITERR flag clear bit /
bogdanm	0:9b334a45a8ff	6742	#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
bogdanm	0:9b334a45a8ff	6743	#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDIOIT flag clear bit /
bogdanm	0:9b334a45a8ff	6744
bogdanm	0:9b334a45a8ff	6745	/**************** Bit definition for SDMMC_MASK register *****************/
bogdanm	0:9b334a45a8ff	6746	#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
bogdanm	0:9b334a45a8ff	6747	#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
bogdanm	0:9b334a45a8ff	6748	#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
bogdanm	0:9b334a45a8ff	6749	#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
bogdanm	0:9b334a45a8ff	6750	#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	6751	#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	6752	#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
bogdanm	0:9b334a45a8ff	6753	#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
bogdanm	0:9b334a45a8ff	6754	#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
bogdanm	0:9b334a45a8ff	6755	#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
bogdanm	0:9b334a45a8ff	6756	#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
bogdanm	0:9b334a45a8ff	6757	#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
bogdanm	0:9b334a45a8ff	6758	#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
bogdanm	0:9b334a45a8ff	6759	#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	6760	#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
bogdanm	0:9b334a45a8ff	6761	#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
bogdanm	0:9b334a45a8ff	6762	#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
bogdanm	0:9b334a45a8ff	6763	#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	6764	#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	6765	#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
bogdanm	0:9b334a45a8ff	6766	#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
bogdanm	0:9b334a45a8ff	6767	#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDIO Mode Interrupt Received interrupt Enable /
bogdanm	0:9b334a45a8ff	6768
bogdanm	0:9b334a45a8ff	6769	/*************** Bit definition for SDMMC_FIFOCNT register ***************/
bogdanm	0:9b334a45a8ff	6770	#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
bogdanm	0:9b334a45a8ff	6771
bogdanm	0:9b334a45a8ff	6772	/**************** Bit definition for SDMMC_FIFO register *****************/
bogdanm	0:9b334a45a8ff	6773	#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
bogdanm	0:9b334a45a8ff	6774
bogdanm	0:9b334a45a8ff	6775	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6776	/* */
bogdanm	0:9b334a45a8ff	6777	/* Serial Peripheral Interface (SPI) */
bogdanm	0:9b334a45a8ff	6778	/* */
bogdanm	0:9b334a45a8ff	6779	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6780	/***************** Bit definition for SPI_CR1 register ******************/
bogdanm	0:9b334a45a8ff	6781	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!<Clock Phase /
bogdanm	0:9b334a45a8ff	6782	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!<Clock Polarity /
bogdanm	0:9b334a45a8ff	6783	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!<Master Selection /
bogdanm	0:9b334a45a8ff	6784
bogdanm	0:9b334a45a8ff	6785	#define SPI_CR1_BR ((uint32_t)0x00000038) /!<BR[2:0] bits (Baud Rate Control) /
bogdanm	0:9b334a45a8ff	6786	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6787	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6788	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	6789
bogdanm	0:9b334a45a8ff	6790	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!<SPI Enable /
bogdanm	0:9b334a45a8ff	6791	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!<Frame Format /
bogdanm	0:9b334a45a8ff	6792	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!<Internal slave select /
bogdanm	0:9b334a45a8ff	6793	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!<Software slave management /
bogdanm	0:9b334a45a8ff	6794	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!<Receive only /
bogdanm	0:9b334a45a8ff	6795	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
bogdanm	0:9b334a45a8ff	6796	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!<Transmit CRC next /
bogdanm	0:9b334a45a8ff	6797	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!<Hardware CRC calculation enable /
bogdanm	0:9b334a45a8ff	6798	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!<Output enable in bidirectional mode /
bogdanm	0:9b334a45a8ff	6799	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!<Bidirectional data mode enable /
bogdanm	0:9b334a45a8ff	6800
bogdanm	0:9b334a45a8ff	6801	/***************** Bit definition for SPI_CR2 register ******************/
bogdanm	0:9b334a45a8ff	6802	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	6803	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	6804	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
bogdanm	0:9b334a45a8ff	6805	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
bogdanm	0:9b334a45a8ff	6806	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
bogdanm	0:9b334a45a8ff	6807	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	6808	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	6809	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	6810	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
bogdanm	0:9b334a45a8ff	6811	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6812	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6813	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6814	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6815	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
bogdanm	0:9b334a45a8ff	6816	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
bogdanm	0:9b334a45a8ff	6817	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
bogdanm	0:9b334a45a8ff	6818
bogdanm	0:9b334a45a8ff	6819	/****************** Bit definition for SPI_SR register ******************/
bogdanm	0:9b334a45a8ff	6820	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
bogdanm	0:9b334a45a8ff	6821	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
bogdanm	0:9b334a45a8ff	6822	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
bogdanm	0:9b334a45a8ff	6823	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
bogdanm	0:9b334a45a8ff	6824	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
bogdanm	0:9b334a45a8ff	6825	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
bogdanm	0:9b334a45a8ff	6826	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
bogdanm	0:9b334a45a8ff	6827	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
bogdanm	0:9b334a45a8ff	6828	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
bogdanm	0:9b334a45a8ff	6829	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
bogdanm	0:9b334a45a8ff	6830	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6831	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6832	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
bogdanm	0:9b334a45a8ff	6833	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6834	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6835
bogdanm	0:9b334a45a8ff	6836	/****************** Bit definition for SPI_DR register ******************/
bogdanm	0:9b334a45a8ff	6837	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!<Data Register /
bogdanm	0:9b334a45a8ff	6838
bogdanm	0:9b334a45a8ff	6839	/***************** Bit definition for SPI_CRCPR register ****************/
bogdanm	0:9b334a45a8ff	6840	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!<CRC polynomial register /
bogdanm	0:9b334a45a8ff	6841
bogdanm	0:9b334a45a8ff	6842	/**************** Bit definition for SPI_RXCRCR register ****************/
bogdanm	0:9b334a45a8ff	6843	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!<Rx CRC Register /
bogdanm	0:9b334a45a8ff	6844
bogdanm	0:9b334a45a8ff	6845	/**************** Bit definition for SPI_TXCRCR register ****************/
bogdanm	0:9b334a45a8ff	6846	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!<Tx CRC Register /
bogdanm	0:9b334a45a8ff	6847
bogdanm	0:9b334a45a8ff	6848	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6849	/* */
bogdanm	0:9b334a45a8ff	6850	/* QUADSPI */
bogdanm	0:9b334a45a8ff	6851	/* */
bogdanm	0:9b334a45a8ff	6852	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6853	/*************** Bit definition for QUADSPI_CR register *****************/
bogdanm	0:9b334a45a8ff	6854	#define QUADSPI_CR_EN ((uint32_t)0x00000001) /!< Enable /
bogdanm	0:9b334a45a8ff	6855	#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /!< Abort request /
bogdanm	0:9b334a45a8ff	6856	#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /!< DMA Enable /
bogdanm	0:9b334a45a8ff	6857	#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /!< Timeout Counter Enable /
bogdanm	0:9b334a45a8ff	6858	#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /!< Sample Shift /
bogdanm	0:9b334a45a8ff	6859	#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /!< FTHRES[3:0] FIFO Level /
bogdanm	0:9b334a45a8ff	6860	#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6861	#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6862	#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6863	#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6864	#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /!< Transfer Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	6865	#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /!< Transfer Complete Interrupt Enable /
bogdanm	0:9b334a45a8ff	6866	#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /!< FIFO Threshold Interrupt Enable /
bogdanm	0:9b334a45a8ff	6867	#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /!< Status Match Interrupt Enable /
bogdanm	0:9b334a45a8ff	6868	#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /!< TimeOut Interrupt Enable /
bogdanm	0:9b334a45a8ff	6869	#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /!< Automatic Polling Mode Stop /
bogdanm	0:9b334a45a8ff	6870	#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /!< Polling Match Mode /
bogdanm	0:9b334a45a8ff	6871	#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /!< PRESCALER[7:0] Clock prescaler /
bogdanm	0:9b334a45a8ff	6872	#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6873	#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6874	#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6875	#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6876	#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6877	#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	6878	#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	6879	#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	6880
bogdanm	0:9b334a45a8ff	6881	/*************** Bit definition for QUADSPI_DCR register ****************/
bogdanm	0:9b334a45a8ff	6882	#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /!< Mode 0 / Mode 3 /
bogdanm	0:9b334a45a8ff	6883	#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /!< CSHT[2:0]: ChipSelect High Time /
bogdanm	0:9b334a45a8ff	6884	#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6885	#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6886	#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6887	#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /!< FSIZE[4:0]: Flash Size /
bogdanm	0:9b334a45a8ff	6888	#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6889	#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6890	#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6891	#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6892	#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6893
bogdanm	0:9b334a45a8ff	6894	/**************** Bit definition for QUADSPI_SR register *****************/
bogdanm	0:9b334a45a8ff	6895	#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /!< Transfer Error Flag /
bogdanm	0:9b334a45a8ff	6896	#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /!< Transfer Complete Flag /
bogdanm	0:9b334a45a8ff	6897	#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /!< FIFO Threshlod Flag /
bogdanm	0:9b334a45a8ff	6898	#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /!< Status Match Flag /
bogdanm	0:9b334a45a8ff	6899	#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /!< Timeout Flag /
bogdanm	0:9b334a45a8ff	6900	#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /!< Busy /
bogdanm	0:9b334a45a8ff	6901	#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /!< FIFO Threshlod Flag /
bogdanm	0:9b334a45a8ff	6902	#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6903	#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6904	#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6905	#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6906	#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6907
bogdanm	0:9b334a45a8ff	6908	/**************** Bit definition for QUADSPI_FCR register ****************/
bogdanm	0:9b334a45a8ff	6909	#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /!< Clear Transfer Error Flag /
bogdanm	0:9b334a45a8ff	6910	#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /!< Clear Transfer Complete Flag /
bogdanm	0:9b334a45a8ff	6911	#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /!< Clear Status Match Flag /
bogdanm	0:9b334a45a8ff	6912	#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /!< Clear Timeout Flag /
bogdanm	0:9b334a45a8ff	6913
bogdanm	0:9b334a45a8ff	6914	/**************** Bit definition for QUADSPI_DLR register ****************/
bogdanm	0:9b334a45a8ff	6915	#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /!< DL[31:0]: Data Length /
bogdanm	0:9b334a45a8ff	6916
bogdanm	0:9b334a45a8ff	6917	/**************** Bit definition for QUADSPI_CCR register ****************/
bogdanm	0:9b334a45a8ff	6918	#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /!< INSTRUCTION[7:0]: Instruction /
bogdanm	0:9b334a45a8ff	6919	#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6920	#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6921	#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6922	#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6923	#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6924	#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	6925	#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	6926	#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	6927	#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /!< IMODE[1:0]: Instruction Mode /
bogdanm	0:9b334a45a8ff	6928	#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6929	#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6930	#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /!< ADMODE[1:0]: Address Mode /
bogdanm	0:9b334a45a8ff	6931	#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6932	#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6933	#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /!< ADSIZE[1:0]: Address Size /
bogdanm	0:9b334a45a8ff	6934	#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6935	#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6936	#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /!< ABMODE[1:0]: Alternate Bytes Mode /
bogdanm	0:9b334a45a8ff	6937	#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6938	#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6939	#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /!< ABSIZE[1:0]: Instruction Mode /
bogdanm	0:9b334a45a8ff	6940	#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6941	#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6942	#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /!< DCYC[4:0]: Dummy Cycles /
bogdanm	0:9b334a45a8ff	6943	#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6944	#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6945	#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6946	#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6947	#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6948	#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /!< DMODE[1:0]: Data Mode /
bogdanm	0:9b334a45a8ff	6949	#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6950	#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6951	#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /!< FMODE[1:0]: Functional Mode /
bogdanm	0:9b334a45a8ff	6952	#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6953	#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6954	#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /!< SIOO: Send Instruction Only Once Mode /
bogdanm	0:9b334a45a8ff	6955	#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /!< DDRM: Double Data Rate Mode /
bogdanm	0:9b334a45a8ff	6956
bogdanm	0:9b334a45a8ff	6957	/**************** Bit definition for QUADSPI_AR register *****************/
bogdanm	0:9b334a45a8ff	6958	#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< ADDRESS[31:0]: Address /
bogdanm	0:9b334a45a8ff	6959
bogdanm	0:9b334a45a8ff	6960	/**************** Bit definition for QUADSPI_ABR register ****************/
bogdanm	0:9b334a45a8ff	6961	#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /!< ALTERNATE[31:0]: Alternate Bytes /
bogdanm	0:9b334a45a8ff	6962
bogdanm	0:9b334a45a8ff	6963	/**************** Bit definition for QUADSPI_DR register *****************/
bogdanm	0:9b334a45a8ff	6964	#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /!< DATA[31:0]: Data /
bogdanm	0:9b334a45a8ff	6965
bogdanm	0:9b334a45a8ff	6966	/**************** Bit definition for QUADSPI_PSMKR register **************/
bogdanm	0:9b334a45a8ff	6967	#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /!< MASK[31:0]: Status Mask /
bogdanm	0:9b334a45a8ff	6968
bogdanm	0:9b334a45a8ff	6969	/**************** Bit definition for QUADSPI_PSMAR register **************/
bogdanm	0:9b334a45a8ff	6970	#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /!< MATCH[31:0]: Status Match /
bogdanm	0:9b334a45a8ff	6971
bogdanm	0:9b334a45a8ff	6972	/**************** Bit definition for QUADSPI_PIR register ***************/
bogdanm	0:9b334a45a8ff	6973	#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /!< INTERVAL[15:0]: Polling Interval /
bogdanm	0:9b334a45a8ff	6974
bogdanm	0:9b334a45a8ff	6975	/**************** Bit definition for QUADSPI_LPTR register ***************/
bogdanm	0:9b334a45a8ff	6976	#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /!< TIMEOUT[15:0]: Timeout period /
bogdanm	0:9b334a45a8ff	6977
bogdanm	0:9b334a45a8ff	6978	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6979	/* */
bogdanm	0:9b334a45a8ff	6980	/* SYSCFG */
bogdanm	0:9b334a45a8ff	6981	/* */
bogdanm	0:9b334a45a8ff	6982	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6983	/**************** Bit definition for SYSCFG_MEMRMP register *************/
bogdanm	0:9b334a45a8ff	6984	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /!< SYSCFG_Memory Remap Config /
bogdanm	0:9b334a45a8ff	6985	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6986	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6987	#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6988
bogdanm	0:9b334a45a8ff	6989	#define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) /!< Flash Bank mode selection /
bogdanm	0:9b334a45a8ff	6990
bogdanm	0:9b334a45a8ff	6991
bogdanm	0:9b334a45a8ff	6992	/**************** Bit definition for SYSCFG_CFGR1 register ****************/
bogdanm	0:9b334a45a8ff	6993	#define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001) /!< FIREWALL access enable/
bogdanm	0:9b334a45a8ff	6994	#define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100) /!< I/O analog switch voltage booster enable /
bogdanm	0:9b334a45a8ff	6995	#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
bogdanm	0:9b334a45a8ff	6996	#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
bogdanm	0:9b334a45a8ff	6997	#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
bogdanm	0:9b334a45a8ff	6998	#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
bogdanm	0:9b334a45a8ff	6999	#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /!< I2C1 Fast mode plus /
bogdanm	0:9b334a45a8ff	7000	#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /!< I2C2 Fast mode plus /
bogdanm	0:9b334a45a8ff	7001	#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000) /!< I2C3 Fast mode plus /
bogdanm	0:9b334a45a8ff	7002	#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /!< Invalid operation Interrupt enable /
bogdanm	0:9b334a45a8ff	7003	#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /!< Divide-by-zero Interrupt enable /
bogdanm	0:9b334a45a8ff	7004	#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /!< Underflow Interrupt enable /
bogdanm	0:9b334a45a8ff	7005	#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /!< Overflow Interrupt enable /
bogdanm	0:9b334a45a8ff	7006	#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /!< Input denormal Interrupt enable /
bogdanm	0:9b334a45a8ff	7007	#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /!< Inexact Interrupt enable (interrupt disabled at reset) /
bogdanm	0:9b334a45a8ff	7008
bogdanm	0:9b334a45a8ff	7009	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
bogdanm	0:9b334a45a8ff	7010	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007) /!<EXTI 0 configuration /
bogdanm	0:9b334a45a8ff	7011	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070) /!<EXTI 1 configuration /
bogdanm	0:9b334a45a8ff	7012	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700) /!<EXTI 2 configuration /
bogdanm	0:9b334a45a8ff	7013	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000) /!<EXTI 3 configuration /
bogdanm	0:9b334a45a8ff	7014	/**
bogdanm	0:9b334a45a8ff	7015	* @brief EXTI0 configuration
bogdanm	0:9b334a45a8ff	7016	*/
bogdanm	0:9b334a45a8ff	7017	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!<PA[0] pin /
bogdanm	0:9b334a45a8ff	7018	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!<PB[0] pin /
bogdanm	0:9b334a45a8ff	7019	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!<PC[0] pin /
bogdanm	0:9b334a45a8ff	7020	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!<PD[0] pin /
bogdanm	0:9b334a45a8ff	7021	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!<PE[0] pin /
bogdanm	0:9b334a45a8ff	7022	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!<PF[0] pin /
bogdanm	0:9b334a45a8ff	7023	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!<PG[0] pin /
bogdanm	0:9b334a45a8ff	7024	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /!<PH[0] pin /
bogdanm	0:9b334a45a8ff	7025
bogdanm	0:9b334a45a8ff	7026
bogdanm	0:9b334a45a8ff	7027	/**
bogdanm	0:9b334a45a8ff	7028	* @brief EXTI1 configuration
bogdanm	0:9b334a45a8ff	7029	*/
bogdanm	0:9b334a45a8ff	7030	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!<PA[1] pin /
bogdanm	0:9b334a45a8ff	7031	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!<PB[1] pin /
bogdanm	0:9b334a45a8ff	7032	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!<PC[1] pin /
bogdanm	0:9b334a45a8ff	7033	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!<PD[1] pin /
bogdanm	0:9b334a45a8ff	7034	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!<PE[1] pin /
bogdanm	0:9b334a45a8ff	7035	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!<PF[1] pin /
bogdanm	0:9b334a45a8ff	7036	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!<PG[1] pin /
bogdanm	0:9b334a45a8ff	7037	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /!<PH[1] pin /
bogdanm	0:9b334a45a8ff	7038
bogdanm	0:9b334a45a8ff	7039	/**
bogdanm	0:9b334a45a8ff	7040	* @brief EXTI2 configuration
bogdanm	0:9b334a45a8ff	7041	*/
bogdanm	0:9b334a45a8ff	7042	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!<PA[2] pin /
bogdanm	0:9b334a45a8ff	7043	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!<PB[2] pin /
bogdanm	0:9b334a45a8ff	7044	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!<PC[2] pin /
bogdanm	0:9b334a45a8ff	7045	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!<PD[2] pin /
bogdanm	0:9b334a45a8ff	7046	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!<PE[2] pin /
bogdanm	0:9b334a45a8ff	7047	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!<PF[2] pin /
bogdanm	0:9b334a45a8ff	7048	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!<PG[2] pin /
bogdanm	0:9b334a45a8ff	7049
bogdanm	0:9b334a45a8ff	7050
bogdanm	0:9b334a45a8ff	7051	/**
bogdanm	0:9b334a45a8ff	7052	* @brief EXTI3 configuration
bogdanm	0:9b334a45a8ff	7053	*/
bogdanm	0:9b334a45a8ff	7054	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!<PA[3] pin /
bogdanm	0:9b334a45a8ff	7055	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!<PB[3] pin /
bogdanm	0:9b334a45a8ff	7056	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!<PC[3] pin /
bogdanm	0:9b334a45a8ff	7057	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!<PD[3] pin /
bogdanm	0:9b334a45a8ff	7058	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!<PE[3] pin /
bogdanm	0:9b334a45a8ff	7059	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!<PF[3] pin /
bogdanm	0:9b334a45a8ff	7060	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!<PG[3] pin /
bogdanm	0:9b334a45a8ff	7061
bogdanm	0:9b334a45a8ff	7062
bogdanm	0:9b334a45a8ff	7063	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
bogdanm	0:9b334a45a8ff	7064	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007) /!<EXTI 4 configuration /
bogdanm	0:9b334a45a8ff	7065	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070) /!<EXTI 5 configuration /
bogdanm	0:9b334a45a8ff	7066	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700) /!<EXTI 6 configuration /
bogdanm	0:9b334a45a8ff	7067	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000) /!<EXTI 7 configuration /
bogdanm	0:9b334a45a8ff	7068	/**
bogdanm	0:9b334a45a8ff	7069	* @brief EXTI4 configuration
bogdanm	0:9b334a45a8ff	7070	*/
bogdanm	0:9b334a45a8ff	7071	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!<PA[4] pin /
bogdanm	0:9b334a45a8ff	7072	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!<PB[4] pin /
bogdanm	0:9b334a45a8ff	7073	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!<PC[4] pin /
bogdanm	0:9b334a45a8ff	7074	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!<PD[4] pin /
bogdanm	0:9b334a45a8ff	7075	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!<PE[4] pin /
bogdanm	0:9b334a45a8ff	7076	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!<PF[4] pin /
bogdanm	0:9b334a45a8ff	7077	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!<PG[4] pin /
bogdanm	0:9b334a45a8ff	7078
bogdanm	0:9b334a45a8ff	7079	/**
bogdanm	0:9b334a45a8ff	7080	* @brief EXTI5 configuration
bogdanm	0:9b334a45a8ff	7081	*/
bogdanm	0:9b334a45a8ff	7082	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!<PA[5] pin /
bogdanm	0:9b334a45a8ff	7083	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!<PB[5] pin /
bogdanm	0:9b334a45a8ff	7084	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!<PC[5] pin /
bogdanm	0:9b334a45a8ff	7085	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!<PD[5] pin /
bogdanm	0:9b334a45a8ff	7086	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!<PE[5] pin /
bogdanm	0:9b334a45a8ff	7087	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!<PF[5] pin /
bogdanm	0:9b334a45a8ff	7088	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!<PG[5] pin /
bogdanm	0:9b334a45a8ff	7089
bogdanm	0:9b334a45a8ff	7090	/**
bogdanm	0:9b334a45a8ff	7091	* @brief EXTI6 configuration
bogdanm	0:9b334a45a8ff	7092	*/
bogdanm	0:9b334a45a8ff	7093	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!<PA[6] pin /
bogdanm	0:9b334a45a8ff	7094	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!<PB[6] pin /
bogdanm	0:9b334a45a8ff	7095	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!<PC[6] pin /
bogdanm	0:9b334a45a8ff	7096	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!<PD[6] pin /
bogdanm	0:9b334a45a8ff	7097	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!<PE[6] pin /
bogdanm	0:9b334a45a8ff	7098	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!<PF[6] pin /
bogdanm	0:9b334a45a8ff	7099	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!<PG[6] pin /
bogdanm	0:9b334a45a8ff	7100
bogdanm	0:9b334a45a8ff	7101	/**
bogdanm	0:9b334a45a8ff	7102	* @brief EXTI7 configuration
bogdanm	0:9b334a45a8ff	7103	*/
bogdanm	0:9b334a45a8ff	7104	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!<PA[7] pin /
bogdanm	0:9b334a45a8ff	7105	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!<PB[7] pin /
bogdanm	0:9b334a45a8ff	7106	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!<PC[7] pin /
bogdanm	0:9b334a45a8ff	7107	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!<PD[7] pin /
bogdanm	0:9b334a45a8ff	7108	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!<PE[7] pin /
bogdanm	0:9b334a45a8ff	7109	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!<PF[7] pin /
bogdanm	0:9b334a45a8ff	7110	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!<PG[7] pin /
bogdanm	0:9b334a45a8ff	7111
bogdanm	0:9b334a45a8ff	7112
bogdanm	0:9b334a45a8ff	7113	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
bogdanm	0:9b334a45a8ff	7114	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007) /!<EXTI 8 configuration /
bogdanm	0:9b334a45a8ff	7115	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070) /!<EXTI 9 configuration /
bogdanm	0:9b334a45a8ff	7116	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700) /!<EXTI 10 configuration /
bogdanm	0:9b334a45a8ff	7117	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000) /!<EXTI 11 configuration /
bogdanm	0:9b334a45a8ff	7118
bogdanm	0:9b334a45a8ff	7119	/**
bogdanm	0:9b334a45a8ff	7120	* @brief EXTI8 configuration
bogdanm	0:9b334a45a8ff	7121	*/
bogdanm	0:9b334a45a8ff	7122	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!<PA[8] pin /
bogdanm	0:9b334a45a8ff	7123	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!<PB[8] pin /
bogdanm	0:9b334a45a8ff	7124	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!<PC[8] pin /
bogdanm	0:9b334a45a8ff	7125	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!<PD[8] pin /
bogdanm	0:9b334a45a8ff	7126	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!<PE[8] pin /
bogdanm	0:9b334a45a8ff	7127	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!<PF[8] pin /
bogdanm	0:9b334a45a8ff	7128	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!<PG[8] pin /
bogdanm	0:9b334a45a8ff	7129
bogdanm	0:9b334a45a8ff	7130	/**
bogdanm	0:9b334a45a8ff	7131	* @brief EXTI9 configuration
bogdanm	0:9b334a45a8ff	7132	*/
bogdanm	0:9b334a45a8ff	7133	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!<PA[9] pin /
bogdanm	0:9b334a45a8ff	7134	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!<PB[9] pin /
bogdanm	0:9b334a45a8ff	7135	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!<PC[9] pin /
bogdanm	0:9b334a45a8ff	7136	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!<PD[9] pin /
bogdanm	0:9b334a45a8ff	7137	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!<PE[9] pin /
bogdanm	0:9b334a45a8ff	7138	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!<PF[9] pin /
bogdanm	0:9b334a45a8ff	7139	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!<PG[9] pin /
bogdanm	0:9b334a45a8ff	7140
bogdanm	0:9b334a45a8ff	7141	/**
bogdanm	0:9b334a45a8ff	7142	* @brief EXTI10 configuration
bogdanm	0:9b334a45a8ff	7143	*/
bogdanm	0:9b334a45a8ff	7144	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!<PA[10] pin /
bogdanm	0:9b334a45a8ff	7145	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!<PB[10] pin /
bogdanm	0:9b334a45a8ff	7146	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!<PC[10] pin /
bogdanm	0:9b334a45a8ff	7147	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!<PD[10] pin /
bogdanm	0:9b334a45a8ff	7148	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!<PE[10] pin /
bogdanm	0:9b334a45a8ff	7149	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!<PF[10] pin /
bogdanm	0:9b334a45a8ff	7150	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!<PG[10] pin /
bogdanm	0:9b334a45a8ff	7151
bogdanm	0:9b334a45a8ff	7152	/**
bogdanm	0:9b334a45a8ff	7153	* @brief EXTI11 configuration
bogdanm	0:9b334a45a8ff	7154	*/
bogdanm	0:9b334a45a8ff	7155	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!<PA[11] pin /
bogdanm	0:9b334a45a8ff	7156	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!<PB[11] pin /
bogdanm	0:9b334a45a8ff	7157	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!<PC[11] pin /
bogdanm	0:9b334a45a8ff	7158	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!<PD[11] pin /
bogdanm	0:9b334a45a8ff	7159	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!<PE[11] pin /
bogdanm	0:9b334a45a8ff	7160	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!<PF[11] pin /
bogdanm	0:9b334a45a8ff	7161	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!<PG[11] pin /
bogdanm	0:9b334a45a8ff	7162
bogdanm	0:9b334a45a8ff	7163	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
bogdanm	0:9b334a45a8ff	7164	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007) /!<EXTI 12 configuration /
bogdanm	0:9b334a45a8ff	7165	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070) /!<EXTI 13 configuration /
bogdanm	0:9b334a45a8ff	7166	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700) /!<EXTI 14 configuration /
bogdanm	0:9b334a45a8ff	7167	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000) /!<EXTI 15 configuration /
bogdanm	0:9b334a45a8ff	7168	/**
bogdanm	0:9b334a45a8ff	7169	* @brief EXTI12 configuration
bogdanm	0:9b334a45a8ff	7170	*/
bogdanm	0:9b334a45a8ff	7171	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!<PA[12] pin /
bogdanm	0:9b334a45a8ff	7172	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!<PB[12] pin /
bogdanm	0:9b334a45a8ff	7173	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!<PC[12] pin /
bogdanm	0:9b334a45a8ff	7174	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!<PD[12] pin /
bogdanm	0:9b334a45a8ff	7175	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!<PE[12] pin /
bogdanm	0:9b334a45a8ff	7176	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!<PF[12] pin /
bogdanm	0:9b334a45a8ff	7177	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!<PG[12] pin /
bogdanm	0:9b334a45a8ff	7178
bogdanm	0:9b334a45a8ff	7179	/**
bogdanm	0:9b334a45a8ff	7180	* @brief EXTI13 configuration
bogdanm	0:9b334a45a8ff	7181	*/
bogdanm	0:9b334a45a8ff	7182	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!<PA[13] pin /
bogdanm	0:9b334a45a8ff	7183	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!<PB[13] pin /
bogdanm	0:9b334a45a8ff	7184	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!<PC[13] pin /
bogdanm	0:9b334a45a8ff	7185	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!<PD[13] pin /
bogdanm	0:9b334a45a8ff	7186	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!<PE[13] pin /
bogdanm	0:9b334a45a8ff	7187	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!<PF[13] pin /
bogdanm	0:9b334a45a8ff	7188	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!<PG[13] pin /
bogdanm	0:9b334a45a8ff	7189
bogdanm	0:9b334a45a8ff	7190	/**
bogdanm	0:9b334a45a8ff	7191	* @brief EXTI14 configuration
bogdanm	0:9b334a45a8ff	7192	*/
bogdanm	0:9b334a45a8ff	7193	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!<PA[14] pin /
bogdanm	0:9b334a45a8ff	7194	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!<PB[14] pin /
bogdanm	0:9b334a45a8ff	7195	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!<PC[14] pin /
bogdanm	0:9b334a45a8ff	7196	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!<PD[14] pin /
bogdanm	0:9b334a45a8ff	7197	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!<PE[14] pin /
bogdanm	0:9b334a45a8ff	7198	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!<PF[14] pin /
bogdanm	0:9b334a45a8ff	7199	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!<PG[14] pin /
bogdanm	0:9b334a45a8ff	7200
bogdanm	0:9b334a45a8ff	7201	/**
bogdanm	0:9b334a45a8ff	7202	* @brief EXTI15 configuration
bogdanm	0:9b334a45a8ff	7203	*/
bogdanm	0:9b334a45a8ff	7204	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!<PA[15] pin /
bogdanm	0:9b334a45a8ff	7205	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!<PB[15] pin /
bogdanm	0:9b334a45a8ff	7206	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!<PC[15] pin /
bogdanm	0:9b334a45a8ff	7207	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!<PD[15] pin /
bogdanm	0:9b334a45a8ff	7208	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!<PE[15] pin /
bogdanm	0:9b334a45a8ff	7209	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!<PF[15] pin /
bogdanm	0:9b334a45a8ff	7210	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!<PG[15] pin /
bogdanm	0:9b334a45a8ff	7211
bogdanm	0:9b334a45a8ff	7212	/**************** Bit definition for SYSCFG_SCSR register **************/
bogdanm	0:9b334a45a8ff	7213	#define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001) /!< SRAM2 Erase Request /
bogdanm	0:9b334a45a8ff	7214	#define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002) /!< SRAM2 Erase Ongoing /
bogdanm	0:9b334a45a8ff	7215
bogdanm	0:9b334a45a8ff	7216	/**************** Bit definition for SYSCFG_CFGR2 register **************/
bogdanm	0:9b334a45a8ff	7217	#define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001) /!< Core Lockup Lock /
bogdanm	0:9b334a45a8ff	7218	#define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002) /!< SRAM Parity Lock/
bogdanm	0:9b334a45a8ff	7219	#define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004) /!< PVD Lock /
bogdanm	0:9b334a45a8ff	7220	#define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008) /!< ECC Lock/
bogdanm	0:9b334a45a8ff	7221	#define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100) /!< SRAM Parity Flag /
bogdanm	0:9b334a45a8ff	7222
bogdanm	0:9b334a45a8ff	7223	/**************** Bit definition for SYSCFG_SWPR register **************/
bogdanm	0:9b334a45a8ff	7224	#define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001) /!< SRAM2 Write protection page 0 /
bogdanm	0:9b334a45a8ff	7225	#define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002) /!< SRAM2 Write protection page 1 /
bogdanm	0:9b334a45a8ff	7226	#define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004) /!< SRAM2 Write protection page 2 /
bogdanm	0:9b334a45a8ff	7227	#define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008) /!< SRAM2 Write protection page 3 /
bogdanm	0:9b334a45a8ff	7228	#define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010) /!< SRAM2 Write protection page 4 /
bogdanm	0:9b334a45a8ff	7229	#define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020) /!< SRAM2 Write protection page 5 /
bogdanm	0:9b334a45a8ff	7230	#define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040) /!< SRAM2 Write protection page 6 /
bogdanm	0:9b334a45a8ff	7231	#define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080) /!< SRAM2 Write protection page 7 /
bogdanm	0:9b334a45a8ff	7232	#define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100) /!< SRAM2 Write protection page 8 /
bogdanm	0:9b334a45a8ff	7233	#define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200) /!< SRAM2 Write protection page 9 /
bogdanm	0:9b334a45a8ff	7234	#define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400) /!< SRAM2 Write protection page 10/
bogdanm	0:9b334a45a8ff	7235	#define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800) /!< SRAM2 Write protection page 11/
bogdanm	0:9b334a45a8ff	7236	#define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000) /!< SRAM2 Write protection page 12/
bogdanm	0:9b334a45a8ff	7237	#define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000) /!< SRAM2 Write protection page 13/
bogdanm	0:9b334a45a8ff	7238	#define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000) /!< SRAM2 Write protection page 14/
bogdanm	0:9b334a45a8ff	7239	#define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000) /!< SRAM2 Write protection page 15/
bogdanm	0:9b334a45a8ff	7240	#define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000) /!< SRAM2 Write protection page 16/
bogdanm	0:9b334a45a8ff	7241	#define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000) /!< SRAM2 Write protection page 17/
bogdanm	0:9b334a45a8ff	7242	#define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000) /!< SRAM2 Write protection page 18/
bogdanm	0:9b334a45a8ff	7243	#define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000) /!< SRAM2 Write protection page 19/
bogdanm	0:9b334a45a8ff	7244	#define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000) /!< SRAM2 Write protection page 20/
bogdanm	0:9b334a45a8ff	7245	#define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000) /!< SRAM2 Write protection page 21/
bogdanm	0:9b334a45a8ff	7246	#define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000) /!< SRAM2 Write protection page 22/
bogdanm	0:9b334a45a8ff	7247	#define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000) /!< SRAM2 Write protection page 23/
bogdanm	0:9b334a45a8ff	7248	#define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000) /!< SRAM2 Write protection page 24/
bogdanm	0:9b334a45a8ff	7249	#define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000) /!< SRAM2 Write protection page 25/
bogdanm	0:9b334a45a8ff	7250	#define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000) /!< SRAM2 Write protection page 26/
bogdanm	0:9b334a45a8ff	7251	#define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000) /!< SRAM2 Write protection page 27/
bogdanm	0:9b334a45a8ff	7252	#define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000) /!< SRAM2 Write protection page 28/
bogdanm	0:9b334a45a8ff	7253	#define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000) /!< SRAM2 Write protection page 29/
bogdanm	0:9b334a45a8ff	7254	#define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000) /!< SRAM2 Write protection page 30/
bogdanm	0:9b334a45a8ff	7255	#define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000) /!< SRAM2 Write protection page 31/
bogdanm	0:9b334a45a8ff	7256
bogdanm	0:9b334a45a8ff	7257	/**************** Bit definition for SYSCFG_SKR register **************/
bogdanm	0:9b334a45a8ff	7258	#define SYSCFG_SKR_KEY ((uint32_t)0x000000FF) /!< SRAM2 write protection key for software erase /
bogdanm	0:9b334a45a8ff	7259
bogdanm	0:9b334a45a8ff	7260
bogdanm	0:9b334a45a8ff	7261
bogdanm	0:9b334a45a8ff	7262
bogdanm	0:9b334a45a8ff	7263	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7264	/* */
bogdanm	0:9b334a45a8ff	7265	/* TIM */
bogdanm	0:9b334a45a8ff	7266	/* */
bogdanm	0:9b334a45a8ff	7267	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7268	/***************** Bit definition for TIM_CR1 register ******************/
bogdanm	0:9b334a45a8ff	7269	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
bogdanm	0:9b334a45a8ff	7270	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
bogdanm	0:9b334a45a8ff	7271	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
bogdanm	0:9b334a45a8ff	7272	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
bogdanm	0:9b334a45a8ff	7273	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
bogdanm	0:9b334a45a8ff	7274
bogdanm	0:9b334a45a8ff	7275	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	0:9b334a45a8ff	7276	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7277	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7278
bogdanm	0:9b334a45a8ff	7279	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
bogdanm	0:9b334a45a8ff	7280
bogdanm	0:9b334a45a8ff	7281	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
bogdanm	0:9b334a45a8ff	7282	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7283	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7284
bogdanm	0:9b334a45a8ff	7285	#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /!<Update interrupt flag remap /
bogdanm	0:9b334a45a8ff	7286
bogdanm	0:9b334a45a8ff	7287	/***************** Bit definition for TIM_CR2 register ******************/
bogdanm	0:9b334a45a8ff	7288	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
bogdanm	0:9b334a45a8ff	7289	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
bogdanm	0:9b334a45a8ff	7290	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
bogdanm	0:9b334a45a8ff	7291
bogdanm	0:9b334a45a8ff	7292	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	7293	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7294	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7295	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7296
bogdanm	0:9b334a45a8ff	7297	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
bogdanm	0:9b334a45a8ff	7298	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
bogdanm	0:9b334a45a8ff	7299	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
bogdanm	0:9b334a45a8ff	7300	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
bogdanm	0:9b334a45a8ff	7301	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
bogdanm	0:9b334a45a8ff	7302	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
bogdanm	0:9b334a45a8ff	7303	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
bogdanm	0:9b334a45a8ff	7304	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	7305	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 5 (OC5 output) /
bogdanm	0:9b334a45a8ff	7306	#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /!<Output Idle state 6 (OC6 output) /
bogdanm	0:9b334a45a8ff	7307
bogdanm	0:9b334a45a8ff	7308	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	7309	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7310	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7311	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7312	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7313
bogdanm	0:9b334a45a8ff	7314	/***************** Bit definition for TIM_SMCR register *****************/
bogdanm	0:9b334a45a8ff	7315	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	0:9b334a45a8ff	7316	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7317	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7318	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7319	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7320
bogdanm	0:9b334a45a8ff	7321	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
bogdanm	0:9b334a45a8ff	7322
bogdanm	0:9b334a45a8ff	7323	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	0:9b334a45a8ff	7324	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7325	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7326	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7327
bogdanm	0:9b334a45a8ff	7328	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
bogdanm	0:9b334a45a8ff	7329
bogdanm	0:9b334a45a8ff	7330	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	0:9b334a45a8ff	7331	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7332	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7333	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7334	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7335
bogdanm	0:9b334a45a8ff	7336	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	0:9b334a45a8ff	7337	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7338	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7339
bogdanm	0:9b334a45a8ff	7340	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
bogdanm	0:9b334a45a8ff	7341	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
bogdanm	0:9b334a45a8ff	7342
bogdanm	0:9b334a45a8ff	7343	/***************** Bit definition for TIM_DIER register *****************/
bogdanm	0:9b334a45a8ff	7344	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
bogdanm	0:9b334a45a8ff	7345	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	7346	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	7347	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	7348	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	7349	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
bogdanm	0:9b334a45a8ff	7350	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
bogdanm	0:9b334a45a8ff	7351	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
bogdanm	0:9b334a45a8ff	7352	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
bogdanm	0:9b334a45a8ff	7353	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	7354	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	7355	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	7356	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	7357	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
bogdanm	0:9b334a45a8ff	7358	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
bogdanm	0:9b334a45a8ff	7359
bogdanm	0:9b334a45a8ff	7360	/****************** Bit definition for TIM_SR register ******************/
bogdanm	0:9b334a45a8ff	7361	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
bogdanm	0:9b334a45a8ff	7362	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	0:9b334a45a8ff	7363	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	0:9b334a45a8ff	7364	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	0:9b334a45a8ff	7365	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	0:9b334a45a8ff	7366	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
bogdanm	0:9b334a45a8ff	7367	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
bogdanm	0:9b334a45a8ff	7368	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
bogdanm	0:9b334a45a8ff	7369	#define TIM_SR_B2IF ((uint32_t)0x00000100) /!<Break 2 interrupt Flag /
bogdanm	0:9b334a45a8ff	7370	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
bogdanm	0:9b334a45a8ff	7371	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
bogdanm	0:9b334a45a8ff	7372	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
bogdanm	0:9b334a45a8ff	7373	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
bogdanm	0:9b334a45a8ff	7374	#define TIM_SR_SBIF ((uint32_t)0x00002000) /!<System Break interrupt Flag /
bogdanm	0:9b334a45a8ff	7375	#define TIM_SR_CC5IF ((uint32_t)0x00010000) /!<Capture/Compare 5 interrupt Flag /
bogdanm	0:9b334a45a8ff	7376	#define TIM_SR_CC6IF ((uint32_t)0x00020000) /!<Capture/Compare 6 interrupt Flag /
bogdanm	0:9b334a45a8ff	7377
bogdanm	0:9b334a45a8ff	7378
bogdanm	0:9b334a45a8ff	7379	/***************** Bit definition for TIM_EGR register ******************/
bogdanm	0:9b334a45a8ff	7380	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
bogdanm	0:9b334a45a8ff	7381	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
bogdanm	0:9b334a45a8ff	7382	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
bogdanm	0:9b334a45a8ff	7383	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
bogdanm	0:9b334a45a8ff	7384	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
bogdanm	0:9b334a45a8ff	7385	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
bogdanm	0:9b334a45a8ff	7386	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
bogdanm	0:9b334a45a8ff	7387	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
bogdanm	0:9b334a45a8ff	7388	#define TIM_EGR_B2G ((uint32_t)0x00000100) /!<Break 2 Generation /
bogdanm	0:9b334a45a8ff	7389
bogdanm	0:9b334a45a8ff	7390
bogdanm	0:9b334a45a8ff	7391	/**************** Bit definition for TIM_CCMR1 register *****************/
bogdanm	0:9b334a45a8ff	7392	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	0:9b334a45a8ff	7393	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7394	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7395
bogdanm	0:9b334a45a8ff	7396	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
bogdanm	0:9b334a45a8ff	7397	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
bogdanm	0:9b334a45a8ff	7398
bogdanm	0:9b334a45a8ff	7399	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	0:9b334a45a8ff	7400	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7401	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7402	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7403	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7404
bogdanm	0:9b334a45a8ff	7405	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1 Clear Enable /
bogdanm	0:9b334a45a8ff	7406
bogdanm	0:9b334a45a8ff	7407	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	0:9b334a45a8ff	7408	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7409	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7410
bogdanm	0:9b334a45a8ff	7411	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
bogdanm	0:9b334a45a8ff	7412	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
bogdanm	0:9b334a45a8ff	7413
bogdanm	0:9b334a45a8ff	7414	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	0:9b334a45a8ff	7415	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7416	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7417	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7418	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7419
bogdanm	0:9b334a45a8ff	7420	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
bogdanm	0:9b334a45a8ff	7421
bogdanm	0:9b334a45a8ff	7422	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	7423	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	0:9b334a45a8ff	7424	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7425	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7426
bogdanm	0:9b334a45a8ff	7427	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	0:9b334a45a8ff	7428	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7429	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7430	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7431	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7432
bogdanm	0:9b334a45a8ff	7433	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	0:9b334a45a8ff	7434	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7435	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7436
bogdanm	0:9b334a45a8ff	7437	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	0:9b334a45a8ff	7438	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7439	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7440	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7441	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7442
bogdanm	0:9b334a45a8ff	7443	/**************** Bit definition for TIM_CCMR2 register *****************/
bogdanm	0:9b334a45a8ff	7444	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	0:9b334a45a8ff	7445	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7446	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7447
bogdanm	0:9b334a45a8ff	7448	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
bogdanm	0:9b334a45a8ff	7449	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
bogdanm	0:9b334a45a8ff	7450
bogdanm	0:9b334a45a8ff	7451	#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	0:9b334a45a8ff	7452	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7453	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7454	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7455	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7456
bogdanm	0:9b334a45a8ff	7457	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
bogdanm	0:9b334a45a8ff	7458
bogdanm	0:9b334a45a8ff	7459	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	0:9b334a45a8ff	7460	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7461	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7462
bogdanm	0:9b334a45a8ff	7463	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	0:9b334a45a8ff	7464	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	0:9b334a45a8ff	7465
bogdanm	0:9b334a45a8ff	7466	#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	0:9b334a45a8ff	7467	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7468	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7469	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7470	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7471
bogdanm	0:9b334a45a8ff	7472	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	0:9b334a45a8ff	7473
bogdanm	0:9b334a45a8ff	7474	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	7475	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	0:9b334a45a8ff	7476	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7477	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7478
bogdanm	0:9b334a45a8ff	7479	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	0:9b334a45a8ff	7480	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7481	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7482	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7483	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7484
bogdanm	0:9b334a45a8ff	7485	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	0:9b334a45a8ff	7486	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7487	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7488
bogdanm	0:9b334a45a8ff	7489	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	0:9b334a45a8ff	7490	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7491	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7492	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7493	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7494
bogdanm	0:9b334a45a8ff	7495	/**************** Bit definition for TIM_CCMR3 register *****************/
bogdanm	0:9b334a45a8ff	7496	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
bogdanm	0:9b334a45a8ff	7497	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
bogdanm	0:9b334a45a8ff	7498
bogdanm	0:9b334a45a8ff	7499	#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /!<OC5M[3:0] bits (Output Compare 5 Mode) /
bogdanm	0:9b334a45a8ff	7500	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7501	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7502	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7503	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7504
bogdanm	0:9b334a45a8ff	7505	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
bogdanm	0:9b334a45a8ff	7506
bogdanm	0:9b334a45a8ff	7507	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 6 Fast enable /
bogdanm	0:9b334a45a8ff	7508	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 6 Preload enable /
bogdanm	0:9b334a45a8ff	7509
bogdanm	0:9b334a45a8ff	7510	#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /!<OC6M[3:0] bits (Output Compare 6 Mode) /
bogdanm	0:9b334a45a8ff	7511	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7512	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7513	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7514	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7515
bogdanm	0:9b334a45a8ff	7516	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 6 Clear Enable /
bogdanm	0:9b334a45a8ff	7517
bogdanm	0:9b334a45a8ff	7518	/***************** Bit definition for TIM_CCER register *****************/
bogdanm	0:9b334a45a8ff	7519	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
bogdanm	0:9b334a45a8ff	7520	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
bogdanm	0:9b334a45a8ff	7521	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	0:9b334a45a8ff	7522	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7523	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
bogdanm	0:9b334a45a8ff	7524	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
bogdanm	0:9b334a45a8ff	7525	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	0:9b334a45a8ff	7526	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7527	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
bogdanm	0:9b334a45a8ff	7528	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
bogdanm	0:9b334a45a8ff	7529	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	0:9b334a45a8ff	7530	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7531	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
bogdanm	0:9b334a45a8ff	7532	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
bogdanm	0:9b334a45a8ff	7533	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7534	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
bogdanm	0:9b334a45a8ff	7535	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
bogdanm	0:9b334a45a8ff	7536	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
bogdanm	0:9b334a45a8ff	7537	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
bogdanm	0:9b334a45a8ff	7538
bogdanm	0:9b334a45a8ff	7539	/***************** Bit definition for TIM_CNT register ******************/
bogdanm	0:9b334a45a8ff	7540	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	0:9b334a45a8ff	7541	#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /!<Update interrupt flag copy (if UIFREMAP=1) /
bogdanm	0:9b334a45a8ff	7542
bogdanm	0:9b334a45a8ff	7543	/***************** Bit definition for TIM_PSC register ******************/
bogdanm	0:9b334a45a8ff	7544	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
bogdanm	0:9b334a45a8ff	7545
bogdanm	0:9b334a45a8ff	7546	/***************** Bit definition for TIM_ARR register ******************/
bogdanm	0:9b334a45a8ff	7547	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<Actual auto-reload Value /
bogdanm	0:9b334a45a8ff	7548
bogdanm	0:9b334a45a8ff	7549	/***************** Bit definition for TIM_RCR register ******************/
bogdanm	0:9b334a45a8ff	7550	#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /!<Repetition Counter Value /
bogdanm	0:9b334a45a8ff	7551
bogdanm	0:9b334a45a8ff	7552	/***************** Bit definition for TIM_CCR1 register *****************/
bogdanm	0:9b334a45a8ff	7553	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
bogdanm	0:9b334a45a8ff	7554
bogdanm	0:9b334a45a8ff	7555	/***************** Bit definition for TIM_CCR2 register *****************/
bogdanm	0:9b334a45a8ff	7556	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
bogdanm	0:9b334a45a8ff	7557
bogdanm	0:9b334a45a8ff	7558	/***************** Bit definition for TIM_CCR3 register *****************/
bogdanm	0:9b334a45a8ff	7559	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
bogdanm	0:9b334a45a8ff	7560
bogdanm	0:9b334a45a8ff	7561	/***************** Bit definition for TIM_CCR4 register *****************/
bogdanm	0:9b334a45a8ff	7562	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
bogdanm	0:9b334a45a8ff	7563
bogdanm	0:9b334a45a8ff	7564	/***************** Bit definition for TIM_CCR5 register *****************/
bogdanm	0:9b334a45a8ff	7565	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
bogdanm	0:9b334a45a8ff	7566	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
bogdanm	0:9b334a45a8ff	7567	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
bogdanm	0:9b334a45a8ff	7568	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
bogdanm	0:9b334a45a8ff	7569
bogdanm	0:9b334a45a8ff	7570	/***************** Bit definition for TIM_CCR6 register *****************/
bogdanm	0:9b334a45a8ff	7571	#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /!<Capture/Compare 6 Value /
bogdanm	0:9b334a45a8ff	7572
bogdanm	0:9b334a45a8ff	7573	/***************** Bit definition for TIM_BDTR register *****************/
bogdanm	0:9b334a45a8ff	7574	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	0:9b334a45a8ff	7575	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7576	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7577	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7578	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7579	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7580	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	7581	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	7582	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	7583
bogdanm	0:9b334a45a8ff	7584	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	0:9b334a45a8ff	7585	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7586	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7587
bogdanm	0:9b334a45a8ff	7588	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
bogdanm	0:9b334a45a8ff	7589	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
bogdanm	0:9b334a45a8ff	7590	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable for Break 1 /
bogdanm	0:9b334a45a8ff	7591	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity for Break 1 /
bogdanm	0:9b334a45a8ff	7592	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
bogdanm	0:9b334a45a8ff	7593	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
bogdanm	0:9b334a45a8ff	7594
bogdanm	0:9b334a45a8ff	7595	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break 1 /
bogdanm	0:9b334a45a8ff	7596	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break 2 /
bogdanm	0:9b334a45a8ff	7597
bogdanm	0:9b334a45a8ff	7598	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break 2 /
bogdanm	0:9b334a45a8ff	7599	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break 2 /
bogdanm	0:9b334a45a8ff	7600
bogdanm	0:9b334a45a8ff	7601	/***************** Bit definition for TIM_DCR register ******************/
bogdanm	0:9b334a45a8ff	7602	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	0:9b334a45a8ff	7603	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7604	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7605	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7606	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7607	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7608
bogdanm	0:9b334a45a8ff	7609	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	0:9b334a45a8ff	7610	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7611	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7612	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7613	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7614	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7615
bogdanm	0:9b334a45a8ff	7616	/***************** Bit definition for TIM_DMAR register *****************/
bogdanm	0:9b334a45a8ff	7617	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
bogdanm	0:9b334a45a8ff	7618
bogdanm	0:9b334a45a8ff	7619	/***************** Bit definition for TIM1_OR1 register *****************/
bogdanm	0:9b334a45a8ff	7620	#define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003) /!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) /
bogdanm	0:9b334a45a8ff	7621	#define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7622	#define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7623
bogdanm	0:9b334a45a8ff	7624	#define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) /
bogdanm	0:9b334a45a8ff	7625	#define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7626	#define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7627
bogdanm	0:9b334a45a8ff	7628	#define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010) /!<TIM1 Input Capture 1 remap /
bogdanm	0:9b334a45a8ff	7629
bogdanm	0:9b334a45a8ff	7630	/***************** Bit definition for TIM1_OR2 register *****************/
bogdanm	0:9b334a45a8ff	7631	#define TIM1_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
bogdanm	0:9b334a45a8ff	7632	#define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
bogdanm	0:9b334a45a8ff	7633	#define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
bogdanm	0:9b334a45a8ff	7634	#define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[0] enable /
bogdanm	0:9b334a45a8ff	7635	#define TIM1_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
bogdanm	0:9b334a45a8ff	7636	#define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7637	#define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7638
bogdanm	0:9b334a45a8ff	7639	#define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM1 ETR source selection) /
bogdanm	0:9b334a45a8ff	7640	#define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7641	#define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7642	#define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7643
bogdanm	0:9b334a45a8ff	7644	/***************** Bit definition for TIM1_OR3 register *****************/
bogdanm	0:9b334a45a8ff	7645	#define TIM1_OR3_BK2INE ((uint32_t)0x00000001) /!<BRK2 BKIN2 input enable /
bogdanm	0:9b334a45a8ff	7646	#define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002) /!<BRK2 COMP1 enable /
bogdanm	0:9b334a45a8ff	7647	#define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004) /!<BRK2 COMP2 enable /
bogdanm	0:9b334a45a8ff	7648	#define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100) /!<BRK2 DFSDM_BREAK[1] enable /
bogdanm	0:9b334a45a8ff	7649	#define TIM1_OR3_BK2INP ((uint32_t)0x00000200) /!<BRK2 BKIN2 input polarity /
bogdanm	0:9b334a45a8ff	7650	#define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400) /!<BRK2 COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7651	#define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800) /!<BRK2 COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7652
bogdanm	0:9b334a45a8ff	7653	/***************** Bit definition for TIM8_OR1 register *****************/
bogdanm	0:9b334a45a8ff	7654	#define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003) /!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) /
bogdanm	0:9b334a45a8ff	7655	#define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7656	#define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7657
bogdanm	0:9b334a45a8ff	7658	#define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) /
bogdanm	0:9b334a45a8ff	7659	#define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7660	#define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7661
bogdanm	0:9b334a45a8ff	7662	#define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010) /!<TIM8 Input Capture 1 remap /
bogdanm	0:9b334a45a8ff	7663
bogdanm	0:9b334a45a8ff	7664	/***************** Bit definition for TIM8_OR2 register *****************/
bogdanm	0:9b334a45a8ff	7665	#define TIM8_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
bogdanm	0:9b334a45a8ff	7666	#define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
bogdanm	0:9b334a45a8ff	7667	#define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
bogdanm	0:9b334a45a8ff	7668	#define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[2] enable /
bogdanm	0:9b334a45a8ff	7669	#define TIM8_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
bogdanm	0:9b334a45a8ff	7670	#define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7671	#define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7672
bogdanm	0:9b334a45a8ff	7673	#define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM8 ETR source selection) /
bogdanm	0:9b334a45a8ff	7674	#define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7675	#define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7676	#define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7677
bogdanm	0:9b334a45a8ff	7678	/***************** Bit definition for TIM8_OR3 register *****************/
bogdanm	0:9b334a45a8ff	7679	#define TIM8_OR3_BK2INE ((uint32_t)0x00000001) /!<BRK2 BKIN2 input enable /
bogdanm	0:9b334a45a8ff	7680	#define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002) /!<BRK2 COMP1 enable /
bogdanm	0:9b334a45a8ff	7681	#define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004) /!<BRK2 COMP2 enable /
bogdanm	0:9b334a45a8ff	7682	#define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100) /!<BRK2 DFSDM_BREAK[3] enable /
bogdanm	0:9b334a45a8ff	7683	#define TIM8_OR3_BK2INP ((uint32_t)0x00000200) /!<BRK2 BKIN2 input polarity /
bogdanm	0:9b334a45a8ff	7684	#define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400) /!<BRK2 COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7685	#define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800) /!<BRK2 COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7686
bogdanm	0:9b334a45a8ff	7687	/***************** Bit definition for TIM2_OR1 register *****************/
bogdanm	0:9b334a45a8ff	7688	#define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001) /!<TIM2 Internal trigger 1 remap /
bogdanm	0:9b334a45a8ff	7689	#define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002) /!<TIM2 External trigger 1 remap /
bogdanm	0:9b334a45a8ff	7690
bogdanm	0:9b334a45a8ff	7691	#define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000C) /!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) /
bogdanm	0:9b334a45a8ff	7692	#define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7693	#define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7694
bogdanm	0:9b334a45a8ff	7695	/***************** Bit definition for TIM2_OR2 register *****************/
bogdanm	0:9b334a45a8ff	7696	#define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM2 ETR source selection) /
bogdanm	0:9b334a45a8ff	7697	#define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7698	#define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7699	#define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7700
bogdanm	0:9b334a45a8ff	7701	/***************** Bit definition for TIM3_OR1 register *****************/
bogdanm	0:9b334a45a8ff	7702	#define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) /
bogdanm	0:9b334a45a8ff	7703	#define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7704	#define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7705
bogdanm	0:9b334a45a8ff	7706	/***************** Bit definition for TIM3_OR2 register *****************/
bogdanm	0:9b334a45a8ff	7707	#define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM3 ETR source selection) /
bogdanm	0:9b334a45a8ff	7708	#define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7709	#define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7710	#define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7711
bogdanm	0:9b334a45a8ff	7712	/***************** Bit definition for TIM15_OR1 register ****************/
bogdanm	0:9b334a45a8ff	7713	#define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001) /!<TIM15 Input Capture 1 remap /
bogdanm	0:9b334a45a8ff	7714
bogdanm	0:9b334a45a8ff	7715	#define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006) /!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) /
bogdanm	0:9b334a45a8ff	7716	#define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7717	#define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7718
bogdanm	0:9b334a45a8ff	7719	/***************** Bit definition for TIM15_OR2 register ****************/
bogdanm	0:9b334a45a8ff	7720	#define TIM15_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
bogdanm	0:9b334a45a8ff	7721	#define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
bogdanm	0:9b334a45a8ff	7722	#define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
bogdanm	0:9b334a45a8ff	7723	#define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[0] enable /
bogdanm	0:9b334a45a8ff	7724	#define TIM15_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
bogdanm	0:9b334a45a8ff	7725	#define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7726	#define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7727
bogdanm	0:9b334a45a8ff	7728	/***************** Bit definition for TIM16_OR1 register ****************/
bogdanm	0:9b334a45a8ff	7729	#define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) /
bogdanm	0:9b334a45a8ff	7730	#define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7731	#define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7732
bogdanm	0:9b334a45a8ff	7733	/***************** Bit definition for TIM16_OR2 register ****************/
bogdanm	0:9b334a45a8ff	7734	#define TIM16_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
bogdanm	0:9b334a45a8ff	7735	#define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
bogdanm	0:9b334a45a8ff	7736	#define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
bogdanm	0:9b334a45a8ff	7737	#define TIM16_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
bogdanm	0:9b334a45a8ff	7738	#define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7739	#define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7740
bogdanm	0:9b334a45a8ff	7741	/***************** Bit definition for TIM17_OR1 register ****************/
bogdanm	0:9b334a45a8ff	7742	#define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) /
bogdanm	0:9b334a45a8ff	7743	#define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7744	#define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7745
bogdanm	0:9b334a45a8ff	7746	/***************** Bit definition for TIM17_OR2 register ****************/
bogdanm	0:9b334a45a8ff	7747	#define TIM17_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
bogdanm	0:9b334a45a8ff	7748	#define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
bogdanm	0:9b334a45a8ff	7749	#define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
bogdanm	0:9b334a45a8ff	7750	#define TIM17_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
bogdanm	0:9b334a45a8ff	7751	#define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
bogdanm	0:9b334a45a8ff	7752	#define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
bogdanm	0:9b334a45a8ff	7753
bogdanm	0:9b334a45a8ff	7754	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7755	/* */
bogdanm	0:9b334a45a8ff	7756	/* Low Power Timer (LPTTIM) */
bogdanm	0:9b334a45a8ff	7757	/* */
bogdanm	0:9b334a45a8ff	7758	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7759	/**************** Bit definition for LPTIM_ISR register *****************/
bogdanm	0:9b334a45a8ff	7760	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /!< Compare match /
bogdanm	0:9b334a45a8ff	7761	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /!< Autoreload match /
bogdanm	0:9b334a45a8ff	7762	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /!< External trigger edge event /
bogdanm	0:9b334a45a8ff	7763	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /!< Compare register update OK /
bogdanm	0:9b334a45a8ff	7764	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /!< Autoreload register update OK /
bogdanm	0:9b334a45a8ff	7765	#define LPTIM_ISR_UP ((uint32_t)0x00000020) /!< Counter direction change down to up /
bogdanm	0:9b334a45a8ff	7766	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /!< Counter direction change up to down /
bogdanm	0:9b334a45a8ff	7767
bogdanm	0:9b334a45a8ff	7768	/**************** Bit definition for LPTIM_ICR register *****************/
bogdanm	0:9b334a45a8ff	7769	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /!< Compare match Clear Flag /
bogdanm	0:9b334a45a8ff	7770	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /!< Autoreload match Clear Flag /
bogdanm	0:9b334a45a8ff	7771	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /!< External trigger edge event Clear Flag /
bogdanm	0:9b334a45a8ff	7772	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /!< Compare register update OK Clear Flag /
bogdanm	0:9b334a45a8ff	7773	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /!< Autoreload register update OK Clear Flag /
bogdanm	0:9b334a45a8ff	7774	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /!< Counter direction change down to up Clear Flag /
bogdanm	0:9b334a45a8ff	7775	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /!< Counter direction change up to down Clear Flag /
bogdanm	0:9b334a45a8ff	7776
bogdanm	0:9b334a45a8ff	7777	/**************** Bit definition for LPTIM_IER register ******************/
bogdanm	0:9b334a45a8ff	7778	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /!< Compare match Interrupt Enable /
bogdanm	0:9b334a45a8ff	7779	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /!< Autoreload match Interrupt Enable /
bogdanm	0:9b334a45a8ff	7780	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /!< External trigger edge event Interrupt Enable /
bogdanm	0:9b334a45a8ff	7781	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /!< Compare register update OK Interrupt Enable /
bogdanm	0:9b334a45a8ff	7782	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /!< Autoreload register update OK Interrupt Enable /
bogdanm	0:9b334a45a8ff	7783	#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /!< Counter direction change down to up Interrupt Enable /
bogdanm	0:9b334a45a8ff	7784	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /!< Counter direction change up to down Interrupt Enable /
bogdanm	0:9b334a45a8ff	7785
bogdanm	0:9b334a45a8ff	7786	/**************** Bit definition for LPTIM_CFGR register *****************/
bogdanm	0:9b334a45a8ff	7787	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /!< Clock selector /
bogdanm	0:9b334a45a8ff	7788
bogdanm	0:9b334a45a8ff	7789	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /!< CKPOL[1:0] bits (Clock polarity) /
bogdanm	0:9b334a45a8ff	7790	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7791	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7792
bogdanm	0:9b334a45a8ff	7793	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
bogdanm	0:9b334a45a8ff	7794	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7795	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7796
bogdanm	0:9b334a45a8ff	7797	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
bogdanm	0:9b334a45a8ff	7798	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7799	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7800
bogdanm	0:9b334a45a8ff	7801	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /!< PRESC[2:0] bits (Clock prescaler) /
bogdanm	0:9b334a45a8ff	7802	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7803	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7804	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	7805
bogdanm	0:9b334a45a8ff	7806	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /!< TRIGSEL[2:0]] bits (Trigger selector) /
bogdanm	0:9b334a45a8ff	7807	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7808	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7809	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	7810
bogdanm	0:9b334a45a8ff	7811	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
bogdanm	0:9b334a45a8ff	7812	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7813	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7814
bogdanm	0:9b334a45a8ff	7815	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /!< Timout enable /
bogdanm	0:9b334a45a8ff	7816	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /!< Waveform shape /
bogdanm	0:9b334a45a8ff	7817	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /!< Waveform shape polarity /
bogdanm	0:9b334a45a8ff	7818	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /!< Reg update mode /
bogdanm	0:9b334a45a8ff	7819	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /!< Counter mode enable /
bogdanm	0:9b334a45a8ff	7820	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /!< Encoder mode enable /
bogdanm	0:9b334a45a8ff	7821
bogdanm	0:9b334a45a8ff	7822	/**************** Bit definition for LPTIM_CR register ******************/
bogdanm	0:9b334a45a8ff	7823	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /!< LPTIMer enable /
bogdanm	0:9b334a45a8ff	7824	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /!< Timer start in single mode /
bogdanm	0:9b334a45a8ff	7825	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /!< Timer start in continuous mode /
bogdanm	0:9b334a45a8ff	7826
bogdanm	0:9b334a45a8ff	7827	/**************** Bit definition for LPTIM_CMP register *****************/
bogdanm	0:9b334a45a8ff	7828	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /!< Compare register /
bogdanm	0:9b334a45a8ff	7829
bogdanm	0:9b334a45a8ff	7830	/**************** Bit definition for LPTIM_ARR register *****************/
bogdanm	0:9b334a45a8ff	7831	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /!< Auto reload register /
bogdanm	0:9b334a45a8ff	7832
bogdanm	0:9b334a45a8ff	7833	/**************** Bit definition for LPTIM_CNT register *****************/
bogdanm	0:9b334a45a8ff	7834	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /!< Counter register /
bogdanm	0:9b334a45a8ff	7835
bogdanm	0:9b334a45a8ff	7836	/**************** Bit definition for LPTIM_OR register *****************/
bogdanm	0:9b334a45a8ff	7837	#define LPTIM_OR_OR ((uint32_t)0x00000003) /!< LPTIMER[1:0] bits (Remap selection) /
bogdanm	0:9b334a45a8ff	7838	#define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7839	#define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7840
bogdanm	0:9b334a45a8ff	7841	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7842	/* */
bogdanm	0:9b334a45a8ff	7843	/* Analog Comparators (COMP) */
bogdanm	0:9b334a45a8ff	7844	/* */
bogdanm	0:9b334a45a8ff	7845	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7846	/******************** Bit definition for COMPx_CSR register *************/
bogdanm	0:9b334a45a8ff	7847	#define COMP_CSR_EN ((uint32_t)0x00000001) /!< COMPx enable /
bogdanm	0:9b334a45a8ff	7848
bogdanm	0:9b334a45a8ff	7849	#define COMP_CSR_PWRMODE ((uint32_t)0x0000000C) /!< COMPx power mode /
bogdanm	0:9b334a45a8ff	7850	#define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004) /!< COMPx power mode bit 0 /
bogdanm	0:9b334a45a8ff	7851	#define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008) /!< COMPx power mode bit 1 /
bogdanm	0:9b334a45a8ff	7852
bogdanm	0:9b334a45a8ff	7853	#define COMP_CSR_INMSEL ((uint32_t)0x00000070) /!< COMPx inverting input selection /
bogdanm	0:9b334a45a8ff	7854	#define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010) /!< COMPx inverting input selection bit 0 /
bogdanm	0:9b334a45a8ff	7855	#define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020) /!< COMPx inverting input selection bit 1 /
bogdanm	0:9b334a45a8ff	7856	#define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040) /!< COMPx inverting input selection bit 2 /
bogdanm	0:9b334a45a8ff	7857
bogdanm	0:9b334a45a8ff	7858	#define COMP_CSR_INPSEL ((uint32_t)0x00000080) /!< COMPx non inverting input selection /
bogdanm	0:9b334a45a8ff	7859	#define COMP_CSR_WINMODE ((uint32_t)0x00000200) /!< COMPx window mode /
bogdanm	0:9b334a45a8ff	7860	#define COMP_CSR_POLARITY ((uint32_t)0x00008000) /!< COMPx output polarity /
bogdanm	0:9b334a45a8ff	7861
bogdanm	0:9b334a45a8ff	7862	#define COMP_CSR_HYST ((uint32_t)0x00030000) /!< COMPx hysteresis /
bogdanm	0:9b334a45a8ff	7863	#define COMP_CSR_HYST_0 ((uint32_t)0x00010000) /!< COMPx hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	7864	#define COMP_CSR_HYST_1 ((uint32_t)0x00020000) /!< COMPx hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	7865
bogdanm	0:9b334a45a8ff	7866	#define COMP_CSR_BLANKING ((uint32_t)0x001C0000) /!< COMPx blanking source /
bogdanm	0:9b334a45a8ff	7867	#define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000) /!< COMPx blanking source bit 0 /
bogdanm	0:9b334a45a8ff	7868	#define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000) /!< COMPx blanking source bit 1 /
bogdanm	0:9b334a45a8ff	7869	#define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000) /!< COMPx blanking source bit 2 /
bogdanm	0:9b334a45a8ff	7870
bogdanm	0:9b334a45a8ff	7871	#define COMP_CSR_BRGEN ((uint32_t)0x00400000) /!< COMPx voltage scaler enable /
bogdanm	0:9b334a45a8ff	7872	#define COMP_CSR_SCALEN ((uint32_t)0x00800000) /!< COMPx scaler bridge enable /
bogdanm	0:9b334a45a8ff	7873	#define COMP_CSR_VALUE ((uint32_t)0x40000000) /!< COMPx value /
bogdanm	0:9b334a45a8ff	7874	#define COMP_CSR_LOCK ((uint32_t)0x80000000) /!< COMPx lock /
bogdanm	0:9b334a45a8ff	7875
bogdanm	0:9b334a45a8ff	7876	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7877	/* */
bogdanm	0:9b334a45a8ff	7878	/* Operational Amplifier (OPAMP) */
bogdanm	0:9b334a45a8ff	7879	/* */
bogdanm	0:9b334a45a8ff	7880	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7881	/******************* Bit definition for OPAMPx_CSR register *************/
bogdanm	0:9b334a45a8ff	7882	#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /!< OPAMP enable /
bogdanm	0:9b334a45a8ff	7883	#define OPAMP_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier Low Power Mode /
bogdanm	0:9b334a45a8ff	7884
bogdanm	0:9b334a45a8ff	7885	#define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier PGA mode /
bogdanm	0:9b334a45a8ff	7886	#define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7887	#define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7888
bogdanm	0:9b334a45a8ff	7889	#define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030) /!< Operational amplifier Programmable amplifier gain value /
bogdanm	0:9b334a45a8ff	7890	#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7891	#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7892
bogdanm	0:9b334a45a8ff	7893	#define OPAMP_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	7894	#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7895	#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7896
bogdanm	0:9b334a45a8ff	7897	#define OPAMP_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
bogdanm	0:9b334a45a8ff	7898	#define OPAMP_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	7899	#define OPAMP_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	7900	#define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	7901	#define OPAMP_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier1 calibration output /
bogdanm	0:9b334a45a8ff	7902
bogdanm	0:9b334a45a8ff	7903	/******************* Bit definition for OPAMP1_CSR register *************/
bogdanm	0:9b334a45a8ff	7904	#define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001) /!< Operational amplifier1 Enable /
bogdanm	0:9b334a45a8ff	7905	#define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier1 Low Power Mode /
bogdanm	0:9b334a45a8ff	7906
bogdanm	0:9b334a45a8ff	7907	#define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier1 PGA mode /
bogdanm	0:9b334a45a8ff	7908	#define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7909	#define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7910
bogdanm	0:9b334a45a8ff	7911	#define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030) /!< Operational amplifier1 Programmable amplifier gain value /
bogdanm	0:9b334a45a8ff	7912	#define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7913	#define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7914
bogdanm	0:9b334a45a8ff	7915	#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	7916	#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7917	#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7918
bogdanm	0:9b334a45a8ff	7919	#define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
bogdanm	0:9b334a45a8ff	7920	#define OPAMP1_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	7921	#define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	7922	#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	7923	#define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier1 calibration output /
bogdanm	0:9b334a45a8ff	7924	#define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000) /!< Operational amplifiers power supply range for stability /
bogdanm	0:9b334a45a8ff	7925
bogdanm	0:9b334a45a8ff	7926	/******************* Bit definition for OPAMP2_CSR register *************/
bogdanm	0:9b334a45a8ff	7927	#define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001) /!< Operational amplifier2 Enable /
bogdanm	0:9b334a45a8ff	7928	#define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier2 Low Power Mode /
bogdanm	0:9b334a45a8ff	7929
bogdanm	0:9b334a45a8ff	7930	#define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier2 PGA mode /
bogdanm	0:9b334a45a8ff	7931	#define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7932	#define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7933
bogdanm	0:9b334a45a8ff	7934	#define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030) /!< Operational amplifier2 Programmable amplifier gain value /
bogdanm	0:9b334a45a8ff	7935	#define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7936	#define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7937
bogdanm	0:9b334a45a8ff	7938	#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	7939	#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7940	#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7941
bogdanm	0:9b334a45a8ff	7942	#define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
bogdanm	0:9b334a45a8ff	7943	#define OPAMP2_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	7944	#define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	7945	#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	7946	#define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier2 calibration output /
bogdanm	0:9b334a45a8ff	7947
bogdanm	0:9b334a45a8ff	7948	/***************** Bit definition for OPAMP_OTR register ****************/
bogdanm	0:9b334a45a8ff	7949	#define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7950	#define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7951
bogdanm	0:9b334a45a8ff	7952	/***************** Bit definition for OPAMP1_OTR register ****************/
bogdanm	0:9b334a45a8ff	7953	#define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7954	#define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7955
bogdanm	0:9b334a45a8ff	7956	/***************** Bit definition for OPAMP2_OTR register ****************/
bogdanm	0:9b334a45a8ff	7957	#define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7958	#define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7959
bogdanm	0:9b334a45a8ff	7960	/***************** Bit definition for OPAMP_LPOTR register **************/
bogdanm	0:9b334a45a8ff	7961	#define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7962	#define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7963
bogdanm	0:9b334a45a8ff	7964	/***************** Bit definition for OPAMP1_LPOTR register **************/
bogdanm	0:9b334a45a8ff	7965	#define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7966	#define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7967
bogdanm	0:9b334a45a8ff	7968	/***************** Bit definition for OPAMP2_LPOTR register **************/
bogdanm	0:9b334a45a8ff	7969	#define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
bogdanm	0:9b334a45a8ff	7970	#define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
bogdanm	0:9b334a45a8ff	7971
bogdanm	0:9b334a45a8ff	7972	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7973	/* */
bogdanm	0:9b334a45a8ff	7974	/* Touch Sensing Controller (TSC) */
bogdanm	0:9b334a45a8ff	7975	/* */
bogdanm	0:9b334a45a8ff	7976	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7977	/***************** Bit definition for TSC_CR register *******************/
bogdanm	0:9b334a45a8ff	7978	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
bogdanm	0:9b334a45a8ff	7979	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
bogdanm	0:9b334a45a8ff	7980	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
bogdanm	0:9b334a45a8ff	7981	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
bogdanm	0:9b334a45a8ff	7982	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
bogdanm	0:9b334a45a8ff	7983
bogdanm	0:9b334a45a8ff	7984	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
bogdanm	0:9b334a45a8ff	7985	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7986	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7987	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7988
bogdanm	0:9b334a45a8ff	7989	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
bogdanm	0:9b334a45a8ff	7990	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7991	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7992	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7993
bogdanm	0:9b334a45a8ff	7994	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
bogdanm	0:9b334a45a8ff	7995	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
bogdanm	0:9b334a45a8ff	7996
bogdanm	0:9b334a45a8ff	7997	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
bogdanm	0:9b334a45a8ff	7998	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7999	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8000	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8001	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8002	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8003	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8004	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8005
bogdanm	0:9b334a45a8ff	8006	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
bogdanm	0:9b334a45a8ff	8007	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8008	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8009	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8010	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8011
bogdanm	0:9b334a45a8ff	8012	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
bogdanm	0:9b334a45a8ff	8013	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8014	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8015	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8016	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8017
bogdanm	0:9b334a45a8ff	8018	/***************** Bit definition for TSC_IER register ******************/
bogdanm	0:9b334a45a8ff	8019	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
bogdanm	0:9b334a45a8ff	8020	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
bogdanm	0:9b334a45a8ff	8021
bogdanm	0:9b334a45a8ff	8022	/***************** Bit definition for TSC_ICR register ******************/
bogdanm	0:9b334a45a8ff	8023	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
bogdanm	0:9b334a45a8ff	8024	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
bogdanm	0:9b334a45a8ff	8025
bogdanm	0:9b334a45a8ff	8026	/***************** Bit definition for TSC_ISR register ******************/
bogdanm	0:9b334a45a8ff	8027	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
bogdanm	0:9b334a45a8ff	8028	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
bogdanm	0:9b334a45a8ff	8029
bogdanm	0:9b334a45a8ff	8030	/***************** Bit definition for TSC_IOHCR register ****************/
bogdanm	0:9b334a45a8ff	8031	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8032	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8033	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8034	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8035	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8036	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8037	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8038	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8039	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8040	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8041	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8042	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8043	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8044	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8045	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8046	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8047	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8048	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8049	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8050	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8051	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8052	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8053	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8054	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8055	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8056	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8057	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8058	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8059	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8060	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8061	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8062	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
bogdanm	0:9b334a45a8ff	8063
bogdanm	0:9b334a45a8ff	8064	/***************** Bit definition for TSC_IOASCR register ***************/
bogdanm	0:9b334a45a8ff	8065	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8066	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8067	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8068	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8069	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8070	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8071	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8072	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8073	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8074	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8075	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8076	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8077	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8078	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8079	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8080	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8081	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8082	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8083	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8084	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8085	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8086	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8087	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8088	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8089	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8090	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8091	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8092	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8093	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
bogdanm	0:9b334a45a8ff	8094	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
bogdanm	0:9b334a45a8ff	8095	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
bogdanm	0:9b334a45a8ff	8096	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
bogdanm	0:9b334a45a8ff	8097
bogdanm	0:9b334a45a8ff	8098	/***************** Bit definition for TSC_IOSCR register ****************/
bogdanm	0:9b334a45a8ff	8099	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8100	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8101	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8102	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8103	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8104	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8105	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8106	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8107	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8108	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8109	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8110	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8111	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8112	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8113	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8114	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8115	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8116	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8117	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8118	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8119	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8120	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8121	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8122	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8123	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8124	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8125	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8126	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8127	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
bogdanm	0:9b334a45a8ff	8128	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
bogdanm	0:9b334a45a8ff	8129	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
bogdanm	0:9b334a45a8ff	8130	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
bogdanm	0:9b334a45a8ff	8131
bogdanm	0:9b334a45a8ff	8132	/***************** Bit definition for TSC_IOCCR register ****************/
bogdanm	0:9b334a45a8ff	8133	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8134	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8135	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8136	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8137	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8138	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8139	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8140	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8141	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8142	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8143	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8144	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8145	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8146	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8147	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8148	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8149	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8150	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8151	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8152	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8153	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8154	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8155	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8156	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8157	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8158	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8159	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8160	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8161	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
bogdanm	0:9b334a45a8ff	8162	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
bogdanm	0:9b334a45a8ff	8163	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
bogdanm	0:9b334a45a8ff	8164	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
bogdanm	0:9b334a45a8ff	8165
bogdanm	0:9b334a45a8ff	8166	/***************** Bit definition for TSC_IOGCSR register ***************/
bogdanm	0:9b334a45a8ff	8167	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
bogdanm	0:9b334a45a8ff	8168	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
bogdanm	0:9b334a45a8ff	8169	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
bogdanm	0:9b334a45a8ff	8170	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
bogdanm	0:9b334a45a8ff	8171	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
bogdanm	0:9b334a45a8ff	8172	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
bogdanm	0:9b334a45a8ff	8173	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
bogdanm	0:9b334a45a8ff	8174	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
bogdanm	0:9b334a45a8ff	8175	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
bogdanm	0:9b334a45a8ff	8176	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
bogdanm	0:9b334a45a8ff	8177	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
bogdanm	0:9b334a45a8ff	8178	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
bogdanm	0:9b334a45a8ff	8179	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
bogdanm	0:9b334a45a8ff	8180	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
bogdanm	0:9b334a45a8ff	8181	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
bogdanm	0:9b334a45a8ff	8182	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
bogdanm	0:9b334a45a8ff	8183
bogdanm	0:9b334a45a8ff	8184	/***************** Bit definition for TSC_IOGXCR register ***************/
bogdanm	0:9b334a45a8ff	8185	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
bogdanm	0:9b334a45a8ff	8186
bogdanm	0:9b334a45a8ff	8187	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8188	/* */
bogdanm	0:9b334a45a8ff	8189	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm	0:9b334a45a8ff	8190	/* */
bogdanm	0:9b334a45a8ff	8191	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8192	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	0:9b334a45a8ff	8193	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
bogdanm	0:9b334a45a8ff	8194	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
bogdanm	0:9b334a45a8ff	8195	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
bogdanm	0:9b334a45a8ff	8196	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
bogdanm	0:9b334a45a8ff	8197	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
bogdanm	0:9b334a45a8ff	8198	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
bogdanm	0:9b334a45a8ff	8199	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
bogdanm	0:9b334a45a8ff	8200	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
bogdanm	0:9b334a45a8ff	8201	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
bogdanm	0:9b334a45a8ff	8202	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
bogdanm	0:9b334a45a8ff	8203	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
bogdanm	0:9b334a45a8ff	8204	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
bogdanm	0:9b334a45a8ff	8205	#define USART_CR1_M ((uint32_t)0x10001000) /!< Word length /
bogdanm	0:9b334a45a8ff	8206	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length - Bit 0 /
bogdanm	0:9b334a45a8ff	8207	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
bogdanm	0:9b334a45a8ff	8208	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
bogdanm	0:9b334a45a8ff	8209	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
bogdanm	0:9b334a45a8ff	8210	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
bogdanm	0:9b334a45a8ff	8211	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8212	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8213	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	8214	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	8215	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	8216	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
bogdanm	0:9b334a45a8ff	8217	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8218	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8219	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	8220	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	8221	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	8222	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
bogdanm	0:9b334a45a8ff	8223	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
bogdanm	0:9b334a45a8ff	8224	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length - Bit 1 /
bogdanm	0:9b334a45a8ff	8225
bogdanm	0:9b334a45a8ff	8226	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	0:9b334a45a8ff	8227	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
bogdanm	0:9b334a45a8ff	8228	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
bogdanm	0:9b334a45a8ff	8229	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
bogdanm	0:9b334a45a8ff	8230	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
bogdanm	0:9b334a45a8ff	8231	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	8232	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	8233	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
bogdanm	0:9b334a45a8ff	8234	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
bogdanm	0:9b334a45a8ff	8235	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8236	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8237	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
bogdanm	0:9b334a45a8ff	8238	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
bogdanm	0:9b334a45a8ff	8239	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
bogdanm	0:9b334a45a8ff	8240	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
bogdanm	0:9b334a45a8ff	8241	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
bogdanm	0:9b334a45a8ff	8242	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
bogdanm	0:9b334a45a8ff	8243	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
bogdanm	0:9b334a45a8ff	8244	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
bogdanm	0:9b334a45a8ff	8245	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8246	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8247	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
bogdanm	0:9b334a45a8ff	8248	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
bogdanm	0:9b334a45a8ff	8249
bogdanm	0:9b334a45a8ff	8250	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	0:9b334a45a8ff	8251	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	8252	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
bogdanm	0:9b334a45a8ff	8253	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
bogdanm	0:9b334a45a8ff	8254	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
bogdanm	0:9b334a45a8ff	8255	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
bogdanm	0:9b334a45a8ff	8256	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
bogdanm	0:9b334a45a8ff	8257	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
bogdanm	0:9b334a45a8ff	8258	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
bogdanm	0:9b334a45a8ff	8259	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
bogdanm	0:9b334a45a8ff	8260	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
bogdanm	0:9b334a45a8ff	8261	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
bogdanm	0:9b334a45a8ff	8262	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
bogdanm	0:9b334a45a8ff	8263	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
bogdanm	0:9b334a45a8ff	8264	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
bogdanm	0:9b334a45a8ff	8265	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
bogdanm	0:9b334a45a8ff	8266	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
bogdanm	0:9b334a45a8ff	8267	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
bogdanm	0:9b334a45a8ff	8268	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8269	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8270	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	8271	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
bogdanm	0:9b334a45a8ff	8272	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	8273	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	8274	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
bogdanm	0:9b334a45a8ff	8275
bogdanm	0:9b334a45a8ff	8276	/**************** Bit definition for USART_BRR register *****************/
bogdanm	0:9b334a45a8ff	8277	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
bogdanm	0:9b334a45a8ff	8278	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
bogdanm	0:9b334a45a8ff	8279
bogdanm	0:9b334a45a8ff	8280	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	0:9b334a45a8ff	8281	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
bogdanm	0:9b334a45a8ff	8282	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
bogdanm	0:9b334a45a8ff	8283
bogdanm	0:9b334a45a8ff	8284
bogdanm	0:9b334a45a8ff	8285	/***************** Bit definition for USART_RTOR register ***************/
bogdanm	0:9b334a45a8ff	8286	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
bogdanm	0:9b334a45a8ff	8287	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
bogdanm	0:9b334a45a8ff	8288
bogdanm	0:9b334a45a8ff	8289	/***************** Bit definition for USART_RQR register ****************/
bogdanm	0:9b334a45a8ff	8290	#define USART_RQR_ABRRQ ((uint16_t)0x0001) /!< Auto-Baud Rate Request /
bogdanm	0:9b334a45a8ff	8291	#define USART_RQR_SBKRQ ((uint16_t)0x0002) /!< Send Break Request /
bogdanm	0:9b334a45a8ff	8292	#define USART_RQR_MMRQ ((uint16_t)0x0004) /!< Mute Mode Request /
bogdanm	0:9b334a45a8ff	8293	#define USART_RQR_RXFRQ ((uint16_t)0x0008) /!< Receive Data flush Request /
bogdanm	0:9b334a45a8ff	8294	#define USART_RQR_TXFRQ ((uint16_t)0x0010) /!< Transmit data flush Request /
bogdanm	0:9b334a45a8ff	8295
bogdanm	0:9b334a45a8ff	8296	/***************** Bit definition for USART_ISR register ****************/
bogdanm	0:9b334a45a8ff	8297	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
bogdanm	0:9b334a45a8ff	8298	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
bogdanm	0:9b334a45a8ff	8299	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
bogdanm	0:9b334a45a8ff	8300	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
bogdanm	0:9b334a45a8ff	8301	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
bogdanm	0:9b334a45a8ff	8302	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
bogdanm	0:9b334a45a8ff	8303	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
bogdanm	0:9b334a45a8ff	8304	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
bogdanm	0:9b334a45a8ff	8305	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
bogdanm	0:9b334a45a8ff	8306	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
bogdanm	0:9b334a45a8ff	8307	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
bogdanm	0:9b334a45a8ff	8308	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
bogdanm	0:9b334a45a8ff	8309	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
bogdanm	0:9b334a45a8ff	8310	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
bogdanm	0:9b334a45a8ff	8311	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
bogdanm	0:9b334a45a8ff	8312	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
bogdanm	0:9b334a45a8ff	8313	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
bogdanm	0:9b334a45a8ff	8314	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
bogdanm	0:9b334a45a8ff	8315	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
bogdanm	0:9b334a45a8ff	8316	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
bogdanm	0:9b334a45a8ff	8317	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	8318	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	8319
bogdanm	0:9b334a45a8ff	8320	/***************** Bit definition for USART_ICR register ****************/
bogdanm	0:9b334a45a8ff	8321	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
bogdanm	0:9b334a45a8ff	8322	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
bogdanm	0:9b334a45a8ff	8323	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
bogdanm	0:9b334a45a8ff	8324	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
bogdanm	0:9b334a45a8ff	8325	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
bogdanm	0:9b334a45a8ff	8326	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
bogdanm	0:9b334a45a8ff	8327	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
bogdanm	0:9b334a45a8ff	8328	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
bogdanm	0:9b334a45a8ff	8329	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
bogdanm	0:9b334a45a8ff	8330	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
bogdanm	0:9b334a45a8ff	8331	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
bogdanm	0:9b334a45a8ff	8332	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
bogdanm	0:9b334a45a8ff	8333
bogdanm	0:9b334a45a8ff	8334	/***************** Bit definition for USART_RDR register ****************/
bogdanm	0:9b334a45a8ff	8335	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
bogdanm	0:9b334a45a8ff	8336
bogdanm	0:9b334a45a8ff	8337	/***************** Bit definition for USART_TDR register ****************/
bogdanm	0:9b334a45a8ff	8338	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
bogdanm	0:9b334a45a8ff	8339
bogdanm	0:9b334a45a8ff	8340	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8341	/* */
bogdanm	0:9b334a45a8ff	8342	/* Single Wire Protocol Master Interface (SWPMI) */
bogdanm	0:9b334a45a8ff	8343	/* */
bogdanm	0:9b334a45a8ff	8344	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8345
bogdanm	0:9b334a45a8ff	8346	/***************** Bit definition for SWPMI_CR register ******************/
bogdanm	0:9b334a45a8ff	8347	#define SWPMI_CR_RXDMA ((uint32_t)0x00000001) /!<Reception DMA enable /
bogdanm	0:9b334a45a8ff	8348	#define SWPMI_CR_TXDMA ((uint32_t)0x00000002) /!<Transmission DMA enable /
bogdanm	0:9b334a45a8ff	8349	#define SWPMI_CR_RXMODE ((uint32_t)0x00000004) /!<Reception buffering mode /
bogdanm	0:9b334a45a8ff	8350	#define SWPMI_CR_TXMODE ((uint32_t)0x00000008) /!<Transmission buffering mode /
bogdanm	0:9b334a45a8ff	8351	#define SWPMI_CR_LPBK ((uint32_t)0x00000010) /!<Loopback mode enable /
bogdanm	0:9b334a45a8ff	8352	#define SWPMI_CR_SWPACT ((uint32_t)0x00000020) /!<Single wire protocol master interface activate /
bogdanm	0:9b334a45a8ff	8353	#define SWPMI_CR_DEACT ((uint32_t)0x00000400) /!<Single wire protocol master interface deactivate /
bogdanm	0:9b334a45a8ff	8354
bogdanm	0:9b334a45a8ff	8355	/***************** Bit definition for SWPMI_BRR register ******************/
bogdanm	0:9b334a45a8ff	8356	#define SWPMI_BRR_BR ((uint32_t)0x0000003F) /!<BR[5:0] bits (Bitrate prescaler) /
bogdanm	0:9b334a45a8ff	8357
bogdanm	0:9b334a45a8ff	8358	/***************** Bit definition for SWPMI_ISR register ******************/
bogdanm	0:9b334a45a8ff	8359	#define SWPMI_ISR_RXBFF ((uint32_t)0x00000001) /!<Receive buffer full flag /
bogdanm	0:9b334a45a8ff	8360	#define SWPMI_ISR_TXBEF ((uint32_t)0x00000002) /!<Transmit buffer empty flag /
bogdanm	0:9b334a45a8ff	8361	#define SWPMI_ISR_RXBERF ((uint32_t)0x00000004) /!<Receive CRC error flag /
bogdanm	0:9b334a45a8ff	8362	#define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008) /!<Receive overrun error flag /
bogdanm	0:9b334a45a8ff	8363	#define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010) /!<Transmit underrun error flag /
bogdanm	0:9b334a45a8ff	8364	#define SWPMI_ISR_RXNE ((uint32_t)0x00000020) /!<Receive data register not empty /
bogdanm	0:9b334a45a8ff	8365	#define SWPMI_ISR_TXE ((uint32_t)0x00000040) /!<Transmit data register empty /
bogdanm	0:9b334a45a8ff	8366	#define SWPMI_ISR_TCF ((uint32_t)0x00000080) /!<Transfer complete flag /
bogdanm	0:9b334a45a8ff	8367	#define SWPMI_ISR_SRF ((uint32_t)0x00000100) /!<Slave resume flag /
bogdanm	0:9b334a45a8ff	8368	#define SWPMI_ISR_SUSP ((uint32_t)0x00000200) /!<SUSPEND flag /
bogdanm	0:9b334a45a8ff	8369	#define SWPMI_ISR_DEACTF ((uint32_t)0x00000400) /!<DEACTIVATED flag /
bogdanm	0:9b334a45a8ff	8370
bogdanm	0:9b334a45a8ff	8371	/***************** Bit definition for SWPMI_ICR register ******************/
bogdanm	0:9b334a45a8ff	8372	#define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001) /!<Clear receive buffer full flag /
bogdanm	0:9b334a45a8ff	8373	#define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002) /!<Clear transmit buffer empty flag /
bogdanm	0:9b334a45a8ff	8374	#define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004) /!<Clear receive CRC error flag /
bogdanm	0:9b334a45a8ff	8375	#define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008) /!<Clear receive overrun error flag /
bogdanm	0:9b334a45a8ff	8376	#define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010) /!<Clear transmit underrun error flag /
bogdanm	0:9b334a45a8ff	8377	#define SWPMI_ICR_CTCF ((uint32_t)0x00000080) /!<Clear transfer complete flag /
bogdanm	0:9b334a45a8ff	8378	#define SWPMI_ICR_CSRF ((uint32_t)0x00000100) /!<Clear slave resume flag /
bogdanm	0:9b334a45a8ff	8379
bogdanm	0:9b334a45a8ff	8380	/***************** Bit definition for SWPMI_IER register ******************/
bogdanm	0:9b334a45a8ff	8381	#define SWPMI_IER_SRIE ((uint32_t)0x00000100) /!<Slave resume interrupt enable /
bogdanm	0:9b334a45a8ff	8382	#define SWPMI_IER_TCIE ((uint32_t)0x00000080) /!<Transmit complete interrupt enable /
bogdanm	0:9b334a45a8ff	8383	#define SWPMI_IER_TIE ((uint32_t)0x00000040) /!<Transmit interrupt enable /
bogdanm	0:9b334a45a8ff	8384	#define SWPMI_IER_RIE ((uint32_t)0x00000020) /!<Receive interrupt enable /
bogdanm	0:9b334a45a8ff	8385	#define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010) /!<Transmit underrun error interrupt enable /
bogdanm	0:9b334a45a8ff	8386	#define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008) /!<Receive overrun error interrupt enable /
bogdanm	0:9b334a45a8ff	8387	#define SWPMI_IER_RXBERIE ((uint32_t)0x00000004) /!<Receive CRC error interrupt enable /
bogdanm	0:9b334a45a8ff	8388	#define SWPMI_IER_TXBEIE ((uint32_t)0x00000002) /!<Transmit buffer empty interrupt enable /
bogdanm	0:9b334a45a8ff	8389	#define SWPMI_IER_RXBFIE ((uint32_t)0x00000001) /!<Receive buffer full interrupt enable /
bogdanm	0:9b334a45a8ff	8390
bogdanm	0:9b334a45a8ff	8391	/***************** Bit definition for SWPMI_RFL register ******************/
bogdanm	0:9b334a45a8ff	8392	#define SWPMI_RFL_RFL ((uint32_t)0x0000001F) /!<RFL[4:0] bits (Receive Frame length) /
bogdanm	0:9b334a45a8ff	8393	#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) /
bogdanm	0:9b334a45a8ff	8394
bogdanm	0:9b334a45a8ff	8395	/***************** Bit definition for SWPMI_TDR register ******************/
bogdanm	0:9b334a45a8ff	8396	#define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFF) /!<Transmit Data Register /
bogdanm	0:9b334a45a8ff	8397
bogdanm	0:9b334a45a8ff	8398	/***************** Bit definition for SWPMI_RDR register ******************/
bogdanm	0:9b334a45a8ff	8399	#define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFF) /!<Receive Data Register /
bogdanm	0:9b334a45a8ff	8400
bogdanm	0:9b334a45a8ff	8401	/***************** Bit definition for SWPMI_OR register ******************/
bogdanm	0:9b334a45a8ff	8402	#define SWPMI_OR_TBYP ((uint32_t)0x00000001) /!<SWP Transceiver Bypass /
bogdanm	0:9b334a45a8ff	8403	#define SWPMI_OR_CLASS ((uint32_t)0x00000002) /!<SWP Voltage Class selection /
bogdanm	0:9b334a45a8ff	8404
bogdanm	0:9b334a45a8ff	8405	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8406	/* */
bogdanm	0:9b334a45a8ff	8407	/* VREFBUF */
bogdanm	0:9b334a45a8ff	8408	/* */
bogdanm	0:9b334a45a8ff	8409	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8410	/***************** Bit definition for VREFBUF_CSR register **************/
bogdanm	0:9b334a45a8ff	8411	#define VREFBUF_CSR_ENVR ((uint32_t)0x00000001) /!<Voltage reference buffer enable /
bogdanm	0:9b334a45a8ff	8412	#define VREFBUF_CSR_HIZ ((uint32_t)0x00000002) /!<High impedance mode /
bogdanm	0:9b334a45a8ff	8413	#define VREFBUF_CSR_VRS ((uint32_t)0x00000004) /!<Voltage reference scale /
bogdanm	0:9b334a45a8ff	8414	#define VREFBUF_CSR_VRR ((uint32_t)0x00000008) /!<Voltage reference buffer ready /
bogdanm	0:9b334a45a8ff	8415
bogdanm	0:9b334a45a8ff	8416	/***************** Bit definition for VREFBUF_CCR register ****************/
bogdanm	0:9b334a45a8ff	8417	#define VREFBUF_CCR_TRIM ((uint32_t)0x0000003F) /!<TRIM[5:0] bits (Trimming code) /
bogdanm	0:9b334a45a8ff	8418
bogdanm	0:9b334a45a8ff	8419	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8420	/* */
bogdanm	0:9b334a45a8ff	8421	/* Window WATCHDOG */
bogdanm	0:9b334a45a8ff	8422	/* */
bogdanm	0:9b334a45a8ff	8423	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8424	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	0:9b334a45a8ff	8425	#define WWDG_CR_T ((uint32_t)0x0000007F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	0:9b334a45a8ff	8426	#define WWDG_CR_T_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8427	#define WWDG_CR_T_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8428	#define WWDG_CR_T_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8429	#define WWDG_CR_T_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8430	#define WWDG_CR_T_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8431	#define WWDG_CR_T_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8432	#define WWDG_CR_T_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8433
bogdanm	0:9b334a45a8ff	8434	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!<Activation bit /
bogdanm	0:9b334a45a8ff	8435
bogdanm	0:9b334a45a8ff	8436	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	0:9b334a45a8ff	8437	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!<W[6:0] bits (7-bit window value) /
bogdanm	0:9b334a45a8ff	8438	#define WWDG_CFR_W_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8439	#define WWDG_CFR_W_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8440	#define WWDG_CFR_W_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8441	#define WWDG_CFR_W_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8442	#define WWDG_CFR_W_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8443	#define WWDG_CFR_W_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8444	#define WWDG_CFR_W_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8445
bogdanm	0:9b334a45a8ff	8446	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!<WDGTB[1:0] bits (Timer Base) /
bogdanm	0:9b334a45a8ff	8447	#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8448	#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8449
bogdanm	0:9b334a45a8ff	8450	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!<Early Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	8451
bogdanm	0:9b334a45a8ff	8452	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	8453	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!<Early Wakeup Interrupt Flag /
bogdanm	0:9b334a45a8ff	8454
bogdanm	0:9b334a45a8ff	8455
bogdanm	0:9b334a45a8ff	8456	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8457	/* */
bogdanm	0:9b334a45a8ff	8458	/* Debug MCU */
bogdanm	0:9b334a45a8ff	8459	/* */
bogdanm	0:9b334a45a8ff	8460	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8461	/****************** Bit definition for DBGMCU_IDCODE register ***********/
bogdanm	0:9b334a45a8ff	8462	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	8463	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm	0:9b334a45a8ff	8464
bogdanm	0:9b334a45a8ff	8465	/****************** Bit definition for DBGMCU_CR register ***************/
bogdanm	0:9b334a45a8ff	8466	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	8467	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	8468	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	8469	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	8470
bogdanm	0:9b334a45a8ff	8471	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	8472	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
bogdanm	0:9b334a45a8ff	8473	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
bogdanm	0:9b334a45a8ff	8474
bogdanm	0:9b334a45a8ff	8475	/****************** Bit definition for DBGMCU_APB1FZR1 register *********/
bogdanm	0:9b334a45a8ff	8476	#define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	8477	#define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	8478	#define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	8479	#define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	8480	#define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	8481	#define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	8482	#define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	8483	#define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	8484	#define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	8485	#define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	8486	#define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	8487	#define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	8488	#define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	8489	#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	8490
bogdanm	0:9b334a45a8ff	8491	/****************** Bit definition for DBGMCU_APB1FZR2 register ********/
bogdanm	0:9b334a45a8ff	8492	#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	8493
bogdanm	0:9b334a45a8ff	8494	/****************** Bit definition for DBGMCU_APB2FZ register **********/
bogdanm	0:9b334a45a8ff	8495	#define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	8496	#define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	8497	#define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	8498	#define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	8499	#define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	8500
bogdanm	0:9b334a45a8ff	8501	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8502	/* */
bogdanm	0:9b334a45a8ff	8503	/* USB_OTG */
bogdanm	0:9b334a45a8ff	8504	/* */
bogdanm	0:9b334a45a8ff	8505	/******************************************************************************/
bogdanm	0:9b334a45a8ff	8506	/****************** Bit definition for USB_OTG_GOTGCTL register ******************/
bogdanm	0:9b334a45a8ff	8507	#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /!< Session request success /
bogdanm	0:9b334a45a8ff	8508	#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /!< Session request /
bogdanm	0:9b334a45a8ff	8509	#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /!< VBUS valid override enable /
bogdanm	0:9b334a45a8ff	8510	#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /!< VBUS valid override value /
bogdanm	0:9b334a45a8ff	8511	#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /!< A-peripheral session valid override enable /
bogdanm	0:9b334a45a8ff	8512	#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /!< A-peripheral session valid override value /
bogdanm	0:9b334a45a8ff	8513	#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /!< B-peripheral session valid override enable /
bogdanm	0:9b334a45a8ff	8514	#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /!< B-peripheral session valid override value /
bogdanm	0:9b334a45a8ff	8515	#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /!< B-session valid/
bogdanm	0:9b334a45a8ff	8516
bogdanm	0:9b334a45a8ff	8517	/****************** Bit definition for USB_OTG_HCFG register ******************/
bogdanm	0:9b334a45a8ff	8518
bogdanm	0:9b334a45a8ff	8519	#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /!< FS/LS PHY clock select /
bogdanm	0:9b334a45a8ff	8520	#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8521	#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8522	#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /!< FS- and LS-only support /
bogdanm	0:9b334a45a8ff	8523
bogdanm	0:9b334a45a8ff	8524	/****************** Bit definition for USB_OTG_DCFG register ******************/
bogdanm	0:9b334a45a8ff	8525
bogdanm	0:9b334a45a8ff	8526	#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /!< Device speed /
bogdanm	0:9b334a45a8ff	8527	#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8528	#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8529	#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /!< Nonzero-length status OUT handshake /
bogdanm	0:9b334a45a8ff	8530	#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /!< Device address /
bogdanm	0:9b334a45a8ff	8531	#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8532	#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8533	#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8534	#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8535	#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8536	#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8537	#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8538	#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /!< Periodic (micro)frame interval /
bogdanm	0:9b334a45a8ff	8539	#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8540	#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8541	#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /!< Periodic scheduling interval /
bogdanm	0:9b334a45a8ff	8542	#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8543	#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8544
bogdanm	0:9b334a45a8ff	8545	/****************** Bit definition for USB_OTG_PCGCR register ******************/
bogdanm	0:9b334a45a8ff	8546	#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /!< Stop PHY clock /
bogdanm	0:9b334a45a8ff	8547	#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /!< Gate HCLK /
bogdanm	0:9b334a45a8ff	8548	#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /!< PHY suspended /
bogdanm	0:9b334a45a8ff	8549
bogdanm	0:9b334a45a8ff	8550	/****************** Bit definition for USB_OTG_GOTGINT register ******************/
bogdanm	0:9b334a45a8ff	8551	#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /!< Session end detected /
bogdanm	0:9b334a45a8ff	8552	#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /!< Session request success status change /
bogdanm	0:9b334a45a8ff	8553	#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /!< Host negotiation success status change /
bogdanm	0:9b334a45a8ff	8554	#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /!< Host negotiation detected /
bogdanm	0:9b334a45a8ff	8555	#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /!< A-device timeout change /
bogdanm	0:9b334a45a8ff	8556	#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /!< Debounce done /
bogdanm	0:9b334a45a8ff	8557
bogdanm	0:9b334a45a8ff	8558	/****************** Bit definition for USB_OTG_DCTL register ******************/
bogdanm	0:9b334a45a8ff	8559	#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /!< Remote wakeup signaling /
bogdanm	0:9b334a45a8ff	8560	#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /!< Soft disconnect /
bogdanm	0:9b334a45a8ff	8561	#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /!< Global IN NAK status /
bogdanm	0:9b334a45a8ff	8562	#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /!< Global OUT NAK status /
bogdanm	0:9b334a45a8ff	8563
bogdanm	0:9b334a45a8ff	8564	#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /!< Test control /
bogdanm	0:9b334a45a8ff	8565	#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8566	#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8567	#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8568	#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /!< Set global IN NAK /
bogdanm	0:9b334a45a8ff	8569	#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /!< Clear global IN NAK /
bogdanm	0:9b334a45a8ff	8570	#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /!< Set global OUT NAK /
bogdanm	0:9b334a45a8ff	8571	#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /!< Clear global OUT NAK /
bogdanm	0:9b334a45a8ff	8572	#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /!< Power-on programming done /
bogdanm	0:9b334a45a8ff	8573
bogdanm	0:9b334a45a8ff	8574	/****************** Bit definition for USB_OTG_HFIR register ******************/
bogdanm	0:9b334a45a8ff	8575	#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /!< Frame interval /
bogdanm	0:9b334a45a8ff	8576
bogdanm	0:9b334a45a8ff	8577	/****************** Bit definition for USB_OTG_HFNUM register ******************/
bogdanm	0:9b334a45a8ff	8578	#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /!< Frame number /
bogdanm	0:9b334a45a8ff	8579	#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /!< Frame time remaining /
bogdanm	0:9b334a45a8ff	8580
bogdanm	0:9b334a45a8ff	8581	/****************** Bit definition for USB_OTG_DSTS register ******************/
bogdanm	0:9b334a45a8ff	8582	#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /!< Suspend status /
bogdanm	0:9b334a45a8ff	8583
bogdanm	0:9b334a45a8ff	8584	#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /!< Enumerated speed /
bogdanm	0:9b334a45a8ff	8585	#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8586	#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8587	#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /!< Erratic error /
bogdanm	0:9b334a45a8ff	8588	#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /!< Frame number of the received SOF /
bogdanm	0:9b334a45a8ff	8589
bogdanm	0:9b334a45a8ff	8590	/****************** Bit definition for USB_OTG_GAHBCFG register ******************/
bogdanm	0:9b334a45a8ff	8591	#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /!< Global interrupt mask /
bogdanm	0:9b334a45a8ff	8592	#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /!< Burst length/type /
bogdanm	0:9b334a45a8ff	8593	#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8594	#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8595	#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8596	#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8597	#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /!< DMA enable /
bogdanm	0:9b334a45a8ff	8598	#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /!< TxFIFO empty level /
bogdanm	0:9b334a45a8ff	8599	#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /!< Periodic TxFIFO empty level /
bogdanm	0:9b334a45a8ff	8600
bogdanm	0:9b334a45a8ff	8601	/****************** Bit definition for USB_OTG_GUSBCFG register ******************/
bogdanm	0:9b334a45a8ff	8602
bogdanm	0:9b334a45a8ff	8603	#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /!< FS timeout calibration /
bogdanm	0:9b334a45a8ff	8604	#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8605	#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8606	#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8607	#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
bogdanm	0:9b334a45a8ff	8608	#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /!< SRP-capable /
bogdanm	0:9b334a45a8ff	8609	#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /!< HNP-capable /
bogdanm	0:9b334a45a8ff	8610	#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /!< USB turnaround time /
bogdanm	0:9b334a45a8ff	8611	#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8612	#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8613	#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8614	#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8615	#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /!< PHY Low-power clock select /
bogdanm	0:9b334a45a8ff	8616	#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /!< ULPI FS/LS select /
bogdanm	0:9b334a45a8ff	8617	#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /!< ULPI Auto-resume /
bogdanm	0:9b334a45a8ff	8618	#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /!< ULPI Clock SuspendM /
bogdanm	0:9b334a45a8ff	8619	#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /!< ULPI External VBUS Drive /
bogdanm	0:9b334a45a8ff	8620	#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /!< ULPI external VBUS indicator /
bogdanm	0:9b334a45a8ff	8621	#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /!< TermSel DLine pulsing selection /
bogdanm	0:9b334a45a8ff	8622	#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /!< Indicator complement /
bogdanm	0:9b334a45a8ff	8623	#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /!< Indicator pass through /
bogdanm	0:9b334a45a8ff	8624	#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /!< ULPI interface protect disable /
bogdanm	0:9b334a45a8ff	8625	#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /!< Forced host mode /
bogdanm	0:9b334a45a8ff	8626	#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /!< Forced peripheral mode /
bogdanm	0:9b334a45a8ff	8627	#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /!< Corrupt Tx packet /
bogdanm	0:9b334a45a8ff	8628
bogdanm	0:9b334a45a8ff	8629	/****************** Bit definition for USB_OTG_GRSTCTL register ******************/
bogdanm	0:9b334a45a8ff	8630	#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /!< Core soft reset /
bogdanm	0:9b334a45a8ff	8631	#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /!< HCLK soft reset /
bogdanm	0:9b334a45a8ff	8632	#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /!< Host frame counter reset /
bogdanm	0:9b334a45a8ff	8633	#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /!< RxFIFO flush /
bogdanm	0:9b334a45a8ff	8634	#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /!< TxFIFO flush /
bogdanm	0:9b334a45a8ff	8635	#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /!< TxFIFO number /
bogdanm	0:9b334a45a8ff	8636	#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8637	#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8638	#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8639	#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8640	#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8641	#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /!< DMA request signal /
bogdanm	0:9b334a45a8ff	8642	#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /!< AHB master idle /
bogdanm	0:9b334a45a8ff	8643
bogdanm	0:9b334a45a8ff	8644	/****************** Bit definition for USB_OTG_DIEPMSK register ******************/
bogdanm	0:9b334a45a8ff	8645	#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
bogdanm	0:9b334a45a8ff	8646	#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
bogdanm	0:9b334a45a8ff	8647	#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
bogdanm	0:9b334a45a8ff	8648	#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
bogdanm	0:9b334a45a8ff	8649	#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
bogdanm	0:9b334a45a8ff	8650	#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
bogdanm	0:9b334a45a8ff	8651	#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
bogdanm	0:9b334a45a8ff	8652	#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
bogdanm	0:9b334a45a8ff	8653
bogdanm	0:9b334a45a8ff	8654	/****************** Bit definition for USB_OTG_HPTXSTS register ******************/
bogdanm	0:9b334a45a8ff	8655	#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /!< Periodic transmit data FIFO space available /
bogdanm	0:9b334a45a8ff	8656	#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /!< Periodic transmit request queue space available /
bogdanm	0:9b334a45a8ff	8657	#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8658	#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8659	#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8660	#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8661	#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8662	#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8663	#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8664	#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	8665
bogdanm	0:9b334a45a8ff	8666	#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /!< Top of the periodic transmit request queue /
bogdanm	0:9b334a45a8ff	8667	#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8668	#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8669	#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8670	#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8671	#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8672	#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8673	#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8674	#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	8675
bogdanm	0:9b334a45a8ff	8676	/****************** Bit definition for USB_OTG_HAINT register ******************/
bogdanm	0:9b334a45a8ff	8677	#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /!< Channel interrupts /
bogdanm	0:9b334a45a8ff	8678
bogdanm	0:9b334a45a8ff	8679	/****************** Bit definition for USB_OTG_DOEPMSK register ******************/
bogdanm	0:9b334a45a8ff	8680	#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
bogdanm	0:9b334a45a8ff	8681	#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
bogdanm	0:9b334a45a8ff	8682	#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /!< SETUP phase done mask /
bogdanm	0:9b334a45a8ff	8683	#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled mask /
bogdanm	0:9b334a45a8ff	8684	#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received mask /
bogdanm	0:9b334a45a8ff	8685	#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /!< OUT packet error mask /
bogdanm	0:9b334a45a8ff	8686	#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
bogdanm	0:9b334a45a8ff	8687
bogdanm	0:9b334a45a8ff	8688	/****************** Bit definition for USB_OTG_GINTSTS register ******************/
bogdanm	0:9b334a45a8ff	8689	#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /!< Current mode of operation /
bogdanm	0:9b334a45a8ff	8690	#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /!< Mode mismatch interrupt /
bogdanm	0:9b334a45a8ff	8691	#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt /
bogdanm	0:9b334a45a8ff	8692	#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /!< Start of frame /
bogdanm	0:9b334a45a8ff	8693	#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /!< RxFIFO nonempty /
bogdanm	0:9b334a45a8ff	8694	#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty /
bogdanm	0:9b334a45a8ff	8695	#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /!< Global IN nonperiodic NAK effective /
bogdanm	0:9b334a45a8ff	8696	#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /!< Global OUT NAK effective /
bogdanm	0:9b334a45a8ff	8697	#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /!< Early suspend /
bogdanm	0:9b334a45a8ff	8698	#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /!< USB suspend /
bogdanm	0:9b334a45a8ff	8699	#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /!< USB reset /
bogdanm	0:9b334a45a8ff	8700	#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /!< Enumeration done /
bogdanm	0:9b334a45a8ff	8701	#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt /
bogdanm	0:9b334a45a8ff	8702	#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /!< End of periodic frame interrupt /
bogdanm	0:9b334a45a8ff	8703	#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /!< IN endpoint interrupt /
bogdanm	0:9b334a45a8ff	8704	#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /!< OUT endpoint interrupt /
bogdanm	0:9b334a45a8ff	8705	#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer /
bogdanm	0:9b334a45a8ff	8706	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /!< Incomplete periodic transfer /
bogdanm	0:9b334a45a8ff	8707	#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /!< Data fetch suspended /
bogdanm	0:9b334a45a8ff	8708	#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /!< Host port interrupt /
bogdanm	0:9b334a45a8ff	8709	#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /!< Host channels interrupt /
bogdanm	0:9b334a45a8ff	8710	#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /!< Periodic TxFIFO empty /
bogdanm	0:9b334a45a8ff	8711	#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /!< LPM interrupt /
bogdanm	0:9b334a45a8ff	8712	#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /!< Connector ID status change /
bogdanm	0:9b334a45a8ff	8713	#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt /
bogdanm	0:9b334a45a8ff	8714	#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /!< Session request/new session detected interrupt /
bogdanm	0:9b334a45a8ff	8715	#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt /
bogdanm	0:9b334a45a8ff	8716
bogdanm	0:9b334a45a8ff	8717	/****************** Bit definition for USB_OTG_GINTMSK register ******************/
bogdanm	0:9b334a45a8ff	8718
bogdanm	0:9b334a45a8ff	8719	#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /!< Mode mismatch interrupt mask /
bogdanm	0:9b334a45a8ff	8720	#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt mask /
bogdanm	0:9b334a45a8ff	8721	#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /!< Start of frame mask /
bogdanm	0:9b334a45a8ff	8722	#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /!< Receive FIFO nonempty mask /
bogdanm	0:9b334a45a8ff	8723	#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty mask /
bogdanm	0:9b334a45a8ff	8724	#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /!< Global nonperiodic IN NAK effective mask /
bogdanm	0:9b334a45a8ff	8725	#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /!< Global OUT NAK effective mask /
bogdanm	0:9b334a45a8ff	8726	#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /!< Early suspend mask /
bogdanm	0:9b334a45a8ff	8727	#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /!< USB suspend mask /
bogdanm	0:9b334a45a8ff	8728	#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /!< USB reset mask /
bogdanm	0:9b334a45a8ff	8729	#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /!< Enumeration done mask /
bogdanm	0:9b334a45a8ff	8730	#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt mask /
bogdanm	0:9b334a45a8ff	8731	#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /!< End of periodic frame interrupt mask /
bogdanm	0:9b334a45a8ff	8732	#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /!< Endpoint mismatch interrupt mask /
bogdanm	0:9b334a45a8ff	8733	#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /!< IN endpoints interrupt mask /
bogdanm	0:9b334a45a8ff	8734	#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /!< OUT endpoints interrupt mask /
bogdanm	0:9b334a45a8ff	8735	#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer mask /
bogdanm	0:9b334a45a8ff	8736	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /!< Incomplete periodic transfer mask /
bogdanm	0:9b334a45a8ff	8737	#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /!< Data fetch suspended mask /
bogdanm	0:9b334a45a8ff	8738	#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /!< Host port interrupt mask /
bogdanm	0:9b334a45a8ff	8739	#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /!< Host channels interrupt mask /
bogdanm	0:9b334a45a8ff	8740	#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /!< Periodic TxFIFO empty mask /
bogdanm	0:9b334a45a8ff	8741	#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /!< LPM interrupt Mask /
bogdanm	0:9b334a45a8ff	8742	#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /!< Connector ID status change mask /
bogdanm	0:9b334a45a8ff	8743	#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt mask /
bogdanm	0:9b334a45a8ff	8744	#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /!< Session request/new session detected interrupt mask /
bogdanm	0:9b334a45a8ff	8745	#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt mask /
bogdanm	0:9b334a45a8ff	8746
bogdanm	0:9b334a45a8ff	8747	/****************** Bit definition for USB_OTG_DAINT register ******************/
bogdanm	0:9b334a45a8ff	8748	#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /!< IN endpoint interrupt bits /
bogdanm	0:9b334a45a8ff	8749	#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /!< OUT endpoint interrupt bits /
bogdanm	0:9b334a45a8ff	8750
bogdanm	0:9b334a45a8ff	8751	/****************** Bit definition for USB_OTG_HAINTMSK register ******************/
bogdanm	0:9b334a45a8ff	8752	#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /!< Channel interrupt mask /
bogdanm	0:9b334a45a8ff	8753
bogdanm	0:9b334a45a8ff	8754	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
bogdanm	0:9b334a45a8ff	8755	#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /!< IN EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8756	#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /!< OUT EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8757	#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /!< OUT EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8758	#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /!< OUT EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8759
bogdanm	0:9b334a45a8ff	8760	/****************** Bit definition for USB_OTG_DAINTMSK register ******************/
bogdanm	0:9b334a45a8ff	8761	#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /!< IN EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8762	#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /!< OUT EP interrupt mask bits /
bogdanm	0:9b334a45a8ff	8763
bogdanm	0:9b334a45a8ff	8764	/****************** Bit definition for OTG register ******************/
bogdanm	0:9b334a45a8ff	8765
bogdanm	0:9b334a45a8ff	8766	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
bogdanm	0:9b334a45a8ff	8767	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8768	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8769	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8770	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8771	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
bogdanm	0:9b334a45a8ff	8772	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
bogdanm	0:9b334a45a8ff	8773	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8774	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8775	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
bogdanm	0:9b334a45a8ff	8776	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8777	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8778	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8779	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8780	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
bogdanm	0:9b334a45a8ff	8781	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8782	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8783	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8784	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8785	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
bogdanm	0:9b334a45a8ff	8786	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8787	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8788	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8789	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8790
bogdanm	0:9b334a45a8ff	8791	/****************** Bit definition for OTG register ******************/
bogdanm	0:9b334a45a8ff	8792
bogdanm	0:9b334a45a8ff	8793	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
bogdanm	0:9b334a45a8ff	8794	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8795	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8796	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8797	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8798	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
bogdanm	0:9b334a45a8ff	8799	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
bogdanm	0:9b334a45a8ff	8800	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8801	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8802	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
bogdanm	0:9b334a45a8ff	8803	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8804	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8805	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8806	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8807	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
bogdanm	0:9b334a45a8ff	8808	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8809	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8810	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8811	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8812	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
bogdanm	0:9b334a45a8ff	8813	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8814	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8815	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8816	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8817
bogdanm	0:9b334a45a8ff	8818	/****************** Bit definition for USB_OTG_GRXFSIZ register ******************/
bogdanm	0:9b334a45a8ff	8819	#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /!< RxFIFO depth /
bogdanm	0:9b334a45a8ff	8820
bogdanm	0:9b334a45a8ff	8821	/****************** Bit definition for USB_OTG_DVBUSDIS register ******************/
bogdanm	0:9b334a45a8ff	8822	#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /!< Device VBUS discharge time /
bogdanm	0:9b334a45a8ff	8823
bogdanm	0:9b334a45a8ff	8824	/****************** Bit definition for OTG register ******************/
bogdanm	0:9b334a45a8ff	8825	#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /!< Nonperiodic transmit RAM start address /
bogdanm	0:9b334a45a8ff	8826	#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /!< Nonperiodic TxFIFO depth /
bogdanm	0:9b334a45a8ff	8827	#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /!< Endpoint 0 transmit RAM start address /
bogdanm	0:9b334a45a8ff	8828	#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /!< Endpoint 0 TxFIFO depth /
bogdanm	0:9b334a45a8ff	8829
bogdanm	0:9b334a45a8ff	8830	/****************** Bit definition for USB_OTG_DVBUSPULSE register ******************/
bogdanm	0:9b334a45a8ff	8831	#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /!< Device VBUS pulsing time /
bogdanm	0:9b334a45a8ff	8832
bogdanm	0:9b334a45a8ff	8833	/****************** Bit definition for USB_OTG_GNPTXSTS register ******************/
bogdanm	0:9b334a45a8ff	8834	#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /!< Nonperiodic TxFIFO space available /
bogdanm	0:9b334a45a8ff	8835
bogdanm	0:9b334a45a8ff	8836	#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /!< Nonperiodic transmit request queue space available /
bogdanm	0:9b334a45a8ff	8837	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8838	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8839	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8840	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8841	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8842	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8843	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8844	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	8845
bogdanm	0:9b334a45a8ff	8846	#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /!< Top of the nonperiodic transmit request queue /
bogdanm	0:9b334a45a8ff	8847	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8848	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8849	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8850	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8851	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8852	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8853	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8854
bogdanm	0:9b334a45a8ff	8855	/****************** Bit definition for USB_OTG_DTHRCTL register *************/
bogdanm	0:9b334a45a8ff	8856	#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /!< Nonisochronous IN endpoints threshold enable /
bogdanm	0:9b334a45a8ff	8857	#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /!< ISO IN endpoint threshold enable /
bogdanm	0:9b334a45a8ff	8858
bogdanm	0:9b334a45a8ff	8859	#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /!< Transmit threshold length /
bogdanm	0:9b334a45a8ff	8860	#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8861	#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8862	#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8863	#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8864	#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8865	#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8866	#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8867	#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	8868	#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /!<Bit 8 /
bogdanm	0:9b334a45a8ff	8869	#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /!< Receive threshold enable /
bogdanm	0:9b334a45a8ff	8870
bogdanm	0:9b334a45a8ff	8871	#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /!< Receive threshold length /
bogdanm	0:9b334a45a8ff	8872	#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8873	#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8874	#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8875	#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8876	#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	8877	#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	8878	#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	8879	#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	8880	#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /!<Bit 8 /
bogdanm	0:9b334a45a8ff	8881	#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /!< Arbiter parking enable /
bogdanm	0:9b334a45a8ff	8882
bogdanm	0:9b334a45a8ff	8883	/****************** Bit definition for USB_OTG_DIEPEMPMSK register *************/
bogdanm	0:9b334a45a8ff	8884	#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /!< IN EP Tx FIFO empty interrupt mask bits /
bogdanm	0:9b334a45a8ff	8885
bogdanm	0:9b334a45a8ff	8886	/****************** Bit definition for USB_OTG_DEACHINT register ******************/
bogdanm	0:9b334a45a8ff	8887	#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /!< IN endpoint 1interrupt bit /
bogdanm	0:9b334a45a8ff	8888	#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /!< OUT endpoint 1 interrupt bit /
bogdanm	0:9b334a45a8ff	8889
bogdanm	0:9b334a45a8ff	8890	/****************** Bit definition for USB_OTG_GCCFG register ******************/
bogdanm	0:9b334a45a8ff	8891	#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /!< Data contact detection (DCD) status /
bogdanm	0:9b334a45a8ff	8892	#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /!< Primary detection (PD) status /
bogdanm	0:9b334a45a8ff	8893	#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /!< Secondary detection (SD) status /
bogdanm	0:9b334a45a8ff	8894	#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /!< DM pull-up detection status /
bogdanm	0:9b334a45a8ff	8895	#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /!< Power down /
bogdanm	0:9b334a45a8ff	8896	#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /!< Battery charging detector (BCD) enable /
bogdanm	0:9b334a45a8ff	8897	#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /!< Data contact detection (DCD) mode enable/
bogdanm	0:9b334a45a8ff	8898	#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /!< Primary detection (PD) mode enable/
bogdanm	0:9b334a45a8ff	8899	#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /!< Secondary detection (SD) mode enable /
bogdanm	0:9b334a45a8ff	8900	#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /!< Secondary detection (SD) mode enable /
bogdanm	0:9b334a45a8ff	8901
bogdanm	0:9b334a45a8ff	8902	/****************** Bit definition for USB_OTG_GPWRDN) register ******************/
bogdanm	0:9b334a45a8ff	8903	#define USB_OTG_GPWRDN_DISABLEVBUS ((uint32_t)0x00000040) /!< Power down /
bogdanm	0:9b334a45a8ff	8904
bogdanm	0:9b334a45a8ff	8905	/****************** Bit definition for USB_OTG_DEACHINTMSK register ******************/
bogdanm	0:9b334a45a8ff	8906	#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /!< IN Endpoint 1 interrupt mask bit /
bogdanm	0:9b334a45a8ff	8907	#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /!< OUT Endpoint 1 interrupt mask bit /
bogdanm	0:9b334a45a8ff	8908
bogdanm	0:9b334a45a8ff	8909	/****************** Bit definition for USB_OTG_CID register ******************/
bogdanm	0:9b334a45a8ff	8910	#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /!< Product ID field /
bogdanm	0:9b334a45a8ff	8911
bogdanm	0:9b334a45a8ff	8912
bogdanm	0:9b334a45a8ff	8913	/****************** Bit definition for USB_OTG_GHWCFG3 register ******************/
bogdanm	0:9b334a45a8ff	8914	#define USB_OTG_GHWCFG3_LPMMode ((uint32_t)0x00004000) /* LPM mode specified for Mode of Operation */
bogdanm	0:9b334a45a8ff	8915
bogdanm	0:9b334a45a8ff	8916	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
bogdanm	0:9b334a45a8ff	8917	#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /* Enable best effort service latency */
bogdanm	0:9b334a45a8ff	8918	#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /* LPM retry count status */
bogdanm	0:9b334a45a8ff	8919	#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /* Send LPM transaction */
bogdanm	0:9b334a45a8ff	8920	#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /* LPM retry count */
bogdanm	0:9b334a45a8ff	8921	#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /* LPMCHIDX: */
bogdanm	0:9b334a45a8ff	8922	#define USB_OTG_GLPMCFG_L1ResumeOK ((uint32_t)0x00010000) /* Sleep State Resume OK */
bogdanm	0:9b334a45a8ff	8923	#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /* Port sleep status */
bogdanm	0:9b334a45a8ff	8924	#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /* LPM response */
bogdanm	0:9b334a45a8ff	8925	#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /* L1 deep sleep enable */
bogdanm	0:9b334a45a8ff	8926	#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /* BESL threshold */
bogdanm	0:9b334a45a8ff	8927	#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /* L1 shallow sleep enable */
bogdanm	0:9b334a45a8ff	8928	#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /* bRemoteWake value received with last ACKed LPM Token */
bogdanm	0:9b334a45a8ff	8929	#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /* BESL value received with last ACKed LPM Token */
bogdanm	0:9b334a45a8ff	8930	#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /* LPM Token acknowledge enable*/
bogdanm	0:9b334a45a8ff	8931	#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /* LPM support enable */
bogdanm	0:9b334a45a8ff	8932
bogdanm	0:9b334a45a8ff	8933
bogdanm	0:9b334a45a8ff	8934	/****************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******************/
bogdanm	0:9b334a45a8ff	8935	#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
bogdanm	0:9b334a45a8ff	8936	#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
bogdanm	0:9b334a45a8ff	8937	#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
bogdanm	0:9b334a45a8ff	8938	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
bogdanm	0:9b334a45a8ff	8939	#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
bogdanm	0:9b334a45a8ff	8940	#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
bogdanm	0:9b334a45a8ff	8941	#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
bogdanm	0:9b334a45a8ff	8942	#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
bogdanm	0:9b334a45a8ff	8943	#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
bogdanm	0:9b334a45a8ff	8944
bogdanm	0:9b334a45a8ff	8945	/****************** Bit definition for USB_OTG_HPRT register ******************/
bogdanm	0:9b334a45a8ff	8946	#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /!< Port connect status /
bogdanm	0:9b334a45a8ff	8947	#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /!< Port connect detected /
bogdanm	0:9b334a45a8ff	8948	#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /!< Port enable /
bogdanm	0:9b334a45a8ff	8949	#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /!< Port enable/disable change /
bogdanm	0:9b334a45a8ff	8950	#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /!< Port overcurrent active /
bogdanm	0:9b334a45a8ff	8951	#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /!< Port overcurrent change /
bogdanm	0:9b334a45a8ff	8952	#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /!< Port resume /
bogdanm	0:9b334a45a8ff	8953	#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /!< Port suspend /
bogdanm	0:9b334a45a8ff	8954	#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /!< Port reset /
bogdanm	0:9b334a45a8ff	8955
bogdanm	0:9b334a45a8ff	8956	#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /!< Port line status /
bogdanm	0:9b334a45a8ff	8957	#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8958	#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8959	#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /!< Port power /
bogdanm	0:9b334a45a8ff	8960
bogdanm	0:9b334a45a8ff	8961	#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /!< Port test control /
bogdanm	0:9b334a45a8ff	8962	#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8963	#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8964	#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	8965	#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	8966
bogdanm	0:9b334a45a8ff	8967	#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /!< Port speed /
bogdanm	0:9b334a45a8ff	8968	#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8969	#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8970
bogdanm	0:9b334a45a8ff	8971	/****************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******************/
bogdanm	0:9b334a45a8ff	8972	#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
bogdanm	0:9b334a45a8ff	8973	#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
bogdanm	0:9b334a45a8ff	8974	#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask /
bogdanm	0:9b334a45a8ff	8975	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
bogdanm	0:9b334a45a8ff	8976	#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
bogdanm	0:9b334a45a8ff	8977	#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
bogdanm	0:9b334a45a8ff	8978	#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< OUT packet error mask /
bogdanm	0:9b334a45a8ff	8979	#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
bogdanm	0:9b334a45a8ff	8980	#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /!< Bubble error interrupt mask /
bogdanm	0:9b334a45a8ff	8981	#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
bogdanm	0:9b334a45a8ff	8982	#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /!< NYET interrupt mask /
bogdanm	0:9b334a45a8ff	8983
bogdanm	0:9b334a45a8ff	8984	/****************** Bit definition for USB_OTG_HPTXFSIZ register ******************/
bogdanm	0:9b334a45a8ff	8985	#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /!< Host periodic TxFIFO start address /
bogdanm	0:9b334a45a8ff	8986	#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /!< Host periodic TxFIFO depth /
bogdanm	0:9b334a45a8ff	8987
bogdanm	0:9b334a45a8ff	8988	/****************** Bit definition for USB_OTG_DIEPCTL register ******************/
bogdanm	0:9b334a45a8ff	8989	#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
bogdanm	0:9b334a45a8ff	8990	#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
bogdanm	0:9b334a45a8ff	8991	#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /!< Even/odd frame /
bogdanm	0:9b334a45a8ff	8992	#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
bogdanm	0:9b334a45a8ff	8993
bogdanm	0:9b334a45a8ff	8994	#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
bogdanm	0:9b334a45a8ff	8995	#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	8996	#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	8997	#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
bogdanm	0:9b334a45a8ff	8998
bogdanm	0:9b334a45a8ff	8999	#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /!< TxFIFO number /
bogdanm	0:9b334a45a8ff	9000	#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9001	#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9002	#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	9003	#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	9004	#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
bogdanm	0:9b334a45a8ff	9005	#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
bogdanm	0:9b334a45a8ff	9006	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
bogdanm	0:9b334a45a8ff	9007	#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
bogdanm	0:9b334a45a8ff	9008	#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
bogdanm	0:9b334a45a8ff	9009	#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
bogdanm	0:9b334a45a8ff	9010
bogdanm	0:9b334a45a8ff	9011	/****************** Bit definition for USB_OTG_HCCHAR register ******************/
bogdanm	0:9b334a45a8ff	9012	#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
bogdanm	0:9b334a45a8ff	9013
bogdanm	0:9b334a45a8ff	9014	#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /!< Endpoint number /
bogdanm	0:9b334a45a8ff	9015	#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9016	#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9017	#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	9018	#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	9019	#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /!< Endpoint direction /
bogdanm	0:9b334a45a8ff	9020	#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /!< Low-speed device /
bogdanm	0:9b334a45a8ff	9021
bogdanm	0:9b334a45a8ff	9022	#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
bogdanm	0:9b334a45a8ff	9023	#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9024	#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9025
bogdanm	0:9b334a45a8ff	9026	#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /!< Multi Count (MC) / Error Count (EC) /
bogdanm	0:9b334a45a8ff	9027	#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9028	#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9029
bogdanm	0:9b334a45a8ff	9030	#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /!< Device address /
bogdanm	0:9b334a45a8ff	9031	#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9032	#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9033	#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	9034	#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	9035	#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	9036	#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	9037	#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	9038	#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /!< Odd frame /
bogdanm	0:9b334a45a8ff	9039	#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /!< Channel disable /
bogdanm	0:9b334a45a8ff	9040	#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /!< Channel enable /
bogdanm	0:9b334a45a8ff	9041
bogdanm	0:9b334a45a8ff	9042	/****************** Bit definition for USB_OTG_HCSPLT register ******************/
bogdanm	0:9b334a45a8ff	9043
bogdanm	0:9b334a45a8ff	9044	#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /!< Port address /
bogdanm	0:9b334a45a8ff	9045	#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9046	#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9047	#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	9048	#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	9049	#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	9050	#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	9051	#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	9052
bogdanm	0:9b334a45a8ff	9053	#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /!< Hub address /
bogdanm	0:9b334a45a8ff	9054	#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9055	#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9056	#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	9057	#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	9058	#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	9059	#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	9060	#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	9061
bogdanm	0:9b334a45a8ff	9062	#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /!< XACTPOS /
bogdanm	0:9b334a45a8ff	9063	#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9064	#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9065	#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /!< Do complete split /
bogdanm	0:9b334a45a8ff	9066	#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /!< Split enable /
bogdanm	0:9b334a45a8ff	9067
bogdanm	0:9b334a45a8ff	9068	/****************** Bit definition for USB_OTG_HCINT register ******************/
bogdanm	0:9b334a45a8ff	9069	#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed /
bogdanm	0:9b334a45a8ff	9070	#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /!< Channel halted /
bogdanm	0:9b334a45a8ff	9071	#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /!< AHB error /
bogdanm	0:9b334a45a8ff	9072	#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /!< STALL response received interrupt /
bogdanm	0:9b334a45a8ff	9073	#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /!< NAK response received interrupt /
bogdanm	0:9b334a45a8ff	9074	#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt /
bogdanm	0:9b334a45a8ff	9075	#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /!< Response received interrupt /
bogdanm	0:9b334a45a8ff	9076	#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /!< Transaction error /
bogdanm	0:9b334a45a8ff	9077	#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /!< Babble error /
bogdanm	0:9b334a45a8ff	9078	#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /!< Frame overrun /
bogdanm	0:9b334a45a8ff	9079	#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /!< Data toggle error /
bogdanm	0:9b334a45a8ff	9080
bogdanm	0:9b334a45a8ff	9081	/****************** Bit definition for USB_OTG_DIEPINT register ******************/
bogdanm	0:9b334a45a8ff	9082	#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
bogdanm	0:9b334a45a8ff	9083	#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
bogdanm	0:9b334a45a8ff	9084	#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /!< Timeout condition /
bogdanm	0:9b334a45a8ff	9085	#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /!< IN token received when TxFIFO is empty /
bogdanm	0:9b334a45a8ff	9086	#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /!< IN endpoint NAK effective /
bogdanm	0:9b334a45a8ff	9087	#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /!< Transmit FIFO empty /
bogdanm	0:9b334a45a8ff	9088	#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /!< Transmit Fifo Underrun /
bogdanm	0:9b334a45a8ff	9089	#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /!< Buffer not available interrupt /
bogdanm	0:9b334a45a8ff	9090	#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /!< Packet dropped status /
bogdanm	0:9b334a45a8ff	9091	#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /!< Babble error interrupt /
bogdanm	0:9b334a45a8ff	9092	#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /!< NAK interrupt /
bogdanm	0:9b334a45a8ff	9093
bogdanm	0:9b334a45a8ff	9094	/****************** Bit definition for USB_OTG_HCINTMSK register ******************/
bogdanm	0:9b334a45a8ff	9095	#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed mask /
bogdanm	0:9b334a45a8ff	9096	#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /!< Channel halted mask /
bogdanm	0:9b334a45a8ff	9097	#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /!< AHB error /
bogdanm	0:9b334a45a8ff	9098	#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /!< STALL response received interrupt mask /
bogdanm	0:9b334a45a8ff	9099	#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /!< NAK response received interrupt mask /
bogdanm	0:9b334a45a8ff	9100	#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt mask /
bogdanm	0:9b334a45a8ff	9101	#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /!< response received interrupt mask /
bogdanm	0:9b334a45a8ff	9102	#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /!< Transaction error mask /
bogdanm	0:9b334a45a8ff	9103	#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /!< Babble error mask /
bogdanm	0:9b334a45a8ff	9104	#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /!< Frame overrun mask /
bogdanm	0:9b334a45a8ff	9105	#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /!< Data toggle error mask /
bogdanm	0:9b334a45a8ff	9106
bogdanm	0:9b334a45a8ff	9107	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
bogdanm	0:9b334a45a8ff	9108
bogdanm	0:9b334a45a8ff	9109	#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
bogdanm	0:9b334a45a8ff	9110	#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
bogdanm	0:9b334a45a8ff	9111	#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /!< Packet count /
bogdanm	0:9b334a45a8ff	9112	/****************** Bit definition for USB_OTG_HCTSIZ register ******************/
bogdanm	0:9b334a45a8ff	9113	#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
bogdanm	0:9b334a45a8ff	9114	#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
bogdanm	0:9b334a45a8ff	9115	#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /!< Do PING /
bogdanm	0:9b334a45a8ff	9116	#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /!< Data PID /
bogdanm	0:9b334a45a8ff	9117	#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9118	#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9119
bogdanm	0:9b334a45a8ff	9120	/****************** Bit definition for USB_OTG_DIEPDMA register ******************/
bogdanm	0:9b334a45a8ff	9121	#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
bogdanm	0:9b334a45a8ff	9122
bogdanm	0:9b334a45a8ff	9123	/****************** Bit definition for USB_OTG_HCDMA register ******************/
bogdanm	0:9b334a45a8ff	9124	#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
bogdanm	0:9b334a45a8ff	9125
bogdanm	0:9b334a45a8ff	9126	/****************** Bit definition for USB_OTG_DTXFSTS register ******************/
bogdanm	0:9b334a45a8ff	9127	#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /!< IN endpoint TxFIFO space avail /
bogdanm	0:9b334a45a8ff	9128
bogdanm	0:9b334a45a8ff	9129	/****************** Bit definition for USB_OTG_DIEPTXF register ******************/
bogdanm	0:9b334a45a8ff	9130	#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /!< IN endpoint FIFOx transmit RAM start address /
bogdanm	0:9b334a45a8ff	9131	#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /!< IN endpoint TxFIFO depth /
bogdanm	0:9b334a45a8ff	9132
bogdanm	0:9b334a45a8ff	9133	/****************** Bit definition for USB_OTG_DOEPCTL register ******************/
bogdanm	0:9b334a45a8ff	9134
bogdanm	0:9b334a45a8ff	9135	#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size / /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9136	#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
bogdanm	0:9b334a45a8ff	9137	#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
bogdanm	0:9b334a45a8ff	9138	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
bogdanm	0:9b334a45a8ff	9139	#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
bogdanm	0:9b334a45a8ff	9140	#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
bogdanm	0:9b334a45a8ff	9141	#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9142	#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9143	#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /!< Snoop mode /
bogdanm	0:9b334a45a8ff	9144	#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
bogdanm	0:9b334a45a8ff	9145	#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
bogdanm	0:9b334a45a8ff	9146	#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
bogdanm	0:9b334a45a8ff	9147	#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
bogdanm	0:9b334a45a8ff	9148	#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
bogdanm	0:9b334a45a8ff	9149
bogdanm	0:9b334a45a8ff	9150	/****************** Bit definition for USB_OTG_DOEPINT register ******************/
bogdanm	0:9b334a45a8ff	9151	#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
bogdanm	0:9b334a45a8ff	9152	#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
bogdanm	0:9b334a45a8ff	9153	#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /!< SETUP phase done /
bogdanm	0:9b334a45a8ff	9154	#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled /
bogdanm	0:9b334a45a8ff	9155	#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received /
bogdanm	0:9b334a45a8ff	9156	#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /!< NYET interrupt /
bogdanm	0:9b334a45a8ff	9157
bogdanm	0:9b334a45a8ff	9158	/****************** Bit definition for USB_OTG_DOEPTSIZ register ******************/
bogdanm	0:9b334a45a8ff	9159
bogdanm	0:9b334a45a8ff	9160	#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
bogdanm	0:9b334a45a8ff	9161	#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
bogdanm	0:9b334a45a8ff	9162
bogdanm	0:9b334a45a8ff	9163	#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /!< SETUP packet count /
bogdanm	0:9b334a45a8ff	9164	#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9165	#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9166
bogdanm	0:9b334a45a8ff	9167	/****************** Bit definition for PCGCCTL register ******************/
bogdanm	0:9b334a45a8ff	9168	#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /!< SETUP packet count /
bogdanm	0:9b334a45a8ff	9169	#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	9170	#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	9171
bogdanm	0:9b334a45a8ff	9172
bogdanm	0:9b334a45a8ff	9173	/**
bogdanm	0:9b334a45a8ff	9174	* @}
bogdanm	0:9b334a45a8ff	9175	*/
bogdanm	0:9b334a45a8ff	9176
bogdanm	0:9b334a45a8ff	9177	/**
bogdanm	0:9b334a45a8ff	9178	* @}
bogdanm	0:9b334a45a8ff	9179	*/
bogdanm	0:9b334a45a8ff	9180
bogdanm	0:9b334a45a8ff	9181	/** @addtogroup Exported_macros
bogdanm	0:9b334a45a8ff	9182	* @{
bogdanm	0:9b334a45a8ff	9183	*/
bogdanm	0:9b334a45a8ff	9184
bogdanm	0:9b334a45a8ff	9185	/***************************** ADC Instances ******************************/
bogdanm	0:9b334a45a8ff	9186	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
bogdanm	0:9b334a45a8ff	9187	((INSTANCE) == ADC2) \|\| \
bogdanm	0:9b334a45a8ff	9188	((INSTANCE) == ADC3))
bogdanm	0:9b334a45a8ff	9189
bogdanm	0:9b334a45a8ff	9190	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm	0:9b334a45a8ff	9191
bogdanm	0:9b334a45a8ff	9192	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
bogdanm	0:9b334a45a8ff	9193
bogdanm	0:9b334a45a8ff	9194	/****************************** CAN Instances ****************************/
bogdanm	0:9b334a45a8ff	9195	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
bogdanm	0:9b334a45a8ff	9196
bogdanm	0:9b334a45a8ff	9197	/****************************** COMP Instances ****************************/
bogdanm	0:9b334a45a8ff	9198	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
bogdanm	0:9b334a45a8ff	9199	((INSTANCE) == COMP2))
bogdanm	0:9b334a45a8ff	9200
bogdanm	0:9b334a45a8ff	9201	/****************** COMP Instances with window mode capability ************/
bogdanm	0:9b334a45a8ff	9202	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
bogdanm	0:9b334a45a8ff	9203
bogdanm	0:9b334a45a8ff	9204	/***************************** CRC Instances ******************************/
bogdanm	0:9b334a45a8ff	9205	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm	0:9b334a45a8ff	9206
bogdanm	0:9b334a45a8ff	9207	/***************************** DAC Instances ******************************/
bogdanm	0:9b334a45a8ff	9208	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
bogdanm	0:9b334a45a8ff	9209
bogdanm	0:9b334a45a8ff	9210	/**************************** DFSDM Instances *****************************/
bogdanm	0:9b334a45a8ff	9211	#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) \|\| \
bogdanm	0:9b334a45a8ff	9212	((INSTANCE) == DFSDM_Filter1) \|\| \
bogdanm	0:9b334a45a8ff	9213	((INSTANCE) == DFSDM_Filter2) \|\| \
bogdanm	0:9b334a45a8ff	9214	((INSTANCE) == DFSDM_Filter3))
bogdanm	0:9b334a45a8ff	9215
bogdanm	0:9b334a45a8ff	9216	#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) \|\| \
bogdanm	0:9b334a45a8ff	9217	((INSTANCE) == DFSDM_Channel1) \|\| \
bogdanm	0:9b334a45a8ff	9218	((INSTANCE) == DFSDM_Channel2) \|\| \
bogdanm	0:9b334a45a8ff	9219	((INSTANCE) == DFSDM_Channel3) \|\| \
bogdanm	0:9b334a45a8ff	9220	((INSTANCE) == DFSDM_Channel4) \|\| \
bogdanm	0:9b334a45a8ff	9221	((INSTANCE) == DFSDM_Channel5) \|\| \
bogdanm	0:9b334a45a8ff	9222	((INSTANCE) == DFSDM_Channel6) \|\| \
bogdanm	0:9b334a45a8ff	9223	((INSTANCE) == DFSDM_Channel7))
bogdanm	0:9b334a45a8ff	9224
bogdanm	0:9b334a45a8ff	9225	/****************************** DMA Instances *****************************/
bogdanm	0:9b334a45a8ff	9226	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
bogdanm	0:9b334a45a8ff	9227	((INSTANCE) == DMA1_Channel2) \|\| \
bogdanm	0:9b334a45a8ff	9228	((INSTANCE) == DMA1_Channel3) \|\| \
bogdanm	0:9b334a45a8ff	9229	((INSTANCE) == DMA1_Channel4) \|\| \
bogdanm	0:9b334a45a8ff	9230	((INSTANCE) == DMA1_Channel5) \|\| \
bogdanm	0:9b334a45a8ff	9231	((INSTANCE) == DMA1_Channel6) \|\| \
bogdanm	0:9b334a45a8ff	9232	((INSTANCE) == DMA1_Channel7) \|\| \
bogdanm	0:9b334a45a8ff	9233	((INSTANCE) == DMA2_Channel1) \|\| \
bogdanm	0:9b334a45a8ff	9234	((INSTANCE) == DMA2_Channel2) \|\| \
bogdanm	0:9b334a45a8ff	9235	((INSTANCE) == DMA2_Channel3) \|\| \
bogdanm	0:9b334a45a8ff	9236	((INSTANCE) == DMA2_Channel4) \|\| \
bogdanm	0:9b334a45a8ff	9237	((INSTANCE) == DMA2_Channel5) \|\| \
bogdanm	0:9b334a45a8ff	9238	((INSTANCE) == DMA2_Channel6) \|\| \
bogdanm	0:9b334a45a8ff	9239	((INSTANCE) == DMA2_Channel7))
bogdanm	0:9b334a45a8ff	9240
bogdanm	0:9b334a45a8ff	9241	/***************************** GPIO Instances *****************************/
bogdanm	0:9b334a45a8ff	9242	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	0:9b334a45a8ff	9243	((INSTANCE) == GPIOB) \|\| \
bogdanm	0:9b334a45a8ff	9244	((INSTANCE) == GPIOC) \|\| \
bogdanm	0:9b334a45a8ff	9245	((INSTANCE) == GPIOD) \|\| \
bogdanm	0:9b334a45a8ff	9246	((INSTANCE) == GPIOE) \|\| \
bogdanm	0:9b334a45a8ff	9247	((INSTANCE) == GPIOF) \|\| \
bogdanm	0:9b334a45a8ff	9248	((INSTANCE) == GPIOG) \|\| \
bogdanm	0:9b334a45a8ff	9249	((INSTANCE) == GPIOH))
bogdanm	0:9b334a45a8ff	9250
bogdanm	0:9b334a45a8ff	9251	/***************************** GPIO AF Instances **************************/
bogdanm	0:9b334a45a8ff	9252	/* On L4, all GPIO Bank support AF */
bogdanm	0:9b334a45a8ff	9253	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
bogdanm	0:9b334a45a8ff	9254
bogdanm	0:9b334a45a8ff	9255	/************************** GPIO Lock Instances ***************************/
bogdanm	0:9b334a45a8ff	9256	/* On L4, all GPIO Bank support the Lock mechanism */
bogdanm	0:9b334a45a8ff	9257	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
bogdanm	0:9b334a45a8ff	9258
bogdanm	0:9b334a45a8ff	9259	/****************************** I2C Instances *****************************/
bogdanm	0:9b334a45a8ff	9260	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
bogdanm	0:9b334a45a8ff	9261	((INSTANCE) == I2C2) \|\| \
bogdanm	0:9b334a45a8ff	9262	((INSTANCE) == I2C3))
bogdanm	0:9b334a45a8ff	9263
bogdanm	0:9b334a45a8ff	9264	/***************************** LCD Instances ******************************/
bogdanm	0:9b334a45a8ff	9265	#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
bogdanm	0:9b334a45a8ff	9266
bogdanm	0:9b334a45a8ff	9267	/***************************** HCD Instances *****************************/
bogdanm	0:9b334a45a8ff	9268	#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
bogdanm	0:9b334a45a8ff	9269
bogdanm	0:9b334a45a8ff	9270	/**************************** OPAMP Instances *****************************/
bogdanm	0:9b334a45a8ff	9271	#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) \|\| \
bogdanm	0:9b334a45a8ff	9272	((INSTANCE) == OPAMP2))
bogdanm	0:9b334a45a8ff	9273
bogdanm	0:9b334a45a8ff	9274	/***************************** PCD Instances *****************************/
bogdanm	0:9b334a45a8ff	9275	#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
bogdanm	0:9b334a45a8ff	9276
bogdanm	0:9b334a45a8ff	9277	/***************************** QSPI Instances *****************************/
bogdanm	0:9b334a45a8ff	9278	#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
bogdanm	0:9b334a45a8ff	9279
bogdanm	0:9b334a45a8ff	9280	/***************************** RNG Instances ******************************/
bogdanm	0:9b334a45a8ff	9281	#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm	0:9b334a45a8ff	9282
bogdanm	0:9b334a45a8ff	9283	/**************************** RTC Instances *******************************/
bogdanm	0:9b334a45a8ff	9284	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm	0:9b334a45a8ff	9285
bogdanm	0:9b334a45a8ff	9286	/****************************** SAI Instances *****************************/
bogdanm	0:9b334a45a8ff	9287	#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) \|\| \
bogdanm	0:9b334a45a8ff	9288	((INSTANCE) == SAI1_Block_B) \|\| \
bogdanm	0:9b334a45a8ff	9289	((INSTANCE) == SAI2_Block_A) \|\| \
bogdanm	0:9b334a45a8ff	9290	((INSTANCE) == SAI2_Block_B))
bogdanm	0:9b334a45a8ff	9291
bogdanm	0:9b334a45a8ff	9292	/**************************** SDMMC Instances *****************************/
bogdanm	0:9b334a45a8ff	9293	#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
bogdanm	0:9b334a45a8ff	9294
bogdanm	0:9b334a45a8ff	9295	/**************************** SMBUS Instances *****************************/
bogdanm	0:9b334a45a8ff	9296	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
bogdanm	0:9b334a45a8ff	9297	((INSTANCE) == I2C2) \|\| \
bogdanm	0:9b334a45a8ff	9298	((INSTANCE) == I2C3))
bogdanm	0:9b334a45a8ff	9299
bogdanm	0:9b334a45a8ff	9300	/****************************** SPI Instances *****************************/
bogdanm	0:9b334a45a8ff	9301	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
bogdanm	0:9b334a45a8ff	9302	((INSTANCE) == SPI2) \|\| \
bogdanm	0:9b334a45a8ff	9303	((INSTANCE) == SPI3))
bogdanm	0:9b334a45a8ff	9304
bogdanm	0:9b334a45a8ff	9305	/****************************** SWPMI Instances ***************************/
bogdanm	0:9b334a45a8ff	9306	#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
bogdanm	0:9b334a45a8ff	9307
bogdanm	0:9b334a45a8ff	9308	/**************** LPTIM Instances : All supported instances ***************/
bogdanm	0:9b334a45a8ff	9309	#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) \|\| \
bogdanm	0:9b334a45a8ff	9310	((INSTANCE) == LPTIM2))
bogdanm	0:9b334a45a8ff	9311
bogdanm	0:9b334a45a8ff	9312	/**************** TIM Instances : All supported instances *****************/
bogdanm	0:9b334a45a8ff	9313	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9314	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9315	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9316	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9317	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9318	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	9319	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	9320	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9321	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9322	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9323	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9324
bogdanm	0:9b334a45a8ff	9325	/**************** TIM Instances : supporting 32 bits counter **************/
bogdanm	0:9b334a45a8ff	9326	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9327	((INSTANCE) == TIM5))
bogdanm	0:9b334a45a8ff	9328
bogdanm	0:9b334a45a8ff	9329	/**************** TIM Instances : supporting the break function ***********/
bogdanm	0:9b334a45a8ff	9330	#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9331	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9332	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9333	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9334	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9335
bogdanm	0:9b334a45a8ff	9336	/************ TIM Instances : supporting Break source selection ***********/
bogdanm	0:9b334a45a8ff	9337	#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9338	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9339	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9340	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9341	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9342
bogdanm	0:9b334a45a8ff	9343	/**************** TIM Instances : supporting 2 break inputs ***************/
bogdanm	0:9b334a45a8ff	9344	#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9345	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9346
bogdanm	0:9b334a45a8ff	9347	/*********** TIM Instances : at least 1 capture/compare channel ***********/
bogdanm	0:9b334a45a8ff	9348	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9349	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9350	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9351	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9352	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9353	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9354	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9355	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9356	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9357
bogdanm	0:9b334a45a8ff	9358	/********** TIM Instances : at least 2 capture/compare channels ***********/
bogdanm	0:9b334a45a8ff	9359	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9360	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9361	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9362	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9363	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9364	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9365	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9366
bogdanm	0:9b334a45a8ff	9367	/********** TIM Instances : at least 3 capture/compare channels ***********/
bogdanm	0:9b334a45a8ff	9368	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9369	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9370	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9371	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9372	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9373	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9374
bogdanm	0:9b334a45a8ff	9375	/********** TIM Instances : at least 4 capture/compare channels ***********/
bogdanm	0:9b334a45a8ff	9376	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9377	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9378	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9379	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9380	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9381	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9382
bogdanm	0:9b334a45a8ff	9383	/**************** TIM Instances : at least 5 capture/compare channels *****/
bogdanm	0:9b334a45a8ff	9384	#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9385	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9386
bogdanm	0:9b334a45a8ff	9387	/**************** TIM Instances : at least 6 capture/compare channels *****/
bogdanm	0:9b334a45a8ff	9388	#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9389	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9390
bogdanm	0:9b334a45a8ff	9391	/********** TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *****/
bogdanm	0:9b334a45a8ff	9392	#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9393	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9394	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9395	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9396	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9397
bogdanm	0:9b334a45a8ff	9398	/**************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) */
bogdanm	0:9b334a45a8ff	9399	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9400	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9401	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9402	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9403	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9404	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	9405	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	9406	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9407	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9408	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9409	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9410
bogdanm	0:9b334a45a8ff	9411	/********** TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *****/
bogdanm	0:9b334a45a8ff	9412	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9413	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9414	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9415	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9416	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9417	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9418	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9419	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9420	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9421
bogdanm	0:9b334a45a8ff	9422	/****************** TIM Instances : DMA burst feature *********************/
bogdanm	0:9b334a45a8ff	9423	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9424	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9425	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9426	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9427	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9428	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9429	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9430	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9431	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9432
bogdanm	0:9b334a45a8ff	9433	/***************** TIM Instances : output(s) available ********************/
bogdanm	0:9b334a45a8ff	9434	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	9435	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	9436	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9437	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9438	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9439	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	9440	((CHANNEL) == TIM_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	9441	((CHANNEL) == TIM_CHANNEL_6))) \
bogdanm	0:9b334a45a8ff	9442	\|\| \
bogdanm	0:9b334a45a8ff	9443	(((INSTANCE) == TIM2) && \
bogdanm	0:9b334a45a8ff	9444	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9445	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9446	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9447	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	9448	\|\| \
bogdanm	0:9b334a45a8ff	9449	(((INSTANCE) == TIM3) && \
bogdanm	0:9b334a45a8ff	9450	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9451	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9452	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9453	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	9454	\|\| \
bogdanm	0:9b334a45a8ff	9455	(((INSTANCE) == TIM4) && \
bogdanm	0:9b334a45a8ff	9456	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9457	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9458	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9459	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	9460	\|\| \
bogdanm	0:9b334a45a8ff	9461	(((INSTANCE) == TIM5) && \
bogdanm	0:9b334a45a8ff	9462	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9463	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9464	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9465	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	9466	\|\| \
bogdanm	0:9b334a45a8ff	9467	(((INSTANCE) == TIM8) && \
bogdanm	0:9b334a45a8ff	9468	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9469	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9470	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	9471	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	9472	((CHANNEL) == TIM_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	9473	((CHANNEL) == TIM_CHANNEL_6))) \
bogdanm	0:9b334a45a8ff	9474	\|\| \
bogdanm	0:9b334a45a8ff	9475	(((INSTANCE) == TIM15) && \
bogdanm	0:9b334a45a8ff	9476	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9477	((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm	0:9b334a45a8ff	9478	\|\| \
bogdanm	0:9b334a45a8ff	9479	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	9480	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	0:9b334a45a8ff	9481	\|\| \
bogdanm	0:9b334a45a8ff	9482	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	9483	(((CHANNEL) == TIM_CHANNEL_1))))
bogdanm	0:9b334a45a8ff	9484
bogdanm	0:9b334a45a8ff	9485	/**************** TIM Instances : supporting complementary output(s) ******/
bogdanm	0:9b334a45a8ff	9486	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	9487	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	9488	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9489	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9490	((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm	0:9b334a45a8ff	9491	\|\| \
bogdanm	0:9b334a45a8ff	9492	(((INSTANCE) == TIM8) && \
bogdanm	0:9b334a45a8ff	9493	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	9494	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	9495	((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm	0:9b334a45a8ff	9496	\|\| \
bogdanm	0:9b334a45a8ff	9497	(((INSTANCE) == TIM15) && \
bogdanm	0:9b334a45a8ff	9498	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	0:9b334a45a8ff	9499	\|\| \
bogdanm	0:9b334a45a8ff	9500	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	9501	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	0:9b334a45a8ff	9502	\|\| \
bogdanm	0:9b334a45a8ff	9503	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	9504	((CHANNEL) == TIM_CHANNEL_1)))
bogdanm	0:9b334a45a8ff	9505
bogdanm	0:9b334a45a8ff	9506	/**************** TIM Instances : supporting clock division ***************/
bogdanm	0:9b334a45a8ff	9507	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9508	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9509	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9510	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9511	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9512	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9513	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9514	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9515	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9516
bogdanm	0:9b334a45a8ff	9517	/**** TIM Instances : supporting external clock mode 1 for ETRF input *****/
bogdanm	0:9b334a45a8ff	9518	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9519	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9520	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9521	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9522	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9523	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9524	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9525
bogdanm	0:9b334a45a8ff	9526	/**** TIM Instances : supporting external clock mode 2 for ETRF input *****/
bogdanm	0:9b334a45a8ff	9527	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9528	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9529	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9530	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9531	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9532	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9533
bogdanm	0:9b334a45a8ff	9534	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
bogdanm	0:9b334a45a8ff	9535	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9536	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9537	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9538	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9539	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9540	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9541	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9542
bogdanm	0:9b334a45a8ff	9543	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
bogdanm	0:9b334a45a8ff	9544	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9545	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9546	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9547	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9548	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9549	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9550	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9551
bogdanm	0:9b334a45a8ff	9552	/**************** TIM Instances : supporting combined 3-phase PWM mode ****/
bogdanm	0:9b334a45a8ff	9553	#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9554	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9555
bogdanm	0:9b334a45a8ff	9556	/**************** TIM Instances : supporting commutation event generation */
bogdanm	0:9b334a45a8ff	9557	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9558	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9559	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9560	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9561	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9562
bogdanm	0:9b334a45a8ff	9563	/**************** TIM Instances : supporting counting mode selection ******/
bogdanm	0:9b334a45a8ff	9564	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9565	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9566	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9567	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9568	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9569	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9570
bogdanm	0:9b334a45a8ff	9571	/**************** TIM Instances : supporting encoder interface ************/
bogdanm	0:9b334a45a8ff	9572	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9573	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9574	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9575	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9576	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9577	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9578
bogdanm	0:9b334a45a8ff	9579	/************** TIM Instances : external trigger input available **********/
bogdanm	0:9b334a45a8ff	9580	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9581	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9582	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9583	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9584	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9585	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9586
bogdanm	0:9b334a45a8ff	9587	/*********** TIM Instances : supporting ETR source selection *************/
bogdanm	0:9b334a45a8ff	9588	#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9589	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9590	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9591	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9592
bogdanm	0:9b334a45a8ff	9593	/**** TIM Instances : Master mode available (TIMx_CR2.MMS available )******/
bogdanm	0:9b334a45a8ff	9594	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9595	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9596	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9597	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9598	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9599	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	9600	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	9601	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9602	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9603
bogdanm	0:9b334a45a8ff	9604	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
bogdanm	0:9b334a45a8ff	9605	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9606	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9607	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9608	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9609	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9610	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9611	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9612
bogdanm	0:9b334a45a8ff	9613	/**************** TIM Instances : supporting OCxREF clear *****************/
bogdanm	0:9b334a45a8ff	9614	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9615	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9616	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9617	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9618	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9619	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9620
bogdanm	0:9b334a45a8ff	9621	/**************** TIM Instances : remapping capability ********************/
bogdanm	0:9b334a45a8ff	9622	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9623	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9624	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9625	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9626	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9627	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9628	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9629
bogdanm	0:9b334a45a8ff	9630	/**************** TIM Instances : supporting repetition counter ***********/
bogdanm	0:9b334a45a8ff	9631	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9632	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9633	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	9634	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	9635	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	9636
bogdanm	0:9b334a45a8ff	9637	/**************** TIM Instances : supporting synchronization **************/
bogdanm	0:9b334a45a8ff	9638	#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
bogdanm	0:9b334a45a8ff	9639
bogdanm	0:9b334a45a8ff	9640	/**************** TIM Instances : supporting ADC triggering through TRGO2 */
bogdanm	0:9b334a45a8ff	9641	#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9642	((INSTANCE) == TIM8))
bogdanm	0:9b334a45a8ff	9643
bogdanm	0:9b334a45a8ff	9644	/***************** TIM Instances : Timer input XOR function ***************/
bogdanm	0:9b334a45a8ff	9645	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	9646	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	9647	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	9648	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	9649	((INSTANCE) == TIM5) \|\| \
bogdanm	0:9b334a45a8ff	9650	((INSTANCE) == TIM8) \|\| \
bogdanm	0:9b334a45a8ff	9651	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	9652
bogdanm	0:9b334a45a8ff	9653	/**************************** TSC Instances *******************************/
bogdanm	0:9b334a45a8ff	9654	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
bogdanm	0:9b334a45a8ff	9655
bogdanm	0:9b334a45a8ff	9656	/****************** UART Instances : Asynchronous mode ********************/
bogdanm	0:9b334a45a8ff	9657	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9658	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9659	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9660	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9661	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9662	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9663
bogdanm	0:9b334a45a8ff	9664
bogdanm	0:9b334a45a8ff	9665	/****************** USART Instances : Synchronous mode ********************/
bogdanm	0:9b334a45a8ff	9666	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9667	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9668	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	9669
bogdanm	0:9b334a45a8ff	9670	/**************** UART Instances : Hardware Flow control ******************/
bogdanm	0:9b334a45a8ff	9671	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9672	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9673	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9674	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9675	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9676	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9677
bogdanm	0:9b334a45a8ff	9678
bogdanm	0:9b334a45a8ff	9679	/******************* USART Instances : Smard card mode *********************/
bogdanm	0:9b334a45a8ff	9680	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9681	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9682	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	9683
bogdanm	0:9b334a45a8ff	9684	/**************** UART Instances : Auto Baud Rate detection **************/
bogdanm	0:9b334a45a8ff	9685	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9686	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9687	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9688	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9689	((INSTANCE) == UART5))
bogdanm	0:9b334a45a8ff	9690
bogdanm	0:9b334a45a8ff	9691	/****************** UART Instances : Half-Duplex mode ********************/
bogdanm	0:9b334a45a8ff	9692	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9693	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9694	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9695	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9696	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9697	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9698
bogdanm	0:9b334a45a8ff	9699	/****************** UART Instances : LIN mode ********************/
bogdanm	0:9b334a45a8ff	9700	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9701	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9702	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9703	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9704	((INSTANCE) == UART5))
bogdanm	0:9b334a45a8ff	9705
bogdanm	0:9b334a45a8ff	9706	/****************** UART Instances : Wake-up from Stop mode ********************/
bogdanm	0:9b334a45a8ff	9707	#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9708	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9709	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9710	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9711	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9712	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9713
bogdanm	0:9b334a45a8ff	9714	/**************** UART Instances : Driver Enable ***************/
bogdanm	0:9b334a45a8ff	9715	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9716	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9717	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9718	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9719	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9720	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9721
bogdanm	0:9b334a45a8ff	9722	/****************** UART Instances : Half-Duplex mode ********************/
bogdanm	0:9b334a45a8ff	9723	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9724	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9725	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9726	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9727	((INSTANCE) == UART5) \|\| \
bogdanm	0:9b334a45a8ff	9728	((INSTANCE) == LPUART1))
bogdanm	0:9b334a45a8ff	9729
bogdanm	0:9b334a45a8ff	9730	/****************** UART Instances : LIN mode ********************/
bogdanm	0:9b334a45a8ff	9731	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9732	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9733	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9734	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9735	((INSTANCE) == UART5))
bogdanm	0:9b334a45a8ff	9736
bogdanm	0:9b334a45a8ff	9737	/********************* UART Instances : IRDA mode *************************/
bogdanm	0:9b334a45a8ff	9738	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	9739	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	9740	((INSTANCE) == USART3) \|\| \
bogdanm	0:9b334a45a8ff	9741	((INSTANCE) == UART4) \|\| \
bogdanm	0:9b334a45a8ff	9742	((INSTANCE) == UART5))
bogdanm	0:9b334a45a8ff	9743
bogdanm	0:9b334a45a8ff	9744	/**************************** IWDG Instances ******************************/
bogdanm	0:9b334a45a8ff	9745	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm	0:9b334a45a8ff	9746
bogdanm	0:9b334a45a8ff	9747	/**************************** WWDG Instances ******************************/
bogdanm	0:9b334a45a8ff	9748	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm	0:9b334a45a8ff	9749
bogdanm	0:9b334a45a8ff	9750	/**
bogdanm	0:9b334a45a8ff	9751	* @}
bogdanm	0:9b334a45a8ff	9752	*/
bogdanm	0:9b334a45a8ff	9753
bogdanm	0:9b334a45a8ff	9754
bogdanm	0:9b334a45a8ff	9755	/******************************************************************************/
bogdanm	0:9b334a45a8ff	9756	/* For a painless codes migration between the STM32L4xx device product */
bogdanm	0:9b334a45a8ff	9757	/* lines, the aliases defined below are put in place to overcome the */
bogdanm	0:9b334a45a8ff	9758	/* differences in the interrupt handlers and IRQn definitions. */
bogdanm	0:9b334a45a8ff	9759	/* No need to update developed interrupt code when moving across */
bogdanm	0:9b334a45a8ff	9760	/* product lines within the same STM32L4 Family */
bogdanm	0:9b334a45a8ff	9761	/******************************************************************************/
bogdanm	0:9b334a45a8ff	9762
bogdanm	0:9b334a45a8ff	9763	/* Aliases for __IRQn */
bogdanm	0:9b334a45a8ff	9764	#define TIM8_IRQn TIM8_UP_IRQn
bogdanm	0:9b334a45a8ff	9765
bogdanm	0:9b334a45a8ff	9766	/* Aliases for __IRQHandler */
bogdanm	0:9b334a45a8ff	9767	#define TIM8_IRQHandler TIM8_UP_IRQHandler
bogdanm	0:9b334a45a8ff	9768
bogdanm	0:9b334a45a8ff	9769
bogdanm	0:9b334a45a8ff	9770	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	9771	}
bogdanm	0:9b334a45a8ff	9772	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	9773
bogdanm	0:9b334a45a8ff	9774	#endif /* __STM32L476xx_H */
bogdanm	0:9b334a45a8ff	9775
bogdanm	0:9b334a45a8ff	9776	/**
bogdanm	0:9b334a45a8ff	9777	* @}
bogdanm	0:9b334a45a8ff	9778	*/
bogdanm	0:9b334a45a8ff	9779
bogdanm	0:9b334a45a8ff	9780	/**
bogdanm	0:9b334a45a8ff	9781	* @}
bogdanm	0:9b334a45a8ff	9782	*/
bogdanm	0:9b334a45a8ff	9783
bogdanm	0:9b334a45a8ff	9784	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/stm32l476xx.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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