en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l1xx_ll_fsmc.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 5-September-2014
bogdanm 0:9b334a45a8ff 7 * @brief Header file of FSMC HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L1xx_LL_FSMC_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L1xx_LL_FSMC_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 49 #include "stm32l1xx_hal_def.h"
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** @addtogroup STM32L1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 52 * @{
bogdanm 0:9b334a45a8ff 53 */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 /** @addtogroup FSMC_LL
bogdanm 0:9b334a45a8ff 56 * @{
bogdanm 0:9b334a45a8ff 57 */
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef
bogdanm 0:9b334a45a8ff 62 * @{
bogdanm 0:9b334a45a8ff 63 */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 #define FSMC_NORSRAM_TYPEDEF FSMC_Bank1_TypeDef
bogdanm 0:9b334a45a8ff 66 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_Bank1E_TypeDef
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
bogdanm 0:9b334a45a8ff 69 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /**
bogdanm 0:9b334a45a8ff 72 * @brief FSMC_NORSRAM Configuration Structure definition
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74 typedef struct
bogdanm 0:9b334a45a8ff 75 {
bogdanm 0:9b334a45a8ff 76 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 0:9b334a45a8ff 77 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 0:9b334a45a8ff 80 multiplexed on the data bus or not.
bogdanm 0:9b334a45a8ff 81 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 0:9b334a45a8ff 84 the corresponding memory device.
bogdanm 0:9b334a45a8ff 85 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 0:9b334a45a8ff 88 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 0:9b334a45a8ff 91 valid only with synchronous burst Flash memories.
bogdanm 0:9b334a45a8ff 92 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 0:9b334a45a8ff 95 the Flash memory in burst mode.
bogdanm 0:9b334a45a8ff 96 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 0:9b334a45a8ff 99 memory, valid only when accessing Flash memories in burst mode.
bogdanm 0:9b334a45a8ff 100 This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 0:9b334a45a8ff 103 clock cycle before the wait state or during the wait state,
bogdanm 0:9b334a45a8ff 104 valid only when accessing memories in burst mode.
bogdanm 0:9b334a45a8ff 105 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm 0:9b334a45a8ff 108 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 0:9b334a45a8ff 111 signal, valid for Flash memory access in burst mode.
bogdanm 0:9b334a45a8ff 112 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 0:9b334a45a8ff 115 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 0:9b334a45a8ff 118 valid only with asynchronous Flash memories.
bogdanm 0:9b334a45a8ff 119 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 0:9b334a45a8ff 122 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 }FSMC_NORSRAM_InitTypeDef;
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /**
bogdanm 0:9b334a45a8ff 128 * @brief FSMC_NORSRAM Timing parameters structure definition
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130 typedef struct
bogdanm 0:9b334a45a8ff 131 {
bogdanm 0:9b334a45a8ff 132 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 0:9b334a45a8ff 133 the duration of the address setup time.
bogdanm 0:9b334a45a8ff 134 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 0:9b334a45a8ff 135 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 0:9b334a45a8ff 138 the duration of the address hold time.
bogdanm 0:9b334a45a8ff 139 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 0:9b334a45a8ff 140 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 0:9b334a45a8ff 143 the duration of the data setup time.
bogdanm 0:9b334a45a8ff 144 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 0:9b334a45a8ff 145 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 0:9b334a45a8ff 146 NOR Flash memories. */
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 0:9b334a45a8ff 149 the duration of the bus turnaround.
bogdanm 0:9b334a45a8ff 150 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 0:9b334a45a8ff 151 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 0:9b334a45a8ff 154 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 0:9b334a45a8ff 155 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 0:9b334a45a8ff 156 accesses. */
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 0:9b334a45a8ff 159 to the memory before getting the first data.
bogdanm 0:9b334a45a8ff 160 The parameter value depends on the memory type as shown below:
bogdanm 0:9b334a45a8ff 161 - It must be set to 0 in case of a CRAM
bogdanm 0:9b334a45a8ff 162 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 0:9b334a45a8ff 163 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 0:9b334a45a8ff 164 with synchronous burst mode enable */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 0:9b334a45a8ff 167 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 }FSMC_NORSRAM_TimingTypeDef;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /**
bogdanm 0:9b334a45a8ff 172 * @}
bogdanm 0:9b334a45a8ff 173 */
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
bogdanm 0:9b334a45a8ff 178 * @{
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
bogdanm 0:9b334a45a8ff 182 * @{
bogdanm 0:9b334a45a8ff 183 */
bogdanm 0:9b334a45a8ff 184 #define FSMC_BANK1_NORSRAM1 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 185 #define FSMC_BANK1_NORSRAM2 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 186 #define FSMC_BANK1_NORSRAM3 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 187 #define FSMC_BANK1_NORSRAM4 ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* To keep compatibility with previous families */
bogdanm 0:9b334a45a8ff 190 #define FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM1
bogdanm 0:9b334a45a8ff 191 #define FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM2
bogdanm 0:9b334a45a8ff 192 #define FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM3
bogdanm 0:9b334a45a8ff 193 #define FSMC_NORSRAM_BANK4 FSMC_BANK1_NORSRAM4
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \
bogdanm 0:9b334a45a8ff 196 ((__BANK__) == FSMC_BANK1_NORSRAM2) || \
bogdanm 0:9b334a45a8ff 197 ((__BANK__) == FSMC_BANK1_NORSRAM3) || \
bogdanm 0:9b334a45a8ff 198 ((__BANK__) == FSMC_BANK1_NORSRAM4))
bogdanm 0:9b334a45a8ff 199 /**
bogdanm 0:9b334a45a8ff 200 * @}
bogdanm 0:9b334a45a8ff 201 */
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
bogdanm 0:9b334a45a8ff 204 * @{
bogdanm 0:9b334a45a8ff 205 */
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 208 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
bogdanm 0:9b334a45a8ff 211 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm 0:9b334a45a8ff 212 /**
bogdanm 0:9b334a45a8ff 213 * @}
bogdanm 0:9b334a45a8ff 214 */
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /** @defgroup FSMC_Memory_Type FSMC Memory Type
bogdanm 0:9b334a45a8ff 217 * @{
bogdanm 0:9b334a45a8ff 218 */
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 221 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
bogdanm 0:9b334a45a8ff 222 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
bogdanm 0:9b334a45a8ff 226 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
bogdanm 0:9b334a45a8ff 227 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
bogdanm 0:9b334a45a8ff 228 /**
bogdanm 0:9b334a45a8ff 229 * @}
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
bogdanm 0:9b334a45a8ff 233 * @{
bogdanm 0:9b334a45a8ff 234 */
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 237 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
bogdanm 0:9b334a45a8ff 238 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
bogdanm 0:9b334a45a8ff 241 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
bogdanm 0:9b334a45a8ff 242 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @}
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
bogdanm 0:9b334a45a8ff 248 * @{
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
bogdanm 0:9b334a45a8ff 252 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 253 /**
bogdanm 0:9b334a45a8ff 254 * @}
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
bogdanm 0:9b334a45a8ff 258 * @{
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 262 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
bogdanm 0:9b334a45a8ff 265 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
bogdanm 0:9b334a45a8ff 266 /**
bogdanm 0:9b334a45a8ff 267 * @}
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
bogdanm 0:9b334a45a8ff 272 * @{
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 276 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
bogdanm 0:9b334a45a8ff 279 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @}
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
bogdanm 0:9b334a45a8ff 285 * @{
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 289 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
bogdanm 0:9b334a45a8ff 292 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
bogdanm 0:9b334a45a8ff 293 /**
bogdanm 0:9b334a45a8ff 294 * @}
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
bogdanm 0:9b334a45a8ff 298 * @{
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 302 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
bogdanm 0:9b334a45a8ff 305 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
bogdanm 0:9b334a45a8ff 306 /**
bogdanm 0:9b334a45a8ff 307 * @}
bogdanm 0:9b334a45a8ff 308 */
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /** @defgroup FSMC_Write_Operation FSMC Write Operation
bogdanm 0:9b334a45a8ff 311 * @{
bogdanm 0:9b334a45a8ff 312 */
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 315 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
bogdanm 0:9b334a45a8ff 318 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
bogdanm 0:9b334a45a8ff 319 /**
bogdanm 0:9b334a45a8ff 320 * @}
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
bogdanm 0:9b334a45a8ff 324 * @{
bogdanm 0:9b334a45a8ff 325 */
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 328 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
bogdanm 0:9b334a45a8ff 331 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /**
bogdanm 0:9b334a45a8ff 334 * @}
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
bogdanm 0:9b334a45a8ff 338 * @{
bogdanm 0:9b334a45a8ff 339 */
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 342 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
bogdanm 0:9b334a45a8ff 345 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
bogdanm 0:9b334a45a8ff 346 /**
bogdanm 0:9b334a45a8ff 347 * @}
bogdanm 0:9b334a45a8ff 348 */
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
bogdanm 0:9b334a45a8ff 351 * @{
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 355 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
bogdanm 0:9b334a45a8ff 358 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /**
bogdanm 0:9b334a45a8ff 361 * @}
bogdanm 0:9b334a45a8ff 362 */
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /** @defgroup FSMC_Write_Burst FSMC Write Burst
bogdanm 0:9b334a45a8ff 365 * @{
bogdanm 0:9b334a45a8ff 366 */
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 369 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
bogdanm 0:9b334a45a8ff 372 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @}
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
bogdanm 0:9b334a45a8ff 378 * @{
bogdanm 0:9b334a45a8ff 379 */
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @}
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
bogdanm 0:9b334a45a8ff 387 * @{
bogdanm 0:9b334a45a8ff 388 */
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
bogdanm 0:9b334a45a8ff 391 /**
bogdanm 0:9b334a45a8ff 392 * @}
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
bogdanm 0:9b334a45a8ff 396 * @{
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
bogdanm 0:9b334a45a8ff 400 /**
bogdanm 0:9b334a45a8ff 401 * @}
bogdanm 0:9b334a45a8ff 402 */
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
bogdanm 0:9b334a45a8ff 405 * @{
bogdanm 0:9b334a45a8ff 406 */
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
bogdanm 0:9b334a45a8ff 409 /**
bogdanm 0:9b334a45a8ff 410 * @}
bogdanm 0:9b334a45a8ff 411 */
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /** @defgroup FSMC_CLK_Division FSMC CLK Division
bogdanm 0:9b334a45a8ff 414 * @{
bogdanm 0:9b334a45a8ff 415 */
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 #define FSMC_CLK_DIV2 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 418 #define FSMC_CLK_DIV3 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 419 #define FSMC_CLK_DIV4 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 420 #define FSMC_CLK_DIV5 ((uint32_t)0x00000005)
bogdanm 0:9b334a45a8ff 421 #define FSMC_CLK_DIV6 ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 422 #define FSMC_CLK_DIV7 ((uint32_t)0x00000007)
bogdanm 0:9b334a45a8ff 423 #define FSMC_CLK_DIV8 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 424 #define FSMC_CLK_DIV9 ((uint32_t)0x00000009)
bogdanm 0:9b334a45a8ff 425 #define FSMC_CLK_DIV10 ((uint32_t)0x0000000A)
bogdanm 0:9b334a45a8ff 426 #define FSMC_CLK_DIV11 ((uint32_t)0x0000000B)
bogdanm 0:9b334a45a8ff 427 #define FSMC_CLK_DIV12 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 428 #define FSMC_CLK_DIV13 ((uint32_t)0x0000000D)
bogdanm 0:9b334a45a8ff 429 #define FSMC_CLK_DIV14 ((uint32_t)0x0000000E)
bogdanm 0:9b334a45a8ff 430 #define FSMC_CLK_DIV15 ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 431 #define FSMC_CLK_DIV16 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 432 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
bogdanm 0:9b334a45a8ff 433 /**
bogdanm 0:9b334a45a8ff 434 * @}
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /** @defgroup FSMC_Data_Latency FSMC Data Latency
bogdanm 0:9b334a45a8ff 438 * @{
bogdanm 0:9b334a45a8ff 439 */
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
bogdanm 0:9b334a45a8ff 442 /**
bogdanm 0:9b334a45a8ff 443 * @}
bogdanm 0:9b334a45a8ff 444 */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /** @defgroup FSMC_Access_Mode FSMC Access Mode
bogdanm 0:9b334a45a8ff 447 * @{
bogdanm 0:9b334a45a8ff 448 */
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 451 #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
bogdanm 0:9b334a45a8ff 452 #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
bogdanm 0:9b334a45a8ff 453 #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
bogdanm 0:9b334a45a8ff 456 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
bogdanm 0:9b334a45a8ff 457 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
bogdanm 0:9b334a45a8ff 458 ((__MODE__) == FSMC_ACCESS_MODE_D))
bogdanm 0:9b334a45a8ff 459 /**
bogdanm 0:9b334a45a8ff 460 * @}
bogdanm 0:9b334a45a8ff 461 */
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
bogdanm 0:9b334a45a8ff 464 * @{
bogdanm 0:9b334a45a8ff 465 */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /**
bogdanm 0:9b334a45a8ff 470 * @}
bogdanm 0:9b334a45a8ff 471 */
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
bogdanm 0:9b334a45a8ff 474 * @{
bogdanm 0:9b334a45a8ff 475 */
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /**
bogdanm 0:9b334a45a8ff 480 * @}
bogdanm 0:9b334a45a8ff 481 */
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @}
bogdanm 0:9b334a45a8ff 485 */
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
bogdanm 0:9b334a45a8ff 490 * @brief macros to handle NOR device enable/disable and read/write operations
bogdanm 0:9b334a45a8ff 491 * @{
bogdanm 0:9b334a45a8ff 492 */
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /**
bogdanm 0:9b334a45a8ff 495 * @brief Enable the NORSRAM device access.
bogdanm 0:9b334a45a8ff 496 * @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm 0:9b334a45a8ff 497 * @param __BANK__: FSMC_NORSRAM Bank
bogdanm 0:9b334a45a8ff 498 * @retval none
bogdanm 0:9b334a45a8ff 499 */
bogdanm 0:9b334a45a8ff 500 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /**
bogdanm 0:9b334a45a8ff 503 * @brief Disable the NORSRAM device access.
bogdanm 0:9b334a45a8ff 504 * @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm 0:9b334a45a8ff 505 * @param __BANK__: FSMC_NORSRAM Bank
bogdanm 0:9b334a45a8ff 506 * @retval none
bogdanm 0:9b334a45a8ff 507 */
bogdanm 0:9b334a45a8ff 508 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /**
bogdanm 0:9b334a45a8ff 511 * @}
bogdanm 0:9b334a45a8ff 512 */
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /** @addtogroup FSMC_Exported_Functions
bogdanm 0:9b334a45a8ff 517 * @{
bogdanm 0:9b334a45a8ff 518 */
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /** @addtogroup HAL_FSMC_NORSRAM_Group1
bogdanm 0:9b334a45a8ff 521 * @{
bogdanm 0:9b334a45a8ff 522 */
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* FSMC_NORSRAM Controller functions ******************************************/
bogdanm 0:9b334a45a8ff 525 /* Initialization/de-initialization functions */
bogdanm 0:9b334a45a8ff 526 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init);
bogdanm 0:9b334a45a8ff 527 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 0:9b334a45a8ff 528 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm 0:9b334a45a8ff 529 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank);
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /**
bogdanm 0:9b334a45a8ff 532 * @}
bogdanm 0:9b334a45a8ff 533 */
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 /** @addtogroup HAL_FSMC_NORSRAM_Group2
bogdanm 0:9b334a45a8ff 536 * @{
bogdanm 0:9b334a45a8ff 537 */
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* FSMC_NORSRAM Control functions */
bogdanm 0:9b334a45a8ff 540 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
bogdanm 0:9b334a45a8ff 541 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 /**
bogdanm 0:9b334a45a8ff 544 * @}
bogdanm 0:9b334a45a8ff 545 */
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /**
bogdanm 0:9b334a45a8ff 550 * @}
bogdanm 0:9b334a45a8ff 551 */
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /**
bogdanm 0:9b334a45a8ff 554 * @}
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /**
bogdanm 0:9b334a45a8ff 558 * @}
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563 #endif
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 #endif /* __STM32L1xx_LL_FSMC_H */
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/