en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l1xx_ll_fsmc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 5-September-2014
bogdanm 0:9b334a45a8ff 7 * @brief FSMC Low Layer HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 =============================================================================
bogdanm 0:9b334a45a8ff 17 ##### FSMC peripheral features #####
bogdanm 0:9b334a45a8ff 18 =============================================================================
bogdanm 0:9b334a45a8ff 19 [..] The Flexible static memory controller (FSMC) includes following memory controllers:
bogdanm 0:9b334a45a8ff 20 (+) The NOR/PSRAM memory controller
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
bogdanm 0:9b334a45a8ff 23 memories and SDRAM memories. Its main purposes are:
bogdanm 0:9b334a45a8ff 24 (+) to translate AHB transactions into the appropriate external device protocol.
bogdanm 0:9b334a45a8ff 25 (+) to meet the access time requirements of the external memory devices.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 [..] All external memories share the addresses, data and control signals with the controller.
bogdanm 0:9b334a45a8ff 28 Each external device is accessed by means of a unique Chip Select. The FSMC performs
bogdanm 0:9b334a45a8ff 29 only one access at a time to an external device.
bogdanm 0:9b334a45a8ff 30 The main features of the FSMC controller are the following:
bogdanm 0:9b334a45a8ff 31 (+) Interface with static-memory mapped devices including:
bogdanm 0:9b334a45a8ff 32 (++) Static random access memory (SRAM).
bogdanm 0:9b334a45a8ff 33 (++) NOR Flash memory.
bogdanm 0:9b334a45a8ff 34 (++) PSRAM (4 memory banks).
bogdanm 0:9b334a45a8ff 35 (+) Independent Chip Select control for each memory bank.
bogdanm 0:9b334a45a8ff 36 (+) Independent configuration for each memory bank.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 =============================================================================
bogdanm 0:9b334a45a8ff 39 ##### How to use NORSRAM device driver #####
bogdanm 0:9b334a45a8ff 40 =============================================================================
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
bogdanm 0:9b334a45a8ff 44 to run the NORSRAM external devices.
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
bogdanm 0:9b334a45a8ff 47 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
bogdanm 0:9b334a45a8ff 48 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 49 (+) FSMC NORSRAM bank extended timing configuration using the function
bogdanm 0:9b334a45a8ff 50 FSMC_NORSRAM_Extended_Timing_Init()
bogdanm 0:9b334a45a8ff 51 (+) FSMC NORSRAM bank enable/disable write operation using the functions
bogdanm 0:9b334a45a8ff 52 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32l1xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32L1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /** @defgroup FSMC_LL FSMC_LL
bogdanm 0:9b334a45a8ff 93 * @brief FSMC driver modules
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED)
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 104 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 105 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 106 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /** @defgroup FSMC_Exported_Functions FSMC Exported Functions
bogdanm 0:9b334a45a8ff 109 * @{
bogdanm 0:9b334a45a8ff 110 */
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 113 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 114 *
bogdanm 0:9b334a45a8ff 115 @verbatim
bogdanm 0:9b334a45a8ff 116 ==============================================================================
bogdanm 0:9b334a45a8ff 117 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 118 ==============================================================================
bogdanm 0:9b334a45a8ff 119 [..]
bogdanm 0:9b334a45a8ff 120 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 121 (+) Initialize and configure the FSMC NORSRAM interface
bogdanm 0:9b334a45a8ff 122 (+) De-initialize the FSMC NORSRAM interface
bogdanm 0:9b334a45a8ff 123 (+) Configure the FSMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 @endverbatim
bogdanm 0:9b334a45a8ff 126 * @{
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /**
bogdanm 0:9b334a45a8ff 130 * @brief Initialize the FSMC_NORSRAM device according to the specified
bogdanm 0:9b334a45a8ff 131 * control parameters in the FSMC_NORSRAM_InitTypeDef
bogdanm 0:9b334a45a8ff 132 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 133 * @param Init: Pointer to NORSRAM Initialization structure
bogdanm 0:9b334a45a8ff 134 * @retval HAL status
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init)
bogdanm 0:9b334a45a8ff 137 {
bogdanm 0:9b334a45a8ff 138 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /* Check the parameters */
bogdanm 0:9b334a45a8ff 141 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
bogdanm 0:9b334a45a8ff 142 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
bogdanm 0:9b334a45a8ff 143 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
bogdanm 0:9b334a45a8ff 144 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm 0:9b334a45a8ff 145 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
bogdanm 0:9b334a45a8ff 146 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
bogdanm 0:9b334a45a8ff 147 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
bogdanm 0:9b334a45a8ff 148 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
bogdanm 0:9b334a45a8ff 149 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
bogdanm 0:9b334a45a8ff 150 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
bogdanm 0:9b334a45a8ff 151 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
bogdanm 0:9b334a45a8ff 152 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
bogdanm 0:9b334a45a8ff 153 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* Set NORSRAM device control parameters */
bogdanm 0:9b334a45a8ff 156 tmpr = (uint32_t)(Init->DataAddressMux |\
bogdanm 0:9b334a45a8ff 157 Init->MemoryType |\
bogdanm 0:9b334a45a8ff 158 Init->MemoryDataWidth |\
bogdanm 0:9b334a45a8ff 159 Init->BurstAccessMode |\
bogdanm 0:9b334a45a8ff 160 Init->WaitSignalPolarity |\
bogdanm 0:9b334a45a8ff 161 Init->WrapMode |\
bogdanm 0:9b334a45a8ff 162 Init->WaitSignalActive |\
bogdanm 0:9b334a45a8ff 163 Init->WriteOperation |\
bogdanm 0:9b334a45a8ff 164 Init->WaitSignal |\
bogdanm 0:9b334a45a8ff 165 Init->ExtendedMode |\
bogdanm 0:9b334a45a8ff 166 Init->AsynchronousWait |\
bogdanm 0:9b334a45a8ff 167 Init->WriteBurst
bogdanm 0:9b334a45a8ff 168 );
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
bogdanm 0:9b334a45a8ff 171 {
bogdanm 0:9b334a45a8ff 172 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
bogdanm 0:9b334a45a8ff 173 }
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 Device->BTCR[Init->NSBank] = tmpr;
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 return HAL_OK;
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /**
bogdanm 0:9b334a45a8ff 182 * @brief DeInitialize the FSMC_NORSRAM peripheral
bogdanm 0:9b334a45a8ff 183 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 184 * @param ExDevice: Pointer to NORSRAM extended mode device instance
bogdanm 0:9b334a45a8ff 185 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 186 * @retval HAL status
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank)
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 /* Check the parameters */
bogdanm 0:9b334a45a8ff 191 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 192 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Disable the FSMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 195 __FSMC_NORSRAM_DISABLE(Device, Bank);
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* De-initialize the FSMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 198 /* FSMC_NORSRAM_BANK1 */
bogdanm 0:9b334a45a8ff 199 if(Bank == FSMC_BANK1_NORSRAM1)
bogdanm 0:9b334a45a8ff 200 {
bogdanm 0:9b334a45a8ff 201 Device->BTCR[Bank] = 0x000030DB;
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203 /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */
bogdanm 0:9b334a45a8ff 204 else
bogdanm 0:9b334a45a8ff 205 {
bogdanm 0:9b334a45a8ff 206 Device->BTCR[Bank] = 0x000030D2;
bogdanm 0:9b334a45a8ff 207 }
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 210 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 return HAL_OK;
bogdanm 0:9b334a45a8ff 213 }
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /**
bogdanm 0:9b334a45a8ff 217 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
bogdanm 0:9b334a45a8ff 218 * parameters in the FSMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 219 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 220 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 221 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 222 * @retval HAL status
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Check the parameters */
bogdanm 0:9b334a45a8ff 229 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 230 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 231 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 232 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 233 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
bogdanm 0:9b334a45a8ff 234 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
bogdanm 0:9b334a45a8ff 235 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /* Set FSMC_NORSRAM device timing parameters */
bogdanm 0:9b334a45a8ff 238 tmpr = (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 239 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) |\
bogdanm 0:9b334a45a8ff 240 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) |\
bogdanm 0:9b334a45a8ff 241 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) |\
bogdanm 0:9b334a45a8ff 242 (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) |\
bogdanm 0:9b334a45a8ff 243 (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) |\
bogdanm 0:9b334a45a8ff 244 (Timing->AccessMode)
bogdanm 0:9b334a45a8ff 245 );
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 Device->BTCR[Bank + 1] = tmpr;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 return HAL_OK;
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /**
bogdanm 0:9b334a45a8ff 253 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
bogdanm 0:9b334a45a8ff 254 * parameters in the FSMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 255 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 256 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 257 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 258 * @param ExtendedMode: FSMC Extended Mode
bogdanm 0:9b334a45a8ff 259 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 260 * @arg FSMC_EXTENDED_MODE_DISABLE
bogdanm 0:9b334a45a8ff 261 * @arg FSMC_EXTENDED_MODE_ENABLE
bogdanm 0:9b334a45a8ff 262 * @retval HAL status
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
bogdanm 0:9b334a45a8ff 265 {
bogdanm 0:9b334a45a8ff 266 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
bogdanm 0:9b334a45a8ff 267 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 /* Check the parameters */
bogdanm 0:9b334a45a8ff 270 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 271 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 272 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 273 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 274 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 277 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) |\
bogdanm 0:9b334a45a8ff 278 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) |\
bogdanm 0:9b334a45a8ff 279 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)) |\
bogdanm 0:9b334a45a8ff 280 (Timing->AccessMode));
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282 else
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 Device->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 return HAL_OK;
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @}
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions
bogdanm 0:9b334a45a8ff 297 * @brief management functions
bogdanm 0:9b334a45a8ff 298 *
bogdanm 0:9b334a45a8ff 299 @verbatim
bogdanm 0:9b334a45a8ff 300 ==============================================================================
bogdanm 0:9b334a45a8ff 301 ##### FSMC_NORSRAM Control functions #####
bogdanm 0:9b334a45a8ff 302 ==============================================================================
bogdanm 0:9b334a45a8ff 303 [..]
bogdanm 0:9b334a45a8ff 304 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 305 the FSMC NORSRAM interface.
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 @endverbatim
bogdanm 0:9b334a45a8ff 308 * @{
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /**
bogdanm 0:9b334a45a8ff 312 * @brief Enables dynamically FSMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 313 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 314 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 315 * @retval HAL status
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 /* Enable write operation */
bogdanm 0:9b334a45a8ff 320 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 return HAL_OK;
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /**
bogdanm 0:9b334a45a8ff 326 * @brief Disables dynamically FSMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 327 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 328 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 329 * @retval HAL status
bogdanm 0:9b334a45a8ff 330 */
bogdanm 0:9b334a45a8ff 331 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 332 {
bogdanm 0:9b334a45a8ff 333 /* Disable write operation */
bogdanm 0:9b334a45a8ff 334 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 return HAL_OK;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /**
bogdanm 0:9b334a45a8ff 340 * @}
bogdanm 0:9b334a45a8ff 341 */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /**
bogdanm 0:9b334a45a8ff 344 * @}
bogdanm 0:9b334a45a8ff 345 */
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 #endif /* HAL_FSMC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /**
bogdanm 0:9b334a45a8ff 352 * @}
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /**
bogdanm 0:9b334a45a8ff 356 * @}
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/