mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l1xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 5-September-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L1xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L1xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l1xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64	typedef struct
bogdanm	0:9b334a45a8ff	65	{
bogdanm	0:9b334a45a8ff	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	70	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	73	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	77	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	/**
bogdanm	0:9b334a45a8ff	82	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	83	*/
bogdanm	0:9b334a45a8ff	84	typedef struct
bogdanm	0:9b334a45a8ff	85	{
bogdanm	0:9b334a45a8ff	86	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	87	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	90	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	93	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	96	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	97	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	100	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	101	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	102	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/**
bogdanm	0:9b334a45a8ff	105	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	106	*/
bogdanm	0:9b334a45a8ff	107	typedef struct
bogdanm	0:9b334a45a8ff	108	{
bogdanm	0:9b334a45a8ff	109	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	110	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	113	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	116	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	119	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	120	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	123	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	126	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	129	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	130	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	/**
bogdanm	0:9b334a45a8ff	134	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	135	*/
bogdanm	0:9b334a45a8ff	136	typedef struct
bogdanm	0:9b334a45a8ff	137	{
bogdanm	0:9b334a45a8ff	138	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	139	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	142	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	145	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	148	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	149	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/**
bogdanm	0:9b334a45a8ff	152	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	153	*/
bogdanm	0:9b334a45a8ff	154	typedef struct
bogdanm	0:9b334a45a8ff	155	{
bogdanm	0:9b334a45a8ff	156	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	157	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	160	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	163	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	166	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	169	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	172	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	175	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	178	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	181	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	182	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	/**
bogdanm	0:9b334a45a8ff	186	* @brief Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	187	*/
bogdanm	0:9b334a45a8ff	188	typedef struct
bogdanm	0:9b334a45a8ff	189	{
bogdanm	0:9b334a45a8ff	190	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	0:9b334a45a8ff	191	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	192	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	0:9b334a45a8ff	193	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	194	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	0:9b334a45a8ff	195	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	196	uint32_t ClockFilter; /*!< TIM clock filter
bogdanm	0:9b334a45a8ff	197	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	198	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/**
bogdanm	0:9b334a45a8ff	201	* @brief Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	202	*/
bogdanm	0:9b334a45a8ff	203	typedef struct
bogdanm	0:9b334a45a8ff	204	{
bogdanm	0:9b334a45a8ff	205	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	0:9b334a45a8ff	206	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	207	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	0:9b334a45a8ff	208	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	0:9b334a45a8ff	209	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	0:9b334a45a8ff	210	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	211	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	0:9b334a45a8ff	212	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	213	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm	0:9b334a45a8ff	214	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	215	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	/**
bogdanm	0:9b334a45a8ff	218	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	219	*/
bogdanm	0:9b334a45a8ff	220	typedef struct {
bogdanm	0:9b334a45a8ff	221	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	0:9b334a45a8ff	222	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	0:9b334a45a8ff	223	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	0:9b334a45a8ff	224	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	225	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	0:9b334a45a8ff	226	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	227	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	0:9b334a45a8ff	228	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	229	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	0:9b334a45a8ff	230	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/**
bogdanm	0:9b334a45a8ff	235	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	236	*/
bogdanm	0:9b334a45a8ff	237	typedef enum
bogdanm	0:9b334a45a8ff	238	{
bogdanm	0:9b334a45a8ff	239	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	240	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	241	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	242	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	243	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	244	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/**
bogdanm	0:9b334a45a8ff	247	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	248	*/
bogdanm	0:9b334a45a8ff	249	typedef enum
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	252	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	253	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	254	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	255	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	256	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/**
bogdanm	0:9b334a45a8ff	259	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	260	*/
bogdanm	0:9b334a45a8ff	261	typedef struct
bogdanm	0:9b334a45a8ff	262	{
bogdanm	0:9b334a45a8ff	263	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	264	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	265	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	266	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	267	This array is accessed by a @ref DMA_Handle_index */
bogdanm	0:9b334a45a8ff	268	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	269	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	270	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/**
bogdanm	0:9b334a45a8ff	273	* @}
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	277	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	278	* @{
bogdanm	0:9b334a45a8ff	279	*/
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity
bogdanm	0:9b334a45a8ff	282	* @{
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	285	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	286	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	287	/**
bogdanm	0:9b334a45a8ff	288	* @}
bogdanm	0:9b334a45a8ff	289	*/
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity
bogdanm	0:9b334a45a8ff	292	* @{
bogdanm	0:9b334a45a8ff	293	*/
bogdanm	0:9b334a45a8ff	294	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	295	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	296	/**
bogdanm	0:9b334a45a8ff	297	* @}
bogdanm	0:9b334a45a8ff	298	*/
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler
bogdanm	0:9b334a45a8ff	301	* @{
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	304	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	305	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	306	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	307	/**
bogdanm	0:9b334a45a8ff	308	* @}
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/** @defgroup TIM_Counter_Mode TIM_Counter_Mode
bogdanm	0:9b334a45a8ff	312	* @{
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	315	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	316	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	317	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	318	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	321	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	322	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	323	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	324	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @}
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/** @defgroup TIM_ClockDivision TIM_ClockDivision
bogdanm	0:9b334a45a8ff	330	* @{
bogdanm	0:9b334a45a8ff	331	*/
bogdanm	0:9b334a45a8ff	332	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	333	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	334	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	337	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	338	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	339	/**
bogdanm	0:9b334a45a8ff	340	* @}
bogdanm	0:9b334a45a8ff	341	*/
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes
bogdanm	0:9b334a45a8ff	344	* @{
bogdanm	0:9b334a45a8ff	345	*/
bogdanm	0:9b334a45a8ff	346	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	347	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	348	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	349	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	350	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	351	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	352	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	353	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	356	((MODE) == TIM_OCMODE_PWM2))
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	359	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	360	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	361	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	362	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	363	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @}
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State
bogdanm	0:9b334a45a8ff	369	* @{
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	372	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	375	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	376	/**
bogdanm	0:9b334a45a8ff	377	* @}
bogdanm	0:9b334a45a8ff	378	*/
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	381	* @{
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	384	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	387	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	388	/**
bogdanm	0:9b334a45a8ff	389	* @}
bogdanm	0:9b334a45a8ff	390	*/
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity
bogdanm	0:9b334a45a8ff	393	* @{
bogdanm	0:9b334a45a8ff	394	*/
bogdanm	0:9b334a45a8ff	395	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	396	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	399	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	400	/**
bogdanm	0:9b334a45a8ff	401	* @}
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	0:9b334a45a8ff	408	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	409	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	410	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	411	/**
bogdanm	0:9b334a45a8ff	412	* @}
bogdanm	0:9b334a45a8ff	413	*/
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/** @defgroup TIM_Channel TIM_Channel
bogdanm	0:9b334a45a8ff	416	* @{
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	419	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	420	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	421	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	422	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	425	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	426	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	427	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	428	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	431	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	434	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	435	/**
bogdanm	0:9b334a45a8ff	436	* @}
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity
bogdanm	0:9b334a45a8ff	440	* @{
bogdanm	0:9b334a45a8ff	441	*/
bogdanm	0:9b334a45a8ff	442	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	443	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	444	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	447	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	448	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	449	/**
bogdanm	0:9b334a45a8ff	450	* @}
bogdanm	0:9b334a45a8ff	451	*/
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection
bogdanm	0:9b334a45a8ff	454	* @{
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	457	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	458	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	459	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	460	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	463	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	464	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	465	/**
bogdanm	0:9b334a45a8ff	466	* @}
bogdanm	0:9b334a45a8ff	467	*/
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler
bogdanm	0:9b334a45a8ff	470	* @{
bogdanm	0:9b334a45a8ff	471	*/
bogdanm	0:9b334a45a8ff	472	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	473	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	474	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	475	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	478	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	479	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	480	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	481	/**
bogdanm	0:9b334a45a8ff	482	* @}
bogdanm	0:9b334a45a8ff	483	*/
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode
bogdanm	0:9b334a45a8ff	486	* @{
bogdanm	0:9b334a45a8ff	487	*/
bogdanm	0:9b334a45a8ff	488	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	489	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	492	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	493	/**
bogdanm	0:9b334a45a8ff	494	* @}
bogdanm	0:9b334a45a8ff	495	*/
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode
bogdanm	0:9b334a45a8ff	498	* @{
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	501	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	502	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	505	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	506	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @}
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition
bogdanm	0:9b334a45a8ff	512	* @{
bogdanm	0:9b334a45a8ff	513	*/
bogdanm	0:9b334a45a8ff	514	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	515	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	516	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	517	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	518	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	519	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/**
bogdanm	0:9b334a45a8ff	522	* @}
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/** @defgroup TIM_DMA_sources TIM_DMA_sources
bogdanm	0:9b334a45a8ff	526	* @{
bogdanm	0:9b334a45a8ff	527	*/
bogdanm	0:9b334a45a8ff	528	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	529	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	530	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	531	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	532	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	533	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	536	/**
bogdanm	0:9b334a45a8ff	537	* @}
bogdanm	0:9b334a45a8ff	538	*/
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	/** @defgroup TIM_Event_Source TIM_Event_Source
bogdanm	0:9b334a45a8ff	541	* @{
bogdanm	0:9b334a45a8ff	542	*/
bogdanm	0:9b334a45a8ff	543	#define TIM_EventSource_Update TIM_EGR_UG
bogdanm	0:9b334a45a8ff	544	#define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm	0:9b334a45a8ff	545	#define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm	0:9b334a45a8ff	546	#define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm	0:9b334a45a8ff	547	#define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm	0:9b334a45a8ff	548	#define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	551	/**
bogdanm	0:9b334a45a8ff	552	* @}
bogdanm	0:9b334a45a8ff	553	*/
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/** @defgroup TIM_Flag_definition TIM_Flag_definition
bogdanm	0:9b334a45a8ff	556	* @{
bogdanm	0:9b334a45a8ff	557	*/
bogdanm	0:9b334a45a8ff	558	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	559	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	560	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	561	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	562	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	563	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	564	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	565	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	566	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	567	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/**
bogdanm	0:9b334a45a8ff	570	* @}
bogdanm	0:9b334a45a8ff	571	*/
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/** @defgroup TIM_Clock_Source TIM_Clock_Source
bogdanm	0:9b334a45a8ff	574	* @{
bogdanm	0:9b334a45a8ff	575	*/
bogdanm	0:9b334a45a8ff	576	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	577	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	578	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	579	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	580	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	581	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	582	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	583	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	584	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	585	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	588	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	589	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	590	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	591	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	592	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	593	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	594	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	595	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	596	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	597	/**
bogdanm	0:9b334a45a8ff	598	* @}
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity
bogdanm	0:9b334a45a8ff	602	* @{
bogdanm	0:9b334a45a8ff	603	*/
bogdanm	0:9b334a45a8ff	604	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	605	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	606	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	607	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	608	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	611	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	612	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	613	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	614	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @}
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler
bogdanm	0:9b334a45a8ff	620	* @{
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	623	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	624	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	625	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	628	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	629	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	630	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	631	/**
bogdanm	0:9b334a45a8ff	632	* @}
bogdanm	0:9b334a45a8ff	633	*/
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/** @defgroup TIM_Clock_Filter TIM_Clock_Filter
bogdanm	0:9b334a45a8ff	636	* @{
bogdanm	0:9b334a45a8ff	637	*/
bogdanm	0:9b334a45a8ff	638	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	639	/**
bogdanm	0:9b334a45a8ff	640	* @}
bogdanm	0:9b334a45a8ff	641	*/
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source
bogdanm	0:9b334a45a8ff	644	* @{
bogdanm	0:9b334a45a8ff	645	*/
bogdanm	0:9b334a45a8ff	646	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	647	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
bogdanm	0:9b334a45a8ff	648	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
bogdanm	0:9b334a45a8ff	651	((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
bogdanm	0:9b334a45a8ff	652	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
bogdanm	0:9b334a45a8ff	653	/**
bogdanm	0:9b334a45a8ff	654	* @}
bogdanm	0:9b334a45a8ff	655	*/
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity
bogdanm	0:9b334a45a8ff	658	* @{
bogdanm	0:9b334a45a8ff	659	*/
bogdanm	0:9b334a45a8ff	660	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	661	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	665	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	666	/**
bogdanm	0:9b334a45a8ff	667	* @}
bogdanm	0:9b334a45a8ff	668	*/
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler
bogdanm	0:9b334a45a8ff	671	* @{
bogdanm	0:9b334a45a8ff	672	*/
bogdanm	0:9b334a45a8ff	673	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	674	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	675	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	676	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	679	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	680	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	681	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	682	/**
bogdanm	0:9b334a45a8ff	683	* @}
bogdanm	0:9b334a45a8ff	684	*/
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter
bogdanm	0:9b334a45a8ff	687	* @{
bogdanm	0:9b334a45a8ff	688	*/
bogdanm	0:9b334a45a8ff	689	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	690	/**
bogdanm	0:9b334a45a8ff	691	* @}
bogdanm	0:9b334a45a8ff	692	*/
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm	0:9b334a45a8ff	695	* @{
bogdanm	0:9b334a45a8ff	696	*/
bogdanm	0:9b334a45a8ff	697	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	0:9b334a45a8ff	698	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	701	((STATE) == TIM_OSSR_DISABLE))
bogdanm	0:9b334a45a8ff	702	/**
bogdanm	0:9b334a45a8ff	703	* @}
bogdanm	0:9b334a45a8ff	704	*/
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm	0:9b334a45a8ff	707	* @{
bogdanm	0:9b334a45a8ff	708	*/
bogdanm	0:9b334a45a8ff	709	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	0:9b334a45a8ff	710	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	713	((STATE) == TIM_OSSI_DISABLE))
bogdanm	0:9b334a45a8ff	714	/**
bogdanm	0:9b334a45a8ff	715	* @}
bogdanm	0:9b334a45a8ff	716	*/
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/** @defgroup TIM_Lock_level TIM_Lock_level
bogdanm	0:9b334a45a8ff	719	* @{
bogdanm	0:9b334a45a8ff	720	*/
bogdanm	0:9b334a45a8ff	721	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	722	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	0:9b334a45a8ff	723	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	0:9b334a45a8ff	724	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	727	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	0:9b334a45a8ff	728	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	0:9b334a45a8ff	729	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	0:9b334a45a8ff	730	/**
bogdanm	0:9b334a45a8ff	731	* @}
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset
bogdanm	0:9b334a45a8ff	735	* @{
bogdanm	0:9b334a45a8ff	736	*/
bogdanm	0:9b334a45a8ff	737	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	0:9b334a45a8ff	738	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	741	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	0:9b334a45a8ff	742	/**
bogdanm	0:9b334a45a8ff	743	* @}
bogdanm	0:9b334a45a8ff	744	*/
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection
bogdanm	0:9b334a45a8ff	747	* @{
bogdanm	0:9b334a45a8ff	748	*/
bogdanm	0:9b334a45a8ff	749	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	750	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	751	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	752	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	753	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	754	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	755	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	756	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	759	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	760	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	761	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	762	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	763	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	764	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	765	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	766	/**
bogdanm	0:9b334a45a8ff	767	* @}
bogdanm	0:9b334a45a8ff	768	*/
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/** @defgroup TIM_Slave_Mode TIM_Slave_Mode
bogdanm	0:9b334a45a8ff	771	* @{
bogdanm	0:9b334a45a8ff	772	*/
bogdanm	0:9b334a45a8ff	773	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	774	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	775	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	0:9b334a45a8ff	776	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	0:9b334a45a8ff	777	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	780	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	781	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	782	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	783	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	0:9b334a45a8ff	784	/**
bogdanm	0:9b334a45a8ff	785	* @}
bogdanm	0:9b334a45a8ff	786	*/
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode
bogdanm	0:9b334a45a8ff	789	* @{
bogdanm	0:9b334a45a8ff	790	*/
bogdanm	0:9b334a45a8ff	791	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	792	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	795	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	796	/**
bogdanm	0:9b334a45a8ff	797	* @}
bogdanm	0:9b334a45a8ff	798	*/
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection
bogdanm	0:9b334a45a8ff	801	* @{
bogdanm	0:9b334a45a8ff	802	*/
bogdanm	0:9b334a45a8ff	803	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	804	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	805	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	806	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	807	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	808	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	809	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	810	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	811	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	812
bogdanm	0:9b334a45a8ff	813	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	814	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	815	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	816	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	817	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	818	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	819	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	820	((SELECTION) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	823	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	824	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	825	((SELECTION) == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	828	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	829	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	830	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	831	((SELECTION) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	832	/**
bogdanm	0:9b334a45a8ff	833	* @}
bogdanm	0:9b334a45a8ff	834	*/
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity
bogdanm	0:9b334a45a8ff	837	* @{
bogdanm	0:9b334a45a8ff	838	*/
bogdanm	0:9b334a45a8ff	839	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	840	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	841	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	842	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	843	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	846	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	847	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	848	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	849	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	850	/**
bogdanm	0:9b334a45a8ff	851	* @}
bogdanm	0:9b334a45a8ff	852	*/
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler
bogdanm	0:9b334a45a8ff	855	* @{
bogdanm	0:9b334a45a8ff	856	*/
bogdanm	0:9b334a45a8ff	857	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	858	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	859	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	860	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	863	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	864	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	865	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	866	/**
bogdanm	0:9b334a45a8ff	867	* @}
bogdanm	0:9b334a45a8ff	868	*/
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter
bogdanm	0:9b334a45a8ff	871	* @{
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	874	/**
bogdanm	0:9b334a45a8ff	875	* @}
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	/** @defgroup TIM_TI1_Selection TIM_TI1_Selection
bogdanm	0:9b334a45a8ff	879	* @{
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	882	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	885	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	886	/**
bogdanm	0:9b334a45a8ff	887	* @}
bogdanm	0:9b334a45a8ff	888	*/
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address
bogdanm	0:9b334a45a8ff	891	* @{
bogdanm	0:9b334a45a8ff	892	*/
bogdanm	0:9b334a45a8ff	893	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	894	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	895	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	896	#define TIM_DMABase_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	897	#define TIM_DMABase_SR (0x00000004)
bogdanm	0:9b334a45a8ff	898	#define TIM_DMABase_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	899	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	900	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	901	#define TIM_DMABase_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	902	#define TIM_DMABase_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	903	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	904	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	905	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	906	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	907	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	908	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	909	#define TIM_DMABase_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	910	#define TIM_DMABase_OR (0x00000013)
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	0:9b334a45a8ff	913	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	0:9b334a45a8ff	914	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	915	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	0:9b334a45a8ff	916	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	0:9b334a45a8ff	917	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	0:9b334a45a8ff	918	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	919	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	920	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	0:9b334a45a8ff	921	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	0:9b334a45a8ff	922	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	0:9b334a45a8ff	923	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	0:9b334a45a8ff	924	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	925	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	926	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	927	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	928	((BASE) == TIM_DMABase_DCR) \|\| \
bogdanm	0:9b334a45a8ff	929	((BASE) == TIM_DMABase_OR))
bogdanm	0:9b334a45a8ff	930	/**
bogdanm	0:9b334a45a8ff	931	* @}
bogdanm	0:9b334a45a8ff	932	*/
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length
bogdanm	0:9b334a45a8ff	935	* @{
bogdanm	0:9b334a45a8ff	936	*/
bogdanm	0:9b334a45a8ff	937	#define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm	0:9b334a45a8ff	938	#define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm	0:9b334a45a8ff	939	#define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm	0:9b334a45a8ff	940	#define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm	0:9b334a45a8ff	941	#define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm	0:9b334a45a8ff	942	#define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm	0:9b334a45a8ff	943	#define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm	0:9b334a45a8ff	944	#define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm	0:9b334a45a8ff	945	#define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm	0:9b334a45a8ff	946	#define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm	0:9b334a45a8ff	947	#define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm	0:9b334a45a8ff	948	#define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm	0:9b334a45a8ff	949	#define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm	0:9b334a45a8ff	950	#define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm	0:9b334a45a8ff	951	#define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm	0:9b334a45a8ff	952	#define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm	0:9b334a45a8ff	953	#define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm	0:9b334a45a8ff	954	#define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	0:9b334a45a8ff	957	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	0:9b334a45a8ff	958	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	0:9b334a45a8ff	959	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	0:9b334a45a8ff	960	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	0:9b334a45a8ff	961	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	0:9b334a45a8ff	962	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	0:9b334a45a8ff	963	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	0:9b334a45a8ff	964	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	0:9b334a45a8ff	965	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	0:9b334a45a8ff	966	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	0:9b334a45a8ff	967	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	0:9b334a45a8ff	968	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	0:9b334a45a8ff	969	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	0:9b334a45a8ff	970	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	0:9b334a45a8ff	971	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	0:9b334a45a8ff	972	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	0:9b334a45a8ff	973	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	0:9b334a45a8ff	974	/**
bogdanm	0:9b334a45a8ff	975	* @}
bogdanm	0:9b334a45a8ff	976	*/
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value
bogdanm	0:9b334a45a8ff	979	* @{
bogdanm	0:9b334a45a8ff	980	*/
bogdanm	0:9b334a45a8ff	981	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	982	/**
bogdanm	0:9b334a45a8ff	983	* @}
bogdanm	0:9b334a45a8ff	984	*/
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/** @defgroup DMA_Handle_index DMA_Handle_index
bogdanm	0:9b334a45a8ff	987	* @{
bogdanm	0:9b334a45a8ff	988	*/
bogdanm	0:9b334a45a8ff	989	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	990	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	991	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	992	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	993	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	994	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	995	/**
bogdanm	0:9b334a45a8ff	996	* @}
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/** @defgroup Channel_CC_State Channel_CC_State
bogdanm	0:9b334a45a8ff	1000	* @{
bogdanm	0:9b334a45a8ff	1001	*/
bogdanm	0:9b334a45a8ff	1002	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	1003	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	1004	/**
bogdanm	0:9b334a45a8ff	1005	* @}
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/**
bogdanm	0:9b334a45a8ff	1009	* @}
bogdanm	0:9b334a45a8ff	1010	*/
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Private Constants -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1013	/** @defgroup TIM_Private_Constants TIM_Private_Constants
bogdanm	0:9b334a45a8ff	1014	* @{
bogdanm	0:9b334a45a8ff	1015	*/
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/* The counter of a timer instance is disabled only if all the CCx
bogdanm	0:9b334a45a8ff	1018	channels have been disabled */
bogdanm	0:9b334a45a8ff	1019	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	1020	/**
bogdanm	0:9b334a45a8ff	1021	* @}
bogdanm	0:9b334a45a8ff	1022	*/
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1027	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	0:9b334a45a8ff	1028	* @{
bogdanm	0:9b334a45a8ff	1029	*/
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/** @brief Reset TIM handle state
bogdanm	0:9b334a45a8ff	1032	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1033	* @retval None
bogdanm	0:9b334a45a8ff	1034	*/
bogdanm	0:9b334a45a8ff	1035	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/**
bogdanm	0:9b334a45a8ff	1038	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1039	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1040	* @retval None
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/**
bogdanm	0:9b334a45a8ff	1045	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1046	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1047	* @retval None
bogdanm	0:9b334a45a8ff	1048	*/
bogdanm	0:9b334a45a8ff	1049	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1050	do { \
bogdanm	0:9b334a45a8ff	1051	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1052	{ \
bogdanm	0:9b334a45a8ff	1053	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	1054	} \
bogdanm	0:9b334a45a8ff	1055	} while(0)
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/**
bogdanm	0:9b334a45a8ff	1058	* @brief Enable the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1059	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1060	* @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	1061	* @retval None
bogdanm	0:9b334a45a8ff	1062	*/
bogdanm	0:9b334a45a8ff	1063	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	/**
bogdanm	0:9b334a45a8ff	1066	* @brief Enable the specified DMA Channel.
bogdanm	0:9b334a45a8ff	1067	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1068	* @param __DMA__: specifies the DMA Channel to be enabled or disabled.
bogdanm	0:9b334a45a8ff	1069	* @retval None
bogdanm	0:9b334a45a8ff	1070	*/
bogdanm	0:9b334a45a8ff	1071	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/**
bogdanm	0:9b334a45a8ff	1074	* @brief Disable the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1075	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1076	* @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	1077	* @retval None
bogdanm	0:9b334a45a8ff	1078	*/
bogdanm	0:9b334a45a8ff	1079	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/**
bogdanm	0:9b334a45a8ff	1082	* @brief Disable the specified DMA Channel.
bogdanm	0:9b334a45a8ff	1083	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1084	* @param __DMA__: specifies the DMA Channel to be enabled or disabled.
bogdanm	0:9b334a45a8ff	1085	* @retval None
bogdanm	0:9b334a45a8ff	1086	*/
bogdanm	0:9b334a45a8ff	1087	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	/**
bogdanm	0:9b334a45a8ff	1090	* @brief Get the TIM Channel pending flags.
bogdanm	0:9b334a45a8ff	1091	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1092	* @param __FLAG__: Get the specified flag.
bogdanm	0:9b334a45a8ff	1093	* @retval The state of FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	1094	*/
bogdanm	0:9b334a45a8ff	1095	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/**
bogdanm	0:9b334a45a8ff	1098	* @brief Clear the TIM Channel pending flags.
bogdanm	0:9b334a45a8ff	1099	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1100	* @param __FLAG__: specifies the flag to clear.
bogdanm	0:9b334a45a8ff	1101	* @retval None
bogdanm	0:9b334a45a8ff	1102	*/
bogdanm	0:9b334a45a8ff	1103	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief Checks whether the specified TIM interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1107	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1108	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
bogdanm	0:9b334a45a8ff	1109	* @retval The state of TIM_IT (SET or RESET).
bogdanm	0:9b334a45a8ff	1110	*/
bogdanm	0:9b334a45a8ff	1111	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/** @brief Clear the TIM interrupt pending bits
bogdanm	0:9b334a45a8ff	1114	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1115	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1116	* @retval None
bogdanm	0:9b334a45a8ff	1117	*/
bogdanm	0:9b334a45a8ff	1118	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/** @brief TIM counter direction
bogdanm	0:9b334a45a8ff	1121	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1122	*/
bogdanm	0:9b334a45a8ff	1123	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/** @brief Set TIM prescaler
bogdanm	0:9b334a45a8ff	1126	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1127	* @param __PRESC__: specifies the prescaler value.
bogdanm	0:9b334a45a8ff	1128	* @retval None
bogdanm	0:9b334a45a8ff	1129	*/
bogdanm	0:9b334a45a8ff	1130	#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/** @brief Set TIM IC prescaler
bogdanm	0:9b334a45a8ff	1133	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1134	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1135	* @param __ICPSC__: specifies the prescaler value.
bogdanm	0:9b334a45a8ff	1136	* @retval None
bogdanm	0:9b334a45a8ff	1137	*/
bogdanm	0:9b334a45a8ff	1138	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1139	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1140	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	1141	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1142	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/** @brief Reset TIM IC prescaler
bogdanm	0:9b334a45a8ff	1145	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1146	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1147	* @retval None
bogdanm	0:9b334a45a8ff	1148	*/
bogdanm	0:9b334a45a8ff	1149	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1150	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1151	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	1152	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1153	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/**
bogdanm	0:9b334a45a8ff	1156	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	1157	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	1158	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1159	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1160	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1161	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1162	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1163	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1164	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1165	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	1166	* @retval None
bogdanm	0:9b334a45a8ff	1167	*/
bogdanm	0:9b334a45a8ff	1168	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	1169	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/**
bogdanm	0:9b334a45a8ff	1172	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	1173	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1174	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	1175	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1176	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	1177	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	1178	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	1179	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	1180	* @retval None
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1183	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/**
bogdanm	0:9b334a45a8ff	1186	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1187	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1188	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1189	* @retval None
bogdanm	0:9b334a45a8ff	1190	*/
bogdanm	0:9b334a45a8ff	1191	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/**
bogdanm	0:9b334a45a8ff	1194	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1195	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1196	* @retval None
bogdanm	0:9b334a45a8ff	1197	*/
bogdanm	0:9b334a45a8ff	1198	#define __HAL_TIM_GetCounter(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1199	((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/**
bogdanm	0:9b334a45a8ff	1202	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	0:9b334a45a8ff	1203	* another time any Init function.
bogdanm	0:9b334a45a8ff	1204	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1205	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1206	* @retval None
bogdanm	0:9b334a45a8ff	1207	*/
bogdanm	0:9b334a45a8ff	1208	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1209	do{ \
bogdanm	0:9b334a45a8ff	1210	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1211	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1212	} while(0)
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	/**
bogdanm	0:9b334a45a8ff	1215	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	0:9b334a45a8ff	1216	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1217	* @retval None
bogdanm	0:9b334a45a8ff	1218	*/
bogdanm	0:9b334a45a8ff	1219	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1220	((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/**
bogdanm	0:9b334a45a8ff	1223	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	0:9b334a45a8ff	1224	* another time any Init function.
bogdanm	0:9b334a45a8ff	1225	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1226	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1227	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1228	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1229	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1230	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1231	* @retval None
bogdanm	0:9b334a45a8ff	1232	*/
bogdanm	0:9b334a45a8ff	1233	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1234	do{ \
bogdanm	0:9b334a45a8ff	1235	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1236	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1237	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1238	} while(0)
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/**
bogdanm	0:9b334a45a8ff	1241	* @brief Gets the TIM Clock Division value on runtime
bogdanm	0:9b334a45a8ff	1242	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1243	* @retval None
bogdanm	0:9b334a45a8ff	1244	*/
bogdanm	0:9b334a45a8ff	1245	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1246	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/**
bogdanm	0:9b334a45a8ff	1249	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	0:9b334a45a8ff	1250	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1251	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1252	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1253	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1254	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1255	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1256	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1257	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1258	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1259	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1260	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1261	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1262	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1263	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1264	* @retval None
bogdanm	0:9b334a45a8ff	1265	*/
bogdanm	0:9b334a45a8ff	1266	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1267	do{ \
bogdanm	0:9b334a45a8ff	1268	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1269	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1270	} while(0)
bogdanm	0:9b334a45a8ff	1271
bogdanm	0:9b334a45a8ff	1272	/**
bogdanm	0:9b334a45a8ff	1273	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	0:9b334a45a8ff	1274	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1275	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1276	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1277	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1278	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1279	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1280	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1281	* @retval None
bogdanm	0:9b334a45a8ff	1282	*/
bogdanm	0:9b334a45a8ff	1283	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1284	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1285	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1286	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1287	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/**
bogdanm	0:9b334a45a8ff	1290	* @}
bogdanm	0:9b334a45a8ff	1291	*/
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Include TIM HAL Extension module */
bogdanm	0:9b334a45a8ff	1294	#include "stm32l1xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1297	/** @addtogroup TIM_Exported_Functions
bogdanm	0:9b334a45a8ff	1298	* @{
bogdanm	0:9b334a45a8ff	1299	*/
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1302	* @{
bogdanm	0:9b334a45a8ff	1303	*/
bogdanm	0:9b334a45a8ff	1304	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1305	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1306	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1307	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1308	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1309	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1310	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1311	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1312	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1313	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1314	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1315	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1316	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1317	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/**
bogdanm	0:9b334a45a8ff	1320	* @}
bogdanm	0:9b334a45a8ff	1321	*/
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1324	* @{
bogdanm	0:9b334a45a8ff	1325	*/
bogdanm	0:9b334a45a8ff	1326	/* Timer Output Compare functions **********************************************/
bogdanm	0:9b334a45a8ff	1327	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1328	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1329	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1330	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1331	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1332	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1333	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1334	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1335	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1336	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1337	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1338	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1339	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/**
bogdanm	0:9b334a45a8ff	1342	* @}
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	1346	* @{
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348	/* Timer PWM functions *********************************************************/
bogdanm	0:9b334a45a8ff	1349	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1350	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1351	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1352	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1353	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1354	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1355	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1356	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1357	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1358	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1359	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1360	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1361	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1362	/**
bogdanm	0:9b334a45a8ff	1363	* @}
bogdanm	0:9b334a45a8ff	1364	*/
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	1367	* @{
bogdanm	0:9b334a45a8ff	1368	*/
bogdanm	0:9b334a45a8ff	1369	/* Timer Input Capture functions ***********************************************/
bogdanm	0:9b334a45a8ff	1370	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1371	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1372	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1373	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1374	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1375	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1376	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1377	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1378	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1379	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1380	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1381	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1382	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1383	/**
bogdanm	0:9b334a45a8ff	1384	* @}
bogdanm	0:9b334a45a8ff	1385	*/
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	0:9b334a45a8ff	1388	* @{
bogdanm	0:9b334a45a8ff	1389	*/
bogdanm	0:9b334a45a8ff	1390	/* Timer One Pulse functions ***************************************************/
bogdanm	0:9b334a45a8ff	1391	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1392	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1393	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1394	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1395	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1396	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1397	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1398	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1399	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1400	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1401	/**
bogdanm	0:9b334a45a8ff	1402	* @}
bogdanm	0:9b334a45a8ff	1403	*/
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	0:9b334a45a8ff	1406	* @{
bogdanm	0:9b334a45a8ff	1407	*/
bogdanm	0:9b334a45a8ff	1408	/* Timer Encoder functions *****************************************************/
bogdanm	0:9b334a45a8ff	1409	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1410	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1411	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1412	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1413	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1414	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1415	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1416	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1417	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1418	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1419	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1420	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1421	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	/**
bogdanm	0:9b334a45a8ff	1424	* @}
bogdanm	0:9b334a45a8ff	1425	*/
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	0:9b334a45a8ff	1428	* @{
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430	/* Interrupt Handler functions **********************************************/
bogdanm	0:9b334a45a8ff	1431	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1432	/**
bogdanm	0:9b334a45a8ff	1433	* @}
bogdanm	0:9b334a45a8ff	1434	*/
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	0:9b334a45a8ff	1437	* @{
bogdanm	0:9b334a45a8ff	1438	*/
bogdanm	0:9b334a45a8ff	1439	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1440	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1441	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1442	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1443	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1444	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1445	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1446	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1447	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1448	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1449	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1450	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1451	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1452	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1453	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1454	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1455	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/**
bogdanm	0:9b334a45a8ff	1458	* @}
bogdanm	0:9b334a45a8ff	1459	*/
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	0:9b334a45a8ff	1462	* @{
bogdanm	0:9b334a45a8ff	1463	*/
bogdanm	0:9b334a45a8ff	1464	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1465	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1466	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1467	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1468	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1469	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1470	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1471	/**
bogdanm	0:9b334a45a8ff	1472	* @}
bogdanm	0:9b334a45a8ff	1473	*/
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	0:9b334a45a8ff	1476	* @{
bogdanm	0:9b334a45a8ff	1477	*/
bogdanm	0:9b334a45a8ff	1478	/* Peripheral State functions **************************************************/
bogdanm	0:9b334a45a8ff	1479	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1480	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1481	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1482	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1483	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1484	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	/**
bogdanm	0:9b334a45a8ff	1487	* @}
bogdanm	0:9b334a45a8ff	1488	*/
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/**
bogdanm	0:9b334a45a8ff	1491	* @}
bogdanm	0:9b334a45a8ff	1492	*/
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/**
bogdanm	0:9b334a45a8ff	1495	* @}
bogdanm	0:9b334a45a8ff	1496	*/
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/**
bogdanm	0:9b334a45a8ff	1499	* @}
bogdanm	0:9b334a45a8ff	1500	*/
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1503	}
bogdanm	0:9b334a45a8ff	1504	#endif
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	#endif /* __STM32L1xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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