mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l1xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 5-September-2014
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + IO operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customed HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	@endverbatim
bogdanm	0:9b334a45a8ff	59	******************************************************************************
bogdanm	0:9b334a45a8ff	60	* @attention
bogdanm	0:9b334a45a8ff	61	*
bogdanm	0:9b334a45a8ff	62	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	63	*
bogdanm	0:9b334a45a8ff	64	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	65	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	66	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	67	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	68	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	69	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	70	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	71	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	72	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	73	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	74	*
bogdanm	0:9b334a45a8ff	75	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	76	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	77	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	78	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	79	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	80	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	81	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	82	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	83	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	84	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	85	*
bogdanm	0:9b334a45a8ff	86	******************************************************************************
bogdanm	0:9b334a45a8ff	87	*/
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	90	#include "stm32l1xx_hal.h"
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	/** @addtogroup STM32L1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	93	* @{
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	97	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	98	* @{
bogdanm	0:9b334a45a8ff	99	*/
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	104	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	105	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	106	* @{
bogdanm	0:9b334a45a8ff	107	*/
bogdanm	0:9b334a45a8ff	108	#define SPI_TIMEOUT_VALUE 10
bogdanm	0:9b334a45a8ff	109	/**
bogdanm	0:9b334a45a8ff	110	* @}
bogdanm	0:9b334a45a8ff	111	*/
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	114	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	115	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	116	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	117	* @{
bogdanm	0:9b334a45a8ff	118	*/
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	121	static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	122	static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	123	static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	124	static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	125	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	126	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	127	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	128	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	129	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	130	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	131	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	132	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	133	/**
bogdanm	0:9b334a45a8ff	134	* @}
bogdanm	0:9b334a45a8ff	135	*/
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	140	* @{
bogdanm	0:9b334a45a8ff	141	*/
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	144	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	145	*
bogdanm	0:9b334a45a8ff	146	@verbatim
bogdanm	0:9b334a45a8ff	147	===============================================================================
bogdanm	0:9b334a45a8ff	148	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	149	===============================================================================
bogdanm	0:9b334a45a8ff	150	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	151	de-initialiaze the SPIx peripheral:
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	154	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	157	the selected configuration:
bogdanm	0:9b334a45a8ff	158	(++) Mode
bogdanm	0:9b334a45a8ff	159	(++) Direction
bogdanm	0:9b334a45a8ff	160	(++) Data Size
bogdanm	0:9b334a45a8ff	161	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	162	(++) NSS Management
bogdanm	0:9b334a45a8ff	163	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	164	(++) FirstBit
bogdanm	0:9b334a45a8ff	165	(++) TIMode
bogdanm	0:9b334a45a8ff	166	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	167	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	170	of the selected SPIx periperal.
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	@endverbatim
bogdanm	0:9b334a45a8ff	173	* @{
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/**
bogdanm	0:9b334a45a8ff	177	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	178	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	179	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	180	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	181	* @retval HAL status
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	184	{
bogdanm	0:9b334a45a8ff	185	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	186	}
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	/**
bogdanm	0:9b334a45a8ff	189	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	190	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	191	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	192	* @retval HAL status
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	195	{
bogdanm	0:9b334a45a8ff	196	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	197	if(hspi == HAL_NULL)
bogdanm	0:9b334a45a8ff	198	{
bogdanm	0:9b334a45a8ff	199	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	200	}
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	203	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	206	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	209	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/* Release Lock */
bogdanm	0:9b334a45a8ff	212	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	return HAL_OK;
bogdanm	0:9b334a45a8ff	215	}
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	/**
bogdanm	0:9b334a45a8ff	218	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	219	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	220	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	221	* @retval None
bogdanm	0:9b334a45a8ff	222	*/
bogdanm	0:9b334a45a8ff	223	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	224	{
bogdanm	0:9b334a45a8ff	225	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	226	the HAL_SPI_MspInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	227	*/
bogdanm	0:9b334a45a8ff	228	}
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	/**
bogdanm	0:9b334a45a8ff	231	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	232	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	233	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	234	* @retval None
bogdanm	0:9b334a45a8ff	235	*/
bogdanm	0:9b334a45a8ff	236	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	237	{
bogdanm	0:9b334a45a8ff	238	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	239	the HAL_SPI_MspDeInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	240	*/
bogdanm	0:9b334a45a8ff	241	}
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @}
bogdanm	0:9b334a45a8ff	245	*/
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	248	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	249	*
bogdanm	0:9b334a45a8ff	250	@verbatim
bogdanm	0:9b334a45a8ff	251	==============================================================================
bogdanm	0:9b334a45a8ff	252	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	253	===============================================================================
bogdanm	0:9b334a45a8ff	254	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	255	data transfers.
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	260	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	261	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	262	after finishing transfer.
bogdanm	0:9b334a45a8ff	263	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	264	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	265	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	266	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	267	using DMA mode.
bogdanm	0:9b334a45a8ff	268	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	269	will be executed respectivelly at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	270	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	(#) Blocking mode APIs are :
bogdanm	0:9b334a45a8ff	273	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	274	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	275	(++) HAL_SPI_TransmitReceive() in full duplex mode
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	(#) Non Blocking mode API's with Interrupt are :
bogdanm	0:9b334a45a8ff	278	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	279	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	280	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
bogdanm	0:9b334a45a8ff	281	(++) HAL_SPI_IRQHandler()
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	(#) Non Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	284	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	285	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	286	(++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	289	(++) HAL_SPI_TxCpltCallback()
bogdanm	0:9b334a45a8ff	290	(++) HAL_SPI_RxCpltCallback()
bogdanm	0:9b334a45a8ff	291	(++) HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	292	(++) HAL_SPI_TxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	293	(++) HAL_SPI_RxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	294	(++) HAL_SPI_TxRxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	295	(++) HAL_SPI_ErrorCallback()
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	@endverbatim
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	/**
bogdanm	0:9b334a45a8ff	302	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	304	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	305	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	306	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	307	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	308	* @retval HAL status
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	311	{
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	314	{
bogdanm	0:9b334a45a8ff	315	if((pData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	316	{
bogdanm	0:9b334a45a8ff	317	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	318	}
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/* Check the parameters */
bogdanm	0:9b334a45a8ff	321	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/* Process Locked */
bogdanm	0:9b334a45a8ff	324	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/* Configure communication */
bogdanm	0:9b334a45a8ff	327	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	328	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	331	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	332	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	335	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	336	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	337	hspi->pRxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	338	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	339	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	342	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	343	{
bogdanm	0:9b334a45a8ff	344	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	345	}
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	348	{
bogdanm	0:9b334a45a8ff	349	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	350	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	351	}
bogdanm	0:9b334a45a8ff	352
bogdanm	0:9b334a45a8ff	353	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	354	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	355	{
bogdanm	0:9b334a45a8ff	356	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	357	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	358	}
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	361	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	362	{
bogdanm	0:9b334a45a8ff	363	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	364	{
bogdanm	0:9b334a45a8ff	365	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	366	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	367	}
bogdanm	0:9b334a45a8ff	368	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	369	{
bogdanm	0:9b334a45a8ff	370	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	371	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	374	}
bogdanm	0:9b334a45a8ff	375	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	376	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	377	}
bogdanm	0:9b334a45a8ff	378	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	379	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	380	{
bogdanm	0:9b334a45a8ff	381	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	382	}
bogdanm	0:9b334a45a8ff	383	}
bogdanm	0:9b334a45a8ff	384	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	385	else
bogdanm	0:9b334a45a8ff	386	{
bogdanm	0:9b334a45a8ff	387	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	388	{
bogdanm	0:9b334a45a8ff	389	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	390	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	391	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	392	}
bogdanm	0:9b334a45a8ff	393	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	394	{
bogdanm	0:9b334a45a8ff	395	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	396	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	397	{
bogdanm	0:9b334a45a8ff	398	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	399	}
bogdanm	0:9b334a45a8ff	400	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	401	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	402	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	403	}
bogdanm	0:9b334a45a8ff	404	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	405	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409	}
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	412	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	413	{
bogdanm	0:9b334a45a8ff	414	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	415	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	419	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	420	{
bogdanm	0:9b334a45a8ff	421	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	422	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	423	}
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	426	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	427	{
bogdanm	0:9b334a45a8ff	428	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	429	}
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	434	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	return HAL_OK;
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438	else
bogdanm	0:9b334a45a8ff	439	{
bogdanm	0:9b334a45a8ff	440	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	441	}
bogdanm	0:9b334a45a8ff	442	}
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/**
bogdanm	0:9b334a45a8ff	445	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	446	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	447	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	448	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	449	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	450	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	451	* @retval HAL status
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	454	{
bogdanm	0:9b334a45a8ff	455	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	458	{
bogdanm	0:9b334a45a8ff	459	if((pData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/* Process Locked */
bogdanm	0:9b334a45a8ff	465	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Configure communication */
bogdanm	0:9b334a45a8ff	468	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	469	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	472	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	473	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	476	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	477	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	478	hspi->pTxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	479	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	480	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	481
bogdanm	0:9b334a45a8ff	482	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	483	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	484	{
bogdanm	0:9b334a45a8ff	485	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	489	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	490	{
bogdanm	0:9b334a45a8ff	491	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	492	}
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	495	{
bogdanm	0:9b334a45a8ff	496	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	497	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	500	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	504	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	505	{
bogdanm	0:9b334a45a8ff	506	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	507	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	508	}
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	511	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	514	{
bogdanm	0:9b334a45a8ff	515	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	516	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	517	{
bogdanm	0:9b334a45a8ff	518	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	519	}
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	522	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	523	}
bogdanm	0:9b334a45a8ff	524	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	525	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	526	{
bogdanm	0:9b334a45a8ff	527	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	528	}
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	531	else
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	534	{
bogdanm	0:9b334a45a8ff	535	/* Wait until RXNE flag is set to read data */
bogdanm	0:9b334a45a8ff	536	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	537	{
bogdanm	0:9b334a45a8ff	538	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	539	}
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	542	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	543	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	544	}
bogdanm	0:9b334a45a8ff	545	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	546	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	547	{
bogdanm	0:9b334a45a8ff	548	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	549	}
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	553	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	554	{
bogdanm	0:9b334a45a8ff	555	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	559	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	562	}
bogdanm	0:9b334a45a8ff	563	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	564	else
bogdanm	0:9b334a45a8ff	565	{
bogdanm	0:9b334a45a8ff	566	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	567	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	568	}
bogdanm	0:9b334a45a8ff	569	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	/* Wait until RXNE flag is set: CRC Received */
bogdanm	0:9b334a45a8ff	572	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	573	{
bogdanm	0:9b334a45a8ff	574	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	575	{
bogdanm	0:9b334a45a8ff	576	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	577	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	578	}
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/* Read CRC to Flush RXNE flag */
bogdanm	0:9b334a45a8ff	581	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	582	}
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	587	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	588	}
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	593	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	598	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	601	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	604	}
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	607	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	return HAL_OK;
bogdanm	0:9b334a45a8ff	610	}
bogdanm	0:9b334a45a8ff	611	else
bogdanm	0:9b334a45a8ff	612	{
bogdanm	0:9b334a45a8ff	613	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	614	}
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/**
bogdanm	0:9b334a45a8ff	618	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	619	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	620	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	621	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	622	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	623	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	624	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	625	* @retval HAL status
bogdanm	0:9b334a45a8ff	626	*/
bogdanm	0:9b334a45a8ff	627	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
bogdanm	0:9b334a45a8ff	632	{
bogdanm	0:9b334a45a8ff	633	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	634	{
bogdanm	0:9b334a45a8ff	635	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	636	}
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	/* Check the parameters */
bogdanm	0:9b334a45a8ff	639	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	/* Process Locked */
bogdanm	0:9b334a45a8ff	642	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	645	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* Configure communication */
bogdanm	0:9b334a45a8ff	651	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	652
bogdanm	0:9b334a45a8ff	653	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	654	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	655	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	658	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	659	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	662	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	663	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	666	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	667	{
bogdanm	0:9b334a45a8ff	668	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	669	}
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	672	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	675	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	679	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	682	{
bogdanm	0:9b334a45a8ff	683	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	684	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	685	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	690	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	696	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	697	{
bogdanm	0:9b334a45a8ff	698	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	702	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	703	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	704	}
bogdanm	0:9b334a45a8ff	705	else
bogdanm	0:9b334a45a8ff	706	{
bogdanm	0:9b334a45a8ff	707	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	708	{
bogdanm	0:9b334a45a8ff	709	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	710	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	716	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	717	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	720	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
bogdanm	0:9b334a45a8ff	721	{
bogdanm	0:9b334a45a8ff	722	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	726	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	727	{
bogdanm	0:9b334a45a8ff	728	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	729	}
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	732	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	733	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	734	}
bogdanm	0:9b334a45a8ff	735	/* Receive the last byte */
bogdanm	0:9b334a45a8ff	736	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	737	{
bogdanm	0:9b334a45a8ff	738	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	739	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	742	}
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	745	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	746	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	747	}
bogdanm	0:9b334a45a8ff	748	}
bogdanm	0:9b334a45a8ff	749	}
bogdanm	0:9b334a45a8ff	750	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	751	else
bogdanm	0:9b334a45a8ff	752	{
bogdanm	0:9b334a45a8ff	753	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	754	{
bogdanm	0:9b334a45a8ff	755	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	756	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	757	}
bogdanm	0:9b334a45a8ff	758	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	761	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	764	}
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	767	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	768	{
bogdanm	0:9b334a45a8ff	769	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	770	}
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	773	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775	else
bogdanm	0:9b334a45a8ff	776	{
bogdanm	0:9b334a45a8ff	777	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	778	{
bogdanm	0:9b334a45a8ff	779	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	780	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	781	{
bogdanm	0:9b334a45a8ff	782	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	783	}
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	786	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	789	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	792	}
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	795	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	796	{
bogdanm	0:9b334a45a8ff	797	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	801	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	806	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	812	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	813	}
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815	}
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	818	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	819	{
bogdanm	0:9b334a45a8ff	820	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	821	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	822	{
bogdanm	0:9b334a45a8ff	823	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	824	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826	/* Read CRC */
bogdanm	0:9b334a45a8ff	827	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	828	}
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	831	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	834	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	840	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	841	{
bogdanm	0:9b334a45a8ff	842	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	845	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	848	}
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	851	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	854	}
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	857	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	return HAL_OK;
bogdanm	0:9b334a45a8ff	860	}
bogdanm	0:9b334a45a8ff	861	else
bogdanm	0:9b334a45a8ff	862	{
bogdanm	0:9b334a45a8ff	863	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	864	}
bogdanm	0:9b334a45a8ff	865	}
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/**
bogdanm	0:9b334a45a8ff	868	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	869	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	870	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	871	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	872	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	873	* @retval HAL status
bogdanm	0:9b334a45a8ff	874	*/
bogdanm	0:9b334a45a8ff	875	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	876	{
bogdanm	0:9b334a45a8ff	877	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	if((pData == HAL_NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	882	}
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	/* Check the parameters */
bogdanm	0:9b334a45a8ff	885	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/* Process Locked */
bogdanm	0:9b334a45a8ff	888	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Configure communication */
bogdanm	0:9b334a45a8ff	891	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	892	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	895	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	896	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	897	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	900	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	901	hspi->pRxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	902	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	903	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	906	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	907	{
bogdanm	0:9b334a45a8ff	908	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	912	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	913	{
bogdanm	0:9b334a45a8ff	914	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	915	}
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	918	{
bogdanm	0:9b334a45a8ff	919	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	920	}else
bogdanm	0:9b334a45a8ff	921	{
bogdanm	0:9b334a45a8ff	922	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	923	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	924	}
bogdanm	0:9b334a45a8ff	925	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	926	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	929	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	932	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	return HAL_OK;
bogdanm	0:9b334a45a8ff	936	}
bogdanm	0:9b334a45a8ff	937	else
bogdanm	0:9b334a45a8ff	938	{
bogdanm	0:9b334a45a8ff	939	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	940	}
bogdanm	0:9b334a45a8ff	941	}
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/**
bogdanm	0:9b334a45a8ff	944	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	945	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	946	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	947	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	948	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	949	* @retval HAL status
bogdanm	0:9b334a45a8ff	950	*/
bogdanm	0:9b334a45a8ff	951	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	954	{
bogdanm	0:9b334a45a8ff	955	if((pData == HAL_NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	956	{
bogdanm	0:9b334a45a8ff	957	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	958	}
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/* Process Locked */
bogdanm	0:9b334a45a8ff	961	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Configure communication */
bogdanm	0:9b334a45a8ff	964	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	965	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	hspi->RxISR = &SPI_RxISR;
bogdanm	0:9b334a45a8ff	968	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	969	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	970	hspi->RxXferCount = Size ;
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	973	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	974	hspi->pTxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	975	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	976	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	979	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	982	}
bogdanm	0:9b334a45a8ff	983	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	984	{
bogdanm	0:9b334a45a8ff	985	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	986	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	989	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	990	}
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	993	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	994	{
bogdanm	0:9b334a45a8ff	995	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	996	}
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	999	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1002	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1005	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1006	process unlock */
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1009	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1010	{
bogdanm	0:9b334a45a8ff	1011	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1012	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1013	}
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	return HAL_OK;
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017	else
bogdanm	0:9b334a45a8ff	1018	{
bogdanm	0:9b334a45a8ff	1019	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1020	}
bogdanm	0:9b334a45a8ff	1021	}
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/**
bogdanm	0:9b334a45a8ff	1024	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1025	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1026	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1027	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1028	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	1029	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1030	* @retval HAL status
bogdanm	0:9b334a45a8ff	1031	*/
bogdanm	0:9b334a45a8ff	1032	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1033	{
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1036	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1037	{
bogdanm	0:9b334a45a8ff	1038	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1039	{
bogdanm	0:9b334a45a8ff	1040	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1044	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/* Process locked */
bogdanm	0:9b334a45a8ff	1047	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1050	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1051	{
bogdanm	0:9b334a45a8ff	1052	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1053	}
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	/* Configure communication */
bogdanm	0:9b334a45a8ff	1056	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1059	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1060	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1061	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	hspi->RxISR = &SPI_2LinesRxISR;
bogdanm	0:9b334a45a8ff	1064	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1065	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1066	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1069	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1070	{
bogdanm	0:9b334a45a8ff	1071	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1072	}
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1075	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1078	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1081	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1082	{
bogdanm	0:9b334a45a8ff	1083	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1084	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1085	}
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	return HAL_OK;
bogdanm	0:9b334a45a8ff	1088	}
bogdanm	0:9b334a45a8ff	1089	else
bogdanm	0:9b334a45a8ff	1090	{
bogdanm	0:9b334a45a8ff	1091	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1092	}
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/**
bogdanm	0:9b334a45a8ff	1096	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1097	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1098	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1099	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1100	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1101	* @retval HAL status
bogdanm	0:9b334a45a8ff	1102	*/
bogdanm	0:9b334a45a8ff	1103	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1104	{
bogdanm	0:9b334a45a8ff	1105	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1106	{
bogdanm	0:9b334a45a8ff	1107	if((pData == HAL_NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1108	{
bogdanm	0:9b334a45a8ff	1109	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1110	}
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1113	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/* Process Locked */
bogdanm	0:9b334a45a8ff	1116	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Configure communication */
bogdanm	0:9b334a45a8ff	1119	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1120	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1123	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1124	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1127	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1128	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1129	hspi->pRxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	1130	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1131	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1134	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1135	{
bogdanm	0:9b334a45a8ff	1136	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1137	}
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1140	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1141	{
bogdanm	0:9b334a45a8ff	1142	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1146	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1149	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1152	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1155	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1158	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1161	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1164	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1165	{
bogdanm	0:9b334a45a8ff	1166	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1167	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	return HAL_OK;
bogdanm	0:9b334a45a8ff	1171	}
bogdanm	0:9b334a45a8ff	1172	else
bogdanm	0:9b334a45a8ff	1173	{
bogdanm	0:9b334a45a8ff	1174	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1175	}
bogdanm	0:9b334a45a8ff	1176	}
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/**
bogdanm	0:9b334a45a8ff	1179	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1180	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1181	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1182	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1183	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1184	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1185	* @retval HAL status
bogdanm	0:9b334a45a8ff	1186	*/
bogdanm	0:9b334a45a8ff	1187	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	if((pData == HAL_NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1192	{
bogdanm	0:9b334a45a8ff	1193	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1194	}
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/* Process Locked */
bogdanm	0:9b334a45a8ff	1197	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Configure communication */
bogdanm	0:9b334a45a8ff	1200	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1201	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1204	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1205	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1208	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1209	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1210	hspi->pTxBuffPtr = HAL_NULL;
bogdanm	0:9b334a45a8ff	1211	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1212	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1215	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1218	}
bogdanm	0:9b334a45a8ff	1219	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1220	{
bogdanm	0:9b334a45a8ff	1221	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1222	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1225	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1226	}
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1229	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1230	{
bogdanm	0:9b334a45a8ff	1231	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1232	}
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1235	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1238	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1241	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1244	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1247	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1250	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1253	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1254	{
bogdanm	0:9b334a45a8ff	1255	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1256	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1257	}
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	return HAL_OK;
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261	else
bogdanm	0:9b334a45a8ff	1262	{
bogdanm	0:9b334a45a8ff	1263	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1264	}
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/**
bogdanm	0:9b334a45a8ff	1268	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1269	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1270	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1271	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1272	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1273	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1274	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1275	* @retval HAL status
bogdanm	0:9b334a45a8ff	1276	*/
bogdanm	0:9b334a45a8ff	1277	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1278	{
bogdanm	0:9b334a45a8ff	1279	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1280	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1281	{
bogdanm	0:9b334a45a8ff	1282	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1288	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	/* Process locked */
bogdanm	0:9b334a45a8ff	1291	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1294	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1295	{
bogdanm	0:9b334a45a8ff	1296	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1297	}
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299	/* Configure communication */
bogdanm	0:9b334a45a8ff	1300	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	hspi->pTxBuffPtr = (uint8_t*)pTxData;
bogdanm	0:9b334a45a8ff	1303	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1304	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	hspi->pRxBuffPtr = (uint8_t*)pRxData;
bogdanm	0:9b334a45a8ff	1307	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1308	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1311	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1312	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1315	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1316	{
bogdanm	0:9b334a45a8ff	1317	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1318	}
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1321	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1322	{
bogdanm	0:9b334a45a8ff	1323	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1324	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328	else
bogdanm	0:9b334a45a8ff	1329	{
bogdanm	0:9b334a45a8ff	1330	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1331	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1337	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1340	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1343	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
bogdanm	0:9b334a45a8ff	1346	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1347	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1350	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1351	}
bogdanm	0:9b334a45a8ff	1352	else
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	hspi->hdmatx->XferErrorCallback = HAL_NULL;
bogdanm	0:9b334a45a8ff	1355	}
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1358	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1361	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1364	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1365	}
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1368	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1371	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	return HAL_OK;
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375	else
bogdanm	0:9b334a45a8ff	1376	{
bogdanm	0:9b334a45a8ff	1377	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379	}
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	/**
bogdanm	0:9b334a45a8ff	1383	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1384	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1385	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1386	* @retval HAL status
bogdanm	0:9b334a45a8ff	1387	*/
bogdanm	0:9b334a45a8ff	1388	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1389	{
bogdanm	0:9b334a45a8ff	1390	/* Process Locked */
bogdanm	0:9b334a45a8ff	1391	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1392
bogdanm	0:9b334a45a8ff	1393	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1394	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1395	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1398	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	return HAL_OK;
bogdanm	0:9b334a45a8ff	1401	}
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/**
bogdanm	0:9b334a45a8ff	1404	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1405	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1406	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1407	* @retval HAL status
bogdanm	0:9b334a45a8ff	1408	*/
bogdanm	0:9b334a45a8ff	1409	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	/* Process Locked */
bogdanm	0:9b334a45a8ff	1412	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1415	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1416	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1419	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	return HAL_OK;
bogdanm	0:9b334a45a8ff	1422	}
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/**
bogdanm	0:9b334a45a8ff	1425	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1426	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1427	* the configuration information for the specified UART module.
bogdanm	0:9b334a45a8ff	1428	* @retval HAL status
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1431	{
bogdanm	0:9b334a45a8ff	1432	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1433	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1434	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1435	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* Abort the SPI DMA tx Channel */
bogdanm	0:9b334a45a8ff	1439	if(hspi->hdmatx != HAL_NULL)
bogdanm	0:9b334a45a8ff	1440	{
bogdanm	0:9b334a45a8ff	1441	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1442	}
bogdanm	0:9b334a45a8ff	1443	/* Abort the SPI DMA rx Channel */
bogdanm	0:9b334a45a8ff	1444	if(hspi->hdmarx != HAL_NULL)
bogdanm	0:9b334a45a8ff	1445	{
bogdanm	0:9b334a45a8ff	1446	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1447	}
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1450	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1451	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	return HAL_OK;
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/**
bogdanm	0:9b334a45a8ff	1459	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1460	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1461	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1462	* @retval HAL status
bogdanm	0:9b334a45a8ff	1463	*/
bogdanm	0:9b334a45a8ff	1464	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1465	{
bogdanm	0:9b334a45a8ff	1466	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
bogdanm	0:9b334a45a8ff	1467	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1470	return;
bogdanm	0:9b334a45a8ff	1471	}
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/* SPI in mode Tramitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1474	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1475	{
bogdanm	0:9b334a45a8ff	1476	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1477	return;
bogdanm	0:9b334a45a8ff	1478	}
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1481	{
bogdanm	0:9b334a45a8ff	1482	/* SPI CRC error interrupt occurred ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1483	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1484	{
bogdanm	0:9b334a45a8ff	1485	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1486	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1487	}
bogdanm	0:9b334a45a8ff	1488	/* SPI Mode Fault error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1489	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1490	{
bogdanm	0:9b334a45a8ff	1491	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
bogdanm	0:9b334a45a8ff	1492	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1493	}
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* SPI Overrun error interrupt occurred -----------------------------------*/
bogdanm	0:9b334a45a8ff	1496	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1499	{
bogdanm	0:9b334a45a8ff	1500	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1501	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1502	}
bogdanm	0:9b334a45a8ff	1503	}
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* SPI Frame error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1506	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1507	{
bogdanm	0:9b334a45a8ff	1508	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
bogdanm	0:9b334a45a8ff	1509	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1510	}
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1513	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1514	{
bogdanm	0:9b334a45a8ff	1515	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1516	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1517	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1518	}
bogdanm	0:9b334a45a8ff	1519	}
bogdanm	0:9b334a45a8ff	1520	}
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/**
bogdanm	0:9b334a45a8ff	1523	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1524	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1525	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1526	* @retval None
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1529	{
bogdanm	0:9b334a45a8ff	1530	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1531	the HAL_SPI_TxCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1532	*/
bogdanm	0:9b334a45a8ff	1533	}
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	/**
bogdanm	0:9b334a45a8ff	1536	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1537	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1538	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1539	* @retval None
bogdanm	0:9b334a45a8ff	1540	*/
bogdanm	0:9b334a45a8ff	1541	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1542	{
bogdanm	0:9b334a45a8ff	1543	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1544	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546	}
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/**
bogdanm	0:9b334a45a8ff	1549	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1550	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1551	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1552	* @retval None
bogdanm	0:9b334a45a8ff	1553	*/
bogdanm	0:9b334a45a8ff	1554	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1555	{
bogdanm	0:9b334a45a8ff	1556	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1557	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1558	*/
bogdanm	0:9b334a45a8ff	1559	}
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	/**
bogdanm	0:9b334a45a8ff	1562	* @brief Tx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1563	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1564	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1565	* @retval None
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1568	{
bogdanm	0:9b334a45a8ff	1569	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1570	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1571	*/
bogdanm	0:9b334a45a8ff	1572	}
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	/**
bogdanm	0:9b334a45a8ff	1575	* @brief Rx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1576	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1577	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1578	* @retval None
bogdanm	0:9b334a45a8ff	1579	*/
bogdanm	0:9b334a45a8ff	1580	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1581	{
bogdanm	0:9b334a45a8ff	1582	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1583	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1584	*/
bogdanm	0:9b334a45a8ff	1585	}
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	/**
bogdanm	0:9b334a45a8ff	1588	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1589	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1590	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1591	* @retval None
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1594	{
bogdanm	0:9b334a45a8ff	1595	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1596	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1597	*/
bogdanm	0:9b334a45a8ff	1598	}
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	/**
bogdanm	0:9b334a45a8ff	1601	* @brief SPI error callbacks
bogdanm	0:9b334a45a8ff	1602	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1603	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1604	* @retval None
bogdanm	0:9b334a45a8ff	1605	*/
bogdanm	0:9b334a45a8ff	1606	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	/* NOTE : - This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1609	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
bogdanm	0:9b334a45a8ff	1610	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1611	and user can use HAL_SPI_GetError() API to check the latest error occurred.
bogdanm	0:9b334a45a8ff	1612	*/
bogdanm	0:9b334a45a8ff	1613	}
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	/**
bogdanm	0:9b334a45a8ff	1616	* @}
bogdanm	0:9b334a45a8ff	1617	*/
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1620	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1621	*
bogdanm	0:9b334a45a8ff	1622	@verbatim
bogdanm	0:9b334a45a8ff	1623	===============================================================================
bogdanm	0:9b334a45a8ff	1624	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1625	===============================================================================
bogdanm	0:9b334a45a8ff	1626	[..]
bogdanm	0:9b334a45a8ff	1627	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1628	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1629	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1630	@endverbatim
bogdanm	0:9b334a45a8ff	1631	* @{
bogdanm	0:9b334a45a8ff	1632	*/
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	/**
bogdanm	0:9b334a45a8ff	1635	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1636	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1637	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1638	* @retval HAL state
bogdanm	0:9b334a45a8ff	1639	*/
bogdanm	0:9b334a45a8ff	1640	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1641	{
bogdanm	0:9b334a45a8ff	1642	return hspi->State;
bogdanm	0:9b334a45a8ff	1643	}
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/**
bogdanm	0:9b334a45a8ff	1646	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1647	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1648	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1649	* @retval SPI Error Code
bogdanm	0:9b334a45a8ff	1650	*/
bogdanm	0:9b334a45a8ff	1651	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/**
bogdanm	0:9b334a45a8ff	1657	* @}
bogdanm	0:9b334a45a8ff	1658	*/
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	/**
bogdanm	0:9b334a45a8ff	1661	* @}
bogdanm	0:9b334a45a8ff	1662	*/
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	1667	* @{
bogdanm	0:9b334a45a8ff	1668	*/
bogdanm	0:9b334a45a8ff	1669
bogdanm	0:9b334a45a8ff	1670
bogdanm	0:9b334a45a8ff	1671	/**
bogdanm	0:9b334a45a8ff	1672	* @brief Interrupt Handler to close Tx transfer
bogdanm	0:9b334a45a8ff	1673	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1674	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1675	* @retval void
bogdanm	0:9b334a45a8ff	1676	*/
bogdanm	0:9b334a45a8ff	1677	static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1678	{
bogdanm	0:9b334a45a8ff	1679	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1680	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1681	{
bogdanm	0:9b334a45a8ff	1682	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1683	}
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	1686	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	/* Disable ERR interrupt if Receive process is finished */
bogdanm	0:9b334a45a8ff	1689	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	1690	{
bogdanm	0:9b334a45a8ff	1691	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1694	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1695	{
bogdanm	0:9b334a45a8ff	1696	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1697	}
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1700	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1701	{
bogdanm	0:9b334a45a8ff	1702	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1703	}
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1706	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1707	{
bogdanm	0:9b334a45a8ff	1708	/* Check if we are in Tx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1709	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1710	{
bogdanm	0:9b334a45a8ff	1711	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1712	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1713	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715	else
bogdanm	0:9b334a45a8ff	1716	{
bogdanm	0:9b334a45a8ff	1717	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1718	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1719	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1720	}
bogdanm	0:9b334a45a8ff	1721	}
bogdanm	0:9b334a45a8ff	1722	else
bogdanm	0:9b334a45a8ff	1723	{
bogdanm	0:9b334a45a8ff	1724	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1725	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1726	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1727	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1728	}
bogdanm	0:9b334a45a8ff	1729	}
bogdanm	0:9b334a45a8ff	1730	}
bogdanm	0:9b334a45a8ff	1731
bogdanm	0:9b334a45a8ff	1732	/**
bogdanm	0:9b334a45a8ff	1733	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1734	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1735	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1736	* @retval void
bogdanm	0:9b334a45a8ff	1737	*/
bogdanm	0:9b334a45a8ff	1738	static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1739	{
bogdanm	0:9b334a45a8ff	1740	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1741	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1742	{
bogdanm	0:9b334a45a8ff	1743	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1744	}
bogdanm	0:9b334a45a8ff	1745	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1746	else
bogdanm	0:9b334a45a8ff	1747	{
bogdanm	0:9b334a45a8ff	1748	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	1749	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1750	}
bogdanm	0:9b334a45a8ff	1751	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1756	{
bogdanm	0:9b334a45a8ff	1757	/* calculate and transfer CRC on Tx line */
bogdanm	0:9b334a45a8ff	1758	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	1759	}
bogdanm	0:9b334a45a8ff	1760	SPI_TxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1761	}
bogdanm	0:9b334a45a8ff	1762	}
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/**
bogdanm	0:9b334a45a8ff	1765	* @brief Interrupt Handler to close Rx transfer
bogdanm	0:9b334a45a8ff	1766	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1767	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1768	* @retval void
bogdanm	0:9b334a45a8ff	1769	*/
bogdanm	0:9b334a45a8ff	1770	static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1771	{
bogdanm	0:9b334a45a8ff	1772	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1775	{
bogdanm	0:9b334a45a8ff	1776	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	1777	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1778	{
bogdanm	0:9b334a45a8ff	1779	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1780	}
bogdanm	0:9b334a45a8ff	1781
bogdanm	0:9b334a45a8ff	1782	/* Read CRC to reset RXNE flag */
bogdanm	0:9b334a45a8ff	1783	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	1786	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1787	{
bogdanm	0:9b334a45a8ff	1788	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1789	}
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1792	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1797	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1798	}
bogdanm	0:9b334a45a8ff	1799	}
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	1802	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
bogdanm	0:9b334a45a8ff	1803
bogdanm	0:9b334a45a8ff	1804	/* if Transmit process is finished */
bogdanm	0:9b334a45a8ff	1805	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1808	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1809
bogdanm	0:9b334a45a8ff	1810	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1811	{
bogdanm	0:9b334a45a8ff	1812	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1813	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1814	}
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1817	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1818	{
bogdanm	0:9b334a45a8ff	1819	/* Check if we are in Rx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1820	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1821	{
bogdanm	0:9b334a45a8ff	1822	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1823	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1824	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1825	}
bogdanm	0:9b334a45a8ff	1826	else
bogdanm	0:9b334a45a8ff	1827	{
bogdanm	0:9b334a45a8ff	1828	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1829	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1830	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1831	}
bogdanm	0:9b334a45a8ff	1832	}
bogdanm	0:9b334a45a8ff	1833	else
bogdanm	0:9b334a45a8ff	1834	{
bogdanm	0:9b334a45a8ff	1835	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1836	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1837	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1838	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1839	}
bogdanm	0:9b334a45a8ff	1840	}
bogdanm	0:9b334a45a8ff	1841	}
bogdanm	0:9b334a45a8ff	1842
bogdanm	0:9b334a45a8ff	1843	/**
bogdanm	0:9b334a45a8ff	1844	* @brief Interrupt Handler to receive amount of data in 2Lines mode
bogdanm	0:9b334a45a8ff	1845	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1846	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1847	* @retval void
bogdanm	0:9b334a45a8ff	1848	*/
bogdanm	0:9b334a45a8ff	1849	static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1850	{
bogdanm	0:9b334a45a8ff	1851	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1852	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1853	{
bogdanm	0:9b334a45a8ff	1854	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1857	else
bogdanm	0:9b334a45a8ff	1858	{
bogdanm	0:9b334a45a8ff	1859	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1860	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1861	}
bogdanm	0:9b334a45a8ff	1862	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1863
bogdanm	0:9b334a45a8ff	1864	if(hspi->RxXferCount==0)
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1867	}
bogdanm	0:9b334a45a8ff	1868	}
bogdanm	0:9b334a45a8ff	1869
bogdanm	0:9b334a45a8ff	1870	/**
bogdanm	0:9b334a45a8ff	1871	* @brief Interrupt Handler to receive amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1872	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1873	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1874	* @retval void
bogdanm	0:9b334a45a8ff	1875	*/
bogdanm	0:9b334a45a8ff	1876	static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1877	{
bogdanm	0:9b334a45a8ff	1878	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1879	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1880	{
bogdanm	0:9b334a45a8ff	1881	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1882	}
bogdanm	0:9b334a45a8ff	1883	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1884	else
bogdanm	0:9b334a45a8ff	1885	{
bogdanm	0:9b334a45a8ff	1886	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1887	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1888	}
bogdanm	0:9b334a45a8ff	1889	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	1892	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
bogdanm	0:9b334a45a8ff	1893	{
bogdanm	0:9b334a45a8ff	1894	/* Set CRC Next to calculate CRC on Rx side */
bogdanm	0:9b334a45a8ff	1895	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	1896	}
bogdanm	0:9b334a45a8ff	1897
bogdanm	0:9b334a45a8ff	1898	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1899	{
bogdanm	0:9b334a45a8ff	1900	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1901	}
bogdanm	0:9b334a45a8ff	1902	}
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	/**
bogdanm	0:9b334a45a8ff	1905	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	1906	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1907	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1908	* @retval None
bogdanm	0:9b334a45a8ff	1909	*/
bogdanm	0:9b334a45a8ff	1910	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1911	{
bogdanm	0:9b334a45a8ff	1912	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	1915	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	1916	{
bogdanm	0:9b334a45a8ff	1917	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1918	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1919	{
bogdanm	0:9b334a45a8ff	1920	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1921	}
bogdanm	0:9b334a45a8ff	1922
bogdanm	0:9b334a45a8ff	1923	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1924	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1927	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1928	{
bogdanm	0:9b334a45a8ff	1929	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1930	}
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1933	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1934	}
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1937	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1938	{
bogdanm	0:9b334a45a8ff	1939	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1943	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1944	{
bogdanm	0:9b334a45a8ff	1945	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1946	}
bogdanm	0:9b334a45a8ff	1947	else
bogdanm	0:9b334a45a8ff	1948	{
bogdanm	0:9b334a45a8ff	1949	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1950	}
bogdanm	0:9b334a45a8ff	1951	}
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953	/**
bogdanm	0:9b334a45a8ff	1954	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	1955	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1956	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1957	* @retval None
bogdanm	0:9b334a45a8ff	1958	*/
bogdanm	0:9b334a45a8ff	1959	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1960	{
bogdanm	0:9b334a45a8ff	1961	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1962
bogdanm	0:9b334a45a8ff	1963	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1964
bogdanm	0:9b334a45a8ff	1965	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	1966	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	1967	{
bogdanm	0:9b334a45a8ff	1968	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1969	{
bogdanm	0:9b334a45a8ff	1970	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1971	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1972	}
bogdanm	0:9b334a45a8ff	1973
bogdanm	0:9b334a45a8ff	1974	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1975	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
bogdanm	0:9b334a45a8ff	1978	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1979
bogdanm	0:9b334a45a8ff	1980	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1981	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	1982	{
bogdanm	0:9b334a45a8ff	1983	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	1984	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1985	{
bogdanm	0:9b334a45a8ff	1986	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1987	}
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	/* Read CRC */
bogdanm	0:9b334a45a8ff	1990	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1991
bogdanm	0:9b334a45a8ff	1992	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	1993	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1994	{
bogdanm	0:9b334a45a8ff	1995	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1996	}
bogdanm	0:9b334a45a8ff	1997
bogdanm	0:9b334a45a8ff	1998	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1999	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2000	{
bogdanm	0:9b334a45a8ff	2001	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2002	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2003	}
bogdanm	0:9b334a45a8ff	2004	}
bogdanm	0:9b334a45a8ff	2005
bogdanm	0:9b334a45a8ff	2006	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2007	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2008
bogdanm	0:9b334a45a8ff	2009	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2010	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2011	{
bogdanm	0:9b334a45a8ff	2012	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2013	}
bogdanm	0:9b334a45a8ff	2014	else
bogdanm	0:9b334a45a8ff	2015	{
bogdanm	0:9b334a45a8ff	2016	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2017	}
bogdanm	0:9b334a45a8ff	2018	}
bogdanm	0:9b334a45a8ff	2019	else
bogdanm	0:9b334a45a8ff	2020	{
bogdanm	0:9b334a45a8ff	2021	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2022	}
bogdanm	0:9b334a45a8ff	2023	}
bogdanm	0:9b334a45a8ff	2024
bogdanm	0:9b334a45a8ff	2025	/**
bogdanm	0:9b334a45a8ff	2026	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2027	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2028	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2029	* @retval None
bogdanm	0:9b334a45a8ff	2030	*/
bogdanm	0:9b334a45a8ff	2031	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2032	{
bogdanm	0:9b334a45a8ff	2033	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2034
bogdanm	0:9b334a45a8ff	2035	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2038	{
bogdanm	0:9b334a45a8ff	2039	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2040	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	2041	{
bogdanm	0:9b334a45a8ff	2042	/* Check if CRC is done on going (RXNE flag set) */
bogdanm	0:9b334a45a8ff	2043	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
bogdanm	0:9b334a45a8ff	2044	{
bogdanm	0:9b334a45a8ff	2045	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2046	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2047	{
bogdanm	0:9b334a45a8ff	2048	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2049	}
bogdanm	0:9b334a45a8ff	2050	}
bogdanm	0:9b334a45a8ff	2051	/* Read CRC */
bogdanm	0:9b334a45a8ff	2052	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2055	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2056	{
bogdanm	0:9b334a45a8ff	2057	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2058	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060	}
bogdanm	0:9b334a45a8ff	2061
bogdanm	0:9b334a45a8ff	2062	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2063	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2064	{
bogdanm	0:9b334a45a8ff	2065	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2066	}
bogdanm	0:9b334a45a8ff	2067
bogdanm	0:9b334a45a8ff	2068	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2069	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2070
bogdanm	0:9b334a45a8ff	2071	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2072	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2075	}
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2078	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2079
bogdanm	0:9b334a45a8ff	2080	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2081	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2082
bogdanm	0:9b334a45a8ff	2083	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2084
bogdanm	0:9b334a45a8ff	2085	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2086	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2087	{
bogdanm	0:9b334a45a8ff	2088	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2089	}
bogdanm	0:9b334a45a8ff	2090	else
bogdanm	0:9b334a45a8ff	2091	{
bogdanm	0:9b334a45a8ff	2092	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2093	}
bogdanm	0:9b334a45a8ff	2094	}
bogdanm	0:9b334a45a8ff	2095	else
bogdanm	0:9b334a45a8ff	2096	{
bogdanm	0:9b334a45a8ff	2097	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2098	}
bogdanm	0:9b334a45a8ff	2099	}
bogdanm	0:9b334a45a8ff	2100
bogdanm	0:9b334a45a8ff	2101	/**
bogdanm	0:9b334a45a8ff	2102	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2103	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2104	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2105	* @retval None
bogdanm	0:9b334a45a8ff	2106	*/
bogdanm	0:9b334a45a8ff	2107	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2108	{
bogdanm	0:9b334a45a8ff	2109	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2110
bogdanm	0:9b334a45a8ff	2111	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2112	}
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	/**
bogdanm	0:9b334a45a8ff	2115	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2116	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2117	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2118	* @retval None
bogdanm	0:9b334a45a8ff	2119	*/
bogdanm	0:9b334a45a8ff	2120	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2121	{
bogdanm	0:9b334a45a8ff	2122	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2123
bogdanm	0:9b334a45a8ff	2124	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2125	}
bogdanm	0:9b334a45a8ff	2126
bogdanm	0:9b334a45a8ff	2127	/**
bogdanm	0:9b334a45a8ff	2128	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2129	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2130	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2131	* @retval None
bogdanm	0:9b334a45a8ff	2132	*/
bogdanm	0:9b334a45a8ff	2133	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2134	{
bogdanm	0:9b334a45a8ff	2135	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2136
bogdanm	0:9b334a45a8ff	2137	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2138	}
bogdanm	0:9b334a45a8ff	2139
bogdanm	0:9b334a45a8ff	2140	/**
bogdanm	0:9b334a45a8ff	2141	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2142	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2143	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2144	* @retval None
bogdanm	0:9b334a45a8ff	2145	*/
bogdanm	0:9b334a45a8ff	2146	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2147	{
bogdanm	0:9b334a45a8ff	2148	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2149	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2150	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2151	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2152	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2153	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2154	}
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	/**
bogdanm	0:9b334a45a8ff	2157	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2158	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2159	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2160	* @param Flag: SPI flag to check
bogdanm	0:9b334a45a8ff	2161	* @param Status: Flag status to check: RESET or set
bogdanm	0:9b334a45a8ff	2162	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2163	* @retval HAL status
bogdanm	0:9b334a45a8ff	2164	*/
bogdanm	0:9b334a45a8ff	2165	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2166	{
bogdanm	0:9b334a45a8ff	2167	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	/* Get tick */
bogdanm	0:9b334a45a8ff	2170	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	2173	if(Status == RESET)
bogdanm	0:9b334a45a8ff	2174	{
bogdanm	0:9b334a45a8ff	2175	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
bogdanm	0:9b334a45a8ff	2176	{
bogdanm	0:9b334a45a8ff	2177	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2178	{
bogdanm	0:9b334a45a8ff	2179	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2180	{
bogdanm	0:9b334a45a8ff	2181	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2182	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2183	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2184
bogdanm	0:9b334a45a8ff	2185	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2186	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2187
bogdanm	0:9b334a45a8ff	2188	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2189	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2192	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	2193	{
bogdanm	0:9b334a45a8ff	2194	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2195	}
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2198
bogdanm	0:9b334a45a8ff	2199	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2200	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2201
bogdanm	0:9b334a45a8ff	2202	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2203	}
bogdanm	0:9b334a45a8ff	2204	}
bogdanm	0:9b334a45a8ff	2205	}
bogdanm	0:9b334a45a8ff	2206	}
bogdanm	0:9b334a45a8ff	2207	else
bogdanm	0:9b334a45a8ff	2208	{
bogdanm	0:9b334a45a8ff	2209	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
bogdanm	0:9b334a45a8ff	2210	{
bogdanm	0:9b334a45a8ff	2211	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2212	{
bogdanm	0:9b334a45a8ff	2213	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2214	{
bogdanm	0:9b334a45a8ff	2215	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2216	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2217	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2218
bogdanm	0:9b334a45a8ff	2219	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2220	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2221
bogdanm	0:9b334a45a8ff	2222	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2223	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2224
bogdanm	0:9b334a45a8ff	2225	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2226	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
bogdanm	0:9b334a45a8ff	2227	{
bogdanm	0:9b334a45a8ff	2228	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2229	}
bogdanm	0:9b334a45a8ff	2230
bogdanm	0:9b334a45a8ff	2231	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2232
bogdanm	0:9b334a45a8ff	2233	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2234	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2237	}
bogdanm	0:9b334a45a8ff	2238	}
bogdanm	0:9b334a45a8ff	2239	}
bogdanm	0:9b334a45a8ff	2240	}
bogdanm	0:9b334a45a8ff	2241	return HAL_OK;
bogdanm	0:9b334a45a8ff	2242	}
bogdanm	0:9b334a45a8ff	2243	/**
bogdanm	0:9b334a45a8ff	2244	* @}
bogdanm	0:9b334a45a8ff	2245	*/
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2248	/**
bogdanm	0:9b334a45a8ff	2249	* @}
bogdanm	0:9b334a45a8ff	2250	*/
bogdanm	0:9b334a45a8ff	2251
bogdanm	0:9b334a45a8ff	2252	/**
bogdanm	0:9b334a45a8ff	2253	* @}
bogdanm	0:9b334a45a8ff	2254	*/
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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