en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l1xx_hal_rcc_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 5-September-2014
bogdanm 0:9b334a45a8ff 7 * @brief Extended RCC HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities RCC extension peripheral:
bogdanm 0:9b334a45a8ff 11 * + Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32l1xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32L1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @defgroup RCCEx RCCEx
bogdanm 0:9b334a45a8ff 51 * @brief RCC Extension HAL module driver
bogdanm 0:9b334a45a8ff 52 * @{
bogdanm 0:9b334a45a8ff 53 */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 61 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 62 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /** @defgroup RCCEx_Private_Functions RCCEx Exported Functions
bogdanm 0:9b334a45a8ff 65 * @{
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 69 * @brief Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 @verbatim
bogdanm 0:9b334a45a8ff 72 ===============================================================================
bogdanm 0:9b334a45a8ff 73 ##### Extended Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 74 ===============================================================================
bogdanm 0:9b334a45a8ff 75 [..]
bogdanm 0:9b334a45a8ff 76 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 77 frequencies.
bogdanm 0:9b334a45a8ff 78 [..]
bogdanm 0:9b334a45a8ff 79 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm 0:9b334a45a8ff 80 select the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 81 order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 82 the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 @endverbatim
bogdanm 0:9b334a45a8ff 85 * @{
bogdanm 0:9b334a45a8ff 86 */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /**
bogdanm 0:9b334a45a8ff 89 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
bogdanm 0:9b334a45a8ff 90 * RCC_PeriphCLKInitTypeDef.
bogdanm 0:9b334a45a8ff 91 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 92 * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
bogdanm 0:9b334a45a8ff 93 * @retval HAL status
bogdanm 0:9b334a45a8ff 94 */
bogdanm 0:9b334a45a8ff 95 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 96 {
bogdanm 0:9b334a45a8ff 97 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 98 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /* Check the parameters */
bogdanm 0:9b334a45a8ff 101 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /*------------------------------- RTC/LCD Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 104 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
bogdanm 0:9b334a45a8ff 105 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
bogdanm 0:9b334a45a8ff 106 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
bogdanm 0:9b334a45a8ff 107 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
bogdanm 0:9b334a45a8ff 108 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
bogdanm 0:9b334a45a8ff 109 defined(STM32L162xE)
bogdanm 0:9b334a45a8ff 110 || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
bogdanm 0:9b334a45a8ff 111 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 112 )
bogdanm 0:9b334a45a8ff 113 {
bogdanm 0:9b334a45a8ff 114 /* Enable Power Controller clock */
bogdanm 0:9b334a45a8ff 115 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 118 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 121 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 124 {
bogdanm 0:9b334a45a8ff 125 if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 126 {
bogdanm 0:9b334a45a8ff 127 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 128 }
bogdanm 0:9b334a45a8ff 129 }
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 tmpreg = (RCC->CSR & RCC_CSR_RTCSEL);
bogdanm 0:9b334a45a8ff 132 /* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm 0:9b334a45a8ff 133 if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
bogdanm 0:9b334a45a8ff 134 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
bogdanm 0:9b334a45a8ff 135 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
bogdanm 0:9b334a45a8ff 136 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
bogdanm 0:9b334a45a8ff 137 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
bogdanm 0:9b334a45a8ff 138 defined(STM32L162xE)
bogdanm 0:9b334a45a8ff 139 || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
bogdanm 0:9b334a45a8ff 140 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 141 )
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 /* Store the content of CSR register before the reset of Backup Domain */
bogdanm 0:9b334a45a8ff 144 tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
bogdanm 0:9b334a45a8ff 145 /* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm 0:9b334a45a8ff 146 __HAL_RCC_BACKUPRESET_FORCE();
bogdanm 0:9b334a45a8ff 147 __HAL_RCC_BACKUPRESET_RELEASE();
bogdanm 0:9b334a45a8ff 148 /* Restore the Content of CSR register */
bogdanm 0:9b334a45a8ff 149 RCC->CSR = tmpreg;
bogdanm 0:9b334a45a8ff 150 }
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
bogdanm 0:9b334a45a8ff 153 if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
bogdanm 0:9b334a45a8ff 154 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
bogdanm 0:9b334a45a8ff 155 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
bogdanm 0:9b334a45a8ff 156 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
bogdanm 0:9b334a45a8ff 157 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
bogdanm 0:9b334a45a8ff 158 defined(STM32L162xE)
bogdanm 0:9b334a45a8ff 159 || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
bogdanm 0:9b334a45a8ff 160 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 161 )
bogdanm 0:9b334a45a8ff 162 {
bogdanm 0:9b334a45a8ff 163 /* Get timeout */
bogdanm 0:9b334a45a8ff 164 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 167 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 168 {
bogdanm 0:9b334a45a8ff 169 if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 170 {
bogdanm 0:9b334a45a8ff 171 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173 }
bogdanm 0:9b334a45a8ff 174 }
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm 0:9b334a45a8ff 177 }
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 return HAL_OK;
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /**
bogdanm 0:9b334a45a8ff 183 * @brief Get the PeriphClkInit according to the internal
bogdanm 0:9b334a45a8ff 184 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 185 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 186 * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
bogdanm 0:9b334a45a8ff 187 * @retval None
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 uint32_t srcclk = 0;
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /* Set all possible values for the extended clock type parameter------------*/
bogdanm 0:9b334a45a8ff 194 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
bogdanm 0:9b334a45a8ff 195 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
bogdanm 0:9b334a45a8ff 196 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
bogdanm 0:9b334a45a8ff 197 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
bogdanm 0:9b334a45a8ff 198 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
bogdanm 0:9b334a45a8ff 199 defined(STM32L162xE)
bogdanm 0:9b334a45a8ff 200 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
bogdanm 0:9b334a45a8ff 201 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Get the RTC/LCD configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 204 srcclk = __HAL_RCC_GET_RTC_SOURCE();
bogdanm 0:9b334a45a8ff 205 if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
bogdanm 0:9b334a45a8ff 206 {
bogdanm 0:9b334a45a8ff 207 /* Source clock is LSE or LSI*/
bogdanm 0:9b334a45a8ff 208 PeriphClkInit->RTCClockSelection = srcclk;
bogdanm 0:9b334a45a8ff 209 }
bogdanm 0:9b334a45a8ff 210 else
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 /* Source clock is HSE. Need to get the prescaler value*/
bogdanm 0:9b334a45a8ff 213 PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
bogdanm 0:9b334a45a8ff 216 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
bogdanm 0:9b334a45a8ff 217 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
bogdanm 0:9b334a45a8ff 218 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
bogdanm 0:9b334a45a8ff 219 defined(STM32L162xE)
bogdanm 0:9b334a45a8ff 220 PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
bogdanm 0:9b334a45a8ff 221 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
bogdanm 0:9b334a45a8ff 225 defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
bogdanm 0:9b334a45a8ff 226 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
bogdanm 0:9b334a45a8ff 227 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /**
bogdanm 0:9b334a45a8ff 230 * @brief Enables the LSE Clock Security System.
bogdanm 0:9b334a45a8ff 231 * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
bogdanm 0:9b334a45a8ff 232 * to the RTC but no hardware action is made to the registers.
bogdanm 0:9b334a45a8ff 233 * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
bogdanm 0:9b334a45a8ff 234 * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
bogdanm 0:9b334a45a8ff 235 * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
bogdanm 0:9b334a45a8ff 236 * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
bogdanm 0:9b334a45a8ff 237 * RTCSEL), or take any required action to secure the application.
bogdanm 0:9b334a45a8ff 238 * @note LSE CSS available only for high density and medium+ devices
bogdanm 0:9b334a45a8ff 239 * @retval None
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241 void HAL_RCCEx_EnableLSECSS(void)
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /**
bogdanm 0:9b334a45a8ff 247 * @brief Disables the LSE Clock Security System.
bogdanm 0:9b334a45a8ff 248 * @note Once enabled this bit cannot be disabled, except after an LSE failure detection
bogdanm 0:9b334a45a8ff 249 * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
bogdanm 0:9b334a45a8ff 250 * Reset by power on reset and RTC software reset (RTCRST bit).
bogdanm 0:9b334a45a8ff 251 * @note LSE CSS available only for high density and medium+ devices
bogdanm 0:9b334a45a8ff 252 * @retval None
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254 void HAL_RCCEx_DisableLSECSS(void)
bogdanm 0:9b334a45a8ff 255 {
bogdanm 0:9b334a45a8ff 256 *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /**
bogdanm 0:9b334a45a8ff 261 * @}
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /**
bogdanm 0:9b334a45a8ff 265 * @}
bogdanm 0:9b334a45a8ff 266 */
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 269 /**
bogdanm 0:9b334a45a8ff 270 * @}
bogdanm 0:9b334a45a8ff 271 */
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /**
bogdanm 0:9b334a45a8ff 274 * @}
bogdanm 0:9b334a45a8ff 275 */
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/