en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l1xx_hal_dma.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 5-September-2014
bogdanm 0:9b334a45a8ff 7 * @brief DMA HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Direct Memory Access (DMA) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + IO operation functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and errors functions
bogdanm 0:9b334a45a8ff 14 @verbatim
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
bogdanm 0:9b334a45a8ff 20 (except for internal SRAM / FLASH memories: no initialization is
bogdanm 0:9b334a45a8ff 21 necessary) please refer to Reference manual for connection between peripherals
bogdanm 0:9b334a45a8ff 22 and DMA requests .
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) For a given Channel, program the required configuration through the following parameters:
bogdanm 0:9b334a45a8ff 25 Transfer Direction, Source and Destination data formats,
bogdanm 0:9b334a45a8ff 26 Circular, Normal or peripheral flow control mode, Channel Priority level,
bogdanm 0:9b334a45a8ff 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
bogdanm 0:9b334a45a8ff 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 31 =================================
bogdanm 0:9b334a45a8ff 32 [..]
bogdanm 0:9b334a45a8ff 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
bogdanm 0:9b334a45a8ff 34 address and destination address and the Length of data to be transferred
bogdanm 0:9b334a45a8ff 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
bogdanm 0:9b334a45a8ff 36 case a fixed Timeout can be configured by User depending from his application.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 39 ===================================
bogdanm 0:9b334a45a8ff 40 [..]
bogdanm 0:9b334a45a8ff 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
bogdanm 0:9b334a45a8ff 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm 0:9b334a45a8ff 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
bogdanm 0:9b334a45a8ff 44 Source address and destination address and the Length of data to be transferred. In this
bogdanm 0:9b334a45a8ff 45 case the DMA interrupt is configured
bogdanm 0:9b334a45a8ff 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 48 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 49 XferErrorCallback (i.e a member of DMA handle structure).
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
bogdanm 0:9b334a45a8ff 52 detection.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 *** DMA HAL driver macros list ***
bogdanm 0:9b334a45a8ff 59 =============================================
bogdanm 0:9b334a45a8ff 60 [..]
bogdanm 0:9b334a45a8ff 61 Below the list of most used macros in DMA HAL driver.
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 64 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 65 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
bogdanm 0:9b334a45a8ff 66 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
bogdanm 0:9b334a45a8ff 67 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 68 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 69 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 [..]
bogdanm 0:9b334a45a8ff 72 (@) You can refer to the DMA HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 @endverbatim
bogdanm 0:9b334a45a8ff 75 ******************************************************************************
bogdanm 0:9b334a45a8ff 76 * @attention
bogdanm 0:9b334a45a8ff 77 *
bogdanm 0:9b334a45a8ff 78 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 79 *
bogdanm 0:9b334a45a8ff 80 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 81 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 82 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 83 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 84 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 85 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 86 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 87 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 88 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 89 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 90 *
bogdanm 0:9b334a45a8ff 91 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 92 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 93 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 94 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 95 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 96 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 97 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 98 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 99 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 100 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 101 *
bogdanm 0:9b334a45a8ff 102 ******************************************************************************
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 106 #include "stm32l1xx_hal.h"
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /** @addtogroup STM32L1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 109 * @{
bogdanm 0:9b334a45a8ff 110 */
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /** @defgroup DMA DMA
bogdanm 0:9b334a45a8ff 113 * @brief DMA HAL module driver
bogdanm 0:9b334a45a8ff 114 * @{
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /** @defgroup DMA_Private_Constants DMA Private Constants
bogdanm 0:9b334a45a8ff 122 * @{
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 125 /**
bogdanm 0:9b334a45a8ff 126 * @}
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 131 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 132 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 133 /** @defgroup DMA_Private_Functions DMA Private Functions
bogdanm 0:9b334a45a8ff 134 * @{
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @}
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /** @defgroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 144 * @{
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /** @defgroup DMA_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 148 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 149 *
bogdanm 0:9b334a45a8ff 150 @verbatim
bogdanm 0:9b334a45a8ff 151 ===============================================================================
bogdanm 0:9b334a45a8ff 152 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 153 ===============================================================================
bogdanm 0:9b334a45a8ff 154 [..]
bogdanm 0:9b334a45a8ff 155 This section provides functions allowing to initialize the DMA Channel source
bogdanm 0:9b334a45a8ff 156 and destination addresses, incrementation and data sizes, transfer direction,
bogdanm 0:9b334a45a8ff 157 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
bogdanm 0:9b334a45a8ff 158 [..]
bogdanm 0:9b334a45a8ff 159 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
bogdanm 0:9b334a45a8ff 160 reference manual.
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 @endverbatim
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @brief Initializes the DMA according to the specified
bogdanm 0:9b334a45a8ff 168 * parameters in the DMA_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 169 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 170 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 171 * @retval HAL status
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 174 {
bogdanm 0:9b334a45a8ff 175 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 178 if(hdma == HAL_NULL)
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Check the parameters */
bogdanm 0:9b334a45a8ff 184 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 185 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
bogdanm 0:9b334a45a8ff 186 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
bogdanm 0:9b334a45a8ff 187 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
bogdanm 0:9b334a45a8ff 188 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
bogdanm 0:9b334a45a8ff 189 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
bogdanm 0:9b334a45a8ff 190 assert_param(IS_DMA_MODE(hdma->Init.Mode));
bogdanm 0:9b334a45a8ff 191 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 194 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 197 tmp = hdma->Instance->CCR;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
bogdanm 0:9b334a45a8ff 200 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
bogdanm 0:9b334a45a8ff 201 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
bogdanm 0:9b334a45a8ff 202 DMA_CCR_DIR));
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Prepare the DMA Channel configuration */
bogdanm 0:9b334a45a8ff 205 tmp |= hdma->Init.Direction |
bogdanm 0:9b334a45a8ff 206 hdma->Init.PeriphInc | hdma->Init.MemInc |
bogdanm 0:9b334a45a8ff 207 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
bogdanm 0:9b334a45a8ff 208 hdma->Init.Mode | hdma->Init.Priority;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Write to DMA Channel CR register */
bogdanm 0:9b334a45a8ff 211 hdma->Instance->CCR = tmp;
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Initialise the error code */
bogdanm 0:9b334a45a8ff 214 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Initialize the DMA state*/
bogdanm 0:9b334a45a8ff 217 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 return HAL_OK;
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /**
bogdanm 0:9b334a45a8ff 223 * @brief DeInitializes the DMA peripheral
bogdanm 0:9b334a45a8ff 224 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 225 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 226 * @retval HAL status
bogdanm 0:9b334a45a8ff 227 */
bogdanm 0:9b334a45a8ff 228 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 229 {
bogdanm 0:9b334a45a8ff 230 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 231 if(hdma == HAL_NULL)
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* Check the DMA peripheral handle */
bogdanm 0:9b334a45a8ff 237 if(hdma->State == HAL_DMA_STATE_BUSY)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 240 }
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /* Disable the selected DMA Channelx */
bogdanm 0:9b334a45a8ff 243 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Reset DMA Channel control register */
bogdanm 0:9b334a45a8ff 246 hdma->Instance->CCR = 0;
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Reset DMA Channel Number of Data to Transfer register */
bogdanm 0:9b334a45a8ff 249 hdma->Instance->CNDTR = 0;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Reset DMA Channel peripheral address register */
bogdanm 0:9b334a45a8ff 252 hdma->Instance->CPAR = 0;
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /* Reset DMA Channel memory address register */
bogdanm 0:9b334a45a8ff 255 hdma->Instance->CMAR = 0;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Clear all flags */
bogdanm 0:9b334a45a8ff 258 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 259 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 260 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* Initialise the error code */
bogdanm 0:9b334a45a8ff 263 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 266 hdma->State = HAL_DMA_STATE_RESET;
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /* Release Lock */
bogdanm 0:9b334a45a8ff 269 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 return HAL_OK;
bogdanm 0:9b334a45a8ff 272 }
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /**
bogdanm 0:9b334a45a8ff 275 * @}
bogdanm 0:9b334a45a8ff 276 */
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /** @defgroup DMA_Group2 I/O operation functions
bogdanm 0:9b334a45a8ff 279 * @brief I/O operation functions
bogdanm 0:9b334a45a8ff 280 *
bogdanm 0:9b334a45a8ff 281 @verbatim
bogdanm 0:9b334a45a8ff 282 ===============================================================================
bogdanm 0:9b334a45a8ff 283 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 284 ===============================================================================
bogdanm 0:9b334a45a8ff 285 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 286 (+) Configure the source, destination address and data length and Start DMA transfer
bogdanm 0:9b334a45a8ff 287 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 288 Start DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 289 (+) Abort DMA transfer
bogdanm 0:9b334a45a8ff 290 (+) Poll for transfer complete
bogdanm 0:9b334a45a8ff 291 (+) Handle DMA interrupt request
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 @endverbatim
bogdanm 0:9b334a45a8ff 294 * @{
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /**
bogdanm 0:9b334a45a8ff 298 * @brief Starts the DMA Transfer.
bogdanm 0:9b334a45a8ff 299 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 300 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 301 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 302 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 303 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 304 * @retval HAL status
bogdanm 0:9b334a45a8ff 305 */
bogdanm 0:9b334a45a8ff 306 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 /* Process locked */
bogdanm 0:9b334a45a8ff 309 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 312 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /* Check the parameters */
bogdanm 0:9b334a45a8ff 315 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 318 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 321 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 324 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 return HAL_OK;
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /**
bogdanm 0:9b334a45a8ff 330 * @brief Start the DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 331 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 332 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 333 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 334 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 335 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 336 * @retval HAL status
bogdanm 0:9b334a45a8ff 337 */
bogdanm 0:9b334a45a8ff 338 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 /* Process locked */
bogdanm 0:9b334a45a8ff 341 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 344 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /* Check the parameters */
bogdanm 0:9b334a45a8ff 347 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 350 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 353 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 356 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Enable the Half transfer complete interrupt */
bogdanm 0:9b334a45a8ff 359 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 362 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 365 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 return HAL_OK;
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /**
bogdanm 0:9b334a45a8ff 371 * @brief Aborts the DMA Transfer.
bogdanm 0:9b334a45a8ff 372 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 373 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 374 *
bogdanm 0:9b334a45a8ff 375 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
bogdanm 0:9b334a45a8ff 376 * effectively disabled is added. If a Channel is disabled
bogdanm 0:9b334a45a8ff 377 * while a data transfer is ongoing, the current data will be transferred
bogdanm 0:9b334a45a8ff 378 * and the Channel will be effectively disabled only after the transfer of
bogdanm 0:9b334a45a8ff 379 * this single data is finished.
bogdanm 0:9b334a45a8ff 380 * @retval HAL status
bogdanm 0:9b334a45a8ff 381 */
bogdanm 0:9b334a45a8ff 382 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Disable the channel */
bogdanm 0:9b334a45a8ff 387 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Get timeout */
bogdanm 0:9b334a45a8ff 390 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Check if the DMA Channel is effectively disabled */
bogdanm 0:9b334a45a8ff 393 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
bogdanm 0:9b334a45a8ff 394 {
bogdanm 0:9b334a45a8ff 395 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 396 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 /* Update error code */
bogdanm 0:9b334a45a8ff 399 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 402 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 405 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 411 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Change the DMA state*/
bogdanm 0:9b334a45a8ff 414 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 return HAL_OK;
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /**
bogdanm 0:9b334a45a8ff 420 * @brief Polling for transfer complete.
bogdanm 0:9b334a45a8ff 421 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 422 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 423 * @param CompleteLevel: Specifies the DMA level complete.
bogdanm 0:9b334a45a8ff 424 * @param Timeout: Timeout duration.
bogdanm 0:9b334a45a8ff 425 * @retval HAL status
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 428 {
bogdanm 0:9b334a45a8ff 429 uint32_t temp;
bogdanm 0:9b334a45a8ff 430 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Get the level transfer complete flag */
bogdanm 0:9b334a45a8ff 433 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 434 {
bogdanm 0:9b334a45a8ff 435 /* Transfer Complete flag */
bogdanm 0:9b334a45a8ff 436 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 437 }
bogdanm 0:9b334a45a8ff 438 else
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 /* Half Transfer Complete flag */
bogdanm 0:9b334a45a8ff 441 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Get timeout */
bogdanm 0:9b334a45a8ff 445 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
bogdanm 0:9b334a45a8ff 448 {
bogdanm 0:9b334a45a8ff 449 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
bogdanm 0:9b334a45a8ff 450 {
bogdanm 0:9b334a45a8ff 451 /* Clear the transfer error flags */
bogdanm 0:9b334a45a8ff 452 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /* Update error code */
bogdanm 0:9b334a45a8ff 455 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 458 hdma->State= HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 461 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 466 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 467 {
bogdanm 0:9b334a45a8ff 468 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 469 {
bogdanm 0:9b334a45a8ff 470 /* Update error code */
bogdanm 0:9b334a45a8ff 471 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 474 hdma->State= HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 477 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 480 }
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 485 {
bogdanm 0:9b334a45a8ff 486 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 487 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 490 all transfers are complete) */
bogdanm 0:9b334a45a8ff 491 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Process unlocked */
bogdanm 0:9b334a45a8ff 494 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496 else
bogdanm 0:9b334a45a8ff 497 {
bogdanm 0:9b334a45a8ff 498 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 499 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 502 all transfers are complete) */
bogdanm 0:9b334a45a8ff 503 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 504 /* Process unlocked */
bogdanm 0:9b334a45a8ff 505 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 return HAL_OK;
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /**
bogdanm 0:9b334a45a8ff 512 * @brief Handles DMA interrupt request.
bogdanm 0:9b334a45a8ff 513 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 514 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 515 * @retval None
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 /* Transfer Error Interrupt management ***************************************/
bogdanm 0:9b334a45a8ff 520 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 521 {
bogdanm 0:9b334a45a8ff 522 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 523 {
bogdanm 0:9b334a45a8ff 524 /* Disable the transfer error interrupt */
bogdanm 0:9b334a45a8ff 525 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /* Clear the transfer error flag */
bogdanm 0:9b334a45a8ff 528 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Update error code */
bogdanm 0:9b334a45a8ff 531 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 534 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 537 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 if (hdma->XferErrorCallback != HAL_NULL)
bogdanm 0:9b334a45a8ff 540 {
bogdanm 0:9b334a45a8ff 541 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 542 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 543 }
bogdanm 0:9b334a45a8ff 544 }
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Half Transfer Complete Interrupt management ******************************/
bogdanm 0:9b334a45a8ff 548 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 549 {
bogdanm 0:9b334a45a8ff 550 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
bogdanm 0:9b334a45a8ff 551 {
bogdanm 0:9b334a45a8ff 552 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 553 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 /* Disable the half transfer interrupt */
bogdanm 0:9b334a45a8ff 556 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 559 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 562 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 if(hdma->XferHalfCpltCallback != HAL_NULL)
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 /* Half transfer callback */
bogdanm 0:9b334a45a8ff 567 hdma->XferHalfCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Transfer Complete Interrupt management ***********************************/
bogdanm 0:9b334a45a8ff 573 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 576 {
bogdanm 0:9b334a45a8ff 577 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 578 {
bogdanm 0:9b334a45a8ff 579 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 580 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 583 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /* Update error code */
bogdanm 0:9b334a45a8ff 586 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 589 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 592 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 if(hdma->XferCpltCallback != HAL_NULL)
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 597 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 598 }
bogdanm 0:9b334a45a8ff 599 }
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601 }
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 /**
bogdanm 0:9b334a45a8ff 604 * @}
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /** @defgroup DMA_Group3 Peripheral State functions
bogdanm 0:9b334a45a8ff 608 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 609 *
bogdanm 0:9b334a45a8ff 610 @verbatim
bogdanm 0:9b334a45a8ff 611 ===============================================================================
bogdanm 0:9b334a45a8ff 612 ##### State and Errors functions #####
bogdanm 0:9b334a45a8ff 613 ===============================================================================
bogdanm 0:9b334a45a8ff 614 [..]
bogdanm 0:9b334a45a8ff 615 This subsection provides functions allowing to
bogdanm 0:9b334a45a8ff 616 (+) Check the DMA state
bogdanm 0:9b334a45a8ff 617 (+) Get error code
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 @endverbatim
bogdanm 0:9b334a45a8ff 620 * @{
bogdanm 0:9b334a45a8ff 621 */
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /**
bogdanm 0:9b334a45a8ff 624 * @brief Returns the DMA state.
bogdanm 0:9b334a45a8ff 625 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 626 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 627 * @retval HAL state
bogdanm 0:9b334a45a8ff 628 */
bogdanm 0:9b334a45a8ff 629 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 630 {
bogdanm 0:9b334a45a8ff 631 return hdma->State;
bogdanm 0:9b334a45a8ff 632 }
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /**
bogdanm 0:9b334a45a8ff 635 * @brief Return the DMA error code
bogdanm 0:9b334a45a8ff 636 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 637 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 638 * @retval DMA Error Code
bogdanm 0:9b334a45a8ff 639 */
bogdanm 0:9b334a45a8ff 640 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 641 {
bogdanm 0:9b334a45a8ff 642 return hdma->ErrorCode;
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 /**
bogdanm 0:9b334a45a8ff 646 * @}
bogdanm 0:9b334a45a8ff 647 */
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649 /**
bogdanm 0:9b334a45a8ff 650 * @}
bogdanm 0:9b334a45a8ff 651 */
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /** @addtogroup DMA_Private_Functions
bogdanm 0:9b334a45a8ff 654 * @{
bogdanm 0:9b334a45a8ff 655 */
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 /**
bogdanm 0:9b334a45a8ff 658 * @brief Sets the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 659 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 660 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 661 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 662 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 663 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 664 * @retval HAL status
bogdanm 0:9b334a45a8ff 665 */
bogdanm 0:9b334a45a8ff 666 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 667 {
bogdanm 0:9b334a45a8ff 668 /* Configure DMA Channel data length */
bogdanm 0:9b334a45a8ff 669 hdma->Instance->CNDTR = DataLength;
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 672 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 675 hdma->Instance->CPAR = DstAddress;
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 678 hdma->Instance->CMAR = SrcAddress;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 681 else
bogdanm 0:9b334a45a8ff 682 {
bogdanm 0:9b334a45a8ff 683 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 684 hdma->Instance->CPAR = SrcAddress;
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 687 hdma->Instance->CMAR = DstAddress;
bogdanm 0:9b334a45a8ff 688 }
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 /**
bogdanm 0:9b334a45a8ff 692 * @}
bogdanm 0:9b334a45a8ff 693 */
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 /**
bogdanm 0:9b334a45a8ff 700 * @}
bogdanm 0:9b334a45a8ff 701 */
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /**
bogdanm 0:9b334a45a8ff 704 * @}
bogdanm 0:9b334a45a8ff 705 */
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/