mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 113:b3775bf36a83

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Timer Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Timer Base Start
bogdanm	0:9b334a45a8ff	12	* + Timer Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Timer Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Timer Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Timer Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Timer Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Timer Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Timer Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Timer Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Timer Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Timer Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Timer Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Timer Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Timer One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Timer One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Timer One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Timer Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Timer Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Timer Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Timer Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Timer OCRef clear configuration
bogdanm	0:9b334a45a8ff	32	* + Timer External Clock configuration
bogdanm	0:9b334a45a8ff	33	* + Timer Complementary signal bread and dead time configuration
bogdanm	0:9b334a45a8ff	34	* + Timer Master and Slave synchronization configuration
bogdanm	0:9b334a45a8ff	35	@verbatim
bogdanm	0:9b334a45a8ff	36	==============================================================================
bogdanm	0:9b334a45a8ff	37	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	38	==============================================================================
bogdanm	0:9b334a45a8ff	39	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	40	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	41	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
bogdanm	0:9b334a45a8ff	42	frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	43	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	44	(++) Input Capture
bogdanm	0:9b334a45a8ff	45	(++) Output Compare
bogdanm	0:9b334a45a8ff	46	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	47	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	48	(#) Synchronization circuit to control the timer with external signals and to interconnect
bogdanm	0:9b334a45a8ff	49	several timers together.
bogdanm	0:9b334a45a8ff	50	(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
bogdanm	0:9b334a45a8ff	51	purposes
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	54	================================================================================
bogdanm	0:9b334a45a8ff	55	[..]
bogdanm	0:9b334a45a8ff	56	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	57	depending from feature used :
bogdanm	0:9b334a45a8ff	58	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	59	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	60	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	61	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	62	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	63	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	64
bogdanm	0:9b334a45a8ff	65	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	66	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	67	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	68	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	69	__HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	70	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
bogdanm	0:9b334a45a8ff	73	using the following function:
bogdanm	0:9b334a45a8ff	74	HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	77	initialization function of this driver:
bogdanm	0:9b334a45a8ff	78	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	80	Output Compare signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	82	PWM signal.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	84	external signal.
bogdanm	0:9b334a45a8ff	85	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
bogdanm	0:9b334a45a8ff	86	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	(#) Activate the TIM peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	89	HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
bogdanm	0:9b334a45a8ff	90	HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
bogdanm	0:9b334a45a8ff	91	HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
bogdanm	0:9b334a45a8ff	92	HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
bogdanm	0:9b334a45a8ff	93	HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
bogdanm	0:9b334a45a8ff	94	HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	97	HAL_TIM_DMABurst_WriteStart
bogdanm	0:9b334a45a8ff	98	HAL_TIM_DMABurst_ReadStart
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	@endverbatim
bogdanm	0:9b334a45a8ff	101	******************************************************************************
bogdanm	0:9b334a45a8ff	102	* @attention
bogdanm	0:9b334a45a8ff	103	*
mbed_official	113:b3775bf36a83	104	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	105	*
bogdanm	0:9b334a45a8ff	106	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	107	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	108	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	109	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	110	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	111	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	112	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	113	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	114	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	115	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	116	*
bogdanm	0:9b334a45a8ff	117	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	118	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	119	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	120	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	121	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	122	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	123	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	124	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	125	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	126	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	127	*
bogdanm	0:9b334a45a8ff	128	******************************************************************************
bogdanm	0:9b334a45a8ff	129	*/
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	132	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	135	* @{
bogdanm	0:9b334a45a8ff	136	*/
bogdanm	0:9b334a45a8ff	137
mbed_official	113:b3775bf36a83	138	#ifdef HAL_TIM_MODULE_ENABLED
mbed_official	113:b3775bf36a83	139
bogdanm	0:9b334a45a8ff	140	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	141	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	142	* @{
bogdanm	0:9b334a45a8ff	143	*/
bogdanm	0:9b334a45a8ff	144
mbed_official	113:b3775bf36a83	145	/** @addtogroup TIM_Private
mbed_official	113:b3775bf36a83	146	* @{
mbed_official	113:b3775bf36a83	147	*/
bogdanm	0:9b334a45a8ff	148	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	149	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	150	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	151	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	152	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	153	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	0:9b334a45a8ff	154	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	155	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	156	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	157	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	158	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	159	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	160	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	161	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	162	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	163	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	164	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm	0:9b334a45a8ff	165	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
bogdanm	0:9b334a45a8ff	166	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	0:9b334a45a8ff	167	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	168	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	169	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef htim,TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	113:b3775bf36a83	170	/**
mbed_official	113:b3775bf36a83	171	* @}
mbed_official	113:b3775bf36a83	172	*/
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	/*******************************************************************************/
bogdanm	0:9b334a45a8ff	175	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	176	/*******************************************************************************/
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	/** @addtogroup TIM_Exported_Functions
bogdanm	0:9b334a45a8ff	179	* @{
bogdanm	0:9b334a45a8ff	180	*/
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	183	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	184	*
bogdanm	0:9b334a45a8ff	185	@verbatim
bogdanm	0:9b334a45a8ff	186	==============================================================================
bogdanm	0:9b334a45a8ff	187	##### Timer Base functions #####
bogdanm	0:9b334a45a8ff	188	==============================================================================
bogdanm	0:9b334a45a8ff	189	[..]
bogdanm	0:9b334a45a8ff	190	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	191	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	192	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	193	(+) Start the Timer Base.
bogdanm	0:9b334a45a8ff	194	(+) Stop the Timer Base.
bogdanm	0:9b334a45a8ff	195	(+) Start the Timer Base and enable interrupt.
bogdanm	0:9b334a45a8ff	196	(+) Stop the Timer Base and disable interrupt.
bogdanm	0:9b334a45a8ff	197	(+) Start the Timer Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	198	(+) Stop the Timer Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	@endverbatim
bogdanm	0:9b334a45a8ff	201	* @{
bogdanm	0:9b334a45a8ff	202	*/
bogdanm	0:9b334a45a8ff	203	/**
bogdanm	0:9b334a45a8ff	204	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	205	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	206	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	207	* @retval HAL status
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	210	{
bogdanm	0:9b334a45a8ff	211	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	212	if(htim == NULL)
bogdanm	0:9b334a45a8ff	213	{
bogdanm	0:9b334a45a8ff	214	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	215	}
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	/* Check the parameters */
bogdanm	0:9b334a45a8ff	218	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	219	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	220	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	221	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	222	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	225	{
mbed_official	113:b3775bf36a83	226	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	227	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	228
bogdanm	0:9b334a45a8ff	229	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	230	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	231	}
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	234	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	237	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	240	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	return HAL_OK;
bogdanm	0:9b334a45a8ff	243	}
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/**
bogdanm	0:9b334a45a8ff	246	* @brief DeInitializes the TIM Base peripheral
bogdanm	0:9b334a45a8ff	247	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	248	* @retval HAL status
bogdanm	0:9b334a45a8ff	249	*/
bogdanm	0:9b334a45a8ff	250	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	251	{
bogdanm	0:9b334a45a8ff	252	/* Check the parameters */
bogdanm	0:9b334a45a8ff	253	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	258	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	261	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Change TIM state */
bogdanm	0:9b334a45a8ff	264	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	/* Release Lock */
bogdanm	0:9b334a45a8ff	267	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	return HAL_OK;
bogdanm	0:9b334a45a8ff	270	}
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/**
bogdanm	0:9b334a45a8ff	273	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	274	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	275	* @retval None
bogdanm	0:9b334a45a8ff	276	*/
bogdanm	0:9b334a45a8ff	277	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	278	{
mbed_official	113:b3775bf36a83	279	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	280	UNUSED(htim);
mbed_official	113:b3775bf36a83	281
bogdanm	0:9b334a45a8ff	282	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	283	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	284	*/
bogdanm	0:9b334a45a8ff	285	}
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/**
bogdanm	0:9b334a45a8ff	288	* @brief DeInitializes TIM Base MSP.
bogdanm	0:9b334a45a8ff	289	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	290	* @retval None
bogdanm	0:9b334a45a8ff	291	*/
bogdanm	0:9b334a45a8ff	292	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	293	{
mbed_official	113:b3775bf36a83	294	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	295	UNUSED(htim);
mbed_official	113:b3775bf36a83	296
bogdanm	0:9b334a45a8ff	297	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	298	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	}
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	304	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	305	* @retval HAL status
bogdanm	0:9b334a45a8ff	306	*/
bogdanm	0:9b334a45a8ff	307	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	308	{
bogdanm	0:9b334a45a8ff	309	/* Check the parameters */
bogdanm	0:9b334a45a8ff	310	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	313	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	316	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	319	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Return function status */
bogdanm	0:9b334a45a8ff	322	return HAL_OK;
bogdanm	0:9b334a45a8ff	323	}
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	327	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	328	* @retval HAL status
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	331	{
bogdanm	0:9b334a45a8ff	332	/* Check the parameters */
bogdanm	0:9b334a45a8ff	333	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	336	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	339	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	342	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/* Return function status */
bogdanm	0:9b334a45a8ff	345	return HAL_OK;
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/**
bogdanm	0:9b334a45a8ff	349	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	350	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	351	* @retval HAL status
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	354	{
bogdanm	0:9b334a45a8ff	355	/* Check the parameters */
bogdanm	0:9b334a45a8ff	356	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	359	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	360
bogdanm	0:9b334a45a8ff	361	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	362	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/* Return function status */
bogdanm	0:9b334a45a8ff	365	return HAL_OK;
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/**
bogdanm	0:9b334a45a8ff	369	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	370	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	371	* @retval HAL status
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	374	{
bogdanm	0:9b334a45a8ff	375	/* Check the parameters */
bogdanm	0:9b334a45a8ff	376	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	377	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	378	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	381	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/* Return function status */
bogdanm	0:9b334a45a8ff	384	return HAL_OK;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	389	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	390	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	391	* @param Length: The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	392	* @retval HAL status
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	/* Check the parameters */
bogdanm	0:9b334a45a8ff	397	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	400	{
bogdanm	0:9b334a45a8ff	401	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	402	}
bogdanm	0:9b334a45a8ff	403	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409	else
bogdanm	0:9b334a45a8ff	410	{
bogdanm	0:9b334a45a8ff	411	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	412	}
bogdanm	0:9b334a45a8ff	413	}
bogdanm	0:9b334a45a8ff	414	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	415	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	416
bogdanm	0:9b334a45a8ff	417	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	418	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	421	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	424	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	427	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/* Return function status */
bogdanm	0:9b334a45a8ff	430	return HAL_OK;
bogdanm	0:9b334a45a8ff	431	}
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/**
bogdanm	0:9b334a45a8ff	434	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	435	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	436	* @retval HAL status
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	439	{
bogdanm	0:9b334a45a8ff	440	/* Check the parameters */
bogdanm	0:9b334a45a8ff	441	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	444	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	447	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/* Change the htim state */
bogdanm	0:9b334a45a8ff	450	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/* Return function status */
bogdanm	0:9b334a45a8ff	453	return HAL_OK;
bogdanm	0:9b334a45a8ff	454	}
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/**
bogdanm	0:9b334a45a8ff	457	* @}
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	462	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	463	*
bogdanm	0:9b334a45a8ff	464	@verbatim
bogdanm	0:9b334a45a8ff	465	==============================================================================
bogdanm	0:9b334a45a8ff	466	##### Timer Output Compare functions #####
bogdanm	0:9b334a45a8ff	467	==============================================================================
bogdanm	0:9b334a45a8ff	468	[..]
bogdanm	0:9b334a45a8ff	469	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	470	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	471	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	472	(+) Start the Timer Output Compare.
bogdanm	0:9b334a45a8ff	473	(+) Stop the Timer Output Compare.
bogdanm	0:9b334a45a8ff	474	(+) Start the Timer Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	475	(+) Stop the Timer Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	476	(+) Start the Timer Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	477	(+) Stop the Timer Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	@endverbatim
bogdanm	0:9b334a45a8ff	480	* @{
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482	/**
bogdanm	0:9b334a45a8ff	483	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	484	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	485	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	486	* @retval HAL status
bogdanm	0:9b334a45a8ff	487	*/
bogdanm	0:9b334a45a8ff	488	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	489	{
bogdanm	0:9b334a45a8ff	490	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	491	if(htim == NULL)
bogdanm	0:9b334a45a8ff	492	{
bogdanm	0:9b334a45a8ff	493	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	494	}
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/* Check the parameters */
bogdanm	0:9b334a45a8ff	497	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	498	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	499	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	500	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	501	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	504	{
mbed_official	113:b3775bf36a83	505	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	506	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	507
bogdanm	0:9b334a45a8ff	508	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
bogdanm	0:9b334a45a8ff	509	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	510	}
bogdanm	0:9b334a45a8ff	511	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	512	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	515	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	518	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	return HAL_OK;
bogdanm	0:9b334a45a8ff	521	}
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/**
bogdanm	0:9b334a45a8ff	524	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	525	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	526	* @retval HAL status
bogdanm	0:9b334a45a8ff	527	*/
bogdanm	0:9b334a45a8ff	528	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	529	{
bogdanm	0:9b334a45a8ff	530	/* Check the parameters */
bogdanm	0:9b334a45a8ff	531	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	536	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	539	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/* Change TIM state */
bogdanm	0:9b334a45a8ff	542	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* Release Lock */
bogdanm	0:9b334a45a8ff	545	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	return HAL_OK;
bogdanm	0:9b334a45a8ff	548	}
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	/**
bogdanm	0:9b334a45a8ff	551	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	552	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	553	* @retval None
bogdanm	0:9b334a45a8ff	554	*/
bogdanm	0:9b334a45a8ff	555	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	556	{
mbed_official	113:b3775bf36a83	557	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	558	UNUSED(htim);
mbed_official	113:b3775bf36a83	559
bogdanm	0:9b334a45a8ff	560	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	561	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563	}
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	/**
bogdanm	0:9b334a45a8ff	566	* @brief DeInitializes TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	567	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	568	* @retval None
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	571	{
mbed_official	113:b3775bf36a83	572	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	573	UNUSED(htim);
mbed_official	113:b3775bf36a83	574
bogdanm	0:9b334a45a8ff	575	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	576	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	577	*/
bogdanm	0:9b334a45a8ff	578	}
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/**
bogdanm	0:9b334a45a8ff	581	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	582	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	583	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	584	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	585	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	586	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	587	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	588	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	589	* @retval HAL status
bogdanm	0:9b334a45a8ff	590	*/
bogdanm	0:9b334a45a8ff	591	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	592	{
bogdanm	0:9b334a45a8ff	593	/* Check the parameters */
bogdanm	0:9b334a45a8ff	594	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	597	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	600	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/* Return function status */
bogdanm	0:9b334a45a8ff	603	return HAL_OK;
bogdanm	0:9b334a45a8ff	604	}
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/**
bogdanm	0:9b334a45a8ff	607	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	608	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	609	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	610	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	611	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	612	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	613	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	614	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	615	* @retval HAL status
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	/* Check the parameters */
bogdanm	0:9b334a45a8ff	620	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	623	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	626	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	/* Return function status */
bogdanm	0:9b334a45a8ff	629	return HAL_OK;
bogdanm	0:9b334a45a8ff	630	}
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	/**
bogdanm	0:9b334a45a8ff	633	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	634	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	635	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	636	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	637	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	638	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	639	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	640	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	641	* @retval HAL status
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	/* Check the parameters */
bogdanm	0:9b334a45a8ff	646	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	switch (Channel)
bogdanm	0:9b334a45a8ff	649	{
bogdanm	0:9b334a45a8ff	650	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	653	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	654	}
bogdanm	0:9b334a45a8ff	655	break;
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	658	{
bogdanm	0:9b334a45a8ff	659	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	660	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	661	}
bogdanm	0:9b334a45a8ff	662	break;
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	667	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669	break;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	672	{
bogdanm	0:9b334a45a8ff	673	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	674	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676	break;
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	default:
bogdanm	0:9b334a45a8ff	679	break;
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	683	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	686	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/* Return function status */
bogdanm	0:9b334a45a8ff	689	return HAL_OK;
bogdanm	0:9b334a45a8ff	690	}
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/**
bogdanm	0:9b334a45a8ff	693	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	694	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	695	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	696	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	697	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	698	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	699	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	700	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	701	* @retval HAL status
bogdanm	0:9b334a45a8ff	702	*/
bogdanm	0:9b334a45a8ff	703	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	704	{
bogdanm	0:9b334a45a8ff	705	/* Check the parameters */
bogdanm	0:9b334a45a8ff	706	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	switch (Channel)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	713	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	714	}
bogdanm	0:9b334a45a8ff	715	break;
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	718	{
bogdanm	0:9b334a45a8ff	719	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	721	}
bogdanm	0:9b334a45a8ff	722	break;
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	725	{
bogdanm	0:9b334a45a8ff	726	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729	break;
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	734	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736	break;
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	default:
bogdanm	0:9b334a45a8ff	739	break;
bogdanm	0:9b334a45a8ff	740	}
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	743	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	746	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Return function status */
bogdanm	0:9b334a45a8ff	749	return HAL_OK;
bogdanm	0:9b334a45a8ff	750	}
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	/**
bogdanm	0:9b334a45a8ff	753	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	754	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	755	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	756	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	757	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	758	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	759	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	760	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	761	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	762	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	763	* @retval HAL status
bogdanm	0:9b334a45a8ff	764	*/
bogdanm	0:9b334a45a8ff	765	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	766	{
bogdanm	0:9b334a45a8ff	767	/* Check the parameters */
bogdanm	0:9b334a45a8ff	768	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	773	}
bogdanm	0:9b334a45a8ff	774	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	775	{
bogdanm	0:9b334a45a8ff	776	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	779	}
bogdanm	0:9b334a45a8ff	780	else
bogdanm	0:9b334a45a8ff	781	{
bogdanm	0:9b334a45a8ff	782	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	783	}
bogdanm	0:9b334a45a8ff	784	}
bogdanm	0:9b334a45a8ff	785	switch (Channel)
bogdanm	0:9b334a45a8ff	786	{
bogdanm	0:9b334a45a8ff	787	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	790	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	793	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	796	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	799	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	800	}
bogdanm	0:9b334a45a8ff	801	break;
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	806	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	809	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	812	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	815	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	816	}
bogdanm	0:9b334a45a8ff	817	break;
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	820	{
bogdanm	0:9b334a45a8ff	821	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	822	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	825	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	828	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	831	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	832	}
bogdanm	0:9b334a45a8ff	833	break;
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	836	{
bogdanm	0:9b334a45a8ff	837	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	838	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	841	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	844	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	847	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	848	}
bogdanm	0:9b334a45a8ff	849	break;
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	default:
bogdanm	0:9b334a45a8ff	852	break;
bogdanm	0:9b334a45a8ff	853	}
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	856	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	859	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/* Return function status */
bogdanm	0:9b334a45a8ff	862	return HAL_OK;
bogdanm	0:9b334a45a8ff	863	}
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/**
bogdanm	0:9b334a45a8ff	866	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	867	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	868	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	869	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	870	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	871	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	872	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	873	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	874	* @retval HAL status
bogdanm	0:9b334a45a8ff	875	*/
bogdanm	0:9b334a45a8ff	876	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	877	{
bogdanm	0:9b334a45a8ff	878	/* Check the parameters */
bogdanm	0:9b334a45a8ff	879	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	switch (Channel)
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	884	{
bogdanm	0:9b334a45a8ff	885	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	886	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	break;
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	891	{
bogdanm	0:9b334a45a8ff	892	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	893	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895	break;
bogdanm	0:9b334a45a8ff	896
bogdanm	0:9b334a45a8ff	897	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	900	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902	break;
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	905	{
bogdanm	0:9b334a45a8ff	906	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909	break;
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	default:
bogdanm	0:9b334a45a8ff	912	break;
bogdanm	0:9b334a45a8ff	913	}
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	916	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	919	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/* Change the htim state */
bogdanm	0:9b334a45a8ff	922	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* Return function status */
bogdanm	0:9b334a45a8ff	925	return HAL_OK;
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/**
bogdanm	0:9b334a45a8ff	929	* @}
bogdanm	0:9b334a45a8ff	930	*/
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	933	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	934	*
bogdanm	0:9b334a45a8ff	935	@verbatim
bogdanm	0:9b334a45a8ff	936	==============================================================================
bogdanm	0:9b334a45a8ff	937	##### Timer PWM functions #####
bogdanm	0:9b334a45a8ff	938	==============================================================================
bogdanm	0:9b334a45a8ff	939	[..]
bogdanm	0:9b334a45a8ff	940	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	941	(+) Initialize and configure the TIM OPWM.
bogdanm	0:9b334a45a8ff	942	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	943	(+) Start the Timer PWM.
bogdanm	0:9b334a45a8ff	944	(+) Stop the Timer PWM.
bogdanm	0:9b334a45a8ff	945	(+) Start the Timer PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	946	(+) Stop the Timer PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	947	(+) Start the Timer PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	948	(+) Stop the Timer PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	@endverbatim
bogdanm	0:9b334a45a8ff	951	* @{
bogdanm	0:9b334a45a8ff	952	*/
bogdanm	0:9b334a45a8ff	953	/**
bogdanm	0:9b334a45a8ff	954	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	955	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	956	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	957	* @retval HAL status
bogdanm	0:9b334a45a8ff	958	*/
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	962	{
bogdanm	0:9b334a45a8ff	963	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	964	if(htim == NULL)
bogdanm	0:9b334a45a8ff	965	{
bogdanm	0:9b334a45a8ff	966	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/* Check the parameters */
bogdanm	0:9b334a45a8ff	970	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	971	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	972	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	973	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	974	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	977	{
mbed_official	113:b3775bf36a83	978	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	979	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	980
bogdanm	0:9b334a45a8ff	981	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	982	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	986	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	989	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	992	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	return HAL_OK;
bogdanm	0:9b334a45a8ff	995	}
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/**
bogdanm	0:9b334a45a8ff	998	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	999	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1000	* @retval HAL status
bogdanm	0:9b334a45a8ff	1001	*/
bogdanm	0:9b334a45a8ff	1002	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1003	{
bogdanm	0:9b334a45a8ff	1004	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1005	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1010	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1013	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1016	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Release Lock */
bogdanm	0:9b334a45a8ff	1019	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	return HAL_OK;
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	/**
bogdanm	0:9b334a45a8ff	1025	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1026	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1027	* @retval None
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1030	{
mbed_official	113:b3775bf36a83	1031	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1032	UNUSED(htim);
mbed_official	113:b3775bf36a83	1033
bogdanm	0:9b334a45a8ff	1034	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1035	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1036	*/
bogdanm	0:9b334a45a8ff	1037	}
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/**
bogdanm	0:9b334a45a8ff	1040	* @brief DeInitializes TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1041	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1042	* @retval None
bogdanm	0:9b334a45a8ff	1043	*/
bogdanm	0:9b334a45a8ff	1044	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1045	{
mbed_official	113:b3775bf36a83	1046	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1047	UNUSED(htim);
mbed_official	113:b3775bf36a83	1048
bogdanm	0:9b334a45a8ff	1049	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1050	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1051	*/
bogdanm	0:9b334a45a8ff	1052	}
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/**
bogdanm	0:9b334a45a8ff	1055	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1056	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1057	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1058	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1059	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1060	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1061	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1062	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1063	* @retval HAL status
bogdanm	0:9b334a45a8ff	1064	*/
bogdanm	0:9b334a45a8ff	1065	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1066	{
bogdanm	0:9b334a45a8ff	1067	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1068	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1071	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1074	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/* Return function status */
bogdanm	0:9b334a45a8ff	1077	return HAL_OK;
bogdanm	0:9b334a45a8ff	1078	}
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/**
bogdanm	0:9b334a45a8ff	1081	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1082	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1083	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1084	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1085	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1086	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1087	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1088	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1089	* @retval HAL status
bogdanm	0:9b334a45a8ff	1090	*/
bogdanm	0:9b334a45a8ff	1091	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1094	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1097	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1100	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1103	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/* Return function status */
bogdanm	0:9b334a45a8ff	1106	return HAL_OK;
bogdanm	0:9b334a45a8ff	1107	}
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/**
bogdanm	0:9b334a45a8ff	1110	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1111	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1112	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	1113	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1114	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1115	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1116	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1117	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1118	* @retval HAL status
bogdanm	0:9b334a45a8ff	1119	*/
bogdanm	0:9b334a45a8ff	1120	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1121	{
bogdanm	0:9b334a45a8ff	1122	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1123	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	switch (Channel)
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1128	{
bogdanm	0:9b334a45a8ff	1129	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1130	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1131	}
bogdanm	0:9b334a45a8ff	1132	break;
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1135	{
bogdanm	0:9b334a45a8ff	1136	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1137	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1138	}
bogdanm	0:9b334a45a8ff	1139	break;
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1142	{
bogdanm	0:9b334a45a8ff	1143	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1144	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1145	}
bogdanm	0:9b334a45a8ff	1146	break;
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1149	{
bogdanm	0:9b334a45a8ff	1150	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1151	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1152	}
bogdanm	0:9b334a45a8ff	1153	break;
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	default:
bogdanm	0:9b334a45a8ff	1156	break;
bogdanm	0:9b334a45a8ff	1157	}
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1160	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1163	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Return function status */
bogdanm	0:9b334a45a8ff	1166	return HAL_OK;
bogdanm	0:9b334a45a8ff	1167	}
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	/**
bogdanm	0:9b334a45a8ff	1170	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1171	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1172	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1173	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1174	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1175	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1176	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1177	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1178	* @retval HAL status
bogdanm	0:9b334a45a8ff	1179	*/
bogdanm	0:9b334a45a8ff	1180	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1181	{
bogdanm	0:9b334a45a8ff	1182	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1183	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	switch (Channel)
bogdanm	0:9b334a45a8ff	1186	{
bogdanm	0:9b334a45a8ff	1187	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1190	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192	break;
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1195	{
bogdanm	0:9b334a45a8ff	1196	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1197	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1198	}
bogdanm	0:9b334a45a8ff	1199	break;
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1202	{
bogdanm	0:9b334a45a8ff	1203	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1204	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206	break;
bogdanm	0:9b334a45a8ff	1207
bogdanm	0:9b334a45a8ff	1208	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1209	{
bogdanm	0:9b334a45a8ff	1210	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1211	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1212	}
bogdanm	0:9b334a45a8ff	1213	break;
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	default:
bogdanm	0:9b334a45a8ff	1216	break;
bogdanm	0:9b334a45a8ff	1217	}
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1220	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1223	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/* Return function status */
bogdanm	0:9b334a45a8ff	1226	return HAL_OK;
bogdanm	0:9b334a45a8ff	1227	}
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	/**
bogdanm	0:9b334a45a8ff	1230	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1231	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1232	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1233	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1234	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1235	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1236	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1237	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1238	* @param pData: The source Buffer address. This buffer contains the values
bogdanm	0:9b334a45a8ff	1239	* which will be loaded inside the capture/compare registers.
bogdanm	0:9b334a45a8ff	1240	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1241	* @retval HAL status
bogdanm	0:9b334a45a8ff	1242	*/
bogdanm	0:9b334a45a8ff	1243	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1244	{
bogdanm	0:9b334a45a8ff	1245	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1246	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1249	{
bogdanm	0:9b334a45a8ff	1250	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1251	}
bogdanm	0:9b334a45a8ff	1252	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1253	{
bogdanm	0:9b334a45a8ff	1254	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1257	}
bogdanm	0:9b334a45a8ff	1258	else
bogdanm	0:9b334a45a8ff	1259	{
bogdanm	0:9b334a45a8ff	1260	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1261	}
bogdanm	0:9b334a45a8ff	1262	}
bogdanm	0:9b334a45a8ff	1263	switch (Channel)
bogdanm	0:9b334a45a8ff	1264	{
bogdanm	0:9b334a45a8ff	1265	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1266	{
bogdanm	0:9b334a45a8ff	1267	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1268	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1271	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1274	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1277	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1278	}
bogdanm	0:9b334a45a8ff	1279	break;
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1284	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1287	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1290	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1293	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1294	}
bogdanm	0:9b334a45a8ff	1295	break;
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1300	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1303	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1306	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1309	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1310	}
bogdanm	0:9b334a45a8ff	1311	break;
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1316	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1319	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1322	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1325	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1326	}
bogdanm	0:9b334a45a8ff	1327	break;
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	default:
bogdanm	0:9b334a45a8ff	1330	break;
bogdanm	0:9b334a45a8ff	1331	}
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1334	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1337	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Return function status */
bogdanm	0:9b334a45a8ff	1340	return HAL_OK;
bogdanm	0:9b334a45a8ff	1341	}
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	/**
bogdanm	0:9b334a45a8ff	1344	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1345	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1346	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1347	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1348	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1349	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1350	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1351	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1352	* @retval HAL status
bogdanm	0:9b334a45a8ff	1353	*/
bogdanm	0:9b334a45a8ff	1354	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1355	{
bogdanm	0:9b334a45a8ff	1356	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1357	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	switch (Channel)
bogdanm	0:9b334a45a8ff	1360	{
bogdanm	0:9b334a45a8ff	1361	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1364	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1365	}
bogdanm	0:9b334a45a8ff	1366	break;
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1369	{
bogdanm	0:9b334a45a8ff	1370	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1371	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1372	}
bogdanm	0:9b334a45a8ff	1373	break;
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1376	{
bogdanm	0:9b334a45a8ff	1377	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1378	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1379	}
bogdanm	0:9b334a45a8ff	1380	break;
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1383	{
bogdanm	0:9b334a45a8ff	1384	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1385	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1386	}
bogdanm	0:9b334a45a8ff	1387	break;
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	default:
bogdanm	0:9b334a45a8ff	1390	break;
bogdanm	0:9b334a45a8ff	1391	}
bogdanm	0:9b334a45a8ff	1392
bogdanm	0:9b334a45a8ff	1393	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1394	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1397	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1400	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	/* Return function status */
bogdanm	0:9b334a45a8ff	1403	return HAL_OK;
bogdanm	0:9b334a45a8ff	1404	}
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/**
bogdanm	0:9b334a45a8ff	1407	* @}
bogdanm	0:9b334a45a8ff	1408	*/
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	1411	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1412	*
bogdanm	0:9b334a45a8ff	1413	@verbatim
bogdanm	0:9b334a45a8ff	1414	==============================================================================
bogdanm	0:9b334a45a8ff	1415	##### Timer Input Capture functions #####
bogdanm	0:9b334a45a8ff	1416	==============================================================================
bogdanm	0:9b334a45a8ff	1417	[..]
bogdanm	0:9b334a45a8ff	1418	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1419	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1420	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1421	(+) Start the Timer Input Capture.
bogdanm	0:9b334a45a8ff	1422	(+) Stop the Timer Input Capture.
bogdanm	0:9b334a45a8ff	1423	(+) Start the Timer Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1424	(+) Stop the Timer Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1425	(+) Start the Timer Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1426	(+) Stop the Timer Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	@endverbatim
bogdanm	0:9b334a45a8ff	1429	* @{
bogdanm	0:9b334a45a8ff	1430	*/
bogdanm	0:9b334a45a8ff	1431	/**
bogdanm	0:9b334a45a8ff	1432	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1433	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1434	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1435	* @retval HAL status
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1438	{
bogdanm	0:9b334a45a8ff	1439	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1440	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1441	{
bogdanm	0:9b334a45a8ff	1442	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1443	}
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1446	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1447	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1448	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1449	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	1450	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1453	{
mbed_official	113:b3775bf36a83	1454	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	1455	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	1456
bogdanm	0:9b334a45a8ff	1457	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1458	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1462	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1465	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1468	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	return HAL_OK;
bogdanm	0:9b334a45a8ff	1471	}
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/**
bogdanm	0:9b334a45a8ff	1474	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1475	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1476	* @retval HAL status
bogdanm	0:9b334a45a8ff	1477	*/
bogdanm	0:9b334a45a8ff	1478	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1479	{
bogdanm	0:9b334a45a8ff	1480	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1481	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1486	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1489	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1492	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/* Release Lock */
bogdanm	0:9b334a45a8ff	1495	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	return HAL_OK;
bogdanm	0:9b334a45a8ff	1498	}
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	/**
bogdanm	0:9b334a45a8ff	1501	* @brief Initializes the TIM INput Capture MSP.
bogdanm	0:9b334a45a8ff	1502	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1503	* @retval None
bogdanm	0:9b334a45a8ff	1504	*/
bogdanm	0:9b334a45a8ff	1505	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1506	{
mbed_official	113:b3775bf36a83	1507	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1508	UNUSED(htim);
mbed_official	113:b3775bf36a83	1509
bogdanm	0:9b334a45a8ff	1510	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1511	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1512	*/
bogdanm	0:9b334a45a8ff	1513	}
bogdanm	0:9b334a45a8ff	1514
bogdanm	0:9b334a45a8ff	1515	/**
bogdanm	0:9b334a45a8ff	1516	* @brief DeInitializes TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1517	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1518	* @retval None
bogdanm	0:9b334a45a8ff	1519	*/
bogdanm	0:9b334a45a8ff	1520	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1521	{
mbed_official	113:b3775bf36a83	1522	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1523	UNUSED(htim);
mbed_official	113:b3775bf36a83	1524
bogdanm	0:9b334a45a8ff	1525	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1526	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529	/**
bogdanm	0:9b334a45a8ff	1530	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1531	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1532	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1533	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1534	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1535	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1536	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1537	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1538	* @retval HAL status
bogdanm	0:9b334a45a8ff	1539	*/
bogdanm	0:9b334a45a8ff	1540	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1541	{
bogdanm	0:9b334a45a8ff	1542	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1543	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1546	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1549	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	/* Return function status */
bogdanm	0:9b334a45a8ff	1552	return HAL_OK;
bogdanm	0:9b334a45a8ff	1553	}
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/**
bogdanm	0:9b334a45a8ff	1556	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1557	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1558	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1559	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1560	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1561	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1562	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1563	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1564	* @retval HAL status
bogdanm	0:9b334a45a8ff	1565	*/
bogdanm	0:9b334a45a8ff	1566	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1567	{
bogdanm	0:9b334a45a8ff	1568	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1569	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1572	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1575	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1576
bogdanm	0:9b334a45a8ff	1577	/* Return function status */
bogdanm	0:9b334a45a8ff	1578	return HAL_OK;
bogdanm	0:9b334a45a8ff	1579	}
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	/**
bogdanm	0:9b334a45a8ff	1582	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1583	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1584	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1585	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1586	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1587	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1588	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1589	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1590	* @retval HAL status
bogdanm	0:9b334a45a8ff	1591	*/
bogdanm	0:9b334a45a8ff	1592	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1593	{
bogdanm	0:9b334a45a8ff	1594	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1595	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	switch (Channel)
bogdanm	0:9b334a45a8ff	1598	{
bogdanm	0:9b334a45a8ff	1599	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1602	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604	break;
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1609	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1610	}
bogdanm	0:9b334a45a8ff	1611	break;
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1614	{
bogdanm	0:9b334a45a8ff	1615	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1616	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1617	}
bogdanm	0:9b334a45a8ff	1618	break;
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1621	{
bogdanm	0:9b334a45a8ff	1622	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1623	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1624	}
bogdanm	0:9b334a45a8ff	1625	break;
bogdanm	0:9b334a45a8ff	1626
bogdanm	0:9b334a45a8ff	1627	default:
bogdanm	0:9b334a45a8ff	1628	break;
bogdanm	0:9b334a45a8ff	1629	}
bogdanm	0:9b334a45a8ff	1630	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1631	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1634	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	/* Return function status */
bogdanm	0:9b334a45a8ff	1637	return HAL_OK;
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/**
bogdanm	0:9b334a45a8ff	1641	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1642	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1643	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1644	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1645	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1646	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1647	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1648	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1649	* @retval HAL status
bogdanm	0:9b334a45a8ff	1650	*/
bogdanm	0:9b334a45a8ff	1651	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1654	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	switch (Channel)
bogdanm	0:9b334a45a8ff	1657	{
bogdanm	0:9b334a45a8ff	1658	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1659	{
bogdanm	0:9b334a45a8ff	1660	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1661	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1662	}
bogdanm	0:9b334a45a8ff	1663	break;
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1666	{
bogdanm	0:9b334a45a8ff	1667	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1668	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1669	}
bogdanm	0:9b334a45a8ff	1670	break;
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1673	{
bogdanm	0:9b334a45a8ff	1674	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1675	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1676	}
bogdanm	0:9b334a45a8ff	1677	break;
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1680	{
bogdanm	0:9b334a45a8ff	1681	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1682	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1683	}
bogdanm	0:9b334a45a8ff	1684	break;
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	default:
bogdanm	0:9b334a45a8ff	1687	break;
bogdanm	0:9b334a45a8ff	1688	}
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1691	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1694	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* Return function status */
bogdanm	0:9b334a45a8ff	1697	return HAL_OK;
bogdanm	0:9b334a45a8ff	1698	}
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/**
bogdanm	0:9b334a45a8ff	1701	* @brief Starts the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1702	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1703	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1704	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1705	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1706	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1707	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1708	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1709	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1710	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1711	* @retval HAL status
bogdanm	0:9b334a45a8ff	1712	*/
bogdanm	0:9b334a45a8ff	1713	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1714	{
bogdanm	0:9b334a45a8ff	1715	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1716	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1717	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1722	}
bogdanm	0:9b334a45a8ff	1723	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1724	{
bogdanm	0:9b334a45a8ff	1725	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1726	{
bogdanm	0:9b334a45a8ff	1727	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1728	}
bogdanm	0:9b334a45a8ff	1729	else
bogdanm	0:9b334a45a8ff	1730	{
bogdanm	0:9b334a45a8ff	1731	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1732	}
bogdanm	0:9b334a45a8ff	1733	}
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	switch (Channel)
bogdanm	0:9b334a45a8ff	1736	{
bogdanm	0:9b334a45a8ff	1737	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1738	{
bogdanm	0:9b334a45a8ff	1739	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1740	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1743	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1746	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1749	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1750	}
bogdanm	0:9b334a45a8ff	1751	break;
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1756	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1757
bogdanm	0:9b334a45a8ff	1758	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1759	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1762	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1765	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1766	}
bogdanm	0:9b334a45a8ff	1767	break;
bogdanm	0:9b334a45a8ff	1768
bogdanm	0:9b334a45a8ff	1769	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1772	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1775	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1776
bogdanm	0:9b334a45a8ff	1777	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1778	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1779
bogdanm	0:9b334a45a8ff	1780	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1781	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1782	}
bogdanm	0:9b334a45a8ff	1783	break;
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1786	{
bogdanm	0:9b334a45a8ff	1787	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1788	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1789
bogdanm	0:9b334a45a8ff	1790	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1791	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1792
bogdanm	0:9b334a45a8ff	1793	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1794	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1797	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1798	}
bogdanm	0:9b334a45a8ff	1799	break;
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	default:
bogdanm	0:9b334a45a8ff	1802	break;
bogdanm	0:9b334a45a8ff	1803	}
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1806	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1809	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1810
bogdanm	0:9b334a45a8ff	1811	/* Return function status */
bogdanm	0:9b334a45a8ff	1812	return HAL_OK;
bogdanm	0:9b334a45a8ff	1813	}
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/**
bogdanm	0:9b334a45a8ff	1816	* @brief Stops the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1817	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1818	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1819	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1820	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1821	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1822	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1823	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1824	* @retval HAL status
bogdanm	0:9b334a45a8ff	1825	*/
bogdanm	0:9b334a45a8ff	1826	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1827	{
bogdanm	0:9b334a45a8ff	1828	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1829	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1830	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	switch (Channel)
bogdanm	0:9b334a45a8ff	1833	{
bogdanm	0:9b334a45a8ff	1834	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1835	{
bogdanm	0:9b334a45a8ff	1836	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1837	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1838	}
bogdanm	0:9b334a45a8ff	1839	break;
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1844	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1845	}
bogdanm	0:9b334a45a8ff	1846	break;
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1849	{
bogdanm	0:9b334a45a8ff	1850	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1851	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1852	}
bogdanm	0:9b334a45a8ff	1853	break;
bogdanm	0:9b334a45a8ff	1854
bogdanm	0:9b334a45a8ff	1855	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1856	{
bogdanm	0:9b334a45a8ff	1857	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1858	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1859	}
bogdanm	0:9b334a45a8ff	1860	break;
bogdanm	0:9b334a45a8ff	1861
bogdanm	0:9b334a45a8ff	1862	default:
bogdanm	0:9b334a45a8ff	1863	break;
bogdanm	0:9b334a45a8ff	1864	}
bogdanm	0:9b334a45a8ff	1865
bogdanm	0:9b334a45a8ff	1866	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1867	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1870	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1871
bogdanm	0:9b334a45a8ff	1872	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1873	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	/* Return function status */
bogdanm	0:9b334a45a8ff	1876	return HAL_OK;
bogdanm	0:9b334a45a8ff	1877	}
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	/**
bogdanm	0:9b334a45a8ff	1880	* @}
bogdanm	0:9b334a45a8ff	1881	*/
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	0:9b334a45a8ff	1884	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1885	*
bogdanm	0:9b334a45a8ff	1886	@verbatim
bogdanm	0:9b334a45a8ff	1887	==============================================================================
bogdanm	0:9b334a45a8ff	1888	##### Timer One Pulse functions #####
bogdanm	0:9b334a45a8ff	1889	==============================================================================
bogdanm	0:9b334a45a8ff	1890	[..]
bogdanm	0:9b334a45a8ff	1891	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1892	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1893	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1894	(+) Start the Timer One Pulse.
bogdanm	0:9b334a45a8ff	1895	(+) Stop the Timer One Pulse.
bogdanm	0:9b334a45a8ff	1896	(+) Start the Timer One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1897	(+) Stop the Timer One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1898	(+) Start the Timer One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1899	(+) Stop the Timer One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	@endverbatim
bogdanm	0:9b334a45a8ff	1902	* @{
bogdanm	0:9b334a45a8ff	1903	*/
bogdanm	0:9b334a45a8ff	1904	/**
bogdanm	0:9b334a45a8ff	1905	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1906	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1907	* @param htim: TIM OnePulse handle
bogdanm	0:9b334a45a8ff	1908	* @param OnePulseMode: Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1909	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1910	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1911	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
bogdanm	0:9b334a45a8ff	1912	* @retval HAL status
bogdanm	0:9b334a45a8ff	1913	*/
bogdanm	0:9b334a45a8ff	1914	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	1915	{
bogdanm	0:9b334a45a8ff	1916	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1917	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1918	{
bogdanm	0:9b334a45a8ff	1919	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1920	}
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1923	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1924	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1925	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1926	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	1927	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	1928	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1931	{
mbed_official	113:b3775bf36a83	1932	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	1933	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	1934
bogdanm	0:9b334a45a8ff	1935	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1936	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	1937	}
bogdanm	0:9b334a45a8ff	1938
bogdanm	0:9b334a45a8ff	1939	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1940	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	1943	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	1946	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	1949	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1952	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	return HAL_OK;
bogdanm	0:9b334a45a8ff	1955	}
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	/**
bogdanm	0:9b334a45a8ff	1958	* @brief DeInitializes the TIM One Pulse
bogdanm	0:9b334a45a8ff	1959	* @param htim: TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1960	* @retval HAL status
bogdanm	0:9b334a45a8ff	1961	*/
bogdanm	0:9b334a45a8ff	1962	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1965	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1970	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1971
bogdanm	0:9b334a45a8ff	1972	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	1973	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1976	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Release Lock */
bogdanm	0:9b334a45a8ff	1979	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	return HAL_OK;
bogdanm	0:9b334a45a8ff	1982	}
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/**
bogdanm	0:9b334a45a8ff	1985	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	1986	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1987	* @retval None
bogdanm	0:9b334a45a8ff	1988	*/
bogdanm	0:9b334a45a8ff	1989	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1990	{
mbed_official	113:b3775bf36a83	1991	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1992	UNUSED(htim);
mbed_official	113:b3775bf36a83	1993
bogdanm	0:9b334a45a8ff	1994	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1995	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1996	*/
bogdanm	0:9b334a45a8ff	1997	}
bogdanm	0:9b334a45a8ff	1998
bogdanm	0:9b334a45a8ff	1999	/**
bogdanm	0:9b334a45a8ff	2000	* @brief DeInitializes TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2001	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2002	* @retval None
bogdanm	0:9b334a45a8ff	2003	*/
bogdanm	0:9b334a45a8ff	2004	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2005	{
mbed_official	113:b3775bf36a83	2006	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2007	UNUSED(htim);
mbed_official	113:b3775bf36a83	2008
bogdanm	0:9b334a45a8ff	2009	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2010	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2011	*/
bogdanm	0:9b334a45a8ff	2012	}
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	/**
bogdanm	0:9b334a45a8ff	2015	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2016	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2017	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2018	* This parameter is not used since both channels TIM_CHANNEL_1 and
bogdanm	0:9b334a45a8ff	2019	* TIM_CHANNEL_2 are automatically selected.
bogdanm	0:9b334a45a8ff	2020	* @retval HAL status
bogdanm	0:9b334a45a8ff	2021	*/
bogdanm	0:9b334a45a8ff	2022	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2023	{
bogdanm	0:9b334a45a8ff	2024	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2025	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2026	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2027	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2028	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2031	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2034	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2035
bogdanm	0:9b334a45a8ff	2036	/* Return function status */
bogdanm	0:9b334a45a8ff	2037	return HAL_OK;
bogdanm	0:9b334a45a8ff	2038	}
bogdanm	0:9b334a45a8ff	2039
bogdanm	0:9b334a45a8ff	2040	/**
bogdanm	0:9b334a45a8ff	2041	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2042	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2043	* @param OutputChannel : TIM Channels to be disable.
bogdanm	0:9b334a45a8ff	2044	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2047	* @retval HAL status
bogdanm	0:9b334a45a8ff	2048	*/
bogdanm	0:9b334a45a8ff	2049	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2050	{
bogdanm	0:9b334a45a8ff	2051	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2052	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2053	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2054	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2055	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2058	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2059
bogdanm	0:9b334a45a8ff	2060	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2061	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2062
bogdanm	0:9b334a45a8ff	2063	/* Return function status */
bogdanm	0:9b334a45a8ff	2064	return HAL_OK;
bogdanm	0:9b334a45a8ff	2065	}
bogdanm	0:9b334a45a8ff	2066
bogdanm	0:9b334a45a8ff	2067	/**
bogdanm	0:9b334a45a8ff	2068	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2069	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2070	* @param OutputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2071	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2072	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2073	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2074	* @retval HAL status
bogdanm	0:9b334a45a8ff	2075	*/
bogdanm	0:9b334a45a8ff	2076	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2077	{
bogdanm	0:9b334a45a8ff	2078	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2079	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2080	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2081	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2082	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2085	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2086
bogdanm	0:9b334a45a8ff	2087	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2088	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2091	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2092
bogdanm	0:9b334a45a8ff	2093	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2094	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2095
bogdanm	0:9b334a45a8ff	2096	/* Return function status */
bogdanm	0:9b334a45a8ff	2097	return HAL_OK;
bogdanm	0:9b334a45a8ff	2098	}
bogdanm	0:9b334a45a8ff	2099
bogdanm	0:9b334a45a8ff	2100	/**
bogdanm	0:9b334a45a8ff	2101	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2102	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2103	* @param OutputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2104	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2105	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2106	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2107	* @retval HAL status
bogdanm	0:9b334a45a8ff	2108	*/
bogdanm	0:9b334a45a8ff	2109	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2110	{
bogdanm	0:9b334a45a8ff	2111	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2112	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2115	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2116
bogdanm	0:9b334a45a8ff	2117	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2118	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2119	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2120	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2121	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2122	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2123	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2124
bogdanm	0:9b334a45a8ff	2125	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2126	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2127
bogdanm	0:9b334a45a8ff	2128	/* Return function status */
bogdanm	0:9b334a45a8ff	2129	return HAL_OK;
bogdanm	0:9b334a45a8ff	2130	}
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	/**
bogdanm	0:9b334a45a8ff	2133	* @}
bogdanm	0:9b334a45a8ff	2134	*/
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	0:9b334a45a8ff	2137	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2138	*
bogdanm	0:9b334a45a8ff	2139	@verbatim
bogdanm	0:9b334a45a8ff	2140	==============================================================================
bogdanm	0:9b334a45a8ff	2141	##### Timer Encoder functions #####
bogdanm	0:9b334a45a8ff	2142	==============================================================================
bogdanm	0:9b334a45a8ff	2143	[..]
bogdanm	0:9b334a45a8ff	2144	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2145	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2146	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2147	(+) Start the Timer Encoder.
bogdanm	0:9b334a45a8ff	2148	(+) Stop the Timer Encoder.
bogdanm	0:9b334a45a8ff	2149	(+) Start the Timer Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2150	(+) Stop the Timer Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2151	(+) Start the Timer Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2152	(+) Stop the Timer Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	@endverbatim
bogdanm	0:9b334a45a8ff	2155	* @{
bogdanm	0:9b334a45a8ff	2156	*/
bogdanm	0:9b334a45a8ff	2157	/**
bogdanm	0:9b334a45a8ff	2158	* @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	2159	* @param htim: TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2160	* @param sConfig: TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2161	* @retval HAL status
bogdanm	0:9b334a45a8ff	2162	*/
bogdanm	0:9b334a45a8ff	2163	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2164	{
bogdanm	0:9b334a45a8ff	2165	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2166	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2167	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2170	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2171	{
bogdanm	0:9b334a45a8ff	2172	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2173	}
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2176	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2177	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2178	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2179	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2180	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2181	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2182	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2183	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2184	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2185	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2186	assert_param(IS_TIM_PERIOD(htim->Init.Period));
bogdanm	0:9b334a45a8ff	2187	assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
bogdanm	0:9b334a45a8ff	2188
bogdanm	0:9b334a45a8ff	2189	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2190	{
mbed_official	113:b3775bf36a83	2191	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	2192	htim->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	2193
bogdanm	0:9b334a45a8ff	2194	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2195	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2196	}
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2199	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2202	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2205	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2206
bogdanm	0:9b334a45a8ff	2207	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2208	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2209
bogdanm	0:9b334a45a8ff	2210	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2211	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2212
bogdanm	0:9b334a45a8ff	2213	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2214	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2215
bogdanm	0:9b334a45a8ff	2216	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2217	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2218
bogdanm	0:9b334a45a8ff	2219	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2220	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2221	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2222
bogdanm	0:9b334a45a8ff	2223	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2224	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2225	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2226	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2227	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2228
bogdanm	0:9b334a45a8ff	2229	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2230	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2231	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2232	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2233
bogdanm	0:9b334a45a8ff	2234	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2235	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2236
bogdanm	0:9b334a45a8ff	2237	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2238	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2239
bogdanm	0:9b334a45a8ff	2240	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2241	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2242
bogdanm	0:9b334a45a8ff	2243	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2244	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	return HAL_OK;
bogdanm	0:9b334a45a8ff	2247	}
bogdanm	0:9b334a45a8ff	2248
bogdanm	0:9b334a45a8ff	2249	/**
bogdanm	0:9b334a45a8ff	2250	* @brief DeInitializes the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2251	* @param htim: TIM Encoder handle
bogdanm	0:9b334a45a8ff	2252	* @retval HAL status
bogdanm	0:9b334a45a8ff	2253	*/
bogdanm	0:9b334a45a8ff	2254	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2255	{
bogdanm	0:9b334a45a8ff	2256	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2257	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2258
bogdanm	0:9b334a45a8ff	2259	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2262	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2263
bogdanm	0:9b334a45a8ff	2264	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2265	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2266
bogdanm	0:9b334a45a8ff	2267	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2268	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	/* Release Lock */
bogdanm	0:9b334a45a8ff	2271	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	return HAL_OK;
bogdanm	0:9b334a45a8ff	2274	}
bogdanm	0:9b334a45a8ff	2275
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277	/**
bogdanm	0:9b334a45a8ff	2278	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2279	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2280	* @retval None
bogdanm	0:9b334a45a8ff	2281	*/
bogdanm	0:9b334a45a8ff	2282	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2283	{
mbed_official	113:b3775bf36a83	2284	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2285	UNUSED(htim);
mbed_official	113:b3775bf36a83	2286
bogdanm	0:9b334a45a8ff	2287	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2288	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2289	*/
bogdanm	0:9b334a45a8ff	2290	}
bogdanm	0:9b334a45a8ff	2291
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/**
bogdanm	0:9b334a45a8ff	2294	* @brief DeInitializes TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2295	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2296	* @retval None
bogdanm	0:9b334a45a8ff	2297	*/
bogdanm	0:9b334a45a8ff	2298	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2299	{
mbed_official	113:b3775bf36a83	2300	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2301	UNUSED(htim);
mbed_official	113:b3775bf36a83	2302
bogdanm	0:9b334a45a8ff	2303	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2304	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2305	*/
bogdanm	0:9b334a45a8ff	2306	}
bogdanm	0:9b334a45a8ff	2307
bogdanm	0:9b334a45a8ff	2308	/**
bogdanm	0:9b334a45a8ff	2309	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2310	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2311	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2312	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2313	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2314	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2315	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2316	* @retval HAL status
bogdanm	0:9b334a45a8ff	2317	*/
bogdanm	0:9b334a45a8ff	2318	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2319	{
bogdanm	0:9b334a45a8ff	2320	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2321	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2322
bogdanm	0:9b334a45a8ff	2323	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2324	switch (Channel)
bogdanm	0:9b334a45a8ff	2325	{
bogdanm	0:9b334a45a8ff	2326	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2327	{
bogdanm	0:9b334a45a8ff	2328	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2329	break;
bogdanm	0:9b334a45a8ff	2330	}
bogdanm	0:9b334a45a8ff	2331	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2332	{
bogdanm	0:9b334a45a8ff	2333	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2334	break;
bogdanm	0:9b334a45a8ff	2335	}
bogdanm	0:9b334a45a8ff	2336	default :
bogdanm	0:9b334a45a8ff	2337	{
bogdanm	0:9b334a45a8ff	2338	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2339	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2340	break;
bogdanm	0:9b334a45a8ff	2341	}
bogdanm	0:9b334a45a8ff	2342	}
bogdanm	0:9b334a45a8ff	2343	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2344	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2345
bogdanm	0:9b334a45a8ff	2346	/* Return function status */
bogdanm	0:9b334a45a8ff	2347	return HAL_OK;
bogdanm	0:9b334a45a8ff	2348	}
bogdanm	0:9b334a45a8ff	2349
bogdanm	0:9b334a45a8ff	2350	/**
bogdanm	0:9b334a45a8ff	2351	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2352	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2353	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2354	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2355	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2356	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2357	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2358	* @retval HAL status
bogdanm	0:9b334a45a8ff	2359	*/
bogdanm	0:9b334a45a8ff	2360	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2361	{
bogdanm	0:9b334a45a8ff	2362	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2363	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2366	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2367	switch (Channel)
bogdanm	0:9b334a45a8ff	2368	{
bogdanm	0:9b334a45a8ff	2369	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2370	{
bogdanm	0:9b334a45a8ff	2371	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2372	break;
bogdanm	0:9b334a45a8ff	2373	}
bogdanm	0:9b334a45a8ff	2374	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2375	{
bogdanm	0:9b334a45a8ff	2376	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2377	break;
bogdanm	0:9b334a45a8ff	2378	}
bogdanm	0:9b334a45a8ff	2379	default :
bogdanm	0:9b334a45a8ff	2380	{
bogdanm	0:9b334a45a8ff	2381	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2382	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2383	break;
bogdanm	0:9b334a45a8ff	2384	}
bogdanm	0:9b334a45a8ff	2385	}
bogdanm	0:9b334a45a8ff	2386	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2387	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	/* Return function status */
bogdanm	0:9b334a45a8ff	2390	return HAL_OK;
bogdanm	0:9b334a45a8ff	2391	}
bogdanm	0:9b334a45a8ff	2392
bogdanm	0:9b334a45a8ff	2393	/**
bogdanm	0:9b334a45a8ff	2394	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2395	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2396	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2397	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2398	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2399	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2400	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2401	* @retval HAL status
bogdanm	0:9b334a45a8ff	2402	*/
bogdanm	0:9b334a45a8ff	2403	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2404	{
bogdanm	0:9b334a45a8ff	2405	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2406	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2407
bogdanm	0:9b334a45a8ff	2408	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2409	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2410	switch (Channel)
bogdanm	0:9b334a45a8ff	2411	{
bogdanm	0:9b334a45a8ff	2412	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2413	{
bogdanm	0:9b334a45a8ff	2414	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2415	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2416	break;
bogdanm	0:9b334a45a8ff	2417	}
bogdanm	0:9b334a45a8ff	2418	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2419	{
bogdanm	0:9b334a45a8ff	2420	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2421	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2422	break;
bogdanm	0:9b334a45a8ff	2423	}
bogdanm	0:9b334a45a8ff	2424	default :
bogdanm	0:9b334a45a8ff	2425	{
bogdanm	0:9b334a45a8ff	2426	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2428	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2429	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2430	break;
bogdanm	0:9b334a45a8ff	2431	}
bogdanm	0:9b334a45a8ff	2432	}
bogdanm	0:9b334a45a8ff	2433
bogdanm	0:9b334a45a8ff	2434	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2435	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2436
bogdanm	0:9b334a45a8ff	2437	/* Return function status */
bogdanm	0:9b334a45a8ff	2438	return HAL_OK;
bogdanm	0:9b334a45a8ff	2439	}
bogdanm	0:9b334a45a8ff	2440
bogdanm	0:9b334a45a8ff	2441	/**
bogdanm	0:9b334a45a8ff	2442	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2443	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2444	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2445	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2446	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2447	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2448	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2449	* @retval HAL status
bogdanm	0:9b334a45a8ff	2450	*/
bogdanm	0:9b334a45a8ff	2451	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2452	{
bogdanm	0:9b334a45a8ff	2453	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2454	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2455
bogdanm	0:9b334a45a8ff	2456	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2457	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2458	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2459	{
bogdanm	0:9b334a45a8ff	2460	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2463	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2464	}
bogdanm	0:9b334a45a8ff	2465	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2466	{
bogdanm	0:9b334a45a8ff	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2468
bogdanm	0:9b334a45a8ff	2469	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2470	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2471	}
bogdanm	0:9b334a45a8ff	2472	else
bogdanm	0:9b334a45a8ff	2473	{
bogdanm	0:9b334a45a8ff	2474	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2475	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2476
bogdanm	0:9b334a45a8ff	2477	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2478	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2479	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2480	}
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2483	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2486	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2487
bogdanm	0:9b334a45a8ff	2488	/* Return function status */
bogdanm	0:9b334a45a8ff	2489	return HAL_OK;
bogdanm	0:9b334a45a8ff	2490	}
bogdanm	0:9b334a45a8ff	2491
bogdanm	0:9b334a45a8ff	2492	/**
bogdanm	0:9b334a45a8ff	2493	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2494	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2495	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2496	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2497	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2498	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2499	* @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
bogdanm	0:9b334a45a8ff	2500	* @param pData1: The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2501	* @param pData2: The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2502	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2503	* @retval HAL status
bogdanm	0:9b334a45a8ff	2504	*/
bogdanm	0:9b334a45a8ff	2505	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2506	{
bogdanm	0:9b334a45a8ff	2507	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2508	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2509
bogdanm	0:9b334a45a8ff	2510	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2511	{
bogdanm	0:9b334a45a8ff	2512	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2513	}
bogdanm	0:9b334a45a8ff	2514	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2515	{
bogdanm	0:9b334a45a8ff	2516	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2517	{
bogdanm	0:9b334a45a8ff	2518	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2519	}
bogdanm	0:9b334a45a8ff	2520	else
bogdanm	0:9b334a45a8ff	2521	{
bogdanm	0:9b334a45a8ff	2522	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2523	}
bogdanm	0:9b334a45a8ff	2524	}
bogdanm	0:9b334a45a8ff	2525
bogdanm	0:9b334a45a8ff	2526	switch (Channel)
bogdanm	0:9b334a45a8ff	2527	{
bogdanm	0:9b334a45a8ff	2528	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2529	{
bogdanm	0:9b334a45a8ff	2530	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2531	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2532
bogdanm	0:9b334a45a8ff	2533	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2534	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2535
bogdanm	0:9b334a45a8ff	2536	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2537	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2540	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2541
bogdanm	0:9b334a45a8ff	2542	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2543	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2546	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2547	}
bogdanm	0:9b334a45a8ff	2548	break;
bogdanm	0:9b334a45a8ff	2549
bogdanm	0:9b334a45a8ff	2550	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2551	{
bogdanm	0:9b334a45a8ff	2552	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2553	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2556	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
bogdanm	0:9b334a45a8ff	2557	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2558	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2559
bogdanm	0:9b334a45a8ff	2560	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2561	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2562
bogdanm	0:9b334a45a8ff	2563	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2564	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2565
bogdanm	0:9b334a45a8ff	2566	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2567	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2568	}
bogdanm	0:9b334a45a8ff	2569	break;
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2572	{
bogdanm	0:9b334a45a8ff	2573	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2574	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2577	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2578
bogdanm	0:9b334a45a8ff	2579	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2580	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2581
bogdanm	0:9b334a45a8ff	2582	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2583	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2584
bogdanm	0:9b334a45a8ff	2585	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2586	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2589	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2590
bogdanm	0:9b334a45a8ff	2591	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2592	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2595	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2596	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2597
bogdanm	0:9b334a45a8ff	2598	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2599	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2600	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2601	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2602	}
bogdanm	0:9b334a45a8ff	2603	break;
bogdanm	0:9b334a45a8ff	2604
bogdanm	0:9b334a45a8ff	2605	default:
bogdanm	0:9b334a45a8ff	2606	break;
bogdanm	0:9b334a45a8ff	2607	}
bogdanm	0:9b334a45a8ff	2608	/* Return function status */
bogdanm	0:9b334a45a8ff	2609	return HAL_OK;
bogdanm	0:9b334a45a8ff	2610	}
bogdanm	0:9b334a45a8ff	2611
bogdanm	0:9b334a45a8ff	2612	/**
bogdanm	0:9b334a45a8ff	2613	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2614	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2615	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2616	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2617	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2618	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2619	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2620	* @retval HAL status
bogdanm	0:9b334a45a8ff	2621	*/
bogdanm	0:9b334a45a8ff	2622	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2623	{
bogdanm	0:9b334a45a8ff	2624	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2625	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2626
bogdanm	0:9b334a45a8ff	2627	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2628	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2629	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2630	{
bogdanm	0:9b334a45a8ff	2631	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2632
bogdanm	0:9b334a45a8ff	2633	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2634	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2635	}
bogdanm	0:9b334a45a8ff	2636	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2637	{
bogdanm	0:9b334a45a8ff	2638	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2639
bogdanm	0:9b334a45a8ff	2640	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2641	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2642	}
bogdanm	0:9b334a45a8ff	2643	else
bogdanm	0:9b334a45a8ff	2644	{
bogdanm	0:9b334a45a8ff	2645	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2646	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2647
bogdanm	0:9b334a45a8ff	2648	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2649	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2650	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2651	}
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2654	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2655
bogdanm	0:9b334a45a8ff	2656	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2657	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	/* Return function status */
bogdanm	0:9b334a45a8ff	2660	return HAL_OK;
bogdanm	0:9b334a45a8ff	2661	}
bogdanm	0:9b334a45a8ff	2662
bogdanm	0:9b334a45a8ff	2663	/**
bogdanm	0:9b334a45a8ff	2664	* @}
bogdanm	0:9b334a45a8ff	2665	*/
bogdanm	0:9b334a45a8ff	2666
bogdanm	0:9b334a45a8ff	2667	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	0:9b334a45a8ff	2668	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2669	*
bogdanm	0:9b334a45a8ff	2670	@verbatim
bogdanm	0:9b334a45a8ff	2671	==============================================================================
bogdanm	0:9b334a45a8ff	2672	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2673	==============================================================================
bogdanm	0:9b334a45a8ff	2674	[..]
bogdanm	0:9b334a45a8ff	2675	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2676
bogdanm	0:9b334a45a8ff	2677	@endverbatim
bogdanm	0:9b334a45a8ff	2678	* @{
bogdanm	0:9b334a45a8ff	2679	*/
bogdanm	0:9b334a45a8ff	2680	/**
bogdanm	0:9b334a45a8ff	2681	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2682	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2683	* @retval None
bogdanm	0:9b334a45a8ff	2684	*/
bogdanm	0:9b334a45a8ff	2685	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2686	{
bogdanm	0:9b334a45a8ff	2687	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2688	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2689	{
bogdanm	0:9b334a45a8ff	2690	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2691	{
bogdanm	0:9b334a45a8ff	2692	{
bogdanm	0:9b334a45a8ff	2693	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2694	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2695
bogdanm	0:9b334a45a8ff	2696	/* Input capture event */
bogdanm	0:9b334a45a8ff	2697	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2698	{
bogdanm	0:9b334a45a8ff	2699	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2700	}
bogdanm	0:9b334a45a8ff	2701	/* Output compare event */
bogdanm	0:9b334a45a8ff	2702	else
bogdanm	0:9b334a45a8ff	2703	{
bogdanm	0:9b334a45a8ff	2704	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2705	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2706	}
bogdanm	0:9b334a45a8ff	2707	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2708	}
bogdanm	0:9b334a45a8ff	2709	}
bogdanm	0:9b334a45a8ff	2710	}
bogdanm	0:9b334a45a8ff	2711	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2712	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2713	{
bogdanm	0:9b334a45a8ff	2714	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2715	{
bogdanm	0:9b334a45a8ff	2716	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2717	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2718	/* Input capture event */
bogdanm	0:9b334a45a8ff	2719	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2720	{
bogdanm	0:9b334a45a8ff	2721	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2722	}
bogdanm	0:9b334a45a8ff	2723	/* Output compare event */
bogdanm	0:9b334a45a8ff	2724	else
bogdanm	0:9b334a45a8ff	2725	{
bogdanm	0:9b334a45a8ff	2726	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2727	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2728	}
bogdanm	0:9b334a45a8ff	2729	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2730	}
bogdanm	0:9b334a45a8ff	2731	}
bogdanm	0:9b334a45a8ff	2732	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2733	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2734	{
bogdanm	0:9b334a45a8ff	2735	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2736	{
bogdanm	0:9b334a45a8ff	2737	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2738	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2739	/* Input capture event */
bogdanm	0:9b334a45a8ff	2740	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2741	{
bogdanm	0:9b334a45a8ff	2742	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2743	}
bogdanm	0:9b334a45a8ff	2744	/* Output compare event */
bogdanm	0:9b334a45a8ff	2745	else
bogdanm	0:9b334a45a8ff	2746	{
bogdanm	0:9b334a45a8ff	2747	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2748	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2749	}
bogdanm	0:9b334a45a8ff	2750	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2751	}
bogdanm	0:9b334a45a8ff	2752	}
bogdanm	0:9b334a45a8ff	2753	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2754	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2755	{
bogdanm	0:9b334a45a8ff	2756	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2757	{
bogdanm	0:9b334a45a8ff	2758	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2759	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2760	/* Input capture event */
bogdanm	0:9b334a45a8ff	2761	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2762	{
bogdanm	0:9b334a45a8ff	2763	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2764	}
bogdanm	0:9b334a45a8ff	2765	/* Output compare event */
bogdanm	0:9b334a45a8ff	2766	else
bogdanm	0:9b334a45a8ff	2767	{
bogdanm	0:9b334a45a8ff	2768	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2769	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2770	}
bogdanm	0:9b334a45a8ff	2771	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2772	}
bogdanm	0:9b334a45a8ff	2773	}
bogdanm	0:9b334a45a8ff	2774	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2775	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2776	{
bogdanm	0:9b334a45a8ff	2777	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2778	{
bogdanm	0:9b334a45a8ff	2779	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2780	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2781	}
bogdanm	0:9b334a45a8ff	2782	}
bogdanm	0:9b334a45a8ff	2783	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2784	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2785	{
bogdanm	0:9b334a45a8ff	2786	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2787	{
bogdanm	0:9b334a45a8ff	2788	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2789	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2790	}
bogdanm	0:9b334a45a8ff	2791	}
bogdanm	0:9b334a45a8ff	2792	}
bogdanm	0:9b334a45a8ff	2793
bogdanm	0:9b334a45a8ff	2794	/**
bogdanm	0:9b334a45a8ff	2795	* @}
bogdanm	0:9b334a45a8ff	2796	*/
bogdanm	0:9b334a45a8ff	2797
bogdanm	0:9b334a45a8ff	2798	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	0:9b334a45a8ff	2799	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2800	*
bogdanm	0:9b334a45a8ff	2801	@verbatim
bogdanm	0:9b334a45a8ff	2802	==============================================================================
bogdanm	0:9b334a45a8ff	2803	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2804	==============================================================================
bogdanm	0:9b334a45a8ff	2805	[..]
bogdanm	0:9b334a45a8ff	2806	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2807	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2808	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2809	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2810	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2811
bogdanm	0:9b334a45a8ff	2812	@endverbatim
bogdanm	0:9b334a45a8ff	2813	* @{
bogdanm	0:9b334a45a8ff	2814	*/
bogdanm	0:9b334a45a8ff	2815	/**
bogdanm	0:9b334a45a8ff	2816	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2817	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2818	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2819	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2820	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2821	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2822	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2823	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2824	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2825	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2826	* @retval HAL status
bogdanm	0:9b334a45a8ff	2827	*/
bogdanm	0:9b334a45a8ff	2828	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2829	{
bogdanm	0:9b334a45a8ff	2830	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2831	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2832	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2833	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2834
bogdanm	0:9b334a45a8ff	2835	/* Check input state */
bogdanm	0:9b334a45a8ff	2836	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2837
bogdanm	0:9b334a45a8ff	2838	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2839
bogdanm	0:9b334a45a8ff	2840	switch (Channel)
bogdanm	0:9b334a45a8ff	2841	{
bogdanm	0:9b334a45a8ff	2842	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2843	{
bogdanm	0:9b334a45a8ff	2844	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2845	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2846	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2847	}
bogdanm	0:9b334a45a8ff	2848	break;
bogdanm	0:9b334a45a8ff	2849
bogdanm	0:9b334a45a8ff	2850	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2851	{
bogdanm	0:9b334a45a8ff	2852	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2853	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	2854	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2855	}
bogdanm	0:9b334a45a8ff	2856	break;
bogdanm	0:9b334a45a8ff	2857
bogdanm	0:9b334a45a8ff	2858	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2859	{
bogdanm	0:9b334a45a8ff	2860	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2861	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	2862	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2863	}
bogdanm	0:9b334a45a8ff	2864	break;
bogdanm	0:9b334a45a8ff	2865
bogdanm	0:9b334a45a8ff	2866	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2867	{
bogdanm	0:9b334a45a8ff	2868	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2869	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	2870	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2871	}
bogdanm	0:9b334a45a8ff	2872	break;
bogdanm	0:9b334a45a8ff	2873
bogdanm	0:9b334a45a8ff	2874	default:
bogdanm	0:9b334a45a8ff	2875	break;
bogdanm	0:9b334a45a8ff	2876	}
bogdanm	0:9b334a45a8ff	2877	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2878
bogdanm	0:9b334a45a8ff	2879	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2880
bogdanm	0:9b334a45a8ff	2881	return HAL_OK;
bogdanm	0:9b334a45a8ff	2882	}
bogdanm	0:9b334a45a8ff	2883
bogdanm	0:9b334a45a8ff	2884	/**
bogdanm	0:9b334a45a8ff	2885	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	2886	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2887	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2888	* @param sConfig: TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	2889	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2890	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2891	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2892	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2893	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2894	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2895	* @retval HAL status
bogdanm	0:9b334a45a8ff	2896	*/
bogdanm	0:9b334a45a8ff	2897	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2898	{
bogdanm	0:9b334a45a8ff	2899	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2900	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2901	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	2902	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	2903	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	2904	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	2905
bogdanm	0:9b334a45a8ff	2906	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2907
bogdanm	0:9b334a45a8ff	2908	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2909
bogdanm	0:9b334a45a8ff	2910	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2911	{
bogdanm	0:9b334a45a8ff	2912	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	2913	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2914	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2915	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2916	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2917
bogdanm	0:9b334a45a8ff	2918	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	2919	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	2920
bogdanm	0:9b334a45a8ff	2921	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	2922	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	2923	}
bogdanm	0:9b334a45a8ff	2924	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2925	{
bogdanm	0:9b334a45a8ff	2926	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	2927	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2928
bogdanm	0:9b334a45a8ff	2929	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2930	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2931	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2932	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2933
bogdanm	0:9b334a45a8ff	2934	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	2935	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	2938	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	2939	}
bogdanm	0:9b334a45a8ff	2940	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	2941	{
bogdanm	0:9b334a45a8ff	2942	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	2943	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2946	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2947	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2948	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2949
bogdanm	0:9b334a45a8ff	2950	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	2951	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	2952
bogdanm	0:9b334a45a8ff	2953	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	2954	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	2955	}
bogdanm	0:9b334a45a8ff	2956	else
bogdanm	0:9b334a45a8ff	2957	{
bogdanm	0:9b334a45a8ff	2958	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	2959	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2960
bogdanm	0:9b334a45a8ff	2961	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2962	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2963	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2964	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2965
bogdanm	0:9b334a45a8ff	2966	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	2967	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	2968
bogdanm	0:9b334a45a8ff	2969	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	2970	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	2971	}
bogdanm	0:9b334a45a8ff	2972
bogdanm	0:9b334a45a8ff	2973	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2974
bogdanm	0:9b334a45a8ff	2975	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	return HAL_OK;
bogdanm	0:9b334a45a8ff	2978	}
bogdanm	0:9b334a45a8ff	2979
bogdanm	0:9b334a45a8ff	2980	/**
bogdanm	0:9b334a45a8ff	2981	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	2982	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2983	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2984	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	2985	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2986	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2987	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2988	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2989	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2990	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2991	* @retval HAL status
bogdanm	0:9b334a45a8ff	2992	*/
bogdanm	0:9b334a45a8ff	2993	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2994	{
bogdanm	0:9b334a45a8ff	2995	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2996
bogdanm	0:9b334a45a8ff	2997	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2998	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2999	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3000	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3001	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3002
bogdanm	0:9b334a45a8ff	3003	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3004
bogdanm	0:9b334a45a8ff	3005	switch (Channel)
bogdanm	0:9b334a45a8ff	3006	{
bogdanm	0:9b334a45a8ff	3007	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3008	{
bogdanm	0:9b334a45a8ff	3009	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3010	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3011	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3012
bogdanm	0:9b334a45a8ff	3013	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3014	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3015
bogdanm	0:9b334a45a8ff	3016	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3017	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3018	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3019	}
bogdanm	0:9b334a45a8ff	3020	break;
bogdanm	0:9b334a45a8ff	3021
bogdanm	0:9b334a45a8ff	3022	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3023	{
bogdanm	0:9b334a45a8ff	3024	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3025	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3026	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3027
bogdanm	0:9b334a45a8ff	3028	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3029	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3030
bogdanm	0:9b334a45a8ff	3031	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3032	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3033	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3034	}
bogdanm	0:9b334a45a8ff	3035	break;
bogdanm	0:9b334a45a8ff	3036
bogdanm	0:9b334a45a8ff	3037	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3038	{
bogdanm	0:9b334a45a8ff	3039	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3040	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3041	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3042
bogdanm	0:9b334a45a8ff	3043	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3044	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3045
bogdanm	0:9b334a45a8ff	3046	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3047	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3048	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3049	}
bogdanm	0:9b334a45a8ff	3050	break;
bogdanm	0:9b334a45a8ff	3051
bogdanm	0:9b334a45a8ff	3052	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3053	{
bogdanm	0:9b334a45a8ff	3054	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3055	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3056	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3057
bogdanm	0:9b334a45a8ff	3058	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3059	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3060
bogdanm	0:9b334a45a8ff	3061	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3062	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3063	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3064	}
bogdanm	0:9b334a45a8ff	3065	break;
bogdanm	0:9b334a45a8ff	3066
bogdanm	0:9b334a45a8ff	3067	default:
bogdanm	0:9b334a45a8ff	3068	break;
bogdanm	0:9b334a45a8ff	3069	}
bogdanm	0:9b334a45a8ff	3070
bogdanm	0:9b334a45a8ff	3071	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3072
bogdanm	0:9b334a45a8ff	3073	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3074
bogdanm	0:9b334a45a8ff	3075	return HAL_OK;
bogdanm	0:9b334a45a8ff	3076	}
bogdanm	0:9b334a45a8ff	3077
bogdanm	0:9b334a45a8ff	3078	/**
bogdanm	0:9b334a45a8ff	3079	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3080	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3081	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3082	* @param sConfig: TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3083	* @param OutputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3084	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3085	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3086	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3087	* @param InputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3088	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3089	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3090	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3091	* @retval HAL status
bogdanm	0:9b334a45a8ff	3092	*/
bogdanm	0:9b334a45a8ff	3093	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3094	{
bogdanm	0:9b334a45a8ff	3095	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3096
bogdanm	0:9b334a45a8ff	3097	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3098	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3099	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3100
bogdanm	0:9b334a45a8ff	3101	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3102	{
bogdanm	0:9b334a45a8ff	3103	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3104
bogdanm	0:9b334a45a8ff	3105	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3106
bogdanm	0:9b334a45a8ff	3107	/* Extract the Ouput compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3108	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3109	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3110	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3111
bogdanm	0:9b334a45a8ff	3112	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3113	{
bogdanm	0:9b334a45a8ff	3114	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3115	{
bogdanm	0:9b334a45a8ff	3116	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3117
bogdanm	0:9b334a45a8ff	3118	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3119	}
bogdanm	0:9b334a45a8ff	3120	break;
bogdanm	0:9b334a45a8ff	3121	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3122	{
bogdanm	0:9b334a45a8ff	3123	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3124
bogdanm	0:9b334a45a8ff	3125	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3126	}
bogdanm	0:9b334a45a8ff	3127	break;
bogdanm	0:9b334a45a8ff	3128	default:
bogdanm	0:9b334a45a8ff	3129	break;
bogdanm	0:9b334a45a8ff	3130	}
bogdanm	0:9b334a45a8ff	3131	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3132	{
bogdanm	0:9b334a45a8ff	3133	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3134	{
bogdanm	0:9b334a45a8ff	3135	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3136
bogdanm	0:9b334a45a8ff	3137	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3138	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3139
bogdanm	0:9b334a45a8ff	3140	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3141	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3142
bogdanm	0:9b334a45a8ff	3143	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3144	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3145	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3146
bogdanm	0:9b334a45a8ff	3147	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3148	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3149	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3150	}
bogdanm	0:9b334a45a8ff	3151	break;
bogdanm	0:9b334a45a8ff	3152	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3153	{
bogdanm	0:9b334a45a8ff	3154	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3155
bogdanm	0:9b334a45a8ff	3156	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3157	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3158
bogdanm	0:9b334a45a8ff	3159	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3160	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3161
bogdanm	0:9b334a45a8ff	3162	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3163	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3164	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3165
bogdanm	0:9b334a45a8ff	3166	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3167	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3168	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3169	}
bogdanm	0:9b334a45a8ff	3170	break;
bogdanm	0:9b334a45a8ff	3171
bogdanm	0:9b334a45a8ff	3172	default:
bogdanm	0:9b334a45a8ff	3173	break;
bogdanm	0:9b334a45a8ff	3174	}
bogdanm	0:9b334a45a8ff	3175
bogdanm	0:9b334a45a8ff	3176	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3177
bogdanm	0:9b334a45a8ff	3178	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3179
bogdanm	0:9b334a45a8ff	3180	return HAL_OK;
bogdanm	0:9b334a45a8ff	3181	}
bogdanm	0:9b334a45a8ff	3182	else
bogdanm	0:9b334a45a8ff	3183	{
bogdanm	0:9b334a45a8ff	3184	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3185	}
bogdanm	0:9b334a45a8ff	3186	}
bogdanm	0:9b334a45a8ff	3187
bogdanm	0:9b334a45a8ff	3188	/**
bogdanm	0:9b334a45a8ff	3189	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3190	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3191	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
bogdanm	0:9b334a45a8ff	3192	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3193	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3194	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3195	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3196	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3197	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3198	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3199	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3200	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3201	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3202	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3203	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3204	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3205	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3206	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3207	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3208	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3209	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3210	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3211	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3212	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3213	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3214	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3215	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3216	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3217	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3218	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3219	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3220	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
bogdanm	0:9b334a45a8ff	3221	* @retval HAL status
bogdanm	0:9b334a45a8ff	3222	*/
bogdanm	0:9b334a45a8ff	3223	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3224	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3225	{
bogdanm	0:9b334a45a8ff	3226	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3227	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3228	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3229	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3230	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3231
bogdanm	0:9b334a45a8ff	3232	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3233	{
bogdanm	0:9b334a45a8ff	3234	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3235	}
bogdanm	0:9b334a45a8ff	3236	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3237	{
bogdanm	0:9b334a45a8ff	3238	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3239	{
bogdanm	0:9b334a45a8ff	3240	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3241	}
bogdanm	0:9b334a45a8ff	3242	else
bogdanm	0:9b334a45a8ff	3243	{
bogdanm	0:9b334a45a8ff	3244	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3245	}
bogdanm	0:9b334a45a8ff	3246	}
bogdanm	0:9b334a45a8ff	3247	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3248	{
bogdanm	0:9b334a45a8ff	3249	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3250	{
bogdanm	0:9b334a45a8ff	3251	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3252	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3253
bogdanm	0:9b334a45a8ff	3254	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3255	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3256
bogdanm	0:9b334a45a8ff	3257	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3258	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3259	}
bogdanm	0:9b334a45a8ff	3260	break;
bogdanm	0:9b334a45a8ff	3261	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3262	{
bogdanm	0:9b334a45a8ff	3263	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3264	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3265
bogdanm	0:9b334a45a8ff	3266	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3267	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3268
bogdanm	0:9b334a45a8ff	3269	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3270	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3271	}
bogdanm	0:9b334a45a8ff	3272	break;
bogdanm	0:9b334a45a8ff	3273	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3274	{
bogdanm	0:9b334a45a8ff	3275	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3276	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3277
bogdanm	0:9b334a45a8ff	3278	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3279	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3280
bogdanm	0:9b334a45a8ff	3281	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3282	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3283	}
bogdanm	0:9b334a45a8ff	3284	break;
bogdanm	0:9b334a45a8ff	3285	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3286	{
bogdanm	0:9b334a45a8ff	3287	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3288	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3289
bogdanm	0:9b334a45a8ff	3290	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3291	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3292
bogdanm	0:9b334a45a8ff	3293	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3294	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3295	}
bogdanm	0:9b334a45a8ff	3296	break;
bogdanm	0:9b334a45a8ff	3297	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3298	{
bogdanm	0:9b334a45a8ff	3299	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3300	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3301
bogdanm	0:9b334a45a8ff	3302	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3303	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3304
bogdanm	0:9b334a45a8ff	3305	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3306	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3307	}
bogdanm	0:9b334a45a8ff	3308	break;
bogdanm	0:9b334a45a8ff	3309	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3310	{
bogdanm	0:9b334a45a8ff	3311	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3312	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3313
bogdanm	0:9b334a45a8ff	3314	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3315	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3316
bogdanm	0:9b334a45a8ff	3317	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3318	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3319	}
bogdanm	0:9b334a45a8ff	3320	break;
bogdanm	0:9b334a45a8ff	3321	default:
bogdanm	0:9b334a45a8ff	3322	break;
bogdanm	0:9b334a45a8ff	3323	}
bogdanm	0:9b334a45a8ff	3324	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3325	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3326
bogdanm	0:9b334a45a8ff	3327	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3328	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3329
bogdanm	0:9b334a45a8ff	3330	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3331
bogdanm	0:9b334a45a8ff	3332	/* Return function status */
bogdanm	0:9b334a45a8ff	3333	return HAL_OK;
bogdanm	0:9b334a45a8ff	3334	}
bogdanm	0:9b334a45a8ff	3335
bogdanm	0:9b334a45a8ff	3336	/**
bogdanm	0:9b334a45a8ff	3337	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3338	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3339	* @param BurstRequestSrc: TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3340	* @retval HAL status
bogdanm	0:9b334a45a8ff	3341	*/
bogdanm	0:9b334a45a8ff	3342	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3343	{
bogdanm	0:9b334a45a8ff	3344	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3345	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3346
bogdanm	0:9b334a45a8ff	3347	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3348	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3349	{
bogdanm	0:9b334a45a8ff	3350	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3351	{
bogdanm	0:9b334a45a8ff	3352	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3353	}
bogdanm	0:9b334a45a8ff	3354	break;
bogdanm	0:9b334a45a8ff	3355	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3356	{
bogdanm	0:9b334a45a8ff	3357	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3358	}
bogdanm	0:9b334a45a8ff	3359	break;
bogdanm	0:9b334a45a8ff	3360	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3361	{
bogdanm	0:9b334a45a8ff	3362	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3363	}
bogdanm	0:9b334a45a8ff	3364	break;
bogdanm	0:9b334a45a8ff	3365	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3366	{
bogdanm	0:9b334a45a8ff	3367	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3368	}
bogdanm	0:9b334a45a8ff	3369	break;
bogdanm	0:9b334a45a8ff	3370	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3371	{
bogdanm	0:9b334a45a8ff	3372	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3373	}
bogdanm	0:9b334a45a8ff	3374	break;
bogdanm	0:9b334a45a8ff	3375	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3376	{
bogdanm	0:9b334a45a8ff	3377	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3378	}
bogdanm	0:9b334a45a8ff	3379	break;
bogdanm	0:9b334a45a8ff	3380	default:
bogdanm	0:9b334a45a8ff	3381	break;
bogdanm	0:9b334a45a8ff	3382	}
bogdanm	0:9b334a45a8ff	3383	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3384	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3385
bogdanm	0:9b334a45a8ff	3386	/* Return function status */
bogdanm	0:9b334a45a8ff	3387	return HAL_OK;
bogdanm	0:9b334a45a8ff	3388	}
bogdanm	0:9b334a45a8ff	3389
bogdanm	0:9b334a45a8ff	3390	/**
bogdanm	0:9b334a45a8ff	3391	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3392	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3393	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
bogdanm	0:9b334a45a8ff	3394	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3395	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3396	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3397	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3398	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3399	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3400	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3401	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3402	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3403	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3404	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3405	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3406	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3407	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3408	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3409	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3410	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3411	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3412	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3413	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3414	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3415	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3416	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3417	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3418	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3419	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3420	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3421	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3422	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
bogdanm	0:9b334a45a8ff	3423	* @retval HAL status
bogdanm	0:9b334a45a8ff	3424	*/
bogdanm	0:9b334a45a8ff	3425	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3426	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3427	{
bogdanm	0:9b334a45a8ff	3428	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3429	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3430	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3431	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3432	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3433
bogdanm	0:9b334a45a8ff	3434	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3435	{
bogdanm	0:9b334a45a8ff	3436	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3437	}
bogdanm	0:9b334a45a8ff	3438	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3439	{
bogdanm	0:9b334a45a8ff	3440	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3441	{
bogdanm	0:9b334a45a8ff	3442	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3443	}
bogdanm	0:9b334a45a8ff	3444	else
bogdanm	0:9b334a45a8ff	3445	{
bogdanm	0:9b334a45a8ff	3446	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3447	}
bogdanm	0:9b334a45a8ff	3448	}
bogdanm	0:9b334a45a8ff	3449	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3450	{
bogdanm	0:9b334a45a8ff	3451	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3452	{
bogdanm	0:9b334a45a8ff	3453	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3454	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3455
bogdanm	0:9b334a45a8ff	3456	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3457	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3458
bogdanm	0:9b334a45a8ff	3459	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3460	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3461	}
bogdanm	0:9b334a45a8ff	3462	break;
bogdanm	0:9b334a45a8ff	3463	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3464	{
bogdanm	0:9b334a45a8ff	3465	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3466	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3467
bogdanm	0:9b334a45a8ff	3468	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3469	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3470
bogdanm	0:9b334a45a8ff	3471	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3472	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3473	}
bogdanm	0:9b334a45a8ff	3474	break;
bogdanm	0:9b334a45a8ff	3475	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3476	{
bogdanm	0:9b334a45a8ff	3477	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3478	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3479
bogdanm	0:9b334a45a8ff	3480	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3481	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3482
bogdanm	0:9b334a45a8ff	3483	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3484	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3485	}
bogdanm	0:9b334a45a8ff	3486	break;
bogdanm	0:9b334a45a8ff	3487	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3488	{
bogdanm	0:9b334a45a8ff	3489	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3490	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3491
bogdanm	0:9b334a45a8ff	3492	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3493	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3494
bogdanm	0:9b334a45a8ff	3495	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3496	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3497	}
bogdanm	0:9b334a45a8ff	3498	break;
bogdanm	0:9b334a45a8ff	3499	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3500	{
bogdanm	0:9b334a45a8ff	3501	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3502	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3503
bogdanm	0:9b334a45a8ff	3504	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3505	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3506
bogdanm	0:9b334a45a8ff	3507	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3508	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3509	}
bogdanm	0:9b334a45a8ff	3510	break;
bogdanm	0:9b334a45a8ff	3511	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3512	{
bogdanm	0:9b334a45a8ff	3513	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3514	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3515
bogdanm	0:9b334a45a8ff	3516	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3517	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3518
bogdanm	0:9b334a45a8ff	3519	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3520	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3521	}
bogdanm	0:9b334a45a8ff	3522	break;
bogdanm	0:9b334a45a8ff	3523	default:
bogdanm	0:9b334a45a8ff	3524	break;
bogdanm	0:9b334a45a8ff	3525	}
bogdanm	0:9b334a45a8ff	3526
bogdanm	0:9b334a45a8ff	3527	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3528	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3529
bogdanm	0:9b334a45a8ff	3530	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3531	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3532
bogdanm	0:9b334a45a8ff	3533	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3534
bogdanm	0:9b334a45a8ff	3535	/* Return function status */
bogdanm	0:9b334a45a8ff	3536	return HAL_OK;
bogdanm	0:9b334a45a8ff	3537	}
bogdanm	0:9b334a45a8ff	3538
bogdanm	0:9b334a45a8ff	3539	/**
bogdanm	0:9b334a45a8ff	3540	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3541	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3542	* @param BurstRequestSrc: TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3543	* @retval HAL status
bogdanm	0:9b334a45a8ff	3544	*/
bogdanm	0:9b334a45a8ff	3545	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3546	{
bogdanm	0:9b334a45a8ff	3547	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3548	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3549
bogdanm	0:9b334a45a8ff	3550	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3551	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3552	{
bogdanm	0:9b334a45a8ff	3553	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3554	{
bogdanm	0:9b334a45a8ff	3555	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3556	}
bogdanm	0:9b334a45a8ff	3557	break;
bogdanm	0:9b334a45a8ff	3558	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3559	{
bogdanm	0:9b334a45a8ff	3560	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3561	}
bogdanm	0:9b334a45a8ff	3562	break;
bogdanm	0:9b334a45a8ff	3563	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3564	{
bogdanm	0:9b334a45a8ff	3565	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3566	}
bogdanm	0:9b334a45a8ff	3567	break;
bogdanm	0:9b334a45a8ff	3568	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3569	{
bogdanm	0:9b334a45a8ff	3570	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3571	}
bogdanm	0:9b334a45a8ff	3572	break;
bogdanm	0:9b334a45a8ff	3573	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3574	{
bogdanm	0:9b334a45a8ff	3575	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3576	}
bogdanm	0:9b334a45a8ff	3577	break;
bogdanm	0:9b334a45a8ff	3578	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3579	{
bogdanm	0:9b334a45a8ff	3580	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3581	}
bogdanm	0:9b334a45a8ff	3582	break;
bogdanm	0:9b334a45a8ff	3583	default:
bogdanm	0:9b334a45a8ff	3584	break;
bogdanm	0:9b334a45a8ff	3585	}
bogdanm	0:9b334a45a8ff	3586
bogdanm	0:9b334a45a8ff	3587	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3588	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3589
bogdanm	0:9b334a45a8ff	3590	/* Return function status */
bogdanm	0:9b334a45a8ff	3591	return HAL_OK;
bogdanm	0:9b334a45a8ff	3592	}
bogdanm	0:9b334a45a8ff	3593
bogdanm	0:9b334a45a8ff	3594	/**
bogdanm	0:9b334a45a8ff	3595	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3596	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3597	* @param EventSource: specifies the event source.
bogdanm	0:9b334a45a8ff	3598	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3599	* @arg TIM_EventSource_Update: Timer update Event source
bogdanm	0:9b334a45a8ff	3600	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3601	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3602	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3603	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3604	* @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3605	* @note TIM6 can only generate an update event.
bogdanm	0:9b334a45a8ff	3606	* @retval HAL status
bogdanm	0:9b334a45a8ff	3607	*/
bogdanm	0:9b334a45a8ff	3608
bogdanm	0:9b334a45a8ff	3609	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3610	{
bogdanm	0:9b334a45a8ff	3611	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3612	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3613	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3614
bogdanm	0:9b334a45a8ff	3615	/* Process Locked */
bogdanm	0:9b334a45a8ff	3616	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3617
bogdanm	0:9b334a45a8ff	3618	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3619	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3620
bogdanm	0:9b334a45a8ff	3621	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3622	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3623
bogdanm	0:9b334a45a8ff	3624	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3625	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3626
bogdanm	0:9b334a45a8ff	3627	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3628
bogdanm	0:9b334a45a8ff	3629	/* Return function status */
bogdanm	0:9b334a45a8ff	3630	return HAL_OK;
bogdanm	0:9b334a45a8ff	3631	}
bogdanm	0:9b334a45a8ff	3632
bogdanm	0:9b334a45a8ff	3633	/**
bogdanm	0:9b334a45a8ff	3634	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3635	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3636	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3637	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3638	* @param Channel: specifies the TIM Channel.
bogdanm	0:9b334a45a8ff	3639	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3640	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3641	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3642	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3643	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3644	* @retval HAL status
bogdanm	0:9b334a45a8ff	3645	*/
bogdanm	0:9b334a45a8ff	3646	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3647	{
bogdanm	0:9b334a45a8ff	3648	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3649	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3650	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3651	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3652	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3653	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3654	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3655
bogdanm	0:9b334a45a8ff	3656	/* Process Locked */
bogdanm	0:9b334a45a8ff	3657	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3658
bogdanm	0:9b334a45a8ff	3659	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3660
bogdanm	0:9b334a45a8ff	3661	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
bogdanm	0:9b334a45a8ff	3662	{
bogdanm	0:9b334a45a8ff	3663	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3664	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3665	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3666	sClearInputConfig->ClearInputFilter);
mbed_official	113:b3775bf36a83	3667
mbed_official	113:b3775bf36a83	3668	/* Set the OCREF clear selection bit */
mbed_official	113:b3775bf36a83	3669	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	3670	}
bogdanm	0:9b334a45a8ff	3671
bogdanm	0:9b334a45a8ff	3672	switch (Channel)
bogdanm	0:9b334a45a8ff	3673	{
bogdanm	0:9b334a45a8ff	3674	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3675	{
bogdanm	0:9b334a45a8ff	3676	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3677	{
bogdanm	0:9b334a45a8ff	3678	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3679	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3680	}
bogdanm	0:9b334a45a8ff	3681	else
bogdanm	0:9b334a45a8ff	3682	{
bogdanm	0:9b334a45a8ff	3683	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3684	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3685	}
bogdanm	0:9b334a45a8ff	3686	}
bogdanm	0:9b334a45a8ff	3687	break;
bogdanm	0:9b334a45a8ff	3688	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3689	{
bogdanm	0:9b334a45a8ff	3690	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3691	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3692	{
bogdanm	0:9b334a45a8ff	3693	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3694	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3695	}
bogdanm	0:9b334a45a8ff	3696	else
bogdanm	0:9b334a45a8ff	3697	{
bogdanm	0:9b334a45a8ff	3698	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3699	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3700	}
bogdanm	0:9b334a45a8ff	3701	}
bogdanm	0:9b334a45a8ff	3702	break;
bogdanm	0:9b334a45a8ff	3703	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3704	{
bogdanm	0:9b334a45a8ff	3705	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3706	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3707	{
bogdanm	0:9b334a45a8ff	3708	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3709	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3710	}
bogdanm	0:9b334a45a8ff	3711	else
bogdanm	0:9b334a45a8ff	3712	{
bogdanm	0:9b334a45a8ff	3713	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3714	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3715	}
bogdanm	0:9b334a45a8ff	3716	}
bogdanm	0:9b334a45a8ff	3717	break;
bogdanm	0:9b334a45a8ff	3718	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3719	{
bogdanm	0:9b334a45a8ff	3720	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3721	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3722	{
bogdanm	0:9b334a45a8ff	3723	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3724	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3725	}
bogdanm	0:9b334a45a8ff	3726	else
bogdanm	0:9b334a45a8ff	3727	{
bogdanm	0:9b334a45a8ff	3728	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3729	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3730	}
bogdanm	0:9b334a45a8ff	3731	}
bogdanm	0:9b334a45a8ff	3732	break;
bogdanm	0:9b334a45a8ff	3733	default:
bogdanm	0:9b334a45a8ff	3734	break;
bogdanm	0:9b334a45a8ff	3735	}
bogdanm	0:9b334a45a8ff	3736
bogdanm	0:9b334a45a8ff	3737	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3738
bogdanm	0:9b334a45a8ff	3739	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3740
bogdanm	0:9b334a45a8ff	3741	return HAL_OK;
bogdanm	0:9b334a45a8ff	3742	}
bogdanm	0:9b334a45a8ff	3743
bogdanm	0:9b334a45a8ff	3744	/**
bogdanm	0:9b334a45a8ff	3745	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3746	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3747	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3748	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3749	* @retval HAL status
bogdanm	0:9b334a45a8ff	3750	*/
bogdanm	0:9b334a45a8ff	3751	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3752	{
bogdanm	0:9b334a45a8ff	3753	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3754
bogdanm	0:9b334a45a8ff	3755	/* Process Locked */
bogdanm	0:9b334a45a8ff	3756	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3757
bogdanm	0:9b334a45a8ff	3758	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3759
mbed_official	113:b3775bf36a83	3760	/* Check the clock source */
bogdanm	0:9b334a45a8ff	3761	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3762
bogdanm	0:9b334a45a8ff	3763	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3764	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3765	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3766	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3767	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3768
bogdanm	0:9b334a45a8ff	3769	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3770	{
bogdanm	0:9b334a45a8ff	3771	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3772	{
bogdanm	0:9b334a45a8ff	3773	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3774	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3775	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3776	}
bogdanm	0:9b334a45a8ff	3777	break;
bogdanm	0:9b334a45a8ff	3778
bogdanm	0:9b334a45a8ff	3779	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3780	{
bogdanm	0:9b334a45a8ff	3781	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	113:b3775bf36a83	3782	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	113:b3775bf36a83	3783	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	113:b3775bf36a83	3784	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3785	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3786	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3787	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3788	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3789	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3790	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	3791	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3792	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	3793	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3794	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	3795	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	3796	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	3797	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3798	}
bogdanm	0:9b334a45a8ff	3799	break;
bogdanm	0:9b334a45a8ff	3800
bogdanm	0:9b334a45a8ff	3801	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	3802	{
bogdanm	0:9b334a45a8ff	3803	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	113:b3775bf36a83	3804	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	113:b3775bf36a83	3805	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	113:b3775bf36a83	3806	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3807	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3808	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3809	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3810	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3811	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3812	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	3813	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	3814	}
bogdanm	0:9b334a45a8ff	3815	break;
bogdanm	0:9b334a45a8ff	3816
bogdanm	0:9b334a45a8ff	3817	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	3818	{
bogdanm	0:9b334a45a8ff	3819	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	113:b3775bf36a83	3820	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	113:b3775bf36a83	3821	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3822	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3823	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3824	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3825	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	3826	}
bogdanm	0:9b334a45a8ff	3827	break;
bogdanm	0:9b334a45a8ff	3828	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	3829	{
bogdanm	0:9b334a45a8ff	3830	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	113:b3775bf36a83	3831	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	113:b3775bf36a83	3832	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3833	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3834	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3835	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3836	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	3837	}
bogdanm	0:9b334a45a8ff	3838	break;
bogdanm	0:9b334a45a8ff	3839	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	3840	{
bogdanm	0:9b334a45a8ff	3841	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	113:b3775bf36a83	3842	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	113:b3775bf36a83	3843	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3844	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3845	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3846	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3847	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	3848	}
bogdanm	0:9b334a45a8ff	3849	break;
bogdanm	0:9b334a45a8ff	3850	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	3851	{
bogdanm	0:9b334a45a8ff	3852	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3853	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	3854	}
bogdanm	0:9b334a45a8ff	3855	break;
bogdanm	0:9b334a45a8ff	3856	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	3857	{
bogdanm	0:9b334a45a8ff	3858	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3859	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	3860	}
bogdanm	0:9b334a45a8ff	3861	break;
bogdanm	0:9b334a45a8ff	3862	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	3863	{
bogdanm	0:9b334a45a8ff	3864	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3865	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	3866	}
bogdanm	0:9b334a45a8ff	3867	break;
bogdanm	0:9b334a45a8ff	3868	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	3869	{
bogdanm	0:9b334a45a8ff	3870	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3871	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	3872	}
bogdanm	0:9b334a45a8ff	3873	break;
bogdanm	0:9b334a45a8ff	3874
bogdanm	0:9b334a45a8ff	3875	default:
bogdanm	0:9b334a45a8ff	3876	break;
bogdanm	0:9b334a45a8ff	3877	}
bogdanm	0:9b334a45a8ff	3878	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3879
bogdanm	0:9b334a45a8ff	3880	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3881
bogdanm	0:9b334a45a8ff	3882	return HAL_OK;
bogdanm	0:9b334a45a8ff	3883	}
bogdanm	0:9b334a45a8ff	3884
bogdanm	0:9b334a45a8ff	3885	/**
bogdanm	0:9b334a45a8ff	3886	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	3887	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	3888	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3889	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	3890	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	3891	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3892	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	3893	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	3894	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	3895	* @retval HAL status
bogdanm	0:9b334a45a8ff	3896	*/
bogdanm	0:9b334a45a8ff	3897	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	3898	{
bogdanm	0:9b334a45a8ff	3899	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	3900
bogdanm	0:9b334a45a8ff	3901	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3902	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3903	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	3904
bogdanm	0:9b334a45a8ff	3905	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	3906	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	3907
bogdanm	0:9b334a45a8ff	3908	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	3909	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	3910
bogdanm	0:9b334a45a8ff	3911	/* Set the the TI1 selection */
bogdanm	0:9b334a45a8ff	3912	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	3913
bogdanm	0:9b334a45a8ff	3914	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	3915	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	3916
bogdanm	0:9b334a45a8ff	3917	return HAL_OK;
bogdanm	0:9b334a45a8ff	3918	}
bogdanm	0:9b334a45a8ff	3919
bogdanm	0:9b334a45a8ff	3920	/**
bogdanm	0:9b334a45a8ff	3921	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	3922	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3923	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3924	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	3925	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	3926	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	3927	* @retval HAL status
bogdanm	0:9b334a45a8ff	3928	*/
bogdanm	0:9b334a45a8ff	3929	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	3930	{
bogdanm	0:9b334a45a8ff	3931	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3932	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3933	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	3934	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	3935
bogdanm	0:9b334a45a8ff	3936	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3937
bogdanm	0:9b334a45a8ff	3938	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3939
bogdanm	0:9b334a45a8ff	3940	/* Configuration in slave mode */
bogdanm	0:9b334a45a8ff	3941	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	3942
bogdanm	0:9b334a45a8ff	3943	/* Disable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	3944	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	3945
bogdanm	0:9b334a45a8ff	3946	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	3947	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	3948
bogdanm	0:9b334a45a8ff	3949	/* Set the new state */
bogdanm	0:9b334a45a8ff	3950	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3951
bogdanm	0:9b334a45a8ff	3952	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3953
bogdanm	0:9b334a45a8ff	3954	return HAL_OK;
bogdanm	0:9b334a45a8ff	3955	}
bogdanm	0:9b334a45a8ff	3956
bogdanm	0:9b334a45a8ff	3957	/**
bogdanm	0:9b334a45a8ff	3958	* @brief Configures the TIM in Slave mode in interrupt mode
bogdanm	0:9b334a45a8ff	3959	* @param htim : TIM handle.
bogdanm	0:9b334a45a8ff	3960	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3961	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	3962	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	3963	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	3964	* @retval HAL status
bogdanm	0:9b334a45a8ff	3965	*/
bogdanm	0:9b334a45a8ff	3966	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	3967	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	3968	{
bogdanm	0:9b334a45a8ff	3969	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3970	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3971	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	3972	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	3973
bogdanm	0:9b334a45a8ff	3974	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3975
bogdanm	0:9b334a45a8ff	3976	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3977
bogdanm	0:9b334a45a8ff	3978	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	3979
bogdanm	0:9b334a45a8ff	3980	/* Enable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	3981	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	3982
bogdanm	0:9b334a45a8ff	3983	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	3984	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	3985
bogdanm	0:9b334a45a8ff	3986	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3987
bogdanm	0:9b334a45a8ff	3988	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3989
bogdanm	0:9b334a45a8ff	3990	return HAL_OK;
bogdanm	0:9b334a45a8ff	3991	}
bogdanm	0:9b334a45a8ff	3992
bogdanm	0:9b334a45a8ff	3993	/**
bogdanm	0:9b334a45a8ff	3994	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	3995	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	3996	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3997	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3998	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3999	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4000	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4001	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4002	* @retval Captured value
bogdanm	0:9b334a45a8ff	4003	*/
bogdanm	0:9b334a45a8ff	4004	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4005	{
bogdanm	0:9b334a45a8ff	4006	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4007
bogdanm	0:9b334a45a8ff	4008	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4009
bogdanm	0:9b334a45a8ff	4010	switch (Channel)
bogdanm	0:9b334a45a8ff	4011	{
bogdanm	0:9b334a45a8ff	4012	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4013	{
bogdanm	0:9b334a45a8ff	4014	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4015	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4016
bogdanm	0:9b334a45a8ff	4017	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4018	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4019
bogdanm	0:9b334a45a8ff	4020	break;
bogdanm	0:9b334a45a8ff	4021	}
bogdanm	0:9b334a45a8ff	4022	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4023	{
bogdanm	0:9b334a45a8ff	4024	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4025	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4026
bogdanm	0:9b334a45a8ff	4027	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4028	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4029
bogdanm	0:9b334a45a8ff	4030	break;
bogdanm	0:9b334a45a8ff	4031	}
bogdanm	0:9b334a45a8ff	4032
bogdanm	0:9b334a45a8ff	4033	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4034	{
bogdanm	0:9b334a45a8ff	4035	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4036	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4037
bogdanm	0:9b334a45a8ff	4038	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4039	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4040
bogdanm	0:9b334a45a8ff	4041	break;
bogdanm	0:9b334a45a8ff	4042	}
bogdanm	0:9b334a45a8ff	4043
bogdanm	0:9b334a45a8ff	4044	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4045	{
bogdanm	0:9b334a45a8ff	4046	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4047	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4048
bogdanm	0:9b334a45a8ff	4049	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4050	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4051
bogdanm	0:9b334a45a8ff	4052	break;
bogdanm	0:9b334a45a8ff	4053	}
bogdanm	0:9b334a45a8ff	4054
bogdanm	0:9b334a45a8ff	4055	default:
bogdanm	0:9b334a45a8ff	4056	break;
bogdanm	0:9b334a45a8ff	4057	}
bogdanm	0:9b334a45a8ff	4058
bogdanm	0:9b334a45a8ff	4059	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4060	return tmpreg;
bogdanm	0:9b334a45a8ff	4061	}
bogdanm	0:9b334a45a8ff	4062
bogdanm	0:9b334a45a8ff	4063	/**
bogdanm	0:9b334a45a8ff	4064	* @}
bogdanm	0:9b334a45a8ff	4065	*/
bogdanm	0:9b334a45a8ff	4066
bogdanm	0:9b334a45a8ff	4067	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	0:9b334a45a8ff	4068	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4069	*
bogdanm	0:9b334a45a8ff	4070	@verbatim
bogdanm	0:9b334a45a8ff	4071	==============================================================================
bogdanm	0:9b334a45a8ff	4072	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4073	==============================================================================
bogdanm	0:9b334a45a8ff	4074	[..]
bogdanm	0:9b334a45a8ff	4075	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4076	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4077	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4078	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4079	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4080	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4081
bogdanm	0:9b334a45a8ff	4082	@endverbatim
bogdanm	0:9b334a45a8ff	4083	* @{
bogdanm	0:9b334a45a8ff	4084	*/
bogdanm	0:9b334a45a8ff	4085
bogdanm	0:9b334a45a8ff	4086	/**
bogdanm	0:9b334a45a8ff	4087	* @brief Period elapsed callback in non blocking mode
bogdanm	0:9b334a45a8ff	4088	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4089	* @retval None
bogdanm	0:9b334a45a8ff	4090	*/
bogdanm	0:9b334a45a8ff	4091	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4092	{
mbed_official	113:b3775bf36a83	4093	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4094	UNUSED(htim);
mbed_official	113:b3775bf36a83	4095
bogdanm	0:9b334a45a8ff	4096	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4097	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4098	*/
bogdanm	0:9b334a45a8ff	4099
bogdanm	0:9b334a45a8ff	4100	}
bogdanm	0:9b334a45a8ff	4101	/**
bogdanm	0:9b334a45a8ff	4102	* @brief Output Compare callback in non blocking mode
bogdanm	0:9b334a45a8ff	4103	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4104	* @retval None
bogdanm	0:9b334a45a8ff	4105	*/
bogdanm	0:9b334a45a8ff	4106	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4107	{
mbed_official	113:b3775bf36a83	4108	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4109	UNUSED(htim);
mbed_official	113:b3775bf36a83	4110
bogdanm	0:9b334a45a8ff	4111	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4112	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4113	*/
bogdanm	0:9b334a45a8ff	4114	}
bogdanm	0:9b334a45a8ff	4115	/**
bogdanm	0:9b334a45a8ff	4116	* @brief Input Capture callback in non blocking mode
bogdanm	0:9b334a45a8ff	4117	* @param htim: TIM IC handle
bogdanm	0:9b334a45a8ff	4118	* @retval None
bogdanm	0:9b334a45a8ff	4119	*/
bogdanm	0:9b334a45a8ff	4120	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4121	{
mbed_official	113:b3775bf36a83	4122	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4123	UNUSED(htim);
mbed_official	113:b3775bf36a83	4124
bogdanm	0:9b334a45a8ff	4125	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4126	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4127	*/
bogdanm	0:9b334a45a8ff	4128	}
bogdanm	0:9b334a45a8ff	4129
bogdanm	0:9b334a45a8ff	4130	/**
bogdanm	0:9b334a45a8ff	4131	* @brief PWM Pulse finished callback in non blocking mode
bogdanm	0:9b334a45a8ff	4132	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4133	* @retval None
bogdanm	0:9b334a45a8ff	4134	*/
bogdanm	0:9b334a45a8ff	4135	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4136	{
mbed_official	113:b3775bf36a83	4137	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4138	UNUSED(htim);
mbed_official	113:b3775bf36a83	4139
bogdanm	0:9b334a45a8ff	4140	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4141	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4142	*/
bogdanm	0:9b334a45a8ff	4143	}
bogdanm	0:9b334a45a8ff	4144
bogdanm	0:9b334a45a8ff	4145	/**
bogdanm	0:9b334a45a8ff	4146	* @brief Hall Trigger detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	4147	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4148	* @retval None
bogdanm	0:9b334a45a8ff	4149	*/
bogdanm	0:9b334a45a8ff	4150	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4151	{
mbed_official	113:b3775bf36a83	4152	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4153	UNUSED(htim);
mbed_official	113:b3775bf36a83	4154
bogdanm	0:9b334a45a8ff	4155	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4156	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4157	*/
bogdanm	0:9b334a45a8ff	4158	}
bogdanm	0:9b334a45a8ff	4159
bogdanm	0:9b334a45a8ff	4160	/**
bogdanm	0:9b334a45a8ff	4161	* @brief Timer error callback in non blocking mode
bogdanm	0:9b334a45a8ff	4162	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4163	* @retval None
bogdanm	0:9b334a45a8ff	4164	*/
bogdanm	0:9b334a45a8ff	4165	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4166	{
mbed_official	113:b3775bf36a83	4167	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	4168	UNUSED(htim);
mbed_official	113:b3775bf36a83	4169
bogdanm	0:9b334a45a8ff	4170	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4171	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4172	*/
bogdanm	0:9b334a45a8ff	4173	}
bogdanm	0:9b334a45a8ff	4174
bogdanm	0:9b334a45a8ff	4175	/**
bogdanm	0:9b334a45a8ff	4176	* @}
bogdanm	0:9b334a45a8ff	4177	*/
bogdanm	0:9b334a45a8ff	4178
bogdanm	0:9b334a45a8ff	4179	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	0:9b334a45a8ff	4180	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4181	*
bogdanm	0:9b334a45a8ff	4182	@verbatim
bogdanm	0:9b334a45a8ff	4183	==============================================================================
bogdanm	0:9b334a45a8ff	4184	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4185	==============================================================================
bogdanm	0:9b334a45a8ff	4186	[..]
bogdanm	0:9b334a45a8ff	4187	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4188	and the data flow.
bogdanm	0:9b334a45a8ff	4189
bogdanm	0:9b334a45a8ff	4190	@endverbatim
bogdanm	0:9b334a45a8ff	4191	* @{
bogdanm	0:9b334a45a8ff	4192	*/
bogdanm	0:9b334a45a8ff	4193
bogdanm	0:9b334a45a8ff	4194	/**
bogdanm	0:9b334a45a8ff	4195	* @brief Return the TIM Base state
bogdanm	0:9b334a45a8ff	4196	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4197	* @retval HAL state
bogdanm	0:9b334a45a8ff	4198	*/
bogdanm	0:9b334a45a8ff	4199	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4200	{
bogdanm	0:9b334a45a8ff	4201	return htim->State;
bogdanm	0:9b334a45a8ff	4202	}
bogdanm	0:9b334a45a8ff	4203
bogdanm	0:9b334a45a8ff	4204	/**
bogdanm	0:9b334a45a8ff	4205	* @brief Return the TIM OC state
bogdanm	0:9b334a45a8ff	4206	* @param htim: TIM Ouput Compare handle
bogdanm	0:9b334a45a8ff	4207	* @retval HAL state
bogdanm	0:9b334a45a8ff	4208	*/
bogdanm	0:9b334a45a8ff	4209	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4210	{
bogdanm	0:9b334a45a8ff	4211	return htim->State;
bogdanm	0:9b334a45a8ff	4212	}
bogdanm	0:9b334a45a8ff	4213
bogdanm	0:9b334a45a8ff	4214	/**
bogdanm	0:9b334a45a8ff	4215	* @brief Return the TIM PWM state
bogdanm	0:9b334a45a8ff	4216	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4217	* @retval HAL state
bogdanm	0:9b334a45a8ff	4218	*/
bogdanm	0:9b334a45a8ff	4219	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4220	{
bogdanm	0:9b334a45a8ff	4221	return htim->State;
bogdanm	0:9b334a45a8ff	4222	}
bogdanm	0:9b334a45a8ff	4223
bogdanm	0:9b334a45a8ff	4224	/**
bogdanm	0:9b334a45a8ff	4225	* @brief Return the TIM Input Capture state
bogdanm	0:9b334a45a8ff	4226	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4227	* @retval HAL state
bogdanm	0:9b334a45a8ff	4228	*/
bogdanm	0:9b334a45a8ff	4229	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4230	{
bogdanm	0:9b334a45a8ff	4231	return htim->State;
bogdanm	0:9b334a45a8ff	4232	}
bogdanm	0:9b334a45a8ff	4233
bogdanm	0:9b334a45a8ff	4234	/**
bogdanm	0:9b334a45a8ff	4235	* @brief Return the TIM One Pulse Mode state
bogdanm	0:9b334a45a8ff	4236	* @param htim: TIM OPM handle
bogdanm	0:9b334a45a8ff	4237	* @retval HAL state
bogdanm	0:9b334a45a8ff	4238	*/
bogdanm	0:9b334a45a8ff	4239	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4240	{
bogdanm	0:9b334a45a8ff	4241	return htim->State;
bogdanm	0:9b334a45a8ff	4242	}
bogdanm	0:9b334a45a8ff	4243
bogdanm	0:9b334a45a8ff	4244	/**
bogdanm	0:9b334a45a8ff	4245	* @brief Return the TIM Encoder Mode state
bogdanm	0:9b334a45a8ff	4246	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4247	* @retval HAL state
bogdanm	0:9b334a45a8ff	4248	*/
bogdanm	0:9b334a45a8ff	4249	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4250	{
bogdanm	0:9b334a45a8ff	4251	return htim->State;
bogdanm	0:9b334a45a8ff	4252	}
bogdanm	0:9b334a45a8ff	4253
bogdanm	0:9b334a45a8ff	4254
bogdanm	0:9b334a45a8ff	4255
bogdanm	0:9b334a45a8ff	4256	/**
bogdanm	0:9b334a45a8ff	4257	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4258	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4259	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4260	* @retval None
bogdanm	0:9b334a45a8ff	4261	*/
bogdanm	0:9b334a45a8ff	4262	void TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4263	{
bogdanm	0:9b334a45a8ff	4264	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4265
bogdanm	0:9b334a45a8ff	4266	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4267
bogdanm	0:9b334a45a8ff	4268	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4269	}
bogdanm	0:9b334a45a8ff	4270
bogdanm	0:9b334a45a8ff	4271	/**
bogdanm	0:9b334a45a8ff	4272	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4273	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4274	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4275	* @retval None
bogdanm	0:9b334a45a8ff	4276	*/
bogdanm	0:9b334a45a8ff	4277	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4278	{
bogdanm	0:9b334a45a8ff	4279	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4280
bogdanm	0:9b334a45a8ff	4281	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4282
bogdanm	0:9b334a45a8ff	4283	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4284	{
bogdanm	0:9b334a45a8ff	4285	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4286	}
bogdanm	0:9b334a45a8ff	4287	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4288	{
bogdanm	0:9b334a45a8ff	4289	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4290	}
bogdanm	0:9b334a45a8ff	4291	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4292	{
bogdanm	0:9b334a45a8ff	4293	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4294	}
bogdanm	0:9b334a45a8ff	4295	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4296	{
bogdanm	0:9b334a45a8ff	4297	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4298	}
bogdanm	0:9b334a45a8ff	4299	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4300
bogdanm	0:9b334a45a8ff	4301	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4302	}
bogdanm	0:9b334a45a8ff	4303	/**
bogdanm	0:9b334a45a8ff	4304	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4305	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4306	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4307	* @retval None
bogdanm	0:9b334a45a8ff	4308	*/
bogdanm	0:9b334a45a8ff	4309	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4310	{
bogdanm	0:9b334a45a8ff	4311	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4312
bogdanm	0:9b334a45a8ff	4313	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4314
bogdanm	0:9b334a45a8ff	4315	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4316	{
bogdanm	0:9b334a45a8ff	4317	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4318	}
bogdanm	0:9b334a45a8ff	4319	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4320	{
bogdanm	0:9b334a45a8ff	4321	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4322	}
bogdanm	0:9b334a45a8ff	4323	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4324	{
bogdanm	0:9b334a45a8ff	4325	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4326	}
bogdanm	0:9b334a45a8ff	4327	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4328	{
bogdanm	0:9b334a45a8ff	4329	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4330	}
bogdanm	0:9b334a45a8ff	4331
bogdanm	0:9b334a45a8ff	4332	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4333
bogdanm	0:9b334a45a8ff	4334	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4335	}
bogdanm	0:9b334a45a8ff	4336
bogdanm	0:9b334a45a8ff	4337
bogdanm	0:9b334a45a8ff	4338	/**
bogdanm	0:9b334a45a8ff	4339	* @}
bogdanm	0:9b334a45a8ff	4340	*/
bogdanm	0:9b334a45a8ff	4341
bogdanm	0:9b334a45a8ff	4342	/**
bogdanm	0:9b334a45a8ff	4343	* @}
bogdanm	0:9b334a45a8ff	4344	*/
bogdanm	0:9b334a45a8ff	4345	/*************************************************************/
bogdanm	0:9b334a45a8ff	4346	/* Private functions */
bogdanm	0:9b334a45a8ff	4347	/*************************************************************/
bogdanm	0:9b334a45a8ff	4348
mbed_official	113:b3775bf36a83	4349	/** @addtogroup TIM_Private TIM Private
bogdanm	0:9b334a45a8ff	4350	* @{
bogdanm	0:9b334a45a8ff	4351	*/
bogdanm	0:9b334a45a8ff	4352	/**
bogdanm	0:9b334a45a8ff	4353	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4354	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4355	* @retval None
bogdanm	0:9b334a45a8ff	4356	*/
bogdanm	0:9b334a45a8ff	4357	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4358	{
bogdanm	0:9b334a45a8ff	4359	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4360
bogdanm	0:9b334a45a8ff	4361	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4362
bogdanm	0:9b334a45a8ff	4363	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4364	}
bogdanm	0:9b334a45a8ff	4365
bogdanm	0:9b334a45a8ff	4366
bogdanm	0:9b334a45a8ff	4367	/**
bogdanm	0:9b334a45a8ff	4368	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4369	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4370	* @retval None
bogdanm	0:9b334a45a8ff	4371	*/
bogdanm	0:9b334a45a8ff	4372	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4373	{
bogdanm	0:9b334a45a8ff	4374	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4375
bogdanm	0:9b334a45a8ff	4376	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4377
bogdanm	0:9b334a45a8ff	4378	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4379	}
bogdanm	0:9b334a45a8ff	4380
bogdanm	0:9b334a45a8ff	4381	/**
bogdanm	0:9b334a45a8ff	4382	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4383	* @param TIMx : TIM peripheral
bogdanm	0:9b334a45a8ff	4384	* @param Structure : TIM Base configuration structure
bogdanm	0:9b334a45a8ff	4385	* @retval None
bogdanm	0:9b334a45a8ff	4386	*/
bogdanm	0:9b334a45a8ff	4387	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4388	{
bogdanm	0:9b334a45a8ff	4389	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4390	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4391
bogdanm	0:9b334a45a8ff	4392	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4393	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4394	{
bogdanm	0:9b334a45a8ff	4395	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4396	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4397	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4398	}
bogdanm	0:9b334a45a8ff	4399
bogdanm	0:9b334a45a8ff	4400	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4401	{
bogdanm	0:9b334a45a8ff	4402	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4403	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4404	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4405	}
bogdanm	0:9b334a45a8ff	4406
bogdanm	0:9b334a45a8ff	4407	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4408
bogdanm	0:9b334a45a8ff	4409	/* Set the Autoreload value */
bogdanm	0:9b334a45a8ff	4410	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4411
bogdanm	0:9b334a45a8ff	4412	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4413	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4414
bogdanm	0:9b334a45a8ff	4415	/* Generate an update event to reload the Prescaler value immediatly */
bogdanm	0:9b334a45a8ff	4416	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4417	}
bogdanm	0:9b334a45a8ff	4418
bogdanm	0:9b334a45a8ff	4419	/**
bogdanm	0:9b334a45a8ff	4420	* @brief Time Ouput Compare 1 configuration
bogdanm	0:9b334a45a8ff	4421	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4422	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4423	* @retval None
bogdanm	0:9b334a45a8ff	4424	*/
bogdanm	0:9b334a45a8ff	4425	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4426	{
bogdanm	0:9b334a45a8ff	4427	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4428	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4429	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4430
bogdanm	0:9b334a45a8ff	4431	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4432	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4433
bogdanm	0:9b334a45a8ff	4434	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4435	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4436	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4437	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4438
bogdanm	0:9b334a45a8ff	4439	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4440	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4441
bogdanm	0:9b334a45a8ff	4442	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4443	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4444	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4445	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4446	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4447
bogdanm	0:9b334a45a8ff	4448	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4449	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4450	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4451	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4452
bogdanm	0:9b334a45a8ff	4453	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4454	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4455
bogdanm	0:9b334a45a8ff	4456	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4457	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4458
bogdanm	0:9b334a45a8ff	4459	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4460	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4461
bogdanm	0:9b334a45a8ff	4462	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4463	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4464	}
bogdanm	0:9b334a45a8ff	4465
bogdanm	0:9b334a45a8ff	4466	/**
bogdanm	0:9b334a45a8ff	4467	* @brief Time Ouput Compare 2 configuration
bogdanm	0:9b334a45a8ff	4468	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4469	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4470	* @retval None
bogdanm	0:9b334a45a8ff	4471	*/
bogdanm	0:9b334a45a8ff	4472	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4473	{
bogdanm	0:9b334a45a8ff	4474	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4475	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4476	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4477
bogdanm	0:9b334a45a8ff	4478	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4479	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4480
bogdanm	0:9b334a45a8ff	4481	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4482	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4483	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4484	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4485
bogdanm	0:9b334a45a8ff	4486	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4487	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4488
bogdanm	0:9b334a45a8ff	4489	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4490	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4491	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4492
bogdanm	0:9b334a45a8ff	4493	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4494	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4495
bogdanm	0:9b334a45a8ff	4496	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4497	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4498	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4499	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4500
bogdanm	0:9b334a45a8ff	4501	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4502	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4503
bogdanm	0:9b334a45a8ff	4504	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4505	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4506
bogdanm	0:9b334a45a8ff	4507	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4508	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4509
bogdanm	0:9b334a45a8ff	4510	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4511	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4512	}
bogdanm	0:9b334a45a8ff	4513
bogdanm	0:9b334a45a8ff	4514	/**
bogdanm	0:9b334a45a8ff	4515	* @brief Time Ouput Compare 3 configuration
bogdanm	0:9b334a45a8ff	4516	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4517	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4518	* @retval None
bogdanm	0:9b334a45a8ff	4519	*/
bogdanm	0:9b334a45a8ff	4520	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4521	{
bogdanm	0:9b334a45a8ff	4522	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4523	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4524	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4525
bogdanm	0:9b334a45a8ff	4526	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4527	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4528
bogdanm	0:9b334a45a8ff	4529	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4530	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4531	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4532	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4533
bogdanm	0:9b334a45a8ff	4534	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4535	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4536
bogdanm	0:9b334a45a8ff	4537	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4538	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4539	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4540	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4541	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4542
bogdanm	0:9b334a45a8ff	4543	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4544	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4545	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4546	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4547
bogdanm	0:9b334a45a8ff	4548	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4549	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4550
bogdanm	0:9b334a45a8ff	4551	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4552	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4553
bogdanm	0:9b334a45a8ff	4554	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4555	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4556
bogdanm	0:9b334a45a8ff	4557	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4558	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4559	}
bogdanm	0:9b334a45a8ff	4560
bogdanm	0:9b334a45a8ff	4561	/**
bogdanm	0:9b334a45a8ff	4562	* @brief Time Ouput Compare 4 configuration
bogdanm	0:9b334a45a8ff	4563	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4564	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4565	* @retval None
bogdanm	0:9b334a45a8ff	4566	*/
bogdanm	0:9b334a45a8ff	4567	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4568	{
bogdanm	0:9b334a45a8ff	4569	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4570	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4571	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4572
bogdanm	0:9b334a45a8ff	4573	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4574	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4575
bogdanm	0:9b334a45a8ff	4576	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4577	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4578	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4579	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4580
bogdanm	0:9b334a45a8ff	4581	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4582	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4583
bogdanm	0:9b334a45a8ff	4584	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4585	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4586	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4587
bogdanm	0:9b334a45a8ff	4588	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4589	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4590
bogdanm	0:9b334a45a8ff	4591	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4592	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4593	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4594	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4595
bogdanm	0:9b334a45a8ff	4596	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4597	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4598
bogdanm	0:9b334a45a8ff	4599	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4600	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4601
bogdanm	0:9b334a45a8ff	4602	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4603	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4604
bogdanm	0:9b334a45a8ff	4605	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4606	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4607	}
bogdanm	0:9b334a45a8ff	4608
bogdanm	0:9b334a45a8ff	4609	/**
bogdanm	0:9b334a45a8ff	4610	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	4611	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4612	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4613	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4614	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4615	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4616	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4617	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4618	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4619	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	4620	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	4621	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4622	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4623	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4624	* @retval None
bogdanm	0:9b334a45a8ff	4625	*/
bogdanm	0:9b334a45a8ff	4626	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4627	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4628	{
bogdanm	0:9b334a45a8ff	4629	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4630	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4631
bogdanm	0:9b334a45a8ff	4632	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4633	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4634	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4635	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4636
bogdanm	0:9b334a45a8ff	4637	/* Select the Input */
bogdanm	0:9b334a45a8ff	4638	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4639	{
bogdanm	0:9b334a45a8ff	4640	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4641	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	4642	}
bogdanm	0:9b334a45a8ff	4643	else
bogdanm	0:9b334a45a8ff	4644	{
bogdanm	0:9b334a45a8ff	4645	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4646	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	4647	}
bogdanm	0:9b334a45a8ff	4648
bogdanm	0:9b334a45a8ff	4649	/* Set the filter */
bogdanm	0:9b334a45a8ff	4650	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4651	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	4652
bogdanm	0:9b334a45a8ff	4653	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	4654	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	4655	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	4656
bogdanm	0:9b334a45a8ff	4657	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4658	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4659	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4660	}
bogdanm	0:9b334a45a8ff	4661
bogdanm	0:9b334a45a8ff	4662	/**
bogdanm	0:9b334a45a8ff	4663	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	4664	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4665	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4666	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4667	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4668	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4669	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4670	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4671	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4672	* @retval None
bogdanm	0:9b334a45a8ff	4673	*/
bogdanm	0:9b334a45a8ff	4674	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4675	{
bogdanm	0:9b334a45a8ff	4676	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4677	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4678
bogdanm	0:9b334a45a8ff	4679	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4680	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4681	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4682	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4683
bogdanm	0:9b334a45a8ff	4684	/* Set the filter */
bogdanm	0:9b334a45a8ff	4685	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4686	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	4687
bogdanm	0:9b334a45a8ff	4688	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	4689	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	4690	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	4691
bogdanm	0:9b334a45a8ff	4692	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4693	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4694	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4695	}
bogdanm	0:9b334a45a8ff	4696
bogdanm	0:9b334a45a8ff	4697	/**
bogdanm	0:9b334a45a8ff	4698	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	4699	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4700	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4701	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4702	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4703	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4704	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4705	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4706	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4707	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	4708	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	4709	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4710	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4711	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4712	* @retval None
bogdanm	0:9b334a45a8ff	4713	*/
bogdanm	0:9b334a45a8ff	4714	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4715	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4716	{
bogdanm	0:9b334a45a8ff	4717	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4718	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4719
bogdanm	0:9b334a45a8ff	4720	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4721	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4722	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4723	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4724
bogdanm	0:9b334a45a8ff	4725	/* Select the Input */
bogdanm	0:9b334a45a8ff	4726	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4727	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	4728
bogdanm	0:9b334a45a8ff	4729	/* Set the filter */
bogdanm	0:9b334a45a8ff	4730	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	4731	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	4732
bogdanm	0:9b334a45a8ff	4733	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	4734	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	4735	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	4736
bogdanm	0:9b334a45a8ff	4737	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4738	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	4739	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4740	}
bogdanm	0:9b334a45a8ff	4741
bogdanm	0:9b334a45a8ff	4742	/**
bogdanm	0:9b334a45a8ff	4743	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	4744	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4745	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4746	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4747	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4748	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4749	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4750	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4751	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4752	* @retval None
bogdanm	0:9b334a45a8ff	4753	*/
bogdanm	0:9b334a45a8ff	4754	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4755	{
bogdanm	0:9b334a45a8ff	4756	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4757	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4758
bogdanm	0:9b334a45a8ff	4759	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4760	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4761	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4762	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4763
bogdanm	0:9b334a45a8ff	4764	/* Set the filter */
bogdanm	0:9b334a45a8ff	4765	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	4766	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	4767
bogdanm	0:9b334a45a8ff	4768	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	4769	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	4770	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	4771
bogdanm	0:9b334a45a8ff	4772	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4773	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	4774	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4775	}
bogdanm	0:9b334a45a8ff	4776
bogdanm	0:9b334a45a8ff	4777	/**
bogdanm	0:9b334a45a8ff	4778	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	4779	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4780	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4781	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4782	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4783	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4784	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4785	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4786	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4787	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	4788	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	4789	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4790	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4791	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4792	* @retval None
bogdanm	0:9b334a45a8ff	4793	*/
bogdanm	0:9b334a45a8ff	4794	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4795	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4796	{
bogdanm	0:9b334a45a8ff	4797	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	4798	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4799
bogdanm	0:9b334a45a8ff	4800	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	4801	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4802	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4803	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4804
bogdanm	0:9b334a45a8ff	4805	/* Select the Input */
bogdanm	0:9b334a45a8ff	4806	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4807	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	4808
bogdanm	0:9b334a45a8ff	4809	/* Set the filter */
bogdanm	0:9b334a45a8ff	4810	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	4811	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	4812
bogdanm	0:9b334a45a8ff	4813	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	4814	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	4815	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	4816
bogdanm	0:9b334a45a8ff	4817	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	4818	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	4819	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4820	}
bogdanm	0:9b334a45a8ff	4821
bogdanm	0:9b334a45a8ff	4822	/**
bogdanm	0:9b334a45a8ff	4823	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	4824	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4825	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4826	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4827	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4828	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4829	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4830	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4831	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4832	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	4833	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	4834	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4835	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4836	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4837	* @retval None
bogdanm	0:9b334a45a8ff	4838	*/
bogdanm	0:9b334a45a8ff	4839	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4840	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4841	{
bogdanm	0:9b334a45a8ff	4842	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	4843	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4844
bogdanm	0:9b334a45a8ff	4845	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4846	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4847	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4848	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4849
bogdanm	0:9b334a45a8ff	4850	/* Select the Input */
bogdanm	0:9b334a45a8ff	4851	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4852	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	4853
bogdanm	0:9b334a45a8ff	4854	/* Set the filter */
bogdanm	0:9b334a45a8ff	4855	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	4856	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	4857
bogdanm	0:9b334a45a8ff	4858	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	4859	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	4860	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	4861
bogdanm	0:9b334a45a8ff	4862	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	4863	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	4864	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	4865	}
bogdanm	0:9b334a45a8ff	4866
bogdanm	0:9b334a45a8ff	4867	/**
bogdanm	0:9b334a45a8ff	4868	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	4869	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4870	* @param InputTriggerSource: The Input Trigger source.
bogdanm	0:9b334a45a8ff	4871	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4872	* @arg TIM_TS_ITR0: Internal Trigger 0
bogdanm	0:9b334a45a8ff	4873	* @arg TIM_TS_ITR1: Internal Trigger 1
bogdanm	0:9b334a45a8ff	4874	* @arg TIM_TS_ITR2: Internal Trigger 2
bogdanm	0:9b334a45a8ff	4875	* @arg TIM_TS_ITR3: Internal Trigger 3
bogdanm	0:9b334a45a8ff	4876	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
bogdanm	0:9b334a45a8ff	4877	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	4878	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	4879	* @arg TIM_TS_ETRF: External Trigger input
bogdanm	0:9b334a45a8ff	4880	* @retval None
bogdanm	0:9b334a45a8ff	4881	*/
bogdanm	0:9b334a45a8ff	4882	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
bogdanm	0:9b334a45a8ff	4883	{
bogdanm	0:9b334a45a8ff	4884	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4885
bogdanm	0:9b334a45a8ff	4886	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4887	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	4888	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	4889	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4890	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	4891	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	4892	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4893	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4894	}
bogdanm	0:9b334a45a8ff	4895	/**
bogdanm	0:9b334a45a8ff	4896	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	4897	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4898	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	4899	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4900	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
bogdanm	0:9b334a45a8ff	4901	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
bogdanm	0:9b334a45a8ff	4902	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
bogdanm	0:9b334a45a8ff	4903	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	4904	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	4905	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4906	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
bogdanm	0:9b334a45a8ff	4907	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
bogdanm	0:9b334a45a8ff	4908	* @param ExtTRGFilter: External Trigger Filter.
bogdanm	0:9b334a45a8ff	4909	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	4910	* @retval None
bogdanm	0:9b334a45a8ff	4911	*/
bogdanm	0:9b334a45a8ff	4912	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	4913	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	4914	{
bogdanm	0:9b334a45a8ff	4915	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4916
bogdanm	0:9b334a45a8ff	4917	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	4918
bogdanm	0:9b334a45a8ff	4919	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	4920	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	4921
bogdanm	0:9b334a45a8ff	4922	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	4923	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	4924
bogdanm	0:9b334a45a8ff	4925	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4926	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4927	}
bogdanm	0:9b334a45a8ff	4928
bogdanm	0:9b334a45a8ff	4929	/**
bogdanm	0:9b334a45a8ff	4930	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	4931	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4932	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	4933	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4934	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	4935	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	4936	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	4937	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	4938	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	4939	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	4940	* @retval None
bogdanm	0:9b334a45a8ff	4941	*/
bogdanm	0:9b334a45a8ff	4942	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	4943	{
bogdanm	0:9b334a45a8ff	4944	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	4945
bogdanm	0:9b334a45a8ff	4946	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4947	assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
bogdanm	0:9b334a45a8ff	4948
bogdanm	0:9b334a45a8ff	4949	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	4950
bogdanm	0:9b334a45a8ff	4951	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	4952	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	4953
bogdanm	0:9b334a45a8ff	4954	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	4955	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	4956	}
bogdanm	0:9b334a45a8ff	4957	/**
bogdanm	0:9b334a45a8ff	4958	* @brief Set the slave timer configuration.
bogdanm	0:9b334a45a8ff	4959	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4960	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4961	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4962	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4963	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4964	* @retval None
bogdanm	0:9b334a45a8ff	4965	*/
bogdanm	0:9b334a45a8ff	4966	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4967	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4968	{
bogdanm	0:9b334a45a8ff	4969	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4970	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4971	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4972
bogdanm	0:9b334a45a8ff	4973	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4974	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4975
bogdanm	0:9b334a45a8ff	4976	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4977	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4978	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4979	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4980
bogdanm	0:9b334a45a8ff	4981	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4982	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4983	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4984	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4985
bogdanm	0:9b334a45a8ff	4986	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4987	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4988
bogdanm	0:9b334a45a8ff	4989	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4990	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4991	{
bogdanm	0:9b334a45a8ff	4992	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4993	{
bogdanm	0:9b334a45a8ff	4994	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4995	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4996	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4997	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4998	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4999	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	5000	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	5001	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	5002	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5003	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5004	}
bogdanm	0:9b334a45a8ff	5005	break;
bogdanm	0:9b334a45a8ff	5006
bogdanm	0:9b334a45a8ff	5007	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	5008	{
bogdanm	0:9b334a45a8ff	5009	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5010	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5011	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5012
bogdanm	0:9b334a45a8ff	5013	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5014	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	5015	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5016	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	5017
bogdanm	0:9b334a45a8ff	5018	/* Set the filter */
bogdanm	0:9b334a45a8ff	5019	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5020	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	5021
bogdanm	0:9b334a45a8ff	5022	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5023	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5024	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5025
bogdanm	0:9b334a45a8ff	5026	}
bogdanm	0:9b334a45a8ff	5027	break;
bogdanm	0:9b334a45a8ff	5028
bogdanm	0:9b334a45a8ff	5029	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	5030	{
bogdanm	0:9b334a45a8ff	5031	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5032	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5033	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5034	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5035
bogdanm	0:9b334a45a8ff	5036	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5037	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5038	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5039	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5040	}
bogdanm	0:9b334a45a8ff	5041	break;
bogdanm	0:9b334a45a8ff	5042
bogdanm	0:9b334a45a8ff	5043	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	5044	{
bogdanm	0:9b334a45a8ff	5045	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5046	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5047	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5048	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5049
bogdanm	0:9b334a45a8ff	5050	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5051	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5052	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5053	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5054	}
bogdanm	0:9b334a45a8ff	5055	break;
bogdanm	0:9b334a45a8ff	5056
bogdanm	0:9b334a45a8ff	5057	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	5058	{
bogdanm	0:9b334a45a8ff	5059	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5060	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5061	}
bogdanm	0:9b334a45a8ff	5062	break;
bogdanm	0:9b334a45a8ff	5063
bogdanm	0:9b334a45a8ff	5064	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	5065	{
bogdanm	0:9b334a45a8ff	5066	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5067	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5068	}
bogdanm	0:9b334a45a8ff	5069	break;
bogdanm	0:9b334a45a8ff	5070
bogdanm	0:9b334a45a8ff	5071	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	5072	{
bogdanm	0:9b334a45a8ff	5073	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5074	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5075	}
bogdanm	0:9b334a45a8ff	5076	break;
bogdanm	0:9b334a45a8ff	5077
bogdanm	0:9b334a45a8ff	5078	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	5079	{
bogdanm	0:9b334a45a8ff	5080	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5081	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5082	}
bogdanm	0:9b334a45a8ff	5083	break;
bogdanm	0:9b334a45a8ff	5084
bogdanm	0:9b334a45a8ff	5085	default:
bogdanm	0:9b334a45a8ff	5086	break;
bogdanm	0:9b334a45a8ff	5087	}
bogdanm	0:9b334a45a8ff	5088	}
bogdanm	0:9b334a45a8ff	5089
bogdanm	0:9b334a45a8ff	5090	/**
bogdanm	0:9b334a45a8ff	5091	* @}
bogdanm	0:9b334a45a8ff	5092	*/
bogdanm	0:9b334a45a8ff	5093
bogdanm	0:9b334a45a8ff	5094	/**
bogdanm	0:9b334a45a8ff	5095	* @}
bogdanm	0:9b334a45a8ff	5096	*/
bogdanm	0:9b334a45a8ff	5097
bogdanm	0:9b334a45a8ff	5098	/**
bogdanm	0:9b334a45a8ff	5099	* @}
bogdanm	0:9b334a45a8ff	5100	*/
bogdanm	0:9b334a45a8ff	5101
bogdanm	0:9b334a45a8ff	5102	/**
bogdanm	0:9b334a45a8ff	5103	* @}
bogdanm	0:9b334a45a8ff	5104	*/
bogdanm	0:9b334a45a8ff	5105
mbed_official	113:b3775bf36a83	5106	#endif /* HAL_TIM_MODULE_ENABLED */
mbed_official	113:b3775bf36a83	5107
bogdanm	0:9b334a45a8ff	5108	/**
bogdanm	0:9b334a45a8ff	5109	* @}
bogdanm	0:9b334a45a8ff	5110	*/
bogdanm	0:9b334a45a8ff	5111	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	5112

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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