en 129
fix LPC812 PWM
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mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 113:b3775bf36a83
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l0xx_hal_dma.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| mbed_official | 113:b3775bf36a83 | 5 | * @version V1.5.0 |
| mbed_official | 113:b3775bf36a83 | 6 | * @date 8-January-2016 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of DMA HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| mbed_official | 113:b3775bf36a83 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L0xx_HAL_DMA_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L0xx_HAL_DMA_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @defgroup DMA DMA |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| mbed_official | 113:b3775bf36a83 | 57 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| mbed_official | 113:b3775bf36a83 | 58 | * @{ |
| mbed_official | 113:b3775bf36a83 | 59 | */ |
| bogdanm | 0:9b334a45a8ff | 60 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 61 | |
| bogdanm | 0:9b334a45a8ff | 62 | /** |
| bogdanm | 0:9b334a45a8ff | 63 | * @brief DMA Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 64 | */ |
| bogdanm | 0:9b334a45a8ff | 65 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 66 | { |
| bogdanm | 0:9b334a45a8ff | 67 | uint32_t Request; /*!< Specifies the request selected for the specified channel. |
| bogdanm | 0:9b334a45a8ff | 68 | This parameter can be a value of @ref DMA_request */ |
| bogdanm | 0:9b334a45a8ff | 69 | |
| bogdanm | 0:9b334a45a8ff | 70 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| bogdanm | 0:9b334a45a8ff | 71 | from memory to memory or from peripheral to memory. |
| bogdanm | 0:9b334a45a8ff | 72 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| bogdanm | 0:9b334a45a8ff | 73 | |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| bogdanm | 0:9b334a45a8ff | 75 | When Memory to Memory transfer is used, this is the Source Increment mode |
| bogdanm | 0:9b334a45a8ff | 76 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| bogdanm | 0:9b334a45a8ff | 79 | When Memory to Memory transfer is used, this is the Destination Increment mode |
| bogdanm | 0:9b334a45a8ff | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| bogdanm | 0:9b334a45a8ff | 81 | |
| bogdanm | 0:9b334a45a8ff | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| bogdanm | 0:9b334a45a8ff | 83 | When Memory to Memory transfer is used, this is the Source Alignment format |
| bogdanm | 0:9b334a45a8ff | 84 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| bogdanm | 0:9b334a45a8ff | 87 | When Memory to Memory transfer is used, this is the Destination Alignment format |
| bogdanm | 0:9b334a45a8ff | 88 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular). |
| bogdanm | 0:9b334a45a8ff | 91 | This parameter can be a value of @ref DMA_mode |
| bogdanm | 0:9b334a45a8ff | 92 | @note The circular buffer mode cannot be used if the memory-to-memory |
| bogdanm | 0:9b334a45a8ff | 93 | data transfer is configured on the selected Channel */ |
| bogdanm | 0:9b334a45a8ff | 94 | |
| bogdanm | 0:9b334a45a8ff | 95 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| bogdanm | 0:9b334a45a8ff | 96 | This parameter can be a value of @ref DMA_Priority_level */ |
| bogdanm | 0:9b334a45a8ff | 97 | } DMA_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 98 | |
| bogdanm | 0:9b334a45a8ff | 99 | /** |
| bogdanm | 0:9b334a45a8ff | 100 | * @brief DMA Configuration enumeration values definition |
| bogdanm | 0:9b334a45a8ff | 101 | */ |
| bogdanm | 0:9b334a45a8ff | 102 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 103 | { |
| bogdanm | 0:9b334a45a8ff | 104 | DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| bogdanm | 0:9b334a45a8ff | 105 | DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| bogdanm | 0:9b334a45a8ff | 106 | |
| bogdanm | 0:9b334a45a8ff | 107 | } DMA_ControlTypeDef; |
| bogdanm | 0:9b334a45a8ff | 108 | |
| bogdanm | 0:9b334a45a8ff | 109 | /** |
| bogdanm | 0:9b334a45a8ff | 110 | * @brief HAL DMA State structures definition |
| bogdanm | 0:9b334a45a8ff | 111 | */ |
| bogdanm | 0:9b334a45a8ff | 112 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 113 | { |
| bogdanm | 0:9b334a45a8ff | 114 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| bogdanm | 0:9b334a45a8ff | 115 | HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ |
| bogdanm | 0:9b334a45a8ff | 116 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 117 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| bogdanm | 0:9b334a45a8ff | 118 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| bogdanm | 0:9b334a45a8ff | 119 | HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */ |
| bogdanm | 0:9b334a45a8ff | 120 | }HAL_DMA_StateTypeDef; |
| bogdanm | 0:9b334a45a8ff | 121 | |
| bogdanm | 0:9b334a45a8ff | 122 | /** |
| bogdanm | 0:9b334a45a8ff | 123 | * @brief HAL DMA Error Code structure definition |
| bogdanm | 0:9b334a45a8ff | 124 | */ |
| bogdanm | 0:9b334a45a8ff | 125 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 126 | { |
| bogdanm | 0:9b334a45a8ff | 127 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| bogdanm | 0:9b334a45a8ff | 128 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| bogdanm | 0:9b334a45a8ff | 129 | |
| bogdanm | 0:9b334a45a8ff | 130 | }HAL_DMA_LevelCompleteTypeDef; |
| bogdanm | 0:9b334a45a8ff | 131 | |
| bogdanm | 0:9b334a45a8ff | 132 | |
| bogdanm | 0:9b334a45a8ff | 133 | /** |
| bogdanm | 0:9b334a45a8ff | 134 | * @brief DMA handle Structure definition |
| bogdanm | 0:9b334a45a8ff | 135 | */ |
| bogdanm | 0:9b334a45a8ff | 136 | typedef struct __DMA_HandleTypeDef |
| bogdanm | 0:9b334a45a8ff | 137 | { |
| bogdanm | 0:9b334a45a8ff | 138 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| bogdanm | 0:9b334a45a8ff | 139 | |
| bogdanm | 0:9b334a45a8ff | 140 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| bogdanm | 0:9b334a45a8ff | 141 | |
| bogdanm | 0:9b334a45a8ff | 142 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| bogdanm | 0:9b334a45a8ff | 143 | |
| bogdanm | 0:9b334a45a8ff | 144 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| bogdanm | 0:9b334a45a8ff | 145 | |
| bogdanm | 0:9b334a45a8ff | 146 | void *Parent; /*!< Parent object state */ |
| bogdanm | 0:9b334a45a8ff | 147 | |
| bogdanm | 0:9b334a45a8ff | 148 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| bogdanm | 0:9b334a45a8ff | 149 | |
| bogdanm | 0:9b334a45a8ff | 150 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| bogdanm | 0:9b334a45a8ff | 151 | |
| bogdanm | 0:9b334a45a8ff | 152 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| bogdanm | 0:9b334a45a8ff | 153 | |
| bogdanm | 0:9b334a45a8ff | 154 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| bogdanm | 0:9b334a45a8ff | 155 | |
| bogdanm | 0:9b334a45a8ff | 156 | } DMA_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 157 | |
| mbed_official | 113:b3775bf36a83 | 158 | /** |
| mbed_official | 113:b3775bf36a83 | 159 | * @} |
| mbed_official | 113:b3775bf36a83 | 160 | */ |
| mbed_official | 113:b3775bf36a83 | 161 | |
| bogdanm | 0:9b334a45a8ff | 162 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 163 | |
| bogdanm | 0:9b334a45a8ff | 164 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| bogdanm | 0:9b334a45a8ff | 165 | * @{ |
| bogdanm | 0:9b334a45a8ff | 166 | */ |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | /** @defgroup DMA_Error_Code DMA Error Codes |
| bogdanm | 0:9b334a45a8ff | 169 | * @{ |
| bogdanm | 0:9b334a45a8ff | 170 | */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| bogdanm | 0:9b334a45a8ff | 174 | |
| mbed_official | 113:b3775bf36a83 | 175 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 176 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| mbed_official | 113:b3775bf36a83 | 177 | ((INSTANCE) == DMA1_Channel2) || \ |
| mbed_official | 113:b3775bf36a83 | 178 | ((INSTANCE) == DMA1_Channel3) || \ |
| mbed_official | 113:b3775bf36a83 | 179 | ((INSTANCE) == DMA1_Channel4) || \ |
| mbed_official | 113:b3775bf36a83 | 180 | ((INSTANCE) == DMA1_Channel5)) |
| mbed_official | 113:b3775bf36a83 | 181 | #else |
| mbed_official | 113:b3775bf36a83 | 182 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| mbed_official | 113:b3775bf36a83 | 183 | ((INSTANCE) == DMA1_Channel2) || \ |
| mbed_official | 113:b3775bf36a83 | 184 | ((INSTANCE) == DMA1_Channel3) || \ |
| mbed_official | 113:b3775bf36a83 | 185 | ((INSTANCE) == DMA1_Channel4) || \ |
| mbed_official | 113:b3775bf36a83 | 186 | ((INSTANCE) == DMA1_Channel5) || \ |
| mbed_official | 113:b3775bf36a83 | 187 | ((INSTANCE) == DMA1_Channel6) || \ |
| mbed_official | 113:b3775bf36a83 | 188 | ((INSTANCE) == DMA1_Channel7)) |
| bogdanm | 0:9b334a45a8ff | 189 | |
| mbed_official | 113:b3775bf36a83 | 190 | #endif |
| bogdanm | 0:9b334a45a8ff | 191 | #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) |
| bogdanm | 0:9b334a45a8ff | 192 | |
| bogdanm | 0:9b334a45a8ff | 193 | /** |
| bogdanm | 0:9b334a45a8ff | 194 | * @} |
| bogdanm | 0:9b334a45a8ff | 195 | */ |
| bogdanm | 0:9b334a45a8ff | 196 | |
| bogdanm | 0:9b334a45a8ff | 197 | /** @defgroup DMA_request DMA request defintiions |
| bogdanm | 0:9b334a45a8ff | 198 | * @{ |
| bogdanm | 0:9b334a45a8ff | 199 | */ |
| bogdanm | 0:9b334a45a8ff | 200 | |
| bogdanm | 0:9b334a45a8ff | 201 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 202 | |
| bogdanm | 0:9b334a45a8ff | 203 | #define DMA_REQUEST_0 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 204 | #define DMA_REQUEST_1 ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 205 | #define DMA_REQUEST_2 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 206 | #define DMA_REQUEST_3 ((uint32_t)0x00000003) |
| bogdanm | 0:9b334a45a8ff | 207 | #define DMA_REQUEST_4 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 208 | #define DMA_REQUEST_5 ((uint32_t)0x00000005) |
| bogdanm | 0:9b334a45a8ff | 209 | #define DMA_REQUEST_6 ((uint32_t)0x00000006) |
| bogdanm | 0:9b334a45a8ff | 210 | #define DMA_REQUEST_7 ((uint32_t)0x00000007) |
| bogdanm | 0:9b334a45a8ff | 211 | #define DMA_REQUEST_8 ((uint32_t)0x00000008) |
| bogdanm | 0:9b334a45a8ff | 212 | #define DMA_REQUEST_9 ((uint32_t)0x00000009) |
| bogdanm | 0:9b334a45a8ff | 213 | #define DMA_REQUEST_10 ((uint32_t)0x0000000A) |
| bogdanm | 0:9b334a45a8ff | 214 | #define DMA_REQUEST_11 ((uint32_t)0x0000000B) |
| bogdanm | 0:9b334a45a8ff | 215 | #define DMA_REQUEST_12 ((uint32_t)0x0000000C) |
| bogdanm | 0:9b334a45a8ff | 216 | #define DMA_REQUEST_13 ((uint32_t)0x0000000D) |
| bogdanm | 0:9b334a45a8ff | 217 | #define DMA_REQUEST_14 ((uint32_t)0x0000000E) |
| bogdanm | 0:9b334a45a8ff | 218 | #define DMA_REQUEST_15 ((uint32_t)0x0000000F) |
| bogdanm | 0:9b334a45a8ff | 219 | |
| bogdanm | 0:9b334a45a8ff | 220 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| bogdanm | 0:9b334a45a8ff | 221 | ((REQUEST) == DMA_REQUEST_1) || \ |
| bogdanm | 0:9b334a45a8ff | 222 | ((REQUEST) == DMA_REQUEST_2) || \ |
| bogdanm | 0:9b334a45a8ff | 223 | ((REQUEST) == DMA_REQUEST_3) || \ |
| bogdanm | 0:9b334a45a8ff | 224 | ((REQUEST) == DMA_REQUEST_4) || \ |
| bogdanm | 0:9b334a45a8ff | 225 | ((REQUEST) == DMA_REQUEST_5) || \ |
| bogdanm | 0:9b334a45a8ff | 226 | ((REQUEST) == DMA_REQUEST_6) || \ |
| bogdanm | 0:9b334a45a8ff | 227 | ((REQUEST) == DMA_REQUEST_7) || \ |
| bogdanm | 0:9b334a45a8ff | 228 | ((REQUEST) == DMA_REQUEST_8) || \ |
| bogdanm | 0:9b334a45a8ff | 229 | ((REQUEST) == DMA_REQUEST_9) || \ |
| bogdanm | 0:9b334a45a8ff | 230 | ((REQUEST) == DMA_REQUEST_10) || \ |
| bogdanm | 0:9b334a45a8ff | 231 | ((REQUEST) == DMA_REQUEST_11) || \ |
| bogdanm | 0:9b334a45a8ff | 232 | ((REQUEST) == DMA_REQUEST_12) || \ |
| bogdanm | 0:9b334a45a8ff | 233 | ((REQUEST) == DMA_REQUEST_13) || \ |
| bogdanm | 0:9b334a45a8ff | 234 | ((REQUEST) == DMA_REQUEST_14) || \ |
| bogdanm | 0:9b334a45a8ff | 235 | ((REQUEST) == DMA_REQUEST_15)) |
| bogdanm | 0:9b334a45a8ff | 236 | |
| bogdanm | 0:9b334a45a8ff | 237 | #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
| bogdanm | 0:9b334a45a8ff | 238 | |
| bogdanm | 0:9b334a45a8ff | 239 | #define DMA_REQUEST_0 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 240 | #define DMA_REQUEST_1 ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 241 | #define DMA_REQUEST_2 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 242 | #define DMA_REQUEST_3 ((uint32_t)0x00000003) |
| bogdanm | 0:9b334a45a8ff | 243 | #define DMA_REQUEST_4 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 244 | #define DMA_REQUEST_5 ((uint32_t)0x00000005) |
| bogdanm | 0:9b334a45a8ff | 245 | #define DMA_REQUEST_6 ((uint32_t)0x00000006) |
| bogdanm | 0:9b334a45a8ff | 246 | #define DMA_REQUEST_7 ((uint32_t)0x00000007) |
| bogdanm | 0:9b334a45a8ff | 247 | #define DMA_REQUEST_8 ((uint32_t)0x00000008) |
| bogdanm | 0:9b334a45a8ff | 248 | #define DMA_REQUEST_9 ((uint32_t)0x00000009) |
| bogdanm | 0:9b334a45a8ff | 249 | #define DMA_REQUEST_11 ((uint32_t)0x0000000B) |
| bogdanm | 0:9b334a45a8ff | 250 | |
| bogdanm | 0:9b334a45a8ff | 251 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| bogdanm | 0:9b334a45a8ff | 252 | ((REQUEST) == DMA_REQUEST_1) || \ |
| bogdanm | 0:9b334a45a8ff | 253 | ((REQUEST) == DMA_REQUEST_2) || \ |
| bogdanm | 0:9b334a45a8ff | 254 | ((REQUEST) == DMA_REQUEST_3) || \ |
| bogdanm | 0:9b334a45a8ff | 255 | ((REQUEST) == DMA_REQUEST_4) || \ |
| bogdanm | 0:9b334a45a8ff | 256 | ((REQUEST) == DMA_REQUEST_5) || \ |
| bogdanm | 0:9b334a45a8ff | 257 | ((REQUEST) == DMA_REQUEST_6) || \ |
| bogdanm | 0:9b334a45a8ff | 258 | ((REQUEST) == DMA_REQUEST_7) || \ |
| bogdanm | 0:9b334a45a8ff | 259 | ((REQUEST) == DMA_REQUEST_8) || \ |
| bogdanm | 0:9b334a45a8ff | 260 | ((REQUEST) == DMA_REQUEST_9) || \ |
| bogdanm | 0:9b334a45a8ff | 261 | ((REQUEST) == DMA_REQUEST_11)) |
| bogdanm | 0:9b334a45a8ff | 262 | #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | /** |
| bogdanm | 0:9b334a45a8ff | 265 | * @} |
| bogdanm | 0:9b334a45a8ff | 266 | */ |
| bogdanm | 0:9b334a45a8ff | 267 | |
| bogdanm | 0:9b334a45a8ff | 268 | /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions |
| bogdanm | 0:9b334a45a8ff | 269 | * @{ |
| bogdanm | 0:9b334a45a8ff | 270 | */ |
| bogdanm | 0:9b334a45a8ff | 271 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| bogdanm | 0:9b334a45a8ff | 272 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| bogdanm | 0:9b334a45a8ff | 273 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| bogdanm | 0:9b334a45a8ff | 274 | |
| bogdanm | 0:9b334a45a8ff | 275 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| bogdanm | 0:9b334a45a8ff | 276 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| bogdanm | 0:9b334a45a8ff | 277 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| bogdanm | 0:9b334a45a8ff | 278 | /** |
| bogdanm | 0:9b334a45a8ff | 279 | * @} |
| bogdanm | 0:9b334a45a8ff | 280 | */ |
| bogdanm | 0:9b334a45a8ff | 281 | |
| mbed_official | 113:b3775bf36a83 | 282 | /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check |
| bogdanm | 0:9b334a45a8ff | 283 | * @{ |
| bogdanm | 0:9b334a45a8ff | 284 | */ |
| bogdanm | 0:9b334a45a8ff | 285 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| bogdanm | 0:9b334a45a8ff | 286 | /** |
| bogdanm | 0:9b334a45a8ff | 287 | * @} |
| bogdanm | 0:9b334a45a8ff | 288 | */ |
| bogdanm | 0:9b334a45a8ff | 289 | |
| mbed_official | 113:b3775bf36a83 | 290 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode |
| bogdanm | 0:9b334a45a8ff | 291 | * @{ |
| bogdanm | 0:9b334a45a8ff | 292 | */ |
| bogdanm | 0:9b334a45a8ff | 293 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| bogdanm | 0:9b334a45a8ff | 294 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 297 | ((STATE) == DMA_PINC_DISABLE)) |
| bogdanm | 0:9b334a45a8ff | 298 | /** |
| bogdanm | 0:9b334a45a8ff | 299 | * @} |
| bogdanm | 0:9b334a45a8ff | 300 | */ |
| bogdanm | 0:9b334a45a8ff | 301 | |
| mbed_official | 113:b3775bf36a83 | 302 | /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode |
| bogdanm | 0:9b334a45a8ff | 303 | * @{ |
| bogdanm | 0:9b334a45a8ff | 304 | */ |
| bogdanm | 0:9b334a45a8ff | 305 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| bogdanm | 0:9b334a45a8ff | 306 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| bogdanm | 0:9b334a45a8ff | 307 | |
| bogdanm | 0:9b334a45a8ff | 308 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 309 | ((STATE) == DMA_MINC_DISABLE)) |
| bogdanm | 0:9b334a45a8ff | 310 | /** |
| bogdanm | 0:9b334a45a8ff | 311 | * @} |
| bogdanm | 0:9b334a45a8ff | 312 | */ |
| bogdanm | 0:9b334a45a8ff | 313 | |
| mbed_official | 113:b3775bf36a83 | 314 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment |
| bogdanm | 0:9b334a45a8ff | 315 | * @{ |
| bogdanm | 0:9b334a45a8ff | 316 | */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ |
| bogdanm | 0:9b334a45a8ff | 318 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| bogdanm | 0:9b334a45a8ff | 320 | |
| bogdanm | 0:9b334a45a8ff | 321 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 322 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| bogdanm | 0:9b334a45a8ff | 323 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| bogdanm | 0:9b334a45a8ff | 324 | /** |
| bogdanm | 0:9b334a45a8ff | 325 | * @} |
| bogdanm | 0:9b334a45a8ff | 326 | */ |
| bogdanm | 0:9b334a45a8ff | 327 | |
| bogdanm | 0:9b334a45a8ff | 328 | |
| mbed_official | 113:b3775bf36a83 | 329 | /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment |
| bogdanm | 0:9b334a45a8ff | 330 | * @{ |
| bogdanm | 0:9b334a45a8ff | 331 | */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| bogdanm | 0:9b334a45a8ff | 334 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| bogdanm | 0:9b334a45a8ff | 335 | |
| bogdanm | 0:9b334a45a8ff | 336 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 337 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| bogdanm | 0:9b334a45a8ff | 338 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| bogdanm | 0:9b334a45a8ff | 339 | /** |
| bogdanm | 0:9b334a45a8ff | 340 | * @} |
| bogdanm | 0:9b334a45a8ff | 341 | */ |
| bogdanm | 0:9b334a45a8ff | 342 | |
| mbed_official | 113:b3775bf36a83 | 343 | /** @defgroup DMA_mode DMA Mode |
| bogdanm | 0:9b334a45a8ff | 344 | * @{ |
| bogdanm | 0:9b334a45a8ff | 345 | */ |
| bogdanm | 0:9b334a45a8ff | 346 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| bogdanm | 0:9b334a45a8ff | 348 | |
| bogdanm | 0:9b334a45a8ff | 349 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| bogdanm | 0:9b334a45a8ff | 350 | ((MODE) == DMA_CIRCULAR)) |
| bogdanm | 0:9b334a45a8ff | 351 | /** |
| bogdanm | 0:9b334a45a8ff | 352 | * @} |
| bogdanm | 0:9b334a45a8ff | 353 | */ |
| bogdanm | 0:9b334a45a8ff | 354 | |
| mbed_official | 113:b3775bf36a83 | 355 | /** @defgroup DMA_Priority_level DMA Priority Level |
| bogdanm | 0:9b334a45a8ff | 356 | * @{ |
| bogdanm | 0:9b334a45a8ff | 357 | */ |
| bogdanm | 0:9b334a45a8ff | 358 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| bogdanm | 0:9b334a45a8ff | 359 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| bogdanm | 0:9b334a45a8ff | 360 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| bogdanm | 0:9b334a45a8ff | 361 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| bogdanm | 0:9b334a45a8ff | 362 | |
| bogdanm | 0:9b334a45a8ff | 363 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| bogdanm | 0:9b334a45a8ff | 364 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| bogdanm | 0:9b334a45a8ff | 365 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| bogdanm | 0:9b334a45a8ff | 366 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| bogdanm | 0:9b334a45a8ff | 367 | /** |
| bogdanm | 0:9b334a45a8ff | 368 | * @} |
| bogdanm | 0:9b334a45a8ff | 369 | */ |
| bogdanm | 0:9b334a45a8ff | 370 | |
| bogdanm | 0:9b334a45a8ff | 371 | |
| mbed_official | 113:b3775bf36a83 | 372 | /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions |
| bogdanm | 0:9b334a45a8ff | 373 | * @{ |
| bogdanm | 0:9b334a45a8ff | 374 | */ |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| bogdanm | 0:9b334a45a8ff | 377 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| bogdanm | 0:9b334a45a8ff | 378 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | /** |
| bogdanm | 0:9b334a45a8ff | 381 | * @} |
| bogdanm | 0:9b334a45a8ff | 382 | */ |
| bogdanm | 0:9b334a45a8ff | 383 | |
| mbed_official | 113:b3775bf36a83 | 384 | /** @defgroup DMA_flag_definitions DMA Flag Definitions |
| bogdanm | 0:9b334a45a8ff | 385 | * @{ |
| bogdanm | 0:9b334a45a8ff | 386 | */ |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 389 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 390 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 391 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| bogdanm | 0:9b334a45a8ff | 392 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| bogdanm | 0:9b334a45a8ff | 393 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| bogdanm | 0:9b334a45a8ff | 394 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| bogdanm | 0:9b334a45a8ff | 395 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| bogdanm | 0:9b334a45a8ff | 396 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| bogdanm | 0:9b334a45a8ff | 397 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| bogdanm | 0:9b334a45a8ff | 398 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| bogdanm | 0:9b334a45a8ff | 399 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| bogdanm | 0:9b334a45a8ff | 400 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| bogdanm | 0:9b334a45a8ff | 401 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| bogdanm | 0:9b334a45a8ff | 402 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| bogdanm | 0:9b334a45a8ff | 403 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| bogdanm | 0:9b334a45a8ff | 404 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| bogdanm | 0:9b334a45a8ff | 405 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| bogdanm | 0:9b334a45a8ff | 406 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| bogdanm | 0:9b334a45a8ff | 407 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| bogdanm | 0:9b334a45a8ff | 408 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| bogdanm | 0:9b334a45a8ff | 409 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| bogdanm | 0:9b334a45a8ff | 410 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| bogdanm | 0:9b334a45a8ff | 411 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| bogdanm | 0:9b334a45a8ff | 412 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| bogdanm | 0:9b334a45a8ff | 413 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| bogdanm | 0:9b334a45a8ff | 414 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| bogdanm | 0:9b334a45a8ff | 415 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| bogdanm | 0:9b334a45a8ff | 416 | |
| bogdanm | 0:9b334a45a8ff | 417 | |
| bogdanm | 0:9b334a45a8ff | 418 | /** |
| bogdanm | 0:9b334a45a8ff | 419 | * @} |
| bogdanm | 0:9b334a45a8ff | 420 | */ |
| bogdanm | 0:9b334a45a8ff | 421 | |
| bogdanm | 0:9b334a45a8ff | 422 | /** |
| bogdanm | 0:9b334a45a8ff | 423 | * @} |
| bogdanm | 0:9b334a45a8ff | 424 | */ |
| bogdanm | 0:9b334a45a8ff | 425 | |
| bogdanm | 0:9b334a45a8ff | 426 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 427 | |
| bogdanm | 0:9b334a45a8ff | 428 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| bogdanm | 0:9b334a45a8ff | 429 | * @{ |
| bogdanm | 0:9b334a45a8ff | 430 | */ |
| bogdanm | 0:9b334a45a8ff | 431 | |
| bogdanm | 0:9b334a45a8ff | 432 | /** @brief Reset DMA handle state |
| bogdanm | 0:9b334a45a8ff | 433 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 434 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 435 | */ |
| bogdanm | 0:9b334a45a8ff | 436 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 437 | |
| bogdanm | 0:9b334a45a8ff | 438 | /** |
| bogdanm | 0:9b334a45a8ff | 439 | * @brief Enable the specified DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 440 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 441 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 442 | */ |
| bogdanm | 0:9b334a45a8ff | 443 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| bogdanm | 0:9b334a45a8ff | 444 | |
| bogdanm | 0:9b334a45a8ff | 445 | /** |
| bogdanm | 0:9b334a45a8ff | 446 | * @brief Disable the specified DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 447 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 448 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 449 | */ |
| bogdanm | 0:9b334a45a8ff | 450 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| bogdanm | 0:9b334a45a8ff | 451 | |
| bogdanm | 0:9b334a45a8ff | 452 | |
| bogdanm | 0:9b334a45a8ff | 453 | /* Interrupt & Flag management */ |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | /** |
| bogdanm | 0:9b334a45a8ff | 456 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 457 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 458 | * @retval The specified transfer complete flag index. |
| bogdanm | 0:9b334a45a8ff | 459 | */ |
| bogdanm | 0:9b334a45a8ff | 460 | |
| mbed_official | 113:b3775bf36a83 | 461 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 462 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| mbed_official | 113:b3775bf36a83 | 463 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| mbed_official | 113:b3775bf36a83 | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| mbed_official | 113:b3775bf36a83 | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| mbed_official | 113:b3775bf36a83 | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| mbed_official | 113:b3775bf36a83 | 467 | DMA_FLAG_TC5) |
| mbed_official | 113:b3775bf36a83 | 468 | #else |
| bogdanm | 0:9b334a45a8ff | 469 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 0:9b334a45a8ff | 470 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 0:9b334a45a8ff | 471 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 0:9b334a45a8ff | 472 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 0:9b334a45a8ff | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 0:9b334a45a8ff | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 0:9b334a45a8ff | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| mbed_official | 113:b3775bf36a83 | 476 | DMA_FLAG_TC7) |
| mbed_official | 113:b3775bf36a83 | 477 | #endif |
| bogdanm | 0:9b334a45a8ff | 478 | /** |
| bogdanm | 0:9b334a45a8ff | 479 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 480 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 481 | * @retval The specified half transfer complete flag index. |
| mbed_official | 113:b3775bf36a83 | 482 | */ |
| mbed_official | 113:b3775bf36a83 | 483 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 484 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 113:b3775bf36a83 | 485 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| mbed_official | 113:b3775bf36a83 | 486 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| mbed_official | 113:b3775bf36a83 | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| mbed_official | 113:b3775bf36a83 | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| mbed_official | 113:b3775bf36a83 | 489 | DMA_FLAG_HT5) |
| mbed_official | 113:b3775bf36a83 | 490 | #else |
| bogdanm | 0:9b334a45a8ff | 491 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 492 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 0:9b334a45a8ff | 493 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 0:9b334a45a8ff | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 0:9b334a45a8ff | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 0:9b334a45a8ff | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 0:9b334a45a8ff | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 0:9b334a45a8ff | 498 | DMA_FLAG_HT7) |
| mbed_official | 113:b3775bf36a83 | 499 | #endif |
| bogdanm | 0:9b334a45a8ff | 500 | /** |
| bogdanm | 0:9b334a45a8ff | 501 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 502 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 503 | * @retval The specified transfer error flag index. |
| bogdanm | 0:9b334a45a8ff | 504 | */ |
| mbed_official | 113:b3775bf36a83 | 505 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 506 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 113:b3775bf36a83 | 507 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| mbed_official | 113:b3775bf36a83 | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| mbed_official | 113:b3775bf36a83 | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| mbed_official | 113:b3775bf36a83 | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| mbed_official | 113:b3775bf36a83 | 511 | DMA_FLAG_TE5) |
| mbed_official | 113:b3775bf36a83 | 512 | #else |
| bogdanm | 0:9b334a45a8ff | 513 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 514 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 0:9b334a45a8ff | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 0:9b334a45a8ff | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 0:9b334a45a8ff | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 0:9b334a45a8ff | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 0:9b334a45a8ff | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 0:9b334a45a8ff | 520 | DMA_FLAG_TE7) |
| mbed_official | 113:b3775bf36a83 | 521 | #endif |
| bogdanm | 0:9b334a45a8ff | 522 | /** |
| bogdanm | 0:9b334a45a8ff | 523 | * @brief Returns the current DMA Channel Global interrupt flag. |
| bogdanm | 0:9b334a45a8ff | 524 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 525 | * @retval The specified transfer error flag index. |
| bogdanm | 0:9b334a45a8ff | 526 | */ |
| mbed_official | 113:b3775bf36a83 | 527 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 528 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 113:b3775bf36a83 | 529 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| mbed_official | 113:b3775bf36a83 | 530 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| mbed_official | 113:b3775bf36a83 | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| mbed_official | 113:b3775bf36a83 | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| mbed_official | 113:b3775bf36a83 | 533 | DMA_ISR_GIF5) |
| mbed_official | 113:b3775bf36a83 | 534 | #else |
| bogdanm | 0:9b334a45a8ff | 535 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 0:9b334a45a8ff | 536 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| bogdanm | 0:9b334a45a8ff | 537 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| bogdanm | 0:9b334a45a8ff | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| bogdanm | 0:9b334a45a8ff | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| bogdanm | 0:9b334a45a8ff | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ |
| bogdanm | 0:9b334a45a8ff | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ |
| bogdanm | 0:9b334a45a8ff | 542 | DMA_ISR_GIF7) |
| mbed_official | 113:b3775bf36a83 | 543 | #endif |
| bogdanm | 0:9b334a45a8ff | 544 | /** |
| bogdanm | 0:9b334a45a8ff | 545 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 546 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 547 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 0:9b334a45a8ff | 548 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 549 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 550 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 551 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 552 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| bogdanm | 0:9b334a45a8ff | 553 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 554 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 555 | */ |
| bogdanm | 0:9b334a45a8ff | 556 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 557 | |
| bogdanm | 0:9b334a45a8ff | 558 | /** |
| bogdanm | 0:9b334a45a8ff | 559 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 0:9b334a45a8ff | 560 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 561 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 562 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 563 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 564 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 0:9b334a45a8ff | 565 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 0:9b334a45a8ff | 566 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| bogdanm | 0:9b334a45a8ff | 567 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 0:9b334a45a8ff | 568 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 569 | */ |
| bogdanm | 0:9b334a45a8ff | 570 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | /** |
| bogdanm | 0:9b334a45a8ff | 573 | * @brief Enables the specified DMA Channel interrupts. |
| bogdanm | 0:9b334a45a8ff | 574 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 575 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| bogdanm | 0:9b334a45a8ff | 576 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 577 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 578 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 579 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 0:9b334a45a8ff | 580 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 581 | */ |
| bogdanm | 0:9b334a45a8ff | 582 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 583 | |
| bogdanm | 0:9b334a45a8ff | 584 | /** |
| bogdanm | 0:9b334a45a8ff | 585 | * @brief Disables the specified DMA Channel interrupts. |
| bogdanm | 0:9b334a45a8ff | 586 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 587 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| bogdanm | 0:9b334a45a8ff | 588 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 589 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 590 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 591 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 0:9b334a45a8ff | 592 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 593 | */ |
| bogdanm | 0:9b334a45a8ff | 594 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 595 | |
| bogdanm | 0:9b334a45a8ff | 596 | /** |
| mbed_official | 113:b3775bf36a83 | 597 | * @brief Checks whether the specified DMA Channel interrupt is enabled or not. |
| bogdanm | 0:9b334a45a8ff | 598 | * @param __HANDLE__: DMA handle |
| bogdanm | 0:9b334a45a8ff | 599 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| bogdanm | 0:9b334a45a8ff | 600 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 601 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 602 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 603 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 0:9b334a45a8ff | 604 | * @retval The state of DMA_IT (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 605 | */ |
| bogdanm | 0:9b334a45a8ff | 606 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 607 | |
| bogdanm | 0:9b334a45a8ff | 608 | /** |
| bogdanm | 0:9b334a45a8ff | 609 | * @} |
| bogdanm | 0:9b334a45a8ff | 610 | */ |
| bogdanm | 0:9b334a45a8ff | 611 | |
| bogdanm | 0:9b334a45a8ff | 612 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 613 | |
| bogdanm | 0:9b334a45a8ff | 614 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| bogdanm | 0:9b334a45a8ff | 615 | * @{ |
| bogdanm | 0:9b334a45a8ff | 616 | */ |
| bogdanm | 0:9b334a45a8ff | 617 | |
| bogdanm | 0:9b334a45a8ff | 618 | /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 619 | * @{ |
| bogdanm | 0:9b334a45a8ff | 620 | */ |
| bogdanm | 0:9b334a45a8ff | 621 | |
| bogdanm | 0:9b334a45a8ff | 622 | /* Initialization and de-initialization functions *****************************/ |
| bogdanm | 0:9b334a45a8ff | 623 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 624 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 625 | |
| bogdanm | 0:9b334a45a8ff | 626 | /** |
| bogdanm | 0:9b334a45a8ff | 627 | * @} |
| bogdanm | 0:9b334a45a8ff | 628 | */ |
| bogdanm | 0:9b334a45a8ff | 629 | |
| bogdanm | 0:9b334a45a8ff | 630 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| bogdanm | 0:9b334a45a8ff | 631 | * @{ |
| bogdanm | 0:9b334a45a8ff | 632 | */ |
| bogdanm | 0:9b334a45a8ff | 633 | |
| bogdanm | 0:9b334a45a8ff | 634 | /* IO operation functions *****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 635 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| bogdanm | 0:9b334a45a8ff | 636 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| bogdanm | 0:9b334a45a8ff | 637 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 638 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 639 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 640 | /** |
| bogdanm | 0:9b334a45a8ff | 641 | * @} |
| bogdanm | 0:9b334a45a8ff | 642 | */ |
| bogdanm | 0:9b334a45a8ff | 643 | |
| bogdanm | 0:9b334a45a8ff | 644 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| bogdanm | 0:9b334a45a8ff | 645 | * @{ |
| bogdanm | 0:9b334a45a8ff | 646 | */ |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | /* Peripheral State and Error functions ***************************************/ |
| bogdanm | 0:9b334a45a8ff | 649 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 650 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| bogdanm | 0:9b334a45a8ff | 651 | |
| bogdanm | 0:9b334a45a8ff | 652 | /** |
| bogdanm | 0:9b334a45a8ff | 653 | * @} |
| bogdanm | 0:9b334a45a8ff | 654 | */ |
| bogdanm | 0:9b334a45a8ff | 655 | |
| bogdanm | 0:9b334a45a8ff | 656 | /** |
| bogdanm | 0:9b334a45a8ff | 657 | * @} |
| bogdanm | 0:9b334a45a8ff | 658 | */ |
| mbed_official | 113:b3775bf36a83 | 659 | /* Define the private group ***********************************/ |
| mbed_official | 113:b3775bf36a83 | 660 | /**************************************************************/ |
| mbed_official | 113:b3775bf36a83 | 661 | /** @defgroup DMA_Private DMA Private |
| mbed_official | 113:b3775bf36a83 | 662 | * @{ |
| mbed_official | 113:b3775bf36a83 | 663 | */ |
| mbed_official | 113:b3775bf36a83 | 664 | /** |
| mbed_official | 113:b3775bf36a83 | 665 | * @} |
| mbed_official | 113:b3775bf36a83 | 666 | */ |
| mbed_official | 113:b3775bf36a83 | 667 | /**************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 668 | |
| bogdanm | 0:9b334a45a8ff | 669 | /** |
| bogdanm | 0:9b334a45a8ff | 670 | * @} |
| bogdanm | 0:9b334a45a8ff | 671 | */ |
| bogdanm | 0:9b334a45a8ff | 672 | |
| bogdanm | 0:9b334a45a8ff | 673 | /** |
| bogdanm | 0:9b334a45a8ff | 674 | * @} |
| bogdanm | 0:9b334a45a8ff | 675 | */ |
| bogdanm | 0:9b334a45a8ff | 676 | |
| bogdanm | 0:9b334a45a8ff | 677 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 678 | } |
| bogdanm | 0:9b334a45a8ff | 679 | #endif |
| bogdanm | 0:9b334a45a8ff | 680 | |
| bogdanm | 0:9b334a45a8ff | 681 | #endif /* __STM32L0xx_HAL_DMA_H */ |
| bogdanm | 0:9b334a45a8ff | 682 | |
| bogdanm | 0:9b334a45a8ff | 683 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| bogdanm | 0:9b334a45a8ff | 684 |