en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
113:b3775bf36a83 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l0xx_hal_dma.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 113:b3775bf36a83 5 * @version V1.5.0
mbed_official 113:b3775bf36a83 6 * @date 8-January-2016
bogdanm 0:9b334a45a8ff 7 * @brief DMA HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Direct Memory Access (DMA) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + I/O operation functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 @verbatim
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 19 ==============================================================================
bogdanm 0:9b334a45a8ff 20 [..]
bogdanm 0:9b334a45a8ff 21 (#) Enable and configure the peripheral to be connected to the DMA Channel
bogdanm 0:9b334a45a8ff 22 (except for internal SRAM / FLASH memories: no initialization is
bogdanm 0:9b334a45a8ff 23 necessary).
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (#) For a given Channel, program the required configuration through the following parameters:
bogdanm 0:9b334a45a8ff 26 Channel request, Transfer Direction, Source and Destination data formats,
bogdanm 0:9b334a45a8ff 27 Circular, Normal or peripheral flow control mode, Channel Priority level,
bogdanm 0:9b334a45a8ff 28 Source and Destination Increment mode using HAL_DMA_Init() function.
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 31 =================================
bogdanm 0:9b334a45a8ff 32 [..]
bogdanm 0:9b334a45a8ff 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
bogdanm 0:9b334a45a8ff 34 address and destination address and the Length of data to be transferred
bogdanm 0:9b334a45a8ff 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
bogdanm 0:9b334a45a8ff 36 case a fixed Timeout can be configured by User depending from his application.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 39 ===================================
bogdanm 0:9b334a45a8ff 40 [..]
bogdanm 0:9b334a45a8ff 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
bogdanm 0:9b334a45a8ff 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm 0:9b334a45a8ff 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
bogdanm 0:9b334a45a8ff 44 Source address and destination address and the Length of data to be transferred. In this
bogdanm 0:9b334a45a8ff 45 case the DMA interrupt is configured
bogdanm 0:9b334a45a8ff 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 48 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 49 XferErrorCallback (i.e a member of DMA handle structure).
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
bogdanm 0:9b334a45a8ff 52 detection.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 @endverbatim
bogdanm 0:9b334a45a8ff 59 ******************************************************************************
bogdanm 0:9b334a45a8ff 60 * @attention
bogdanm 0:9b334a45a8ff 61 *
mbed_official 113:b3775bf36a83 62 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 63 *
bogdanm 0:9b334a45a8ff 64 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 65 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 66 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 67 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 69 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 70 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 72 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 73 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 74 *
bogdanm 0:9b334a45a8ff 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 85 *
bogdanm 0:9b334a45a8ff 86 ******************************************************************************
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 90 #include "stm32l0xx_hal.h"
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 93 * @{
bogdanm 0:9b334a45a8ff 94 */
mbed_official 113:b3775bf36a83 95 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup DMA DMA
bogdanm 0:9b334a45a8ff 98 * @brief DMA HAL module driver
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* Private typedef -----------------------------------------------------------*/
mbed_official 113:b3775bf36a83 103 /** @addtogroup DMA_Private
bogdanm 0:9b334a45a8ff 104 *
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @}
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 116 * @{
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /** @addtogroup DMA_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 120 * @brief Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 121 *
bogdanm 0:9b334a45a8ff 122 @verbatim
bogdanm 0:9b334a45a8ff 123 ===============================================================================
bogdanm 0:9b334a45a8ff 124 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 125 ===============================================================================
bogdanm 0:9b334a45a8ff 126 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 127 (+) Initialize and configure the DMA
bogdanm 0:9b334a45a8ff 128 (+) De-Initialize the DMA
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 @endverbatim
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @brief Initializes the DMA according to the specified
bogdanm 0:9b334a45a8ff 136 * parameters in the DMA_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 137 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 138 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 139 * @retval HAL status
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 146 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 147 {
bogdanm 0:9b334a45a8ff 148 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 149 }
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* Check the parameters */
mbed_official 113:b3775bf36a83 152 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 153 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
bogdanm 0:9b334a45a8ff 154 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
bogdanm 0:9b334a45a8ff 155 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
bogdanm 0:9b334a45a8ff 156 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
bogdanm 0:9b334a45a8ff 157 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
bogdanm 0:9b334a45a8ff 158 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
bogdanm 0:9b334a45a8ff 159 assert_param(IS_DMA_MODE(hdma->Init.Mode));
bogdanm 0:9b334a45a8ff 160 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
bogdanm 0:9b334a45a8ff 161
mbed_official 113:b3775bf36a83 162 if(hdma->State == HAL_DMA_STATE_RESET)
mbed_official 113:b3775bf36a83 163 {
mbed_official 113:b3775bf36a83 164 /* Allocate lock resource and initialize it */
mbed_official 113:b3775bf36a83 165 hdma->Lock = HAL_UNLOCKED;
mbed_official 113:b3775bf36a83 166 }
mbed_official 113:b3775bf36a83 167
bogdanm 0:9b334a45a8ff 168 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 169 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 172 tmp = hdma->Instance->CCR;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
bogdanm 0:9b334a45a8ff 175 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
bogdanm 0:9b334a45a8ff 176 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
bogdanm 0:9b334a45a8ff 177 DMA_CCR_DIR));
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /* Prepare the DMA Channel configuration */
bogdanm 0:9b334a45a8ff 180 tmp |= hdma->Init.Direction |
bogdanm 0:9b334a45a8ff 181 hdma->Init.PeriphInc | hdma->Init.MemInc |
bogdanm 0:9b334a45a8ff 182 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
bogdanm 0:9b334a45a8ff 183 hdma->Init.Mode | hdma->Init.Priority;
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Write to DMA Channel CR register */
bogdanm 0:9b334a45a8ff 186 hdma->Instance->CCR = tmp;
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Write to DMA channel selection register */
bogdanm 0:9b334a45a8ff 189 if (hdma->Instance == DMA1_Channel1)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 /*Reset request selection for DMA1 Channel1*/
bogdanm 0:9b334a45a8ff 192 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Configure request selection for DMA1 Channel1 */
bogdanm 0:9b334a45a8ff 195 DMA1_CSELR->CSELR |= hdma->Init.Request;
bogdanm 0:9b334a45a8ff 196 }
bogdanm 0:9b334a45a8ff 197 else if (hdma->Instance == DMA1_Channel2)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /*Reset request selection for DMA1 Channel2*/
bogdanm 0:9b334a45a8ff 200 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Configure request selection for DMA1 Channel2 */
bogdanm 0:9b334a45a8ff 203 DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205 else if (hdma->Instance == DMA1_Channel3)
bogdanm 0:9b334a45a8ff 206 {
bogdanm 0:9b334a45a8ff 207 /*Reset request selection for DMA1 Channel3*/
bogdanm 0:9b334a45a8ff 208 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Configure request selection for DMA1 Channel3 */
bogdanm 0:9b334a45a8ff 211 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
bogdanm 0:9b334a45a8ff 212 }
bogdanm 0:9b334a45a8ff 213 else if (hdma->Instance == DMA1_Channel4)
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 /*Reset request selection for DMA1 Channel4*/
bogdanm 0:9b334a45a8ff 216 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Configure request selection for DMA1 Channel4 */
bogdanm 0:9b334a45a8ff 219 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221 else if (hdma->Instance == DMA1_Channel5)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 /*Reset request selection for DMA1 Channel5*/
bogdanm 0:9b334a45a8ff 224 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Configure request selection for DMA1 Channel5 */
bogdanm 0:9b334a45a8ff 227 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
bogdanm 0:9b334a45a8ff 228 }
mbed_official 113:b3775bf36a83 229 #if !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm 0:9b334a45a8ff 230 else if (hdma->Instance == DMA1_Channel6)
bogdanm 0:9b334a45a8ff 231 {
bogdanm 0:9b334a45a8ff 232 /*Reset request selection for DMA1 Channel6*/
bogdanm 0:9b334a45a8ff 233 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Configure request selection for DMA1 Channel6 */
bogdanm 0:9b334a45a8ff 236 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238 else if (hdma->Instance == DMA1_Channel7)
bogdanm 0:9b334a45a8ff 239 {
bogdanm 0:9b334a45a8ff 240 /*Reset request selection for DMA1 Channel7*/
bogdanm 0:9b334a45a8ff 241 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /* Configure request selection for DMA1 Channel7 */
bogdanm 0:9b334a45a8ff 244 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
bogdanm 0:9b334a45a8ff 245 }
mbed_official 113:b3775bf36a83 246 #endif
bogdanm 0:9b334a45a8ff 247 /* Initialize the DMA state*/
bogdanm 0:9b334a45a8ff 248 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 return HAL_OK;
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /**
bogdanm 0:9b334a45a8ff 254 * @brief DeInitializes the DMA peripheral
bogdanm 0:9b334a45a8ff 255 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 256 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 257 * @retval HAL status
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 260 {
bogdanm 0:9b334a45a8ff 261 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 262 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 263 {
bogdanm 0:9b334a45a8ff 264 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 268 if(hdma->State == HAL_DMA_STATE_BUSY)
bogdanm 0:9b334a45a8ff 269 {
bogdanm 0:9b334a45a8ff 270 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 271 }
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /* Disable the selected DMA Channelx */
bogdanm 0:9b334a45a8ff 274 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Reset DMA Channel control register */
bogdanm 0:9b334a45a8ff 277 hdma->Instance->CCR = 0;
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* Reset DMA Channel Number of Data to Transfer register */
bogdanm 0:9b334a45a8ff 280 hdma->Instance->CNDTR = 0;
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Reset DMA Channel peripheral address register */
bogdanm 0:9b334a45a8ff 283 hdma->Instance->CPAR = 0;
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* Reset DMA Channel memory address register */
bogdanm 0:9b334a45a8ff 286 hdma->Instance->CMAR = 0;
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /* Clear all flags */
bogdanm 0:9b334a45a8ff 289 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 290 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 291 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 292 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /* Reset DMA channel selection register */
bogdanm 0:9b334a45a8ff 295 if (hdma->Instance == DMA1_Channel1)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 298 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 else if (hdma->Instance == DMA1_Channel2)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 303 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 else if (hdma->Instance == DMA1_Channel3)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 308 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310 else if (hdma->Instance == DMA1_Channel4)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 313 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 else if (hdma->Instance == DMA1_Channel5)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 318 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
bogdanm 0:9b334a45a8ff 319 }
mbed_official 113:b3775bf36a83 320 #if !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm 0:9b334a45a8ff 321 else if (hdma->Instance == DMA1_Channel6)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 324 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326 else if (hdma->Instance == DMA1_Channel7)
bogdanm 0:9b334a45a8ff 327 {
bogdanm 0:9b334a45a8ff 328 /*Reset DMA request*/
bogdanm 0:9b334a45a8ff 329 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
bogdanm 0:9b334a45a8ff 330 }
mbed_official 113:b3775bf36a83 331 #endif
bogdanm 0:9b334a45a8ff 332 /* Initialise the error code */
bogdanm 0:9b334a45a8ff 333 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 336 hdma->State = HAL_DMA_STATE_RESET;
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Release Lock */
bogdanm 0:9b334a45a8ff 339 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 return HAL_OK;
bogdanm 0:9b334a45a8ff 342 }
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /**
bogdanm 0:9b334a45a8ff 345 * @}
bogdanm 0:9b334a45a8ff 346 */
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /** @addtogroup DMA_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 349 * @brief I/O operation functions
bogdanm 0:9b334a45a8ff 350 *
bogdanm 0:9b334a45a8ff 351 @verbatim
bogdanm 0:9b334a45a8ff 352 ===============================================================================
bogdanm 0:9b334a45a8ff 353 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 354 ===============================================================================
bogdanm 0:9b334a45a8ff 355 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 356 (+) Configure the source, destination address and data length and Start DMA transfer
bogdanm 0:9b334a45a8ff 357 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 358 Start DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 359 (+) Abort DMA transfer
bogdanm 0:9b334a45a8ff 360 (+) Poll for transfer complete
bogdanm 0:9b334a45a8ff 361 (+) Handle DMA interrupt request
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 @endverbatim
bogdanm 0:9b334a45a8ff 364 * @{
bogdanm 0:9b334a45a8ff 365 */
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /**
bogdanm 0:9b334a45a8ff 368 * @brief Starts the DMA Transfer.
bogdanm 0:9b334a45a8ff 369 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 370 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 371 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 372 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 373 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 374 * @retval HAL status
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 377 {
bogdanm 0:9b334a45a8ff 378 /* Process locked */
bogdanm 0:9b334a45a8ff 379 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 382 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 /* Check the parameters */
bogdanm 0:9b334a45a8ff 385 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 388 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 391 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 394 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 return HAL_OK;
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /**
bogdanm 0:9b334a45a8ff 400 * @brief Start the DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 401 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 402 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 403 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 404 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 405 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 406 * @retval HAL status
bogdanm 0:9b334a45a8ff 407 */
bogdanm 0:9b334a45a8ff 408 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 409 {
bogdanm 0:9b334a45a8ff 410 /* Process locked */
bogdanm 0:9b334a45a8ff 411 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 414 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Check the parameters */
bogdanm 0:9b334a45a8ff 417 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 420 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 423 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 426 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /* Enable the Half transfer complete interrupt */
bogdanm 0:9b334a45a8ff 429 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 432 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 435 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 return HAL_OK;
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /**
bogdanm 0:9b334a45a8ff 441 * @brief Aborts the DMA Transfer.
bogdanm 0:9b334a45a8ff 442 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 443 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 444 * @retval HAL status
bogdanm 0:9b334a45a8ff 445 */
bogdanm 0:9b334a45a8ff 446 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Disable the channel */
bogdanm 0:9b334a45a8ff 451 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Get timeout */
bogdanm 0:9b334a45a8ff 454 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Check if the DMA Channel is effectively disabled */
bogdanm 0:9b334a45a8ff 457 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 460 if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 /* Update error code */
bogdanm 0:9b334a45a8ff 463 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 466 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 469 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 472 }
bogdanm 0:9b334a45a8ff 473 }
bogdanm 0:9b334a45a8ff 474 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 475 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Change the DMA state*/
bogdanm 0:9b334a45a8ff 478 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 return HAL_OK;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief Polling for transfer complete.
bogdanm 0:9b334a45a8ff 485 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 486 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 487 * @param CompleteLevel: Specifies the DMA level complete.
bogdanm 0:9b334a45a8ff 488 * @param Timeout: Timeout duration.
bogdanm 0:9b334a45a8ff 489 * @retval HAL status
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 uint32_t temp;
bogdanm 0:9b334a45a8ff 494 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Get the level transfer complete flag */
bogdanm 0:9b334a45a8ff 497 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 /* Transfer Complete flag */
bogdanm 0:9b334a45a8ff 500 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 501 }
bogdanm 0:9b334a45a8ff 502 else
bogdanm 0:9b334a45a8ff 503 {
bogdanm 0:9b334a45a8ff 504 /* Half Transfer Complete flag */
bogdanm 0:9b334a45a8ff 505 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Get timeout */
bogdanm 0:9b334a45a8ff 509 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
bogdanm 0:9b334a45a8ff 514 {
bogdanm 0:9b334a45a8ff 515 /* Clear the transfer error flags */
bogdanm 0:9b334a45a8ff 516 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Update error code */
bogdanm 0:9b334a45a8ff 519 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 522 hdma->State= HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 525 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 530 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 531 {
bogdanm 0:9b334a45a8ff 532 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 533 {
bogdanm 0:9b334a45a8ff 534 /* Update error code */
bogdanm 0:9b334a45a8ff 535 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 538 hdma->State= HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 541 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 544 }
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546 }
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 549 {
bogdanm 0:9b334a45a8ff 550 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 551 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 554 all transfers are complete) */
bogdanm 0:9b334a45a8ff 555 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* Process unlocked */
bogdanm 0:9b334a45a8ff 558 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560 else
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 563 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* The selected Channelx EN bit is cleared (DMA is disabled and
bogdanm 0:9b334a45a8ff 566 all transfers are complete) */
bogdanm 0:9b334a45a8ff 567 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 /* Process unlocked */
bogdanm 0:9b334a45a8ff 570 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 571 }
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 return HAL_OK;
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 /**
bogdanm 0:9b334a45a8ff 576 * @brief Handles DMA interrupt request.
bogdanm 0:9b334a45a8ff 577 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 578 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 579 * @retval None
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 582 {
bogdanm 0:9b334a45a8ff 583 /* Transfer Error Interrupt management ***************************************/
bogdanm 0:9b334a45a8ff 584 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 585 {
bogdanm 0:9b334a45a8ff 586 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 587 {
bogdanm 0:9b334a45a8ff 588 /* Disable the transfer error interrupt */
bogdanm 0:9b334a45a8ff 589 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Clear the transfer error flag */
bogdanm 0:9b334a45a8ff 592 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Update error code */
bogdanm 0:9b334a45a8ff 595 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 598 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 601 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 if (hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 604 {
bogdanm 0:9b334a45a8ff 605 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 606 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 607 }
bogdanm 0:9b334a45a8ff 608 }
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 /* Half Transfer Complete Interrupt management ******************************/
bogdanm 0:9b334a45a8ff 612 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
bogdanm 0:9b334a45a8ff 615 {
bogdanm 0:9b334a45a8ff 616 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 617 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 618 {
bogdanm 0:9b334a45a8ff 619 /* Disable the half transfer interrupt */
bogdanm 0:9b334a45a8ff 620 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 621 }
bogdanm 0:9b334a45a8ff 622 /* Clear the half transfer complete flag */
bogdanm 0:9b334a45a8ff 623 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 624
bogdanm 0:9b334a45a8ff 625 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 626 hdma->State = HAL_DMA_STATE_READY_HALF;
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 if(hdma->XferHalfCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 629 {
bogdanm 0:9b334a45a8ff 630 /* Half transfer callback */
bogdanm 0:9b334a45a8ff 631 hdma->XferHalfCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 632 }
bogdanm 0:9b334a45a8ff 633 }
bogdanm 0:9b334a45a8ff 634 }
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /* Transfer Complete Interrupt management ***********************************/
bogdanm 0:9b334a45a8ff 637 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
bogdanm 0:9b334a45a8ff 638 {
bogdanm 0:9b334a45a8ff 639 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 640 {
bogdanm 0:9b334a45a8ff 641 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 642 {
bogdanm 0:9b334a45a8ff 643 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 644 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 647 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649 /* Update error code */
bogdanm 0:9b334a45a8ff 650 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 653 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 656 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 661 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 662 }
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 }
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /**
bogdanm 0:9b334a45a8ff 668 * @}
bogdanm 0:9b334a45a8ff 669 */
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /** @addtogroup DMA_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 672 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 673 *
bogdanm 0:9b334a45a8ff 674 @verbatim
bogdanm 0:9b334a45a8ff 675 ===============================================================================
bogdanm 0:9b334a45a8ff 676 ##### Peripheral State functions #####
bogdanm 0:9b334a45a8ff 677 ===============================================================================
bogdanm 0:9b334a45a8ff 678 [..]
bogdanm 0:9b334a45a8ff 679 This subsection provides functions allowing to
bogdanm 0:9b334a45a8ff 680 (+) Check the DMA state
bogdanm 0:9b334a45a8ff 681 (+) Get error code
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 @endverbatim
bogdanm 0:9b334a45a8ff 684 * @{
bogdanm 0:9b334a45a8ff 685 */
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 /**
bogdanm 0:9b334a45a8ff 688 * @brief Returns the DMA state.
bogdanm 0:9b334a45a8ff 689 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 690 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 691 * @retval HAL state
bogdanm 0:9b334a45a8ff 692 */
bogdanm 0:9b334a45a8ff 693 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 694 {
bogdanm 0:9b334a45a8ff 695 return hdma->State;
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /**
bogdanm 0:9b334a45a8ff 699 * @brief Return the DMA error code
bogdanm 0:9b334a45a8ff 700 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 701 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 702 * @retval DMA Error Code
bogdanm 0:9b334a45a8ff 703 */
bogdanm 0:9b334a45a8ff 704 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 705 {
bogdanm 0:9b334a45a8ff 706 return hdma->ErrorCode;
bogdanm 0:9b334a45a8ff 707 }
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /**
bogdanm 0:9b334a45a8ff 710 * @}
bogdanm 0:9b334a45a8ff 711 */
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /**
bogdanm 0:9b334a45a8ff 714 * @}
bogdanm 0:9b334a45a8ff 715 */
bogdanm 0:9b334a45a8ff 716 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 717 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 /* Private function prototypes -----------------------------------------------*/
mbed_official 113:b3775bf36a83 721 /** @addtogroup DMA_Private
bogdanm 0:9b334a45a8ff 722 * @{
bogdanm 0:9b334a45a8ff 723 */
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /*
bogdanm 0:9b334a45a8ff 726 * @brief Sets the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 727 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 728 * the configuration information for the specified DMA Channel.
bogdanm 0:9b334a45a8ff 729 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 730 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 731 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 732 * @retval HAL status
bogdanm 0:9b334a45a8ff 733 */
bogdanm 0:9b334a45a8ff 734 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 735 {
bogdanm 0:9b334a45a8ff 736 /* Configure DMA Channel data length */
bogdanm 0:9b334a45a8ff 737 hdma->Instance->CNDTR = DataLength;
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 740 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 743 hdma->Instance->CPAR = DstAddress;
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 746 hdma->Instance->CMAR = SrcAddress;
bogdanm 0:9b334a45a8ff 747 }
bogdanm 0:9b334a45a8ff 748 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 749 else
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 /* Configure DMA Channel source address */
bogdanm 0:9b334a45a8ff 752 hdma->Instance->CPAR = SrcAddress;
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /* Configure DMA Channel destination address */
bogdanm 0:9b334a45a8ff 755 hdma->Instance->CMAR = DstAddress;
bogdanm 0:9b334a45a8ff 756 }
bogdanm 0:9b334a45a8ff 757 }
bogdanm 0:9b334a45a8ff 758 /**
bogdanm 0:9b334a45a8ff 759 * @}
bogdanm 0:9b334a45a8ff 760 */
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 /**
bogdanm 0:9b334a45a8ff 763 * @}
bogdanm 0:9b334a45a8ff 764 */
bogdanm 0:9b334a45a8ff 765
mbed_official 113:b3775bf36a83 766 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 767 /**
bogdanm 0:9b334a45a8ff 768 * @}
bogdanm 0:9b334a45a8ff 769 */
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 772