fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 113:b3775bf36a83
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l0xx_hal_cortex.h |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
mbed_official | 113:b3775bf36a83 | 5 | * @version V1.5.0 |
mbed_official | 113:b3775bf36a83 | 6 | * @date 8-January-2016 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of CORTEX HAL module. |
bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 9 | * @attention |
bogdanm | 0:9b334a45a8ff | 10 | * |
mbed_official | 113:b3775bf36a83 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 12 | * |
bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 34 | * |
bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 36 | */ |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L0xx_HAL_CORTEX_H |
bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L0xx_HAL_CORTEX_H |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
bogdanm | 0:9b334a45a8ff | 44 | #endif |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l0xx_hal_def.h" |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 50 | * @{ |
bogdanm | 0:9b334a45a8ff | 51 | */ |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | /** @defgroup CORTEX CORTEX |
bogdanm | 0:9b334a45a8ff | 54 | * @{ |
bogdanm | 0:9b334a45a8ff | 55 | */ |
bogdanm | 0:9b334a45a8ff | 56 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 113:b3775bf36a83 | 57 | |
mbed_official | 113:b3775bf36a83 | 58 | /** @defgroup CORTEX_Exported_Types CORTEX Exported Types |
mbed_official | 113:b3775bf36a83 | 59 | * @{ |
mbed_official | 113:b3775bf36a83 | 60 | */ |
mbed_official | 113:b3775bf36a83 | 61 | |
mbed_official | 113:b3775bf36a83 | 62 | #if (__MPU_PRESENT == 1) |
mbed_official | 113:b3775bf36a83 | 63 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
mbed_official | 113:b3775bf36a83 | 64 | * @{ |
mbed_official | 113:b3775bf36a83 | 65 | */ |
mbed_official | 113:b3775bf36a83 | 66 | typedef struct |
mbed_official | 113:b3775bf36a83 | 67 | { |
mbed_official | 113:b3775bf36a83 | 68 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
mbed_official | 113:b3775bf36a83 | 69 | |
mbed_official | 113:b3775bf36a83 | 70 | uint8_t Enable; /*!< Specifies the status of the region. |
mbed_official | 113:b3775bf36a83 | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
mbed_official | 113:b3775bf36a83 | 72 | uint8_t Number; /*!< Specifies the number of the region to protect. |
mbed_official | 113:b3775bf36a83 | 73 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
mbed_official | 113:b3775bf36a83 | 74 | |
mbed_official | 113:b3775bf36a83 | 75 | uint8_t Size; /*!< Specifies the size of the region to protect. |
mbed_official | 113:b3775bf36a83 | 76 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
mbed_official | 113:b3775bf36a83 | 77 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
mbed_official | 113:b3775bf36a83 | 78 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
mbed_official | 113:b3775bf36a83 | 79 | uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/ |
mbed_official | 113:b3775bf36a83 | 80 | |
mbed_official | 113:b3775bf36a83 | 81 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
mbed_official | 113:b3775bf36a83 | 82 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
mbed_official | 113:b3775bf36a83 | 83 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
mbed_official | 113:b3775bf36a83 | 84 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
mbed_official | 113:b3775bf36a83 | 85 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
mbed_official | 113:b3775bf36a83 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
mbed_official | 113:b3775bf36a83 | 87 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
mbed_official | 113:b3775bf36a83 | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
mbed_official | 113:b3775bf36a83 | 89 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
mbed_official | 113:b3775bf36a83 | 90 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
mbed_official | 113:b3775bf36a83 | 91 | }MPU_Region_InitTypeDef; |
mbed_official | 113:b3775bf36a83 | 92 | /** |
mbed_official | 113:b3775bf36a83 | 93 | * @} |
mbed_official | 113:b3775bf36a83 | 94 | */ |
mbed_official | 113:b3775bf36a83 | 95 | #endif /* __MPU_PRESENT */ |
mbed_official | 113:b3775bf36a83 | 96 | |
mbed_official | 113:b3775bf36a83 | 97 | /** |
mbed_official | 113:b3775bf36a83 | 98 | * @} |
mbed_official | 113:b3775bf36a83 | 99 | */ |
mbed_official | 113:b3775bf36a83 | 100 | |
mbed_official | 113:b3775bf36a83 | 101 | |
bogdanm | 0:9b334a45a8ff | 102 | /* Exported constants --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 103 | |
mbed_official | 113:b3775bf36a83 | 104 | /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants |
bogdanm | 0:9b334a45a8ff | 105 | * @{ |
bogdanm | 0:9b334a45a8ff | 106 | */ |
bogdanm | 0:9b334a45a8ff | 107 | |
bogdanm | 0:9b334a45a8ff | 108 | |
bogdanm | 0:9b334a45a8ff | 109 | #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4) |
bogdanm | 0:9b334a45a8ff | 110 | |
bogdanm | 0:9b334a45a8ff | 111 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
bogdanm | 0:9b334a45a8ff | 112 | |
mbed_official | 113:b3775bf36a83 | 113 | /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source |
bogdanm | 0:9b334a45a8ff | 114 | * @{ |
bogdanm | 0:9b334a45a8ff | 115 | */ |
bogdanm | 0:9b334a45a8ff | 116 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 117 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 118 | #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ |
bogdanm | 0:9b334a45a8ff | 119 | ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
bogdanm | 0:9b334a45a8ff | 120 | /** |
bogdanm | 0:9b334a45a8ff | 121 | * @} |
bogdanm | 0:9b334a45a8ff | 122 | */ |
mbed_official | 113:b3775bf36a83 | 123 | |
mbed_official | 113:b3775bf36a83 | 124 | #if (__MPU_PRESENT == 1) |
mbed_official | 113:b3775bf36a83 | 125 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control |
mbed_official | 113:b3775bf36a83 | 126 | * @{ |
mbed_official | 113:b3775bf36a83 | 127 | */ |
mbed_official | 113:b3775bf36a83 | 128 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) |
mbed_official | 113:b3775bf36a83 | 129 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) |
mbed_official | 113:b3775bf36a83 | 130 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) |
mbed_official | 113:b3775bf36a83 | 131 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) |
mbed_official | 113:b3775bf36a83 | 132 | /** |
mbed_official | 113:b3775bf36a83 | 133 | * @} |
mbed_official | 113:b3775bf36a83 | 134 | */ |
mbed_official | 113:b3775bf36a83 | 135 | |
mbed_official | 113:b3775bf36a83 | 136 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
mbed_official | 113:b3775bf36a83 | 137 | * @{ |
mbed_official | 113:b3775bf36a83 | 138 | */ |
mbed_official | 113:b3775bf36a83 | 139 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 140 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 141 | /** |
mbed_official | 113:b3775bf36a83 | 142 | * @} |
mbed_official | 113:b3775bf36a83 | 143 | */ |
mbed_official | 113:b3775bf36a83 | 144 | |
mbed_official | 113:b3775bf36a83 | 145 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
mbed_official | 113:b3775bf36a83 | 146 | * @{ |
mbed_official | 113:b3775bf36a83 | 147 | */ |
mbed_official | 113:b3775bf36a83 | 148 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 149 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 150 | /** |
mbed_official | 113:b3775bf36a83 | 151 | * @} |
mbed_official | 113:b3775bf36a83 | 152 | */ |
mbed_official | 113:b3775bf36a83 | 153 | |
mbed_official | 113:b3775bf36a83 | 154 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
mbed_official | 113:b3775bf36a83 | 155 | * @{ |
mbed_official | 113:b3775bf36a83 | 156 | */ |
mbed_official | 113:b3775bf36a83 | 157 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 158 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 159 | /** |
mbed_official | 113:b3775bf36a83 | 160 | * @} |
mbed_official | 113:b3775bf36a83 | 161 | */ |
mbed_official | 113:b3775bf36a83 | 162 | |
mbed_official | 113:b3775bf36a83 | 163 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
mbed_official | 113:b3775bf36a83 | 164 | * @{ |
mbed_official | 113:b3775bf36a83 | 165 | */ |
mbed_official | 113:b3775bf36a83 | 166 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 167 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 168 | /** |
mbed_official | 113:b3775bf36a83 | 169 | * @} |
mbed_official | 113:b3775bf36a83 | 170 | */ |
mbed_official | 113:b3775bf36a83 | 171 | |
mbed_official | 113:b3775bf36a83 | 172 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
mbed_official | 113:b3775bf36a83 | 173 | * @{ |
mbed_official | 113:b3775bf36a83 | 174 | */ |
mbed_official | 113:b3775bf36a83 | 175 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 176 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 177 | /** |
mbed_official | 113:b3775bf36a83 | 178 | * @} |
mbed_official | 113:b3775bf36a83 | 179 | */ |
mbed_official | 113:b3775bf36a83 | 180 | |
mbed_official | 113:b3775bf36a83 | 181 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
mbed_official | 113:b3775bf36a83 | 182 | * @{ |
mbed_official | 113:b3775bf36a83 | 183 | */ |
mbed_official | 113:b3775bf36a83 | 184 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
mbed_official | 113:b3775bf36a83 | 185 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
mbed_official | 113:b3775bf36a83 | 186 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
mbed_official | 113:b3775bf36a83 | 187 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
mbed_official | 113:b3775bf36a83 | 188 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
mbed_official | 113:b3775bf36a83 | 189 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
mbed_official | 113:b3775bf36a83 | 190 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
mbed_official | 113:b3775bf36a83 | 191 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
mbed_official | 113:b3775bf36a83 | 192 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
mbed_official | 113:b3775bf36a83 | 193 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
mbed_official | 113:b3775bf36a83 | 194 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
mbed_official | 113:b3775bf36a83 | 195 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
mbed_official | 113:b3775bf36a83 | 196 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
mbed_official | 113:b3775bf36a83 | 197 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
mbed_official | 113:b3775bf36a83 | 198 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
mbed_official | 113:b3775bf36a83 | 199 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
mbed_official | 113:b3775bf36a83 | 200 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
mbed_official | 113:b3775bf36a83 | 201 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
mbed_official | 113:b3775bf36a83 | 202 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
mbed_official | 113:b3775bf36a83 | 203 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
mbed_official | 113:b3775bf36a83 | 204 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
mbed_official | 113:b3775bf36a83 | 205 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
mbed_official | 113:b3775bf36a83 | 206 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
mbed_official | 113:b3775bf36a83 | 207 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
mbed_official | 113:b3775bf36a83 | 208 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
mbed_official | 113:b3775bf36a83 | 209 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
mbed_official | 113:b3775bf36a83 | 210 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
mbed_official | 113:b3775bf36a83 | 211 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
mbed_official | 113:b3775bf36a83 | 212 | /** |
mbed_official | 113:b3775bf36a83 | 213 | * @} |
mbed_official | 113:b3775bf36a83 | 214 | */ |
mbed_official | 113:b3775bf36a83 | 215 | |
mbed_official | 113:b3775bf36a83 | 216 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
mbed_official | 113:b3775bf36a83 | 217 | * @{ |
mbed_official | 113:b3775bf36a83 | 218 | */ |
mbed_official | 113:b3775bf36a83 | 219 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 220 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 221 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
mbed_official | 113:b3775bf36a83 | 222 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
mbed_official | 113:b3775bf36a83 | 223 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
mbed_official | 113:b3775bf36a83 | 224 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
mbed_official | 113:b3775bf36a83 | 225 | /** |
mbed_official | 113:b3775bf36a83 | 226 | * @} |
mbed_official | 113:b3775bf36a83 | 227 | */ |
mbed_official | 113:b3775bf36a83 | 228 | |
mbed_official | 113:b3775bf36a83 | 229 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
mbed_official | 113:b3775bf36a83 | 230 | * @{ |
mbed_official | 113:b3775bf36a83 | 231 | */ |
mbed_official | 113:b3775bf36a83 | 232 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
mbed_official | 113:b3775bf36a83 | 233 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
mbed_official | 113:b3775bf36a83 | 234 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
mbed_official | 113:b3775bf36a83 | 235 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
mbed_official | 113:b3775bf36a83 | 236 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
mbed_official | 113:b3775bf36a83 | 237 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
mbed_official | 113:b3775bf36a83 | 238 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
mbed_official | 113:b3775bf36a83 | 239 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
mbed_official | 113:b3775bf36a83 | 240 | /** |
mbed_official | 113:b3775bf36a83 | 241 | * @} |
mbed_official | 113:b3775bf36a83 | 242 | */ |
mbed_official | 113:b3775bf36a83 | 243 | #endif /* __MPU_PRESENT */ |
mbed_official | 113:b3775bf36a83 | 244 | |
mbed_official | 113:b3775bf36a83 | 245 | |
bogdanm | 0:9b334a45a8ff | 246 | /** |
bogdanm | 0:9b334a45a8ff | 247 | * @} |
bogdanm | 0:9b334a45a8ff | 248 | */ |
bogdanm | 0:9b334a45a8ff | 249 | |
bogdanm | 0:9b334a45a8ff | 250 | /* Exported functions --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 251 | /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
bogdanm | 0:9b334a45a8ff | 252 | * @{ |
bogdanm | 0:9b334a45a8ff | 253 | */ |
bogdanm | 0:9b334a45a8ff | 254 | |
bogdanm | 0:9b334a45a8ff | 255 | /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 256 | * @brief Initialization and Configuration functions |
bogdanm | 0:9b334a45a8ff | 257 | * @{ |
bogdanm | 0:9b334a45a8ff | 258 | */ |
bogdanm | 0:9b334a45a8ff | 259 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
bogdanm | 0:9b334a45a8ff | 260 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 261 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 262 | void HAL_NVIC_SystemReset(void); |
bogdanm | 0:9b334a45a8ff | 263 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
mbed_official | 113:b3775bf36a83 | 264 | #if (__MPU_PRESENT == 1) |
mbed_official | 113:b3775bf36a83 | 265 | /** |
mbed_official | 113:b3775bf36a83 | 266 | * @brief Disable the MPU. |
mbed_official | 113:b3775bf36a83 | 267 | * @retval None |
mbed_official | 113:b3775bf36a83 | 268 | */ |
mbed_official | 113:b3775bf36a83 | 269 | __STATIC_INLINE void HAL_MPU_Disable(void) |
mbed_official | 113:b3775bf36a83 | 270 | { |
mbed_official | 113:b3775bf36a83 | 271 | |
mbed_official | 113:b3775bf36a83 | 272 | /*Data Memory Barrier setup */ |
mbed_official | 113:b3775bf36a83 | 273 | __DMB(); |
mbed_official | 113:b3775bf36a83 | 274 | /* Disable the MPU */ |
mbed_official | 113:b3775bf36a83 | 275 | MPU->CTRL = 0; |
mbed_official | 113:b3775bf36a83 | 276 | } |
mbed_official | 113:b3775bf36a83 | 277 | |
mbed_official | 113:b3775bf36a83 | 278 | /** |
mbed_official | 113:b3775bf36a83 | 279 | * @brief Enable the MPU. |
mbed_official | 113:b3775bf36a83 | 280 | * @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
mbed_official | 113:b3775bf36a83 | 281 | * NMI, FAULTMASK and privileged access to the default memory |
mbed_official | 113:b3775bf36a83 | 282 | * This parameter can be one of the following values: |
mbed_official | 113:b3775bf36a83 | 283 | * @arg MPU_HFNMI_PRIVDEF_NONE |
mbed_official | 113:b3775bf36a83 | 284 | * @arg MPU_HARDFAULT_NMI |
mbed_official | 113:b3775bf36a83 | 285 | * @arg MPU_PRIVILEGED_DEFAULT |
mbed_official | 113:b3775bf36a83 | 286 | * @arg MPU_HFNMI_PRIVDEF |
mbed_official | 113:b3775bf36a83 | 287 | * @retval None |
mbed_official | 113:b3775bf36a83 | 288 | */ |
mbed_official | 113:b3775bf36a83 | 289 | |
mbed_official | 113:b3775bf36a83 | 290 | __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) |
mbed_official | 113:b3775bf36a83 | 291 | { |
mbed_official | 113:b3775bf36a83 | 292 | /* Enable the MPU */ |
mbed_official | 113:b3775bf36a83 | 293 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
mbed_official | 113:b3775bf36a83 | 294 | /* Data Synchronization Barrier setup */ |
mbed_official | 113:b3775bf36a83 | 295 | __DSB(); |
mbed_official | 113:b3775bf36a83 | 296 | /* Instruction Synchronization Barrier setup */ |
mbed_official | 113:b3775bf36a83 | 297 | __ISB(); |
mbed_official | 113:b3775bf36a83 | 298 | |
mbed_official | 113:b3775bf36a83 | 299 | } |
mbed_official | 113:b3775bf36a83 | 300 | #endif /* __MPU_PRESENT */ |
bogdanm | 0:9b334a45a8ff | 301 | /** |
bogdanm | 0:9b334a45a8ff | 302 | * @} |
bogdanm | 0:9b334a45a8ff | 303 | */ |
bogdanm | 0:9b334a45a8ff | 304 | |
bogdanm | 0:9b334a45a8ff | 305 | /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 306 | * @brief Cortex control functions |
bogdanm | 0:9b334a45a8ff | 307 | * @{ |
bogdanm | 0:9b334a45a8ff | 308 | */ |
mbed_official | 113:b3775bf36a83 | 309 | |
mbed_official | 113:b3775bf36a83 | 310 | uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 311 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 312 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 313 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
bogdanm | 0:9b334a45a8ff | 314 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
bogdanm | 0:9b334a45a8ff | 315 | void HAL_SYSTICK_IRQHandler(void); |
bogdanm | 0:9b334a45a8ff | 316 | void HAL_SYSTICK_Callback(void); |
mbed_official | 113:b3775bf36a83 | 317 | #if (__MPU_PRESENT == 1) |
mbed_official | 113:b3775bf36a83 | 318 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
mbed_official | 113:b3775bf36a83 | 319 | #endif /* __MPU_PRESENT */ |
bogdanm | 0:9b334a45a8ff | 320 | /** |
bogdanm | 0:9b334a45a8ff | 321 | * @} |
bogdanm | 0:9b334a45a8ff | 322 | */ |
bogdanm | 0:9b334a45a8ff | 323 | |
bogdanm | 0:9b334a45a8ff | 324 | /** |
bogdanm | 0:9b334a45a8ff | 325 | * @} |
bogdanm | 0:9b334a45a8ff | 326 | */ |
mbed_official | 113:b3775bf36a83 | 327 | |
mbed_official | 113:b3775bf36a83 | 328 | /* Private types -------------------------------------------------------------*/ |
mbed_official | 113:b3775bf36a83 | 329 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 113:b3775bf36a83 | 330 | /* Private constants ---------------------------------------------------------*/ |
mbed_official | 113:b3775bf36a83 | 331 | /* Private macros ------------------------------------------------------------*/ |
mbed_official | 113:b3775bf36a83 | 332 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
mbed_official | 113:b3775bf36a83 | 333 | * @{ |
mbed_official | 113:b3775bf36a83 | 334 | */ |
mbed_official | 113:b3775bf36a83 | 335 | |
mbed_official | 113:b3775bf36a83 | 336 | #if (__MPU_PRESENT == 1) |
mbed_official | 113:b3775bf36a83 | 337 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
mbed_official | 113:b3775bf36a83 | 338 | ((STATE) == MPU_REGION_DISABLE)) |
mbed_official | 113:b3775bf36a83 | 339 | |
mbed_official | 113:b3775bf36a83 | 340 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
mbed_official | 113:b3775bf36a83 | 341 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
mbed_official | 113:b3775bf36a83 | 342 | |
mbed_official | 113:b3775bf36a83 | 343 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
mbed_official | 113:b3775bf36a83 | 344 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
mbed_official | 113:b3775bf36a83 | 345 | |
mbed_official | 113:b3775bf36a83 | 346 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
mbed_official | 113:b3775bf36a83 | 347 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
mbed_official | 113:b3775bf36a83 | 348 | |
mbed_official | 113:b3775bf36a83 | 349 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
mbed_official | 113:b3775bf36a83 | 350 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
mbed_official | 113:b3775bf36a83 | 351 | |
mbed_official | 113:b3775bf36a83 | 352 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
mbed_official | 113:b3775bf36a83 | 353 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
mbed_official | 113:b3775bf36a83 | 354 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
mbed_official | 113:b3775bf36a83 | 355 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
mbed_official | 113:b3775bf36a83 | 356 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
mbed_official | 113:b3775bf36a83 | 357 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
mbed_official | 113:b3775bf36a83 | 358 | |
mbed_official | 113:b3775bf36a83 | 359 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
mbed_official | 113:b3775bf36a83 | 360 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
mbed_official | 113:b3775bf36a83 | 361 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
mbed_official | 113:b3775bf36a83 | 362 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
mbed_official | 113:b3775bf36a83 | 363 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
mbed_official | 113:b3775bf36a83 | 364 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
mbed_official | 113:b3775bf36a83 | 365 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
mbed_official | 113:b3775bf36a83 | 366 | ((NUMBER) == MPU_REGION_NUMBER7)) |
mbed_official | 113:b3775bf36a83 | 367 | |
mbed_official | 113:b3775bf36a83 | 368 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ |
mbed_official | 113:b3775bf36a83 | 369 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
mbed_official | 113:b3775bf36a83 | 370 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
mbed_official | 113:b3775bf36a83 | 371 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
mbed_official | 113:b3775bf36a83 | 372 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
mbed_official | 113:b3775bf36a83 | 373 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
mbed_official | 113:b3775bf36a83 | 374 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
mbed_official | 113:b3775bf36a83 | 375 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
mbed_official | 113:b3775bf36a83 | 376 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
mbed_official | 113:b3775bf36a83 | 377 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
mbed_official | 113:b3775bf36a83 | 378 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
mbed_official | 113:b3775bf36a83 | 379 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
mbed_official | 113:b3775bf36a83 | 380 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
mbed_official | 113:b3775bf36a83 | 381 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
mbed_official | 113:b3775bf36a83 | 382 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
mbed_official | 113:b3775bf36a83 | 383 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
mbed_official | 113:b3775bf36a83 | 384 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
mbed_official | 113:b3775bf36a83 | 385 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
mbed_official | 113:b3775bf36a83 | 386 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
mbed_official | 113:b3775bf36a83 | 387 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
mbed_official | 113:b3775bf36a83 | 388 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
mbed_official | 113:b3775bf36a83 | 389 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
mbed_official | 113:b3775bf36a83 | 390 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
mbed_official | 113:b3775bf36a83 | 391 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
mbed_official | 113:b3775bf36a83 | 392 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
mbed_official | 113:b3775bf36a83 | 393 | |
mbed_official | 113:b3775bf36a83 | 394 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
mbed_official | 113:b3775bf36a83 | 395 | #endif /* __MPU_PRESENT */ |
mbed_official | 113:b3775bf36a83 | 396 | |
mbed_official | 113:b3775bf36a83 | 397 | |
mbed_official | 113:b3775bf36a83 | 398 | /** |
mbed_official | 113:b3775bf36a83 | 399 | * @} |
mbed_official | 113:b3775bf36a83 | 400 | */ |
mbed_official | 113:b3775bf36a83 | 401 | |
bogdanm | 0:9b334a45a8ff | 402 | /** |
bogdanm | 0:9b334a45a8ff | 403 | * @} |
bogdanm | 0:9b334a45a8ff | 404 | */ |
bogdanm | 0:9b334a45a8ff | 405 | |
bogdanm | 0:9b334a45a8ff | 406 | /** |
bogdanm | 0:9b334a45a8ff | 407 | * @} |
bogdanm | 0:9b334a45a8ff | 408 | */ |
bogdanm | 0:9b334a45a8ff | 409 | |
bogdanm | 0:9b334a45a8ff | 410 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 411 | } |
bogdanm | 0:9b334a45a8ff | 412 | #endif |
bogdanm | 0:9b334a45a8ff | 413 | |
bogdanm | 0:9b334a45a8ff | 414 | #endif /* __STM32L0xx_HAL_CORTEX_H */ |
bogdanm | 0:9b334a45a8ff | 415 | |
bogdanm | 0:9b334a45a8ff | 416 | |
bogdanm | 0:9b334a45a8ff | 417 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
bogdanm | 0:9b334a45a8ff | 418 |