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fix LPC812 PWM

Dependents:   IR_LED_Send

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
83:a036322b8637 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_tim_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief TIM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Timer extension peripheral:
bogdanm 0:9b334a45a8ff 10 * + Time Hall Sensor Interface Initialization
bogdanm 0:9b334a45a8ff 11 * + Time Hall Sensor Interface Start
bogdanm 0:9b334a45a8ff 12 * + Time Complementary signal bread and dead time configuration
bogdanm 0:9b334a45a8ff 13 * + Time Master and Slave synchronization configuration
bogdanm 0:9b334a45a8ff 14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
bogdanm 0:9b334a45a8ff 15 * + Time OCRef clear configuration
bogdanm 0:9b334a45a8ff 16 * + Timer remapping capabilities configuration
bogdanm 0:9b334a45a8ff 17 @verbatim
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 ##### TIMER Extended features #####
bogdanm 0:9b334a45a8ff 20 ==============================================================================
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 The Timer Extension features include:
bogdanm 0:9b334a45a8ff 23 (#) Complementary outputs with programmable dead-time for :
bogdanm 0:9b334a45a8ff 24 (++) Input Capture
bogdanm 0:9b334a45a8ff 25 (++) Output Compare
bogdanm 0:9b334a45a8ff 26 (++) PWM generation (Edge and Center-aligned Mode)
bogdanm 0:9b334a45a8ff 27 (++) One-pulse mode output
bogdanm 0:9b334a45a8ff 28 (#) Synchronization circuit to control the timer with external signals and to
bogdanm 0:9b334a45a8ff 29 interconnect several timers together.
bogdanm 0:9b334a45a8ff 30 (#) Break input to put the timer output signals in reset state or in a known state.
bogdanm 0:9b334a45a8ff 31 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
bogdanm 0:9b334a45a8ff 32 positioning purposes
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 35 ==============================================================================
bogdanm 0:9b334a45a8ff 36 [..]
bogdanm 0:9b334a45a8ff 37 (#) Initialize the TIM low level resources by implementing the following functions
bogdanm 0:9b334a45a8ff 38 depending from feature used :
bogdanm 0:9b334a45a8ff 39 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
bogdanm 0:9b334a45a8ff 40 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
bogdanm 0:9b334a45a8ff 41 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm 0:9b334a45a8ff 42 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 (#) Initialize the TIM low level resources :
bogdanm 0:9b334a45a8ff 45 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 46 (##) TIM pins configuration
bogdanm 0:9b334a45a8ff 47 (+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm 0:9b334a45a8ff 48 __GPIOx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 49 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 (#) The external Clock can be configured, if needed (the default clock is the
bogdanm 0:9b334a45a8ff 52 internal clock from the APBx), using the following function:
bogdanm 0:9b334a45a8ff 53 HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm 0:9b334a45a8ff 54 any start function.
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 (#) Configure the TIM in the desired functioning mode using one of the
bogdanm 0:9b334a45a8ff 57 initialization function of this driver:
bogdanm 0:9b334a45a8ff 58 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
bogdanm 0:9b334a45a8ff 59 Timer Hall Sensor Interface and the commutation event with the corresponding
bogdanm 0:9b334a45a8ff 60 Interrupt and DMA request if needed (Note that One Timer is used to interface
bogdanm 0:9b334a45a8ff 61 with the Hall sensor Interface and another Timer should be used to use
bogdanm 0:9b334a45a8ff 62 the commutation event).
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 (#) Activate the TIM peripheral using one of the start functions:
bogdanm 0:9b334a45a8ff 65 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
bogdanm 0:9b334a45a8ff 66 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
bogdanm 0:9b334a45a8ff 67 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
bogdanm 0:9b334a45a8ff 68 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 @endverbatim
bogdanm 0:9b334a45a8ff 72 ******************************************************************************
bogdanm 0:9b334a45a8ff 73 * @attention
bogdanm 0:9b334a45a8ff 74 *
bogdanm 0:9b334a45a8ff 75 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 76 *
bogdanm 0:9b334a45a8ff 77 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 78 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 79 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 80 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 82 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 83 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 85 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 86 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 87 *
bogdanm 0:9b334a45a8ff 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 98 *
bogdanm 0:9b334a45a8ff 99 ******************************************************************************
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 106 * @{
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /** @defgroup TIMEx TIMEx
bogdanm 0:9b334a45a8ff 110 * @brief TIM Extended HAL module driver
bogdanm 0:9b334a45a8ff 111 * @{
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 #ifdef HAL_TIM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 117 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 #define BDTR_BKF_SHIFT (16)
bogdanm 0:9b334a45a8ff 119 #define BDTR_BK2F_SHIFT (20)
bogdanm 0:9b334a45a8ff 120 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 123 /** @addtogroup TIMEx_Private_Functions
bogdanm 0:9b334a45a8ff 124 * @{
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
bogdanm 0:9b334a45a8ff 127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 129 /**
bogdanm 0:9b334a45a8ff 130 * @}
bogdanm 0:9b334a45a8ff 131 */
bogdanm 0:9b334a45a8ff 132 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
bogdanm 0:9b334a45a8ff 135 * @{
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
bogdanm 0:9b334a45a8ff 139 * @brief Timer Hall Sensor functions
bogdanm 0:9b334a45a8ff 140 *
bogdanm 0:9b334a45a8ff 141 @verbatim
bogdanm 0:9b334a45a8ff 142 ==============================================================================
bogdanm 0:9b334a45a8ff 143 ##### Timer Hall Sensor functions #####
bogdanm 0:9b334a45a8ff 144 ==============================================================================
bogdanm 0:9b334a45a8ff 145 [..]
bogdanm 0:9b334a45a8ff 146 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 147 (+) Initialize and configure TIM HAL Sensor.
bogdanm 0:9b334a45a8ff 148 (+) De-initialize TIM HAL Sensor.
bogdanm 0:9b334a45a8ff 149 (+) Start the Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 150 (+) Stop the Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 151 (+) Start the Hall Sensor Interface and enable interrupts.
bogdanm 0:9b334a45a8ff 152 (+) Stop the Hall Sensor Interface and disable interrupts.
bogdanm 0:9b334a45a8ff 153 (+) Start the Hall Sensor Interface and enable DMA transfers.
bogdanm 0:9b334a45a8ff 154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 @endverbatim
bogdanm 0:9b334a45a8ff 157 * @{
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159 /**
bogdanm 0:9b334a45a8ff 160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
bogdanm 0:9b334a45a8ff 161 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 162 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 163 * @param sConfig: TIM Hall Sensor configuration structure
bogdanm 0:9b334a45a8ff 164 * @retval HAL status
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 TIM_OC_InitTypeDef OC_Config;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 171 if(htim == NULL)
bogdanm 0:9b334a45a8ff 172 {
bogdanm 0:9b334a45a8ff 173 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 174 }
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 177 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 178 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 179 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm 0:9b334a45a8ff 180 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm 0:9b334a45a8ff 181 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 184 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 187 HAL_TIMEx_HallSensor_MspInit(htim);
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* Configure the Time base in the Encoder Mode */
bogdanm 0:9b334a45a8ff 190 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
bogdanm 0:9b334a45a8ff 193 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* Reset the IC1PSC Bits */
bogdanm 0:9b334a45a8ff 196 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm 0:9b334a45a8ff 197 /* Set the IC1PSC value */
bogdanm 0:9b334a45a8ff 198 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Enable the Hall sensor interface (XOR function of the three inputs) */
bogdanm 0:9b334a45a8ff 201 htim->Instance->CR2 |= TIM_CR2_TI1S;
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
bogdanm 0:9b334a45a8ff 204 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 205 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
bogdanm 0:9b334a45a8ff 208 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 209 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
bogdanm 0:9b334a45a8ff 212 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
bogdanm 0:9b334a45a8ff 213 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
bogdanm 0:9b334a45a8ff 214 OC_Config.OCMode = TIM_OCMODE_PWM2;
bogdanm 0:9b334a45a8ff 215 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
bogdanm 0:9b334a45a8ff 216 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
bogdanm 0:9b334a45a8ff 217 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
bogdanm 0:9b334a45a8ff 218 OC_Config.Pulse = sConfig->Commutation_Delay;
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
bogdanm 0:9b334a45a8ff 223 register to 101 */
bogdanm 0:9b334a45a8ff 224 htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm 0:9b334a45a8ff 225 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 228 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 return HAL_OK;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /**
bogdanm 0:9b334a45a8ff 234 * @brief DeInitializes the TIM Hall Sensor interface
bogdanm 0:9b334a45a8ff 235 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 236 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 237 * @retval HAL status
bogdanm 0:9b334a45a8ff 238 */
bogdanm 0:9b334a45a8ff 239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 240 {
bogdanm 0:9b334a45a8ff 241 /* Check the parameters */
bogdanm 0:9b334a45a8ff 242 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 247 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 250 HAL_TIMEx_HallSensor_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /* Change TIM state */
bogdanm 0:9b334a45a8ff 253 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /* Release Lock */
bogdanm 0:9b334a45a8ff 256 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 return HAL_OK;
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 /**
bogdanm 0:9b334a45a8ff 262 * @brief Initializes the TIM Hall Sensor MSP.
bogdanm 0:9b334a45a8ff 263 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 264 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 265 * @retval None
bogdanm 0:9b334a45a8ff 266 */
bogdanm 0:9b334a45a8ff 267 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 268 {
mbed_official 83:a036322b8637 269 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 270 UNUSED(htim);
mbed_official 83:a036322b8637 271
bogdanm 0:9b334a45a8ff 272 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 273 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /**
bogdanm 0:9b334a45a8ff 278 * @brief DeInitializes TIM Hall Sensor MSP.
bogdanm 0:9b334a45a8ff 279 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 280 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 281 * @retval None
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 284 {
mbed_official 83:a036322b8637 285 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 286 UNUSED(htim);
mbed_official 83:a036322b8637 287
bogdanm 0:9b334a45a8ff 288 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 289 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291 }
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /**
bogdanm 0:9b334a45a8ff 294 * @brief Starts the TIM Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 295 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 296 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 297 * @retval HAL status
bogdanm 0:9b334a45a8ff 298 */
bogdanm 0:9b334a45a8ff 299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 300 {
bogdanm 0:9b334a45a8ff 301 /* Check the parameters */
bogdanm 0:9b334a45a8ff 302 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 305 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 309 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Return function status */
bogdanm 0:9b334a45a8ff 312 return HAL_OK;
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /**
bogdanm 0:9b334a45a8ff 316 * @brief Stops the TIM Hall sensor Interface.
bogdanm 0:9b334a45a8ff 317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 318 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 319 * @retval HAL status
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 /* Check the parameters */
bogdanm 0:9b334a45a8ff 324 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Disable the Input Capture channels 1, 2 and 3
bogdanm 0:9b334a45a8ff 327 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 328 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 331 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /* Return function status */
bogdanm 0:9b334a45a8ff 334 return HAL_OK;
bogdanm 0:9b334a45a8ff 335 }
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /**
bogdanm 0:9b334a45a8ff 338 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 339 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 340 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 341 * @retval HAL status
bogdanm 0:9b334a45a8ff 342 */
bogdanm 0:9b334a45a8ff 343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 344 {
bogdanm 0:9b334a45a8ff 345 /* Check the parameters */
bogdanm 0:9b334a45a8ff 346 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /* Enable the capture compare Interrupts 1 event */
bogdanm 0:9b334a45a8ff 349 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 352 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 353 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 356 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Return function status */
bogdanm 0:9b334a45a8ff 359 return HAL_OK;
bogdanm 0:9b334a45a8ff 360 }
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /**
bogdanm 0:9b334a45a8ff 363 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 364 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 365 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 366 * @retval HAL status
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 /* Check the parameters */
bogdanm 0:9b334a45a8ff 371 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Disable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 374 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 375 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /* Disable the capture compare Interrupts event */
bogdanm 0:9b334a45a8ff 378 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 381 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Return function status */
bogdanm 0:9b334a45a8ff 384 return HAL_OK;
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /**
bogdanm 0:9b334a45a8ff 388 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
bogdanm 0:9b334a45a8ff 389 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 390 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 391 * @param pData: The destination Buffer address.
bogdanm 0:9b334a45a8ff 392 * @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm 0:9b334a45a8ff 393 * @retval HAL status
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 396 {
bogdanm 0:9b334a45a8ff 397 /* Check the parameters */
bogdanm 0:9b334a45a8ff 398 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 401 {
bogdanm 0:9b334a45a8ff 402 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 405 {
bogdanm 0:9b334a45a8ff 406 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 else
bogdanm 0:9b334a45a8ff 411 {
bogdanm 0:9b334a45a8ff 412 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414 }
bogdanm 0:9b334a45a8ff 415 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 416 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 417 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Set the DMA Input Capture 1 Callback */
bogdanm 0:9b334a45a8ff 420 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 421 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 422 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Enable the DMA Stream for Capture 1*/
bogdanm 0:9b334a45a8ff 425 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Enable the capture compare 1 Interrupt */
bogdanm 0:9b334a45a8ff 428 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 431 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* Return function status */
bogdanm 0:9b334a45a8ff 434 return HAL_OK;
bogdanm 0:9b334a45a8ff 435 }
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /**
bogdanm 0:9b334a45a8ff 438 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
bogdanm 0:9b334a45a8ff 439 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 440 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 441 * @retval HAL status
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 444 {
bogdanm 0:9b334a45a8ff 445 /* Check the parameters */
bogdanm 0:9b334a45a8ff 446 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /* Disable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 449 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Disable the capture compare Interrupts 1 event */
bogdanm 0:9b334a45a8ff 454 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 457 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /* Return function status */
bogdanm 0:9b334a45a8ff 460 return HAL_OK;
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /**
bogdanm 0:9b334a45a8ff 464 * @}
bogdanm 0:9b334a45a8ff 465 */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
bogdanm 0:9b334a45a8ff 468 * @brief Timer Complementary Output Compare functions
bogdanm 0:9b334a45a8ff 469 *
bogdanm 0:9b334a45a8ff 470 @verbatim
bogdanm 0:9b334a45a8ff 471 ==============================================================================
bogdanm 0:9b334a45a8ff 472 ##### Timer Complementary Output Compare functions #####
bogdanm 0:9b334a45a8ff 473 ==============================================================================
bogdanm 0:9b334a45a8ff 474 [..]
bogdanm 0:9b334a45a8ff 475 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 476 (+) Start the Complementary Output Compare/PWM.
bogdanm 0:9b334a45a8ff 477 (+) Stop the Complementary Output Compare/PWM.
bogdanm 0:9b334a45a8ff 478 (+) Start the Complementary Output Compare/PWM and enable interrupts.
bogdanm 0:9b334a45a8ff 479 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
bogdanm 0:9b334a45a8ff 480 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
bogdanm 0:9b334a45a8ff 481 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 @endverbatim
bogdanm 0:9b334a45a8ff 484 * @{
bogdanm 0:9b334a45a8ff 485 */
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /**
bogdanm 0:9b334a45a8ff 488 * @brief Starts the TIM Output Compare signal generation on the complementary
bogdanm 0:9b334a45a8ff 489 * output.
bogdanm 0:9b334a45a8ff 490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 491 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 492 * @param Channel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 493 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 494 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 495 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 496 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 497 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 498 * @retval HAL status
bogdanm 0:9b334a45a8ff 499 */
bogdanm 0:9b334a45a8ff 500 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 /* Check the parameters */
bogdanm 0:9b334a45a8ff 503 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 506 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 509 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 512 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Return function status */
bogdanm 0:9b334a45a8ff 515 return HAL_OK;
bogdanm 0:9b334a45a8ff 516 }
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /**
bogdanm 0:9b334a45a8ff 519 * @brief Stops the TIM Output Compare signal generation on the complementary
bogdanm 0:9b334a45a8ff 520 * output.
bogdanm 0:9b334a45a8ff 521 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 522 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 523 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 524 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 527 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 528 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 529 * @retval HAL status
bogdanm 0:9b334a45a8ff 530 */
bogdanm 0:9b334a45a8ff 531 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 /* Check the parameters */
bogdanm 0:9b334a45a8ff 534 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 537 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 540 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 543 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Return function status */
bogdanm 0:9b334a45a8ff 546 return HAL_OK;
bogdanm 0:9b334a45a8ff 547 }
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /**
bogdanm 0:9b334a45a8ff 550 * @brief Starts the TIM Output Compare signal generation in interrupt mode
bogdanm 0:9b334a45a8ff 551 * on the complementary output.
bogdanm 0:9b334a45a8ff 552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 553 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 554 * @param Channel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 555 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 560 * @retval HAL status
bogdanm 0:9b334a45a8ff 561 */
bogdanm 0:9b334a45a8ff 562 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 563 {
bogdanm 0:9b334a45a8ff 564 /* Check the parameters */
bogdanm 0:9b334a45a8ff 565 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 switch (Channel)
bogdanm 0:9b334a45a8ff 568 {
bogdanm 0:9b334a45a8ff 569 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574 break;
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 577 {
bogdanm 0:9b334a45a8ff 578 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 580 }
bogdanm 0:9b334a45a8ff 581 break;
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 584 {
bogdanm 0:9b334a45a8ff 585 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588 break;
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 591 {
bogdanm 0:9b334a45a8ff 592 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 593 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 594 }
bogdanm 0:9b334a45a8ff 595 break;
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 default:
bogdanm 0:9b334a45a8ff 598 break;
bogdanm 0:9b334a45a8ff 599 }
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /* Enable the TIM Break interrupt */
bogdanm 0:9b334a45a8ff 602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 605 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 608 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 611 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Return function status */
bogdanm 0:9b334a45a8ff 614 return HAL_OK;
bogdanm 0:9b334a45a8ff 615 }
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /**
bogdanm 0:9b334a45a8ff 618 * @brief Stops the TIM Output Compare signal generation in interrupt mode
bogdanm 0:9b334a45a8ff 619 * on the complementary output.
bogdanm 0:9b334a45a8ff 620 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 621 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 622 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 623 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 624 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 625 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 626 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 627 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 628 * @retval HAL status
bogdanm 0:9b334a45a8ff 629 */
bogdanm 0:9b334a45a8ff 630 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /* Check the parameters */
bogdanm 0:9b334a45a8ff 635 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 switch (Channel)
bogdanm 0:9b334a45a8ff 638 {
bogdanm 0:9b334a45a8ff 639 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 640 {
bogdanm 0:9b334a45a8ff 641 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 642 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644 break;
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 649 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 650 }
bogdanm 0:9b334a45a8ff 651 break;
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 654 {
bogdanm 0:9b334a45a8ff 655 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 656 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658 break;
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 661 {
bogdanm 0:9b334a45a8ff 662 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 663 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 break;
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 default:
bogdanm 0:9b334a45a8ff 668 break;
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 672 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm 0:9b334a45a8ff 675 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 676 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 682 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 685 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 /* Return function status */
bogdanm 0:9b334a45a8ff 688 return HAL_OK;
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 /**
bogdanm 0:9b334a45a8ff 692 * @brief Starts the TIM Output Compare signal generation in DMA mode
bogdanm 0:9b334a45a8ff 693 * on the complementary output.
bogdanm 0:9b334a45a8ff 694 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 695 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 696 * @param Channel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 697 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 702 * @param pData: The source Buffer address.
bogdanm 0:9b334a45a8ff 703 * @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 704 * @retval HAL status
bogdanm 0:9b334a45a8ff 705 */
bogdanm 0:9b334a45a8ff 706 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 707 {
bogdanm 0:9b334a45a8ff 708 /* Check the parameters */
bogdanm 0:9b334a45a8ff 709 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 712 {
bogdanm 0:9b334a45a8ff 713 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 716 {
bogdanm 0:9b334a45a8ff 717 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 718 {
bogdanm 0:9b334a45a8ff 719 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 720 }
bogdanm 0:9b334a45a8ff 721 else
bogdanm 0:9b334a45a8ff 722 {
bogdanm 0:9b334a45a8ff 723 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725 }
bogdanm 0:9b334a45a8ff 726 switch (Channel)
bogdanm 0:9b334a45a8ff 727 {
bogdanm 0:9b334a45a8ff 728 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 729 {
bogdanm 0:9b334a45a8ff 730 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 731 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 732
bogdanm 0:9b334a45a8ff 733 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 734 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 737 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 741 }
bogdanm 0:9b334a45a8ff 742 break;
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 745 {
bogdanm 0:9b334a45a8ff 746 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 747 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 750 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 753 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 756 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 757 }
bogdanm 0:9b334a45a8ff 758 break;
bogdanm 0:9b334a45a8ff 759
bogdanm 0:9b334a45a8ff 760 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 761 {
bogdanm 0:9b334a45a8ff 762 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 763 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 766 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 769 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 772 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 773 }
bogdanm 0:9b334a45a8ff 774 break;
bogdanm 0:9b334a45a8ff 775
bogdanm 0:9b334a45a8ff 776 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 777 {
bogdanm 0:9b334a45a8ff 778 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 779 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 782 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 785 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 788 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 789 }
bogdanm 0:9b334a45a8ff 790 break;
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 default:
bogdanm 0:9b334a45a8ff 793 break;
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 797 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 800 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 803 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /* Return function status */
bogdanm 0:9b334a45a8ff 806 return HAL_OK;
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 /**
bogdanm 0:9b334a45a8ff 810 * @brief Stops the TIM Output Compare signal generation in DMA mode
bogdanm 0:9b334a45a8ff 811 * on the complementary output.
bogdanm 0:9b334a45a8ff 812 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 813 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 814 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 815 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 816 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 817 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 818 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 819 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 820 * @retval HAL status
bogdanm 0:9b334a45a8ff 821 */
bogdanm 0:9b334a45a8ff 822 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 823 {
bogdanm 0:9b334a45a8ff 824 /* Check the parameters */
bogdanm 0:9b334a45a8ff 825 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 switch (Channel)
bogdanm 0:9b334a45a8ff 828 {
bogdanm 0:9b334a45a8ff 829 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 830 {
bogdanm 0:9b334a45a8ff 831 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 832 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 833 }
bogdanm 0:9b334a45a8ff 834 break;
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 839 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841 break;
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 846 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 847 }
bogdanm 0:9b334a45a8ff 848 break;
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 853 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855 break;
bogdanm 0:9b334a45a8ff 856
bogdanm 0:9b334a45a8ff 857 default:
bogdanm 0:9b334a45a8ff 858 break;
bogdanm 0:9b334a45a8ff 859 }
bogdanm 0:9b334a45a8ff 860
bogdanm 0:9b334a45a8ff 861 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 862 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 865 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 868 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* Change the htim state */
bogdanm 0:9b334a45a8ff 871 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 /* Return function status */
bogdanm 0:9b334a45a8ff 874 return HAL_OK;
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 /**
bogdanm 0:9b334a45a8ff 878 * @}
bogdanm 0:9b334a45a8ff 879 */
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
bogdanm 0:9b334a45a8ff 882 * @brief Timer Complementary PWM functions
bogdanm 0:9b334a45a8ff 883 *
bogdanm 0:9b334a45a8ff 884 @verbatim
bogdanm 0:9b334a45a8ff 885 ==============================================================================
bogdanm 0:9b334a45a8ff 886 ##### Timer Complementary PWM functions #####
bogdanm 0:9b334a45a8ff 887 ==============================================================================
bogdanm 0:9b334a45a8ff 888 [..]
bogdanm 0:9b334a45a8ff 889 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 890 (+) Start the Complementary PWM.
bogdanm 0:9b334a45a8ff 891 (+) Stop the Complementary PWM.
bogdanm 0:9b334a45a8ff 892 (+) Start the Complementary PWM and enable interrupts.
bogdanm 0:9b334a45a8ff 893 (+) Stop the Complementary PWM and disable interrupts.
bogdanm 0:9b334a45a8ff 894 (+) Start the Complementary PWM and enable DMA transfers.
bogdanm 0:9b334a45a8ff 895 (+) Stop the Complementary PWM and disable DMA transfers.
bogdanm 0:9b334a45a8ff 896 (+) Start the Complementary Input Capture measurement.
bogdanm 0:9b334a45a8ff 897 (+) Stop the Complementary Input Capture.
bogdanm 0:9b334a45a8ff 898 (+) Start the Complementary Input Capture and enable interrupts.
bogdanm 0:9b334a45a8ff 899 (+) Stop the Complementary Input Capture and disable interrupts.
bogdanm 0:9b334a45a8ff 900 (+) Start the Complementary Input Capture and enable DMA transfers.
bogdanm 0:9b334a45a8ff 901 (+) Stop the Complementary Input Capture and disable DMA transfers.
bogdanm 0:9b334a45a8ff 902 (+) Start the Complementary One Pulse generation.
bogdanm 0:9b334a45a8ff 903 (+) Stop the Complementary One Pulse.
bogdanm 0:9b334a45a8ff 904 (+) Start the Complementary One Pulse and enable interrupts.
bogdanm 0:9b334a45a8ff 905 (+) Stop the Complementary One Pulse and disable interrupts.
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 @endverbatim
bogdanm 0:9b334a45a8ff 908 * @{
bogdanm 0:9b334a45a8ff 909 */
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 /**
bogdanm 0:9b334a45a8ff 912 * @brief Starts the PWM signal generation on the complementary output.
bogdanm 0:9b334a45a8ff 913 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 914 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 915 * @param Channel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 916 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 917 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 918 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 919 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 920 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 921 * @retval HAL status
bogdanm 0:9b334a45a8ff 922 */
bogdanm 0:9b334a45a8ff 923 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 924 {
bogdanm 0:9b334a45a8ff 925 /* Check the parameters */
bogdanm 0:9b334a45a8ff 926 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 929 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 930
bogdanm 0:9b334a45a8ff 931 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 932 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 933
bogdanm 0:9b334a45a8ff 934 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 935 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 936
bogdanm 0:9b334a45a8ff 937 /* Return function status */
bogdanm 0:9b334a45a8ff 938 return HAL_OK;
bogdanm 0:9b334a45a8ff 939 }
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 /**
bogdanm 0:9b334a45a8ff 942 * @brief Stops the PWM signal generation on the complementary output.
bogdanm 0:9b334a45a8ff 943 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 944 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 945 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 946 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 951 * @retval HAL status
bogdanm 0:9b334a45a8ff 952 */
bogdanm 0:9b334a45a8ff 953 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 954 {
bogdanm 0:9b334a45a8ff 955 /* Check the parameters */
bogdanm 0:9b334a45a8ff 956 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 959 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 960
bogdanm 0:9b334a45a8ff 961 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 962 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 965 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 966
bogdanm 0:9b334a45a8ff 967 /* Return function status */
bogdanm 0:9b334a45a8ff 968 return HAL_OK;
bogdanm 0:9b334a45a8ff 969 }
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 /**
bogdanm 0:9b334a45a8ff 972 * @brief Starts the PWM signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 973 * complementary output.
bogdanm 0:9b334a45a8ff 974 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 975 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 976 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 977 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 978 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 979 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 980 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 981 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 982 * @retval HAL status
bogdanm 0:9b334a45a8ff 983 */
bogdanm 0:9b334a45a8ff 984 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 985 {
bogdanm 0:9b334a45a8ff 986 /* Check the parameters */
bogdanm 0:9b334a45a8ff 987 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 988
bogdanm 0:9b334a45a8ff 989 switch (Channel)
bogdanm 0:9b334a45a8ff 990 {
bogdanm 0:9b334a45a8ff 991 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 992 {
bogdanm 0:9b334a45a8ff 993 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 995 }
bogdanm 0:9b334a45a8ff 996 break;
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1001 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1002 }
bogdanm 0:9b334a45a8ff 1003 break;
bogdanm 0:9b334a45a8ff 1004
bogdanm 0:9b334a45a8ff 1005 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1006 {
bogdanm 0:9b334a45a8ff 1007 /* Enable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1008 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1009 }
bogdanm 0:9b334a45a8ff 1010 break;
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1013 {
bogdanm 0:9b334a45a8ff 1014 /* Enable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1015 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1016 }
bogdanm 0:9b334a45a8ff 1017 break;
bogdanm 0:9b334a45a8ff 1018
bogdanm 0:9b334a45a8ff 1019 default:
bogdanm 0:9b334a45a8ff 1020 break;
bogdanm 0:9b334a45a8ff 1021 }
bogdanm 0:9b334a45a8ff 1022
bogdanm 0:9b334a45a8ff 1023 /* Enable the TIM Break interrupt */
bogdanm 0:9b334a45a8ff 1024 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1027 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 1030 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1033 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /* Return function status */
bogdanm 0:9b334a45a8ff 1036 return HAL_OK;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @brief Stops the PWM signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1041 * complementary output.
bogdanm 0:9b334a45a8ff 1042 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1043 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1044 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 1045 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1046 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1047 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1048 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1049 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1050 * @retval HAL status
bogdanm 0:9b334a45a8ff 1051 */
bogdanm 0:9b334a45a8ff 1052 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1053 {
bogdanm 0:9b334a45a8ff 1054 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1057 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1058
bogdanm 0:9b334a45a8ff 1059 switch (Channel)
bogdanm 0:9b334a45a8ff 1060 {
bogdanm 0:9b334a45a8ff 1061 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1065 }
bogdanm 0:9b334a45a8ff 1066 break;
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1069 {
bogdanm 0:9b334a45a8ff 1070 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1071 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1072 }
bogdanm 0:9b334a45a8ff 1073 break;
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1076 {
bogdanm 0:9b334a45a8ff 1077 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1078 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1079 }
bogdanm 0:9b334a45a8ff 1080 break;
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1083 {
bogdanm 0:9b334a45a8ff 1084 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1085 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1086 }
bogdanm 0:9b334a45a8ff 1087 break;
bogdanm 0:9b334a45a8ff 1088
bogdanm 0:9b334a45a8ff 1089 default:
bogdanm 0:9b334a45a8ff 1090 break;
bogdanm 0:9b334a45a8ff 1091 }
bogdanm 0:9b334a45a8ff 1092
bogdanm 0:9b334a45a8ff 1093 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1094 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096 /* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm 0:9b334a45a8ff 1097 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 1098 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
bogdanm 0:9b334a45a8ff 1099 {
bogdanm 0:9b334a45a8ff 1100 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 1101 }
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 1104 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1105
bogdanm 0:9b334a45a8ff 1106 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1107 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1108
bogdanm 0:9b334a45a8ff 1109 /* Return function status */
bogdanm 0:9b334a45a8ff 1110 return HAL_OK;
bogdanm 0:9b334a45a8ff 1111 }
bogdanm 0:9b334a45a8ff 1112
bogdanm 0:9b334a45a8ff 1113 /**
bogdanm 0:9b334a45a8ff 1114 * @brief Starts the TIM PWM signal generation in DMA mode on the
bogdanm 0:9b334a45a8ff 1115 * complementary output
bogdanm 0:9b334a45a8ff 1116 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1117 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1118 * @param Channel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 1119 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1122 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1123 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1124 * @param pData: The source Buffer address.
bogdanm 0:9b334a45a8ff 1125 * @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 1126 * @retval HAL status
bogdanm 0:9b334a45a8ff 1127 */
bogdanm 0:9b334a45a8ff 1128 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 1129 {
bogdanm 0:9b334a45a8ff 1130 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1131 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 1134 {
bogdanm 0:9b334a45a8ff 1135 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1136 }
bogdanm 0:9b334a45a8ff 1137 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 1138 {
bogdanm 0:9b334a45a8ff 1139 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 1140 {
bogdanm 0:9b334a45a8ff 1141 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1142 }
bogdanm 0:9b334a45a8ff 1143 else
bogdanm 0:9b334a45a8ff 1144 {
bogdanm 0:9b334a45a8ff 1145 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1146 }
bogdanm 0:9b334a45a8ff 1147 }
bogdanm 0:9b334a45a8ff 1148 switch (Channel)
bogdanm 0:9b334a45a8ff 1149 {
bogdanm 0:9b334a45a8ff 1150 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1151 {
bogdanm 0:9b334a45a8ff 1152 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1153 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1156 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1157
bogdanm 0:9b334a45a8ff 1158 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 1159 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 1160
bogdanm 0:9b334a45a8ff 1161 /* Enable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1163 }
bogdanm 0:9b334a45a8ff 1164 break;
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1167 {
bogdanm 0:9b334a45a8ff 1168 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1169 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1170
bogdanm 0:9b334a45a8ff 1171 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1172 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1173
bogdanm 0:9b334a45a8ff 1174 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 1175 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 1176
bogdanm 0:9b334a45a8ff 1177 /* Enable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1178 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1179 }
bogdanm 0:9b334a45a8ff 1180 break;
bogdanm 0:9b334a45a8ff 1181
bogdanm 0:9b334a45a8ff 1182 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1183 {
bogdanm 0:9b334a45a8ff 1184 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1185 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1188 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1189
bogdanm 0:9b334a45a8ff 1190 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 1191 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 1192
bogdanm 0:9b334a45a8ff 1193 /* Enable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1194 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1195 }
bogdanm 0:9b334a45a8ff 1196 break;
bogdanm 0:9b334a45a8ff 1197
bogdanm 0:9b334a45a8ff 1198 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1199 {
bogdanm 0:9b334a45a8ff 1200 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1201 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1204 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1205
bogdanm 0:9b334a45a8ff 1206 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 1207 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 1208
bogdanm 0:9b334a45a8ff 1209 /* Enable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1210 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1211 }
bogdanm 0:9b334a45a8ff 1212 break;
bogdanm 0:9b334a45a8ff 1213
bogdanm 0:9b334a45a8ff 1214 default:
bogdanm 0:9b334a45a8ff 1215 break;
bogdanm 0:9b334a45a8ff 1216 }
bogdanm 0:9b334a45a8ff 1217
bogdanm 0:9b334a45a8ff 1218 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1219 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 1222 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1223
bogdanm 0:9b334a45a8ff 1224 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1225 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1226
bogdanm 0:9b334a45a8ff 1227 /* Return function status */
bogdanm 0:9b334a45a8ff 1228 return HAL_OK;
bogdanm 0:9b334a45a8ff 1229 }
bogdanm 0:9b334a45a8ff 1230
bogdanm 0:9b334a45a8ff 1231 /**
bogdanm 0:9b334a45a8ff 1232 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
bogdanm 0:9b334a45a8ff 1233 * output
bogdanm 0:9b334a45a8ff 1234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1235 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1236 * @param Channel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 1237 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1240 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1241 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1242 * @retval HAL status
bogdanm 0:9b334a45a8ff 1243 */
bogdanm 0:9b334a45a8ff 1244 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1245 {
bogdanm 0:9b334a45a8ff 1246 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1247 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1248
bogdanm 0:9b334a45a8ff 1249 switch (Channel)
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1252 {
bogdanm 0:9b334a45a8ff 1253 /* Disable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1254 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1255 }
bogdanm 0:9b334a45a8ff 1256 break;
bogdanm 0:9b334a45a8ff 1257
bogdanm 0:9b334a45a8ff 1258 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1259 {
bogdanm 0:9b334a45a8ff 1260 /* Disable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1261 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1262 }
bogdanm 0:9b334a45a8ff 1263 break;
bogdanm 0:9b334a45a8ff 1264
bogdanm 0:9b334a45a8ff 1265 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1266 {
bogdanm 0:9b334a45a8ff 1267 /* Disable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1268 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1269 }
bogdanm 0:9b334a45a8ff 1270 break;
bogdanm 0:9b334a45a8ff 1271
bogdanm 0:9b334a45a8ff 1272 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1273 {
bogdanm 0:9b334a45a8ff 1274 /* Disable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1275 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1276 }
bogdanm 0:9b334a45a8ff 1277 break;
bogdanm 0:9b334a45a8ff 1278
bogdanm 0:9b334a45a8ff 1279 default:
bogdanm 0:9b334a45a8ff 1280 break;
bogdanm 0:9b334a45a8ff 1281 }
bogdanm 0:9b334a45a8ff 1282
bogdanm 0:9b334a45a8ff 1283 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1284 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1285
bogdanm 0:9b334a45a8ff 1286 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 1287 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1290 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1291
bogdanm 0:9b334a45a8ff 1292 /* Change the htim state */
bogdanm 0:9b334a45a8ff 1293 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1294
bogdanm 0:9b334a45a8ff 1295 /* Return function status */
bogdanm 0:9b334a45a8ff 1296 return HAL_OK;
bogdanm 0:9b334a45a8ff 1297 }
bogdanm 0:9b334a45a8ff 1298
bogdanm 0:9b334a45a8ff 1299 /**
bogdanm 0:9b334a45a8ff 1300 * @}
bogdanm 0:9b334a45a8ff 1301 */
bogdanm 0:9b334a45a8ff 1302
bogdanm 0:9b334a45a8ff 1303 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
bogdanm 0:9b334a45a8ff 1304 * @brief Timer Complementary One Pulse functions
bogdanm 0:9b334a45a8ff 1305 *
bogdanm 0:9b334a45a8ff 1306 @verbatim
bogdanm 0:9b334a45a8ff 1307 ==============================================================================
bogdanm 0:9b334a45a8ff 1308 ##### Timer Complementary One Pulse functions #####
bogdanm 0:9b334a45a8ff 1309 ==============================================================================
bogdanm 0:9b334a45a8ff 1310 [..]
bogdanm 0:9b334a45a8ff 1311 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1312 (+) Start the Complementary One Pulse generation.
bogdanm 0:9b334a45a8ff 1313 (+) Stop the Complementary One Pulse.
bogdanm 0:9b334a45a8ff 1314 (+) Start the Complementary One Pulse and enable interrupts.
bogdanm 0:9b334a45a8ff 1315 (+) Stop the Complementary One Pulse and disable interrupts.
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 @endverbatim
bogdanm 0:9b334a45a8ff 1318 * @{
bogdanm 0:9b334a45a8ff 1319 */
bogdanm 0:9b334a45a8ff 1320
bogdanm 0:9b334a45a8ff 1321 /**
bogdanm 0:9b334a45a8ff 1322 * @brief Starts the TIM One Pulse signal generation on the complemetary
bogdanm 0:9b334a45a8ff 1323 * output.
bogdanm 0:9b334a45a8ff 1324 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1325 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1326 * @param OutputChannel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 1327 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1328 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1329 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1330 * @retval HAL status
bogdanm 0:9b334a45a8ff 1331 */
bogdanm 0:9b334a45a8ff 1332 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1333 {
bogdanm 0:9b334a45a8ff 1334 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1335 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1336
bogdanm 0:9b334a45a8ff 1337 /* Enable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1338 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1339
bogdanm 0:9b334a45a8ff 1340 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 1341 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 /* Return function status */
bogdanm 0:9b334a45a8ff 1344 return HAL_OK;
bogdanm 0:9b334a45a8ff 1345 }
bogdanm 0:9b334a45a8ff 1346
bogdanm 0:9b334a45a8ff 1347 /**
bogdanm 0:9b334a45a8ff 1348 * @brief Stops the TIM One Pulse signal generation on the complementary
bogdanm 0:9b334a45a8ff 1349 * output.
bogdanm 0:9b334a45a8ff 1350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1351 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1352 * @param OutputChannel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 1353 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1354 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1355 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1356 * @retval HAL status
bogdanm 0:9b334a45a8ff 1357 */
bogdanm 0:9b334a45a8ff 1358 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1359 {
bogdanm 0:9b334a45a8ff 1360
bogdanm 0:9b334a45a8ff 1361 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1362 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1363
bogdanm 0:9b334a45a8ff 1364 /* Disable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1365 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1366
bogdanm 0:9b334a45a8ff 1367 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 1368 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1369
bogdanm 0:9b334a45a8ff 1370 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1371 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1372
bogdanm 0:9b334a45a8ff 1373 /* Return function status */
bogdanm 0:9b334a45a8ff 1374 return HAL_OK;
bogdanm 0:9b334a45a8ff 1375 }
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377 /**
bogdanm 0:9b334a45a8ff 1378 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1379 * complementary channel.
bogdanm 0:9b334a45a8ff 1380 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1381 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1382 * @param OutputChannel: TIM Channel to be enabled.
bogdanm 0:9b334a45a8ff 1383 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1384 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1385 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1386 * @retval HAL status
bogdanm 0:9b334a45a8ff 1387 */
bogdanm 0:9b334a45a8ff 1388 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1389 {
bogdanm 0:9b334a45a8ff 1390 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1391 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1392
bogdanm 0:9b334a45a8ff 1393 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1394 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1395
bogdanm 0:9b334a45a8ff 1396 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1397 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1398
bogdanm 0:9b334a45a8ff 1399 /* Enable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1400 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1401
bogdanm 0:9b334a45a8ff 1402 /* Enable the Main Output */
bogdanm 0:9b334a45a8ff 1403 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1404
bogdanm 0:9b334a45a8ff 1405 /* Return function status */
bogdanm 0:9b334a45a8ff 1406 return HAL_OK;
bogdanm 0:9b334a45a8ff 1407 }
bogdanm 0:9b334a45a8ff 1408
bogdanm 0:9b334a45a8ff 1409 /**
bogdanm 0:9b334a45a8ff 1410 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1411 * complementary channel.
bogdanm 0:9b334a45a8ff 1412 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1413 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1414 * @param OutputChannel: TIM Channel to be disabled.
bogdanm 0:9b334a45a8ff 1415 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1416 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1417 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1418 * @retval HAL status
bogdanm 0:9b334a45a8ff 1419 */
bogdanm 0:9b334a45a8ff 1420 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1421 {
bogdanm 0:9b334a45a8ff 1422 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1423 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1426 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1427
bogdanm 0:9b334a45a8ff 1428 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1429 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1430
bogdanm 0:9b334a45a8ff 1431 /* Disable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1432 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1433
bogdanm 0:9b334a45a8ff 1434 /* Disable the Main Output */
bogdanm 0:9b334a45a8ff 1435 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1436
bogdanm 0:9b334a45a8ff 1437 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1438 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1439
bogdanm 0:9b334a45a8ff 1440 /* Return function status */
bogdanm 0:9b334a45a8ff 1441 return HAL_OK;
bogdanm 0:9b334a45a8ff 1442 }
bogdanm 0:9b334a45a8ff 1443
bogdanm 0:9b334a45a8ff 1444 /**
bogdanm 0:9b334a45a8ff 1445 * @}
bogdanm 0:9b334a45a8ff 1446 */
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 1449 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 1450 *
bogdanm 0:9b334a45a8ff 1451 @verbatim
bogdanm 0:9b334a45a8ff 1452 ==============================================================================
bogdanm 0:9b334a45a8ff 1453 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 1454 ==============================================================================
bogdanm 0:9b334a45a8ff 1455 [..]
bogdanm 0:9b334a45a8ff 1456 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1457 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm 0:9b334a45a8ff 1458 (+) Configure External Clock source.
bogdanm 0:9b334a45a8ff 1459 (+) Configure Complementary channels, break features and dead time.
bogdanm 0:9b334a45a8ff 1460 (+) Configure Master and the Slave synchronization.
bogdanm 0:9b334a45a8ff 1461 (+) Configure the commutation event in case of use of the Hall sensor interface.
bogdanm 0:9b334a45a8ff 1462 (+) Configure the DMA Burst Mode.
bogdanm 0:9b334a45a8ff 1463
bogdanm 0:9b334a45a8ff 1464 @endverbatim
bogdanm 0:9b334a45a8ff 1465 * @{
bogdanm 0:9b334a45a8ff 1466 */
bogdanm 0:9b334a45a8ff 1467 /**
bogdanm 0:9b334a45a8ff 1468 * @brief Configure the TIM commutation event sequence.
bogdanm 0:9b334a45a8ff 1469 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1470 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1471 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1472 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1473 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1474 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1475 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1476 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1477 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
bogdanm 0:9b334a45a8ff 1478 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1479 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1480 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1481 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1482 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1483 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1484 * @param CommutationSource: the Commutation Event source.
bogdanm 0:9b334a45a8ff 1485 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1486 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1487 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1488 * @retval HAL status
bogdanm 0:9b334a45a8ff 1489 */
bogdanm 0:9b334a45a8ff 1490 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1491 {
bogdanm 0:9b334a45a8ff 1492 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1493 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1494 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1495
bogdanm 0:9b334a45a8ff 1496 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1497
bogdanm 0:9b334a45a8ff 1498 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1499 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1500 {
bogdanm 0:9b334a45a8ff 1501 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1502 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1503 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1504 }
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1507 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1508 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1509 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1510 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1511
bogdanm 0:9b334a45a8ff 1512 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1513
bogdanm 0:9b334a45a8ff 1514 return HAL_OK;
bogdanm 0:9b334a45a8ff 1515 }
bogdanm 0:9b334a45a8ff 1516
bogdanm 0:9b334a45a8ff 1517 /**
bogdanm 0:9b334a45a8ff 1518 * @brief Configure the TIM commutation event sequence with interrupt.
bogdanm 0:9b334a45a8ff 1519 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1520 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1521 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1522 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1523 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1524 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1526 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1527 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
bogdanm 0:9b334a45a8ff 1528 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1529 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1530 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1531 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1532 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1533 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1534 * @param CommutationSource: the Commutation Event source.
bogdanm 0:9b334a45a8ff 1535 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1536 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1537 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1538 * @retval HAL status
bogdanm 0:9b334a45a8ff 1539 */
bogdanm 0:9b334a45a8ff 1540 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1541 {
bogdanm 0:9b334a45a8ff 1542 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1543 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1544 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1545
bogdanm 0:9b334a45a8ff 1546 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1547
bogdanm 0:9b334a45a8ff 1548 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1549 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1550 {
bogdanm 0:9b334a45a8ff 1551 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1552 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1553 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1554 }
bogdanm 0:9b334a45a8ff 1555
bogdanm 0:9b334a45a8ff 1556 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1557 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1558 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1559 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1560 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1561
bogdanm 0:9b334a45a8ff 1562 /* Enable the Commutation Interrupt Request */
bogdanm 0:9b334a45a8ff 1563 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
bogdanm 0:9b334a45a8ff 1564
bogdanm 0:9b334a45a8ff 1565 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1566
bogdanm 0:9b334a45a8ff 1567 return HAL_OK;
bogdanm 0:9b334a45a8ff 1568 }
bogdanm 0:9b334a45a8ff 1569
bogdanm 0:9b334a45a8ff 1570 /**
bogdanm 0:9b334a45a8ff 1571 * @brief Configure the TIM commutation event sequence with DMA.
bogdanm 0:9b334a45a8ff 1572 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1573 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1574 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1575 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1576 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1577 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1578 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
bogdanm 0:9b334a45a8ff 1579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1580 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 1581 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
bogdanm 0:9b334a45a8ff 1582 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1583 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1584 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1585 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1586 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1587 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1588 * @param CommutationSource: the Commutation Event source.
bogdanm 0:9b334a45a8ff 1589 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1590 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1591 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1592 * @retval HAL status
bogdanm 0:9b334a45a8ff 1593 */
bogdanm 0:9b334a45a8ff 1594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1595 {
bogdanm 0:9b334a45a8ff 1596 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1597 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1598 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1599
bogdanm 0:9b334a45a8ff 1600 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1601
bogdanm 0:9b334a45a8ff 1602 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1603 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1604 {
bogdanm 0:9b334a45a8ff 1605 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1606 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1607 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1608 }
bogdanm 0:9b334a45a8ff 1609
bogdanm 0:9b334a45a8ff 1610 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1611 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1612 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1613 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1614 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1615
bogdanm 0:9b334a45a8ff 1616 /* Enable the Commutation DMA Request */
bogdanm 0:9b334a45a8ff 1617 /* Set the DMA Commutation Callback */
bogdanm 0:9b334a45a8ff 1618 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm 0:9b334a45a8ff 1619 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1620 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
bogdanm 0:9b334a45a8ff 1621
bogdanm 0:9b334a45a8ff 1622 /* Enable the Commutation DMA Request */
bogdanm 0:9b334a45a8ff 1623 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
bogdanm 0:9b334a45a8ff 1624
bogdanm 0:9b334a45a8ff 1625 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1626
bogdanm 0:9b334a45a8ff 1627 return HAL_OK;
bogdanm 0:9b334a45a8ff 1628 }
bogdanm 0:9b334a45a8ff 1629
bogdanm 0:9b334a45a8ff 1630 /**
bogdanm 0:9b334a45a8ff 1631 * @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm 0:9b334a45a8ff 1632 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 1633 * @param htim: TIM Output Compare handle
bogdanm 0:9b334a45a8ff 1634 * @param sConfig: TIM Output Compare configuration structure
bogdanm 0:9b334a45a8ff 1635 * @param Channel : TIM Channels to configure
bogdanm 0:9b334a45a8ff 1636 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1641 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm 0:9b334a45a8ff 1642 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm 0:9b334a45a8ff 1643 * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
bogdanm 0:9b334a45a8ff 1644 * @retval HAL status
bogdanm 0:9b334a45a8ff 1645 */
bogdanm 0:9b334a45a8ff 1646 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1647 {
bogdanm 0:9b334a45a8ff 1648 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1649 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 1650 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 1651 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 1652
bogdanm 0:9b334a45a8ff 1653 /* Check input state */
bogdanm 0:9b334a45a8ff 1654 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1655
bogdanm 0:9b334a45a8ff 1656 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1657
bogdanm 0:9b334a45a8ff 1658 switch (Channel)
bogdanm 0:9b334a45a8ff 1659 {
bogdanm 0:9b334a45a8ff 1660 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1661 {
bogdanm 0:9b334a45a8ff 1662 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1663 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1664
bogdanm 0:9b334a45a8ff 1665 /* Configure the TIM Channel 1 in Output Compare */
bogdanm 0:9b334a45a8ff 1666 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1667 }
bogdanm 0:9b334a45a8ff 1668 break;
bogdanm 0:9b334a45a8ff 1669
bogdanm 0:9b334a45a8ff 1670 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1671 {
bogdanm 0:9b334a45a8ff 1672 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1673 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1674
bogdanm 0:9b334a45a8ff 1675 /* Configure the TIM Channel 2 in Output Compare */
bogdanm 0:9b334a45a8ff 1676 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1677 }
bogdanm 0:9b334a45a8ff 1678 break;
bogdanm 0:9b334a45a8ff 1679
bogdanm 0:9b334a45a8ff 1680 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1681 {
bogdanm 0:9b334a45a8ff 1682 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1683 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1684
bogdanm 0:9b334a45a8ff 1685 /* Configure the TIM Channel 3 in Output Compare */
bogdanm 0:9b334a45a8ff 1686 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1687 }
bogdanm 0:9b334a45a8ff 1688 break;
bogdanm 0:9b334a45a8ff 1689
bogdanm 0:9b334a45a8ff 1690 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1691 {
bogdanm 0:9b334a45a8ff 1692 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1693 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1694
bogdanm 0:9b334a45a8ff 1695 /* Configure the TIM Channel 4 in Output Compare */
bogdanm 0:9b334a45a8ff 1696 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1697 }
bogdanm 0:9b334a45a8ff 1698 break;
bogdanm 0:9b334a45a8ff 1699
bogdanm 0:9b334a45a8ff 1700 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 1701 {
bogdanm 0:9b334a45a8ff 1702 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1703 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1704
bogdanm 0:9b334a45a8ff 1705 /* Configure the TIM Channel 5 in Output Compare */
bogdanm 0:9b334a45a8ff 1706 TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1707 }
bogdanm 0:9b334a45a8ff 1708 break;
bogdanm 0:9b334a45a8ff 1709
bogdanm 0:9b334a45a8ff 1710 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 1711 {
bogdanm 0:9b334a45a8ff 1712 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1713 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1714
bogdanm 0:9b334a45a8ff 1715 /* Configure the TIM Channel 6 in Output Compare */
bogdanm 0:9b334a45a8ff 1716 TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1717 }
bogdanm 0:9b334a45a8ff 1718 break;
bogdanm 0:9b334a45a8ff 1719
bogdanm 0:9b334a45a8ff 1720 default:
bogdanm 0:9b334a45a8ff 1721 break;
bogdanm 0:9b334a45a8ff 1722 }
bogdanm 0:9b334a45a8ff 1723
bogdanm 0:9b334a45a8ff 1724 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1725
bogdanm 0:9b334a45a8ff 1726 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1727
bogdanm 0:9b334a45a8ff 1728 return HAL_OK;
bogdanm 0:9b334a45a8ff 1729 }
bogdanm 0:9b334a45a8ff 1730
bogdanm 0:9b334a45a8ff 1731 /**
bogdanm 0:9b334a45a8ff 1732 * @brief Initializes the TIM PWM channels according to the specified
bogdanm 0:9b334a45a8ff 1733 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 1734 * @param htim: TIM PWM handle
bogdanm 0:9b334a45a8ff 1735 * @param sConfig: TIM PWM configuration structure
bogdanm 0:9b334a45a8ff 1736 * @param Channel : TIM Channels to be configured
bogdanm 0:9b334a45a8ff 1737 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1740 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1741 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1742 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm 0:9b334a45a8ff 1743 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm 0:9b334a45a8ff 1744 * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
bogdanm 0:9b334a45a8ff 1745 * @retval HAL status
bogdanm 0:9b334a45a8ff 1746 */
bogdanm 0:9b334a45a8ff 1747 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 1748 TIM_OC_InitTypeDef* sConfig,
bogdanm 0:9b334a45a8ff 1749 uint32_t Channel)
bogdanm 0:9b334a45a8ff 1750 {
bogdanm 0:9b334a45a8ff 1751 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1752 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 1753 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 1754 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 1755 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm 0:9b334a45a8ff 1756
bogdanm 0:9b334a45a8ff 1757 /* Check input state */
bogdanm 0:9b334a45a8ff 1758 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1759
bogdanm 0:9b334a45a8ff 1760 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1761
bogdanm 0:9b334a45a8ff 1762 switch (Channel)
bogdanm 0:9b334a45a8ff 1763 {
bogdanm 0:9b334a45a8ff 1764 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1765 {
bogdanm 0:9b334a45a8ff 1766 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1767 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1768
bogdanm 0:9b334a45a8ff 1769 /* Configure the Channel 1 in PWM mode */
bogdanm 0:9b334a45a8ff 1770 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1771
bogdanm 0:9b334a45a8ff 1772 /* Set the Preload enable bit for channel1 */
bogdanm 0:9b334a45a8ff 1773 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
bogdanm 0:9b334a45a8ff 1774
bogdanm 0:9b334a45a8ff 1775 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1776 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm 0:9b334a45a8ff 1777 htim->Instance->CCMR1 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1778 }
bogdanm 0:9b334a45a8ff 1779 break;
bogdanm 0:9b334a45a8ff 1780
bogdanm 0:9b334a45a8ff 1781 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1782 {
bogdanm 0:9b334a45a8ff 1783 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1784 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1785
bogdanm 0:9b334a45a8ff 1786 /* Configure the Channel 2 in PWM mode */
bogdanm 0:9b334a45a8ff 1787 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1788
bogdanm 0:9b334a45a8ff 1789 /* Set the Preload enable bit for channel2 */
bogdanm 0:9b334a45a8ff 1790 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
bogdanm 0:9b334a45a8ff 1791
bogdanm 0:9b334a45a8ff 1792 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1793 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm 0:9b334a45a8ff 1794 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1795 }
bogdanm 0:9b334a45a8ff 1796 break;
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1799 {
bogdanm 0:9b334a45a8ff 1800 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1801 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1802
bogdanm 0:9b334a45a8ff 1803 /* Configure the Channel 3 in PWM mode */
bogdanm 0:9b334a45a8ff 1804 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1805
bogdanm 0:9b334a45a8ff 1806 /* Set the Preload enable bit for channel3 */
bogdanm 0:9b334a45a8ff 1807 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
bogdanm 0:9b334a45a8ff 1808
bogdanm 0:9b334a45a8ff 1809 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1810 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm 0:9b334a45a8ff 1811 htim->Instance->CCMR2 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1812 }
bogdanm 0:9b334a45a8ff 1813 break;
bogdanm 0:9b334a45a8ff 1814
bogdanm 0:9b334a45a8ff 1815 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1816 {
bogdanm 0:9b334a45a8ff 1817 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1818 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1819
bogdanm 0:9b334a45a8ff 1820 /* Configure the Channel 4 in PWM mode */
bogdanm 0:9b334a45a8ff 1821 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1822
bogdanm 0:9b334a45a8ff 1823 /* Set the Preload enable bit for channel4 */
bogdanm 0:9b334a45a8ff 1824 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
bogdanm 0:9b334a45a8ff 1825
bogdanm 0:9b334a45a8ff 1826 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1827 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm 0:9b334a45a8ff 1828 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1829 }
bogdanm 0:9b334a45a8ff 1830 break;
bogdanm 0:9b334a45a8ff 1831
bogdanm 0:9b334a45a8ff 1832 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 1833 {
bogdanm 0:9b334a45a8ff 1834 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1835 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1836
bogdanm 0:9b334a45a8ff 1837 /* Configure the Channel 5 in PWM mode */
bogdanm 0:9b334a45a8ff 1838 TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1839
bogdanm 0:9b334a45a8ff 1840 /* Set the Preload enable bit for channel5*/
bogdanm 0:9b334a45a8ff 1841 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
bogdanm 0:9b334a45a8ff 1842
bogdanm 0:9b334a45a8ff 1843 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1844 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
bogdanm 0:9b334a45a8ff 1845 htim->Instance->CCMR3 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1846 }
bogdanm 0:9b334a45a8ff 1847 break;
bogdanm 0:9b334a45a8ff 1848
bogdanm 0:9b334a45a8ff 1849 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 1850 {
bogdanm 0:9b334a45a8ff 1851 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1852 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1853
bogdanm 0:9b334a45a8ff 1854 /* Configure the Channel 5 in PWM mode */
bogdanm 0:9b334a45a8ff 1855 TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1856
bogdanm 0:9b334a45a8ff 1857 /* Set the Preload enable bit for channel6 */
bogdanm 0:9b334a45a8ff 1858 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
bogdanm 0:9b334a45a8ff 1859
bogdanm 0:9b334a45a8ff 1860 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1861 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
bogdanm 0:9b334a45a8ff 1862 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1863 }
bogdanm 0:9b334a45a8ff 1864 break;
bogdanm 0:9b334a45a8ff 1865
bogdanm 0:9b334a45a8ff 1866 default:
bogdanm 0:9b334a45a8ff 1867 break;
bogdanm 0:9b334a45a8ff 1868 }
bogdanm 0:9b334a45a8ff 1869
bogdanm 0:9b334a45a8ff 1870 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1871
bogdanm 0:9b334a45a8ff 1872 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1873
bogdanm 0:9b334a45a8ff 1874 return HAL_OK;
bogdanm 0:9b334a45a8ff 1875 }
bogdanm 0:9b334a45a8ff 1876
bogdanm 0:9b334a45a8ff 1877 /**
bogdanm 0:9b334a45a8ff 1878 * @brief Configures the OCRef clear feature
bogdanm 0:9b334a45a8ff 1879 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 1880 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 1881 * contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm 0:9b334a45a8ff 1882 * @param Channel: specifies the TIM Channel
bogdanm 0:9b334a45a8ff 1883 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1884 * @arg TIM_Channel_1: TIM Channel 1
bogdanm 0:9b334a45a8ff 1885 * @arg TIM_Channel_2: TIM Channel 2
bogdanm 0:9b334a45a8ff 1886 * @arg TIM_Channel_3: TIM Channel 3
bogdanm 0:9b334a45a8ff 1887 * @arg TIM_Channel_4: TIM Channel 4
bogdanm 0:9b334a45a8ff 1888 * @arg TIM_Channel_5: TIM Channel 5
bogdanm 0:9b334a45a8ff 1889 * @arg TIM_Channel_6: TIM Channel 6
bogdanm 0:9b334a45a8ff 1890 * @retval None
bogdanm 0:9b334a45a8ff 1891 */
bogdanm 0:9b334a45a8ff 1892 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 1893 TIM_ClearInputConfigTypeDef *sClearInputConfig,
bogdanm 0:9b334a45a8ff 1894 uint32_t Channel)
bogdanm 0:9b334a45a8ff 1895 {
bogdanm 0:9b334a45a8ff 1896 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 1897
bogdanm 0:9b334a45a8ff 1898 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1899 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1900 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm 0:9b334a45a8ff 1901
bogdanm 0:9b334a45a8ff 1902 /* Check input state */
bogdanm 0:9b334a45a8ff 1903 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1904
bogdanm 0:9b334a45a8ff 1905 switch (sClearInputConfig->ClearInputSource)
bogdanm 0:9b334a45a8ff 1906 {
bogdanm 0:9b334a45a8ff 1907 case TIM_CLEARINPUTSOURCE_NONE:
bogdanm 0:9b334a45a8ff 1908 {
bogdanm 0:9b334a45a8ff 1909 /* Clear the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 1910 tmpsmcr &= ~TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 1911
bogdanm 0:9b334a45a8ff 1912 /* Clear the ETR Bits */
bogdanm 0:9b334a45a8ff 1913 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
bogdanm 0:9b334a45a8ff 1914
bogdanm 0:9b334a45a8ff 1915 /* Set TIMx_SMCR */
bogdanm 0:9b334a45a8ff 1916 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 1917 }
bogdanm 0:9b334a45a8ff 1918 break;
bogdanm 0:9b334a45a8ff 1919
bogdanm 0:9b334a45a8ff 1920 case TIM_CLEARINPUTSOURCE_OCREFCLR:
bogdanm 0:9b334a45a8ff 1921 {
bogdanm 0:9b334a45a8ff 1922 /* Clear the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 1923 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 1924 }
bogdanm 0:9b334a45a8ff 1925 break;
bogdanm 0:9b334a45a8ff 1926
bogdanm 0:9b334a45a8ff 1927 case TIM_CLEARINPUTSOURCE_ETR:
bogdanm 0:9b334a45a8ff 1928 {
bogdanm 0:9b334a45a8ff 1929 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1930 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm 0:9b334a45a8ff 1931 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm 0:9b334a45a8ff 1932 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm 0:9b334a45a8ff 1933
bogdanm 0:9b334a45a8ff 1934 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 1935 sClearInputConfig->ClearInputPrescaler,
bogdanm 0:9b334a45a8ff 1936 sClearInputConfig->ClearInputPolarity,
bogdanm 0:9b334a45a8ff 1937 sClearInputConfig->ClearInputFilter);
bogdanm 0:9b334a45a8ff 1938
bogdanm 0:9b334a45a8ff 1939 /* Set the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 1940 htim->Instance->SMCR |= TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 1941 }
bogdanm 0:9b334a45a8ff 1942 break;
bogdanm 0:9b334a45a8ff 1943 default:
bogdanm 0:9b334a45a8ff 1944 break;
bogdanm 0:9b334a45a8ff 1945 }
bogdanm 0:9b334a45a8ff 1946
bogdanm 0:9b334a45a8ff 1947 switch (Channel)
bogdanm 0:9b334a45a8ff 1948 {
bogdanm 0:9b334a45a8ff 1949 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1950 {
bogdanm 0:9b334a45a8ff 1951 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 1952 {
bogdanm 0:9b334a45a8ff 1953 /* Enable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 1954 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 1955 }
bogdanm 0:9b334a45a8ff 1956 else
bogdanm 0:9b334a45a8ff 1957 {
bogdanm 0:9b334a45a8ff 1958 /* Disable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 1959 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 1960 }
bogdanm 0:9b334a45a8ff 1961 }
bogdanm 0:9b334a45a8ff 1962 break;
bogdanm 0:9b334a45a8ff 1963 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1964 {
bogdanm 0:9b334a45a8ff 1965 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 1966 {
bogdanm 0:9b334a45a8ff 1967 /* Enable the Ocref clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 1968 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 1969 }
bogdanm 0:9b334a45a8ff 1970 else
bogdanm 0:9b334a45a8ff 1971 {
bogdanm 0:9b334a45a8ff 1972 /* Disable the Ocref clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 1973 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 1974 }
bogdanm 0:9b334a45a8ff 1975 }
bogdanm 0:9b334a45a8ff 1976 break;
bogdanm 0:9b334a45a8ff 1977 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1978 {
bogdanm 0:9b334a45a8ff 1979 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 1980 {
bogdanm 0:9b334a45a8ff 1981 /* Enable the Ocref clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 1982 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 1983 }
bogdanm 0:9b334a45a8ff 1984 else
bogdanm 0:9b334a45a8ff 1985 {
bogdanm 0:9b334a45a8ff 1986 /* Disable the Ocref clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 1987 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 1988 }
bogdanm 0:9b334a45a8ff 1989 }
bogdanm 0:9b334a45a8ff 1990 break;
bogdanm 0:9b334a45a8ff 1991 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1992 {
bogdanm 0:9b334a45a8ff 1993 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 1994 {
bogdanm 0:9b334a45a8ff 1995 /* Enable the Ocref clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 1996 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 1997 }
bogdanm 0:9b334a45a8ff 1998 else
bogdanm 0:9b334a45a8ff 1999 {
bogdanm 0:9b334a45a8ff 2000 /* Disable the Ocref clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 2001 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 2002 }
bogdanm 0:9b334a45a8ff 2003 }
bogdanm 0:9b334a45a8ff 2004 break;
bogdanm 0:9b334a45a8ff 2005 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 2006 {
bogdanm 0:9b334a45a8ff 2007 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2008 {
bogdanm 0:9b334a45a8ff 2009 /* Enable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2010 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
bogdanm 0:9b334a45a8ff 2011 }
bogdanm 0:9b334a45a8ff 2012 else
bogdanm 0:9b334a45a8ff 2013 {
bogdanm 0:9b334a45a8ff 2014 /* Disable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2015 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
bogdanm 0:9b334a45a8ff 2016 }
bogdanm 0:9b334a45a8ff 2017 }
bogdanm 0:9b334a45a8ff 2018 break;
bogdanm 0:9b334a45a8ff 2019 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 2020 {
bogdanm 0:9b334a45a8ff 2021 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2022 {
bogdanm 0:9b334a45a8ff 2023 /* Enable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2024 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
bogdanm 0:9b334a45a8ff 2025 }
bogdanm 0:9b334a45a8ff 2026 else
bogdanm 0:9b334a45a8ff 2027 {
bogdanm 0:9b334a45a8ff 2028 /* Disable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2029 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
bogdanm 0:9b334a45a8ff 2030 }
bogdanm 0:9b334a45a8ff 2031 }
bogdanm 0:9b334a45a8ff 2032 break;
bogdanm 0:9b334a45a8ff 2033 default:
bogdanm 0:9b334a45a8ff 2034 break;
bogdanm 0:9b334a45a8ff 2035 }
bogdanm 0:9b334a45a8ff 2036
bogdanm 0:9b334a45a8ff 2037 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2038
bogdanm 0:9b334a45a8ff 2039 return HAL_OK;
bogdanm 0:9b334a45a8ff 2040 }
bogdanm 0:9b334a45a8ff 2041
bogdanm 0:9b334a45a8ff 2042 /**
bogdanm 0:9b334a45a8ff 2043 * @brief Configures the TIM in master mode.
bogdanm 0:9b334a45a8ff 2044 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2045 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2046 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 2047 * contains the selected trigger output (TRGO) and the Master/Slave
bogdanm 0:9b334a45a8ff 2048 * mode.
bogdanm 0:9b334a45a8ff 2049 * @retval HAL status
bogdanm 0:9b334a45a8ff 2050 */
bogdanm 0:9b334a45a8ff 2051 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
bogdanm 0:9b334a45a8ff 2052 {
bogdanm 0:9b334a45a8ff 2053 uint32_t tmpcr2;
bogdanm 0:9b334a45a8ff 2054 uint32_t tmpsmcr;
bogdanm 0:9b334a45a8ff 2055
bogdanm 0:9b334a45a8ff 2056 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2057 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2058 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
bogdanm 0:9b334a45a8ff 2059 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
bogdanm 0:9b334a45a8ff 2060
bogdanm 0:9b334a45a8ff 2061 /* Check input state */
bogdanm 0:9b334a45a8ff 2062 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2063
bogdanm 0:9b334a45a8ff 2064 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 2065 tmpcr2 = htim->Instance->CR2;
bogdanm 0:9b334a45a8ff 2066
bogdanm 0:9b334a45a8ff 2067 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 2068 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 2069
bogdanm 0:9b334a45a8ff 2070 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
bogdanm 0:9b334a45a8ff 2071 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
bogdanm 0:9b334a45a8ff 2072 {
bogdanm 0:9b334a45a8ff 2073 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2074 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
bogdanm 0:9b334a45a8ff 2075
bogdanm 0:9b334a45a8ff 2076 /* Clear the MMS2 bits */
bogdanm 0:9b334a45a8ff 2077 tmpcr2 &= ~TIM_CR2_MMS2;
bogdanm 0:9b334a45a8ff 2078 /* Select the TRGO2 source*/
bogdanm 0:9b334a45a8ff 2079 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
bogdanm 0:9b334a45a8ff 2080 }
bogdanm 0:9b334a45a8ff 2081
bogdanm 0:9b334a45a8ff 2082 /* Reset the MMS Bits */
bogdanm 0:9b334a45a8ff 2083 tmpcr2 &= ~TIM_CR2_MMS;
bogdanm 0:9b334a45a8ff 2084 /* Select the TRGO source */
bogdanm 0:9b334a45a8ff 2085 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
bogdanm 0:9b334a45a8ff 2086
bogdanm 0:9b334a45a8ff 2087 /* Reset the MSM Bit */
bogdanm 0:9b334a45a8ff 2088 tmpsmcr &= ~TIM_SMCR_MSM;
bogdanm 0:9b334a45a8ff 2089 /* Set master mode */
bogdanm 0:9b334a45a8ff 2090 tmpsmcr |= sMasterConfig->MasterSlaveMode;
bogdanm 0:9b334a45a8ff 2091
bogdanm 0:9b334a45a8ff 2092 /* Update TIMx CR2 */
bogdanm 0:9b334a45a8ff 2093 htim->Instance->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 2094
bogdanm 0:9b334a45a8ff 2095 /* Update TIMx SMCR */
bogdanm 0:9b334a45a8ff 2096 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 2097
bogdanm 0:9b334a45a8ff 2098 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2099
bogdanm 0:9b334a45a8ff 2100 return HAL_OK;
bogdanm 0:9b334a45a8ff 2101 }
bogdanm 0:9b334a45a8ff 2102
bogdanm 0:9b334a45a8ff 2103 /**
bogdanm 0:9b334a45a8ff 2104 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
bogdanm 0:9b334a45a8ff 2105 * and the AOE(automatic output enable).
bogdanm 0:9b334a45a8ff 2106 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2107 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2108 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
bogdanm 0:9b334a45a8ff 2109 * contains the BDTR Register configuration information for the TIM peripheral.
bogdanm 0:9b334a45a8ff 2110 * @retval HAL status
bogdanm 0:9b334a45a8ff 2111 */
bogdanm 0:9b334a45a8ff 2112 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 2113 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
bogdanm 0:9b334a45a8ff 2114 {
bogdanm 0:9b334a45a8ff 2115 uint32_t tmpbdtr = 0;
bogdanm 0:9b334a45a8ff 2116
bogdanm 0:9b334a45a8ff 2117 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2118 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2119 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
bogdanm 0:9b334a45a8ff 2120 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
bogdanm 0:9b334a45a8ff 2121 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
bogdanm 0:9b334a45a8ff 2122 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
bogdanm 0:9b334a45a8ff 2123 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
bogdanm 0:9b334a45a8ff 2124 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
bogdanm 0:9b334a45a8ff 2125 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
bogdanm 0:9b334a45a8ff 2126 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
bogdanm 0:9b334a45a8ff 2127 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
bogdanm 0:9b334a45a8ff 2128 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
bogdanm 0:9b334a45a8ff 2129 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
bogdanm 0:9b334a45a8ff 2130
bogdanm 0:9b334a45a8ff 2131 /* Check input state */
bogdanm 0:9b334a45a8ff 2132 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2133
bogdanm 0:9b334a45a8ff 2134 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2135
bogdanm 0:9b334a45a8ff 2136 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
bogdanm 0:9b334a45a8ff 2137 the OSSI State, the dead time value and the Automatic Output Enable Bit */
bogdanm 0:9b334a45a8ff 2138
bogdanm 0:9b334a45a8ff 2139 /* Clear the BDTR bits */
bogdanm 0:9b334a45a8ff 2140 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
bogdanm 0:9b334a45a8ff 2141 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
bogdanm 0:9b334a45a8ff 2142 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
bogdanm 0:9b334a45a8ff 2143 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
bogdanm 0:9b334a45a8ff 2144
bogdanm 0:9b334a45a8ff 2145 /* Set the BDTR bits */
bogdanm 0:9b334a45a8ff 2146 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
bogdanm 0:9b334a45a8ff 2147 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
bogdanm 0:9b334a45a8ff 2148 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
bogdanm 0:9b334a45a8ff 2149 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
bogdanm 0:9b334a45a8ff 2150 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
bogdanm 0:9b334a45a8ff 2151 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
bogdanm 0:9b334a45a8ff 2152 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
bogdanm 0:9b334a45a8ff 2153 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
bogdanm 0:9b334a45a8ff 2154 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
bogdanm 0:9b334a45a8ff 2155 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
bogdanm 0:9b334a45a8ff 2156 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
bogdanm 0:9b334a45a8ff 2157
bogdanm 0:9b334a45a8ff 2158 /* Set TIMx_BDTR */
bogdanm 0:9b334a45a8ff 2159 htim->Instance->BDTR = tmpbdtr;
bogdanm 0:9b334a45a8ff 2160
bogdanm 0:9b334a45a8ff 2161 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2162
bogdanm 0:9b334a45a8ff 2163 return HAL_OK;
bogdanm 0:9b334a45a8ff 2164 }
bogdanm 0:9b334a45a8ff 2165
bogdanm 0:9b334a45a8ff 2166 /**
bogdanm 0:9b334a45a8ff 2167 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
bogdanm 0:9b334a45a8ff 2168 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2169 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2170 * @param Remap: specifies the TIM input remapping source.
bogdanm 0:9b334a45a8ff 2171 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2172 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
bogdanm 0:9b334a45a8ff 2173 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
bogdanm 0:9b334a45a8ff 2174 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
bogdanm 0:9b334a45a8ff 2175 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
bogdanm 0:9b334a45a8ff 2176 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
bogdanm 0:9b334a45a8ff 2177 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
bogdanm 0:9b334a45a8ff 2178 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
bogdanm 0:9b334a45a8ff 2179 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
bogdanm 0:9b334a45a8ff 2180 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
bogdanm 0:9b334a45a8ff 2181 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
bogdanm 0:9b334a45a8ff 2182 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
bogdanm 0:9b334a45a8ff 2183 * (HSE divided by a programmable prescaler)
bogdanm 0:9b334a45a8ff 2184 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
bogdanm 0:9b334a45a8ff 2185 * @retval HAL status
bogdanm 0:9b334a45a8ff 2186 */
bogdanm 0:9b334a45a8ff 2187 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
bogdanm 0:9b334a45a8ff 2188 {
bogdanm 0:9b334a45a8ff 2189 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2190
bogdanm 0:9b334a45a8ff 2191 /* Check parameters */
bogdanm 0:9b334a45a8ff 2192 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2193 assert_param(IS_TIM_REMAP(Remap));
bogdanm 0:9b334a45a8ff 2194
bogdanm 0:9b334a45a8ff 2195 /* Set the Timer remapping configuration */
bogdanm 0:9b334a45a8ff 2196 htim->Instance->OR = Remap;
bogdanm 0:9b334a45a8ff 2197
bogdanm 0:9b334a45a8ff 2198 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2199
bogdanm 0:9b334a45a8ff 2200 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2201
bogdanm 0:9b334a45a8ff 2202 return HAL_OK;
bogdanm 0:9b334a45a8ff 2203 }
bogdanm 0:9b334a45a8ff 2204
bogdanm 0:9b334a45a8ff 2205 /**
bogdanm 0:9b334a45a8ff 2206 * @brief Group channel 5 and channel 1, 2 or 3
bogdanm 0:9b334a45a8ff 2207 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 2208 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
bogdanm 0:9b334a45a8ff 2209 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 2210 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
bogdanm 0:9b334a45a8ff 2211 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
bogdanm 0:9b334a45a8ff 2212 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
bogdanm 0:9b334a45a8ff 2213 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
bogdanm 0:9b334a45a8ff 2214 * @retval HAL status
bogdanm 0:9b334a45a8ff 2215 */
bogdanm 0:9b334a45a8ff 2216 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
bogdanm 0:9b334a45a8ff 2217 {
bogdanm 0:9b334a45a8ff 2218 /* Check parameters */
bogdanm 0:9b334a45a8ff 2219 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2220 assert_param(IS_TIM_GROUPCH5(OCRef));
bogdanm 0:9b334a45a8ff 2221
bogdanm 0:9b334a45a8ff 2222 /* Process Locked */
bogdanm 0:9b334a45a8ff 2223 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2224
bogdanm 0:9b334a45a8ff 2225 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2226
bogdanm 0:9b334a45a8ff 2227 /* Clear GC5Cx bit fields */
bogdanm 0:9b334a45a8ff 2228 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
bogdanm 0:9b334a45a8ff 2229
bogdanm 0:9b334a45a8ff 2230 /* Set GC5Cx bit fields */
bogdanm 0:9b334a45a8ff 2231 htim->Instance->CCR5 |= OCRef;
bogdanm 0:9b334a45a8ff 2232
bogdanm 0:9b334a45a8ff 2233 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2234
bogdanm 0:9b334a45a8ff 2235 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2236
bogdanm 0:9b334a45a8ff 2237 return HAL_OK;
bogdanm 0:9b334a45a8ff 2238 }
bogdanm 0:9b334a45a8ff 2239
bogdanm 0:9b334a45a8ff 2240 /**
bogdanm 0:9b334a45a8ff 2241 * @}
bogdanm 0:9b334a45a8ff 2242 */
bogdanm 0:9b334a45a8ff 2243
bogdanm 0:9b334a45a8ff 2244 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
bogdanm 0:9b334a45a8ff 2245 * @brief Extended Callbacks functions
bogdanm 0:9b334a45a8ff 2246 *
bogdanm 0:9b334a45a8ff 2247 @verbatim
bogdanm 0:9b334a45a8ff 2248 ==============================================================================
bogdanm 0:9b334a45a8ff 2249 ##### Extension Callbacks functions #####
bogdanm 0:9b334a45a8ff 2250 ==============================================================================
bogdanm 0:9b334a45a8ff 2251 [..]
bogdanm 0:9b334a45a8ff 2252 This section provides Extension TIM callback functions:
bogdanm 0:9b334a45a8ff 2253 (+) Timer Commutation callback
bogdanm 0:9b334a45a8ff 2254 (+) Timer Break callback
bogdanm 0:9b334a45a8ff 2255
bogdanm 0:9b334a45a8ff 2256 @endverbatim
bogdanm 0:9b334a45a8ff 2257 * @{
bogdanm 0:9b334a45a8ff 2258 */
bogdanm 0:9b334a45a8ff 2259
bogdanm 0:9b334a45a8ff 2260 /**
bogdanm 0:9b334a45a8ff 2261 * @brief Hall commutation changed callback in non blocking mode
bogdanm 0:9b334a45a8ff 2262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2263 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2264 * @retval None
bogdanm 0:9b334a45a8ff 2265 */
bogdanm 0:9b334a45a8ff 2266 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2267 {
mbed_official 83:a036322b8637 2268 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 2269 UNUSED(htim);
mbed_official 83:a036322b8637 2270
bogdanm 0:9b334a45a8ff 2271 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2272 the HAL_TIMEx_CommutationCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 2273 */
bogdanm 0:9b334a45a8ff 2274 }
bogdanm 0:9b334a45a8ff 2275
bogdanm 0:9b334a45a8ff 2276 /**
bogdanm 0:9b334a45a8ff 2277 * @brief Hall Break detection callback in non blocking mode
bogdanm 0:9b334a45a8ff 2278 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2279 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2280 * @retval None
bogdanm 0:9b334a45a8ff 2281 */
bogdanm 0:9b334a45a8ff 2282 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2283 {
mbed_official 83:a036322b8637 2284 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 2285 UNUSED(htim);
mbed_official 83:a036322b8637 2286
bogdanm 0:9b334a45a8ff 2287 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2288 the HAL_TIMEx_BreakCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 2289 */
bogdanm 0:9b334a45a8ff 2290 }
bogdanm 0:9b334a45a8ff 2291
bogdanm 0:9b334a45a8ff 2292 /**
bogdanm 0:9b334a45a8ff 2293 * @}
bogdanm 0:9b334a45a8ff 2294 */
bogdanm 0:9b334a45a8ff 2295
bogdanm 0:9b334a45a8ff 2296 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
bogdanm 0:9b334a45a8ff 2297 * @brief Extended Peripheral State functions
bogdanm 0:9b334a45a8ff 2298 *
bogdanm 0:9b334a45a8ff 2299 @verbatim
bogdanm 0:9b334a45a8ff 2300 ==============================================================================
bogdanm 0:9b334a45a8ff 2301 ##### Extension Peripheral State functions #####
bogdanm 0:9b334a45a8ff 2302 ==============================================================================
bogdanm 0:9b334a45a8ff 2303 [..]
bogdanm 0:9b334a45a8ff 2304 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 2305 and the data flow.
bogdanm 0:9b334a45a8ff 2306
bogdanm 0:9b334a45a8ff 2307 @endverbatim
bogdanm 0:9b334a45a8ff 2308 * @{
bogdanm 0:9b334a45a8ff 2309 */
bogdanm 0:9b334a45a8ff 2310
bogdanm 0:9b334a45a8ff 2311 /**
bogdanm 0:9b334a45a8ff 2312 * @brief Return the TIM Hall Sensor interface state
bogdanm 0:9b334a45a8ff 2313 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2314 * the configuration information for TIM module.
bogdanm 0:9b334a45a8ff 2315 * @retval HAL state
bogdanm 0:9b334a45a8ff 2316 */
bogdanm 0:9b334a45a8ff 2317 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2318 {
bogdanm 0:9b334a45a8ff 2319 return htim->State;
bogdanm 0:9b334a45a8ff 2320 }
bogdanm 0:9b334a45a8ff 2321
bogdanm 0:9b334a45a8ff 2322 /**
bogdanm 0:9b334a45a8ff 2323 * @}
bogdanm 0:9b334a45a8ff 2324 */
bogdanm 0:9b334a45a8ff 2325
bogdanm 0:9b334a45a8ff 2326 /**
bogdanm 0:9b334a45a8ff 2327 * @brief TIM DMA Commutation callback.
bogdanm 0:9b334a45a8ff 2328 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 2329 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 2330 * @retval None
bogdanm 0:9b334a45a8ff 2331 */
bogdanm 0:9b334a45a8ff 2332 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 2333 {
bogdanm 0:9b334a45a8ff 2334 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 2335
bogdanm 0:9b334a45a8ff 2336 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2337
bogdanm 0:9b334a45a8ff 2338 HAL_TIMEx_CommutationCallback(htim);
bogdanm 0:9b334a45a8ff 2339 }
bogdanm 0:9b334a45a8ff 2340
bogdanm 0:9b334a45a8ff 2341 /**
bogdanm 0:9b334a45a8ff 2342 * @brief Enables or disables the TIM Capture Compare Channel xN.
bogdanm 0:9b334a45a8ff 2343 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 2344 * @param Channel: specifies the TIM Channel
bogdanm 0:9b334a45a8ff 2345 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2346 * @arg TIM_Channel_1: TIM Channel 1
bogdanm 0:9b334a45a8ff 2347 * @arg TIM_Channel_2: TIM Channel 2
bogdanm 0:9b334a45a8ff 2348 * @arg TIM_Channel_3: TIM Channel 3
bogdanm 0:9b334a45a8ff 2349 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
bogdanm 0:9b334a45a8ff 2350 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
bogdanm 0:9b334a45a8ff 2351 * @retval None
bogdanm 0:9b334a45a8ff 2352 */
bogdanm 0:9b334a45a8ff 2353 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
bogdanm 0:9b334a45a8ff 2354 {
bogdanm 0:9b334a45a8ff 2355 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 2356
bogdanm 0:9b334a45a8ff 2357 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2358 assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
bogdanm 0:9b334a45a8ff 2359 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 2360
bogdanm 0:9b334a45a8ff 2361 tmp = TIM_CCER_CC1NE << Channel;
bogdanm 0:9b334a45a8ff 2362
bogdanm 0:9b334a45a8ff 2363 /* Reset the CCxNE Bit */
bogdanm 0:9b334a45a8ff 2364 TIMx->CCER &= ~tmp;
bogdanm 0:9b334a45a8ff 2365
bogdanm 0:9b334a45a8ff 2366 /* Set or reset the CCxNE Bit */
bogdanm 0:9b334a45a8ff 2367 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
bogdanm 0:9b334a45a8ff 2368 }
bogdanm 0:9b334a45a8ff 2369
bogdanm 0:9b334a45a8ff 2370 /**
bogdanm 0:9b334a45a8ff 2371 * @brief Timer Output Compare 5 configuration
bogdanm 0:9b334a45a8ff 2372 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 2373 * @param OC_Config: The output configuration structure
bogdanm 0:9b334a45a8ff 2374 * @retval None
bogdanm 0:9b334a45a8ff 2375 */
bogdanm 0:9b334a45a8ff 2376 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 2377 {
bogdanm 0:9b334a45a8ff 2378 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 2379 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 2380 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 2381
bogdanm 0:9b334a45a8ff 2382 /* Disable the output: Reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 2383 TIMx->CCER &= ~TIM_CCER_CC5E;
bogdanm 0:9b334a45a8ff 2384
bogdanm 0:9b334a45a8ff 2385 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 2386 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 2387 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 2388 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 2389 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 2390 tmpccmrx = TIMx->CCMR3;
bogdanm 0:9b334a45a8ff 2391
bogdanm 0:9b334a45a8ff 2392 /* Reset the Output Compare Mode Bits */
bogdanm 0:9b334a45a8ff 2393 tmpccmrx &= ~(TIM_CCMR3_OC5M);
bogdanm 0:9b334a45a8ff 2394 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 2395 tmpccmrx |= OC_Config->OCMode;
bogdanm 0:9b334a45a8ff 2396
bogdanm 0:9b334a45a8ff 2397 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 2398 tmpccer &= ~TIM_CCER_CC5P;
bogdanm 0:9b334a45a8ff 2399 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 2400 tmpccer |= (OC_Config->OCPolarity << 16);
bogdanm 0:9b334a45a8ff 2401
bogdanm 0:9b334a45a8ff 2402 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 2403 {
bogdanm 0:9b334a45a8ff 2404 /* Reset the Output Compare IDLE State */
bogdanm 0:9b334a45a8ff 2405 tmpcr2 &= ~TIM_CR2_OIS5;
bogdanm 0:9b334a45a8ff 2406 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 2407 tmpcr2 |= (OC_Config->OCIdleState << 8);
bogdanm 0:9b334a45a8ff 2408 }
bogdanm 0:9b334a45a8ff 2409 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 2410 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 2411
bogdanm 0:9b334a45a8ff 2412 /* Write to TIMx CCMR3 */
bogdanm 0:9b334a45a8ff 2413 TIMx->CCMR3 = tmpccmrx;
bogdanm 0:9b334a45a8ff 2414
bogdanm 0:9b334a45a8ff 2415 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 2416 TIMx->CCR5 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 2417
bogdanm 0:9b334a45a8ff 2418 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 2419 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 2420 }
bogdanm 0:9b334a45a8ff 2421
bogdanm 0:9b334a45a8ff 2422 /**
bogdanm 0:9b334a45a8ff 2423 * @brief Timer Output Compare 6 configuration
bogdanm 0:9b334a45a8ff 2424 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 2425 * @param OC_Config: The output configuration structure
bogdanm 0:9b334a45a8ff 2426 * @retval None
bogdanm 0:9b334a45a8ff 2427 */
bogdanm 0:9b334a45a8ff 2428 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 2429 {
bogdanm 0:9b334a45a8ff 2430 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 2431 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 2432 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 2433
bogdanm 0:9b334a45a8ff 2434 /* Disable the output: Reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 2435 TIMx->CCER &= ~TIM_CCER_CC6E;
bogdanm 0:9b334a45a8ff 2436
bogdanm 0:9b334a45a8ff 2437 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 2438 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 2439 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 2440 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 2441 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 2442 tmpccmrx = TIMx->CCMR3;
bogdanm 0:9b334a45a8ff 2443
bogdanm 0:9b334a45a8ff 2444 /* Reset the Output Compare Mode Bits */
bogdanm 0:9b334a45a8ff 2445 tmpccmrx &= ~(TIM_CCMR3_OC6M);
bogdanm 0:9b334a45a8ff 2446 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 2447 tmpccmrx |= (OC_Config->OCMode << 8);
bogdanm 0:9b334a45a8ff 2448
bogdanm 0:9b334a45a8ff 2449 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 2450 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
bogdanm 0:9b334a45a8ff 2451 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 2452 tmpccer |= (OC_Config->OCPolarity << 20);
bogdanm 0:9b334a45a8ff 2453
bogdanm 0:9b334a45a8ff 2454 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 2455 {
bogdanm 0:9b334a45a8ff 2456 /* Reset the Output Compare IDLE State */
bogdanm 0:9b334a45a8ff 2457 tmpcr2 &= ~TIM_CR2_OIS6;
bogdanm 0:9b334a45a8ff 2458 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 2459 tmpcr2 |= (OC_Config->OCIdleState << 10);
bogdanm 0:9b334a45a8ff 2460 }
bogdanm 0:9b334a45a8ff 2461
bogdanm 0:9b334a45a8ff 2462 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 2463 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 2464
bogdanm 0:9b334a45a8ff 2465 /* Write to TIMx CCMR3 */
bogdanm 0:9b334a45a8ff 2466 TIMx->CCMR3 = tmpccmrx;
bogdanm 0:9b334a45a8ff 2467
bogdanm 0:9b334a45a8ff 2468 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 2469 TIMx->CCR6 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 2470
bogdanm 0:9b334a45a8ff 2471 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 2472 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 2473 }
bogdanm 0:9b334a45a8ff 2474
bogdanm 0:9b334a45a8ff 2475 /**
bogdanm 0:9b334a45a8ff 2476 * @}
bogdanm 0:9b334a45a8ff 2477 */
bogdanm 0:9b334a45a8ff 2478
bogdanm 0:9b334a45a8ff 2479 #endif /* HAL_TIM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 2480 /**
bogdanm 0:9b334a45a8ff 2481 * @}
bogdanm 0:9b334a45a8ff 2482 */
bogdanm 0:9b334a45a8ff 2483
bogdanm 0:9b334a45a8ff 2484 /**
bogdanm 0:9b334a45a8ff 2485 * @}
bogdanm 0:9b334a45a8ff 2486 */
bogdanm 0:9b334a45a8ff 2487 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/