mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_rcc_ex.h
mbed_official	83:a036322b8637	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL Extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F7xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F7xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f7xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCCEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief PLLI2S Clock structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	83:a036322b8637	68	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	69	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	0:9b334a45a8ff	72	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	73	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	76	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	77	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
mbed_official	83:a036322b8637	80	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
mbed_official	83:a036322b8637	81	This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
bogdanm	0:9b334a45a8ff	82	}RCC_PLLI2SInitTypeDef;
bogdanm	0:9b334a45a8ff	83
bogdanm	0:9b334a45a8ff	84	/**
bogdanm	0:9b334a45a8ff	85	* @brief PLLSAI Clock structure definition
bogdanm	0:9b334a45a8ff	86	*/
bogdanm	0:9b334a45a8ff	87	typedef struct
bogdanm	0:9b334a45a8ff	88	{
bogdanm	0:9b334a45a8ff	89	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	83:a036322b8637	90	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	91	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	94	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	95	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	0:9b334a45a8ff	98	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	99	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
mbed_official	83:a036322b8637	102	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
bogdanm	0:9b334a45a8ff	103	This parameter will be used only when PLLSAI is disabled */
bogdanm	0:9b334a45a8ff	104	}RCC_PLLSAIInitTypeDef;
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	/**
bogdanm	0:9b334a45a8ff	107	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109	typedef struct
bogdanm	0:9b334a45a8ff	110	{
bogdanm	0:9b334a45a8ff	111	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	112	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	0:9b334a45a8ff	115	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	0:9b334a45a8ff	118	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	121	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	122	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	125	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	126	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm	0:9b334a45a8ff	129	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
bogdanm	0:9b334a45a8ff	132	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
bogdanm	0:9b334a45a8ff	135	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm	0:9b334a45a8ff	138	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	141	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	144	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	147	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	150	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	0:9b334a45a8ff	153	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	0:9b334a45a8ff	156	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	0:9b334a45a8ff	159	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	uint32_t Usart6ClockSelection; /*!< USART6 clock source
bogdanm	0:9b334a45a8ff	162	This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	uint32_t Uart7ClockSelection; /*!< UART7 clock source
bogdanm	0:9b334a45a8ff	165	This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	uint32_t Uart8ClockSelection; /*!< UART8 clock source
bogdanm	0:9b334a45a8ff	168	This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	171	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	0:9b334a45a8ff	174	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	0:9b334a45a8ff	177	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	uint32_t I2c4ClockSelection; /*!< I2C4 clock source
bogdanm	0:9b334a45a8ff	180	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint32_t CecClockSelection; /*!< CEC clock source
bogdanm	0:9b334a45a8ff	186	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
bogdanm	0:9b334a45a8ff	189	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
bogdanm	0:9b334a45a8ff	193	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	194	/**
bogdanm	0:9b334a45a8ff	195	* @}
bogdanm	0:9b334a45a8ff	196	*/
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	199	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	0:9b334a45a8ff	200	* @{
bogdanm	0:9b334a45a8ff	201	*/
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
bogdanm	0:9b334a45a8ff	204	* @{
bogdanm	0:9b334a45a8ff	205	*/
bogdanm	0:9b334a45a8ff	206	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official	83:a036322b8637	207	#if defined(STM32F746xx) \|\| defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	208	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official	83:a036322b8637	209	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	210	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	211	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	212	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	213	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	214	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	215	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	216	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	217	#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	218	#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	219	#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	220	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	221	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	222	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	223	#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	224	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	225	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	226	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	227	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	228	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	229	#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	230	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	231	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	232
mbed_official	83:a036322b8637	233	/**
mbed_official	83:a036322b8637	234	* @}
mbed_official	83:a036322b8637	235	*/
bogdanm	0:9b334a45a8ff	236
mbed_official	83:a036322b8637	237	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
mbed_official	83:a036322b8637	238	* @{
mbed_official	83:a036322b8637	239	*/
mbed_official	83:a036322b8637	240	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000)
mbed_official	83:a036322b8637	241	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001)
mbed_official	83:a036322b8637	242	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002)
mbed_official	83:a036322b8637	243	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	244	/**
bogdanm	0:9b334a45a8ff	245	* @}
bogdanm	0:9b334a45a8ff	246	*/
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
bogdanm	0:9b334a45a8ff	249	* @{
bogdanm	0:9b334a45a8ff	250	*/
bogdanm	0:9b334a45a8ff	251	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	252	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	253	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	254	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	255	/**
bogdanm	0:9b334a45a8ff	256	* @}
bogdanm	0:9b334a45a8ff	257	*/
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
bogdanm	0:9b334a45a8ff	260	* @{
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	263	#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
bogdanm	0:9b334a45a8ff	264	#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
bogdanm	0:9b334a45a8ff	265	#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
bogdanm	0:9b334a45a8ff	266	/**
bogdanm	0:9b334a45a8ff	267	* @}
bogdanm	0:9b334a45a8ff	268	*/
bogdanm	0:9b334a45a8ff	269
bogdanm	0:9b334a45a8ff	270	/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
bogdanm	0:9b334a45a8ff	271	* @{
bogdanm	0:9b334a45a8ff	272	*/
bogdanm	0:9b334a45a8ff	273	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	274	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/**
bogdanm	0:9b334a45a8ff	277	* @}
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
bogdanm	0:9b334a45a8ff	282	* @{
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	285	#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
bogdanm	0:9b334a45a8ff	286	#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/**
bogdanm	0:9b334a45a8ff	289	* @}
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
bogdanm	0:9b334a45a8ff	293	* @{
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	296	#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
bogdanm	0:9b334a45a8ff	297	#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @}
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm	0:9b334a45a8ff	303	* @{
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305	#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	306	#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
bogdanm	0:9b334a45a8ff	307	/**
bogdanm	0:9b334a45a8ff	308	* @}
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
bogdanm	0:9b334a45a8ff	312	* @{
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	315	#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
bogdanm	0:9b334a45a8ff	316	#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
bogdanm	0:9b334a45a8ff	317	#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
bogdanm	0:9b334a45a8ff	318	/**
bogdanm	0:9b334a45a8ff	319	* @}
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm	0:9b334a45a8ff	323	* @{
bogdanm	0:9b334a45a8ff	324	*/
bogdanm	0:9b334a45a8ff	325	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	326	#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
bogdanm	0:9b334a45a8ff	327	#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
bogdanm	0:9b334a45a8ff	328	#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
bogdanm	0:9b334a45a8ff	329	/**
bogdanm	0:9b334a45a8ff	330	* @}
bogdanm	0:9b334a45a8ff	331	*/
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm	0:9b334a45a8ff	334	* @{
bogdanm	0:9b334a45a8ff	335	*/
bogdanm	0:9b334a45a8ff	336	#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	337	#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
bogdanm	0:9b334a45a8ff	338	#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
bogdanm	0:9b334a45a8ff	339	#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
bogdanm	0:9b334a45a8ff	340	/**
bogdanm	0:9b334a45a8ff	341	* @}
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
bogdanm	0:9b334a45a8ff	345	* @{
bogdanm	0:9b334a45a8ff	346	*/
bogdanm	0:9b334a45a8ff	347	#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	348	#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
bogdanm	0:9b334a45a8ff	349	#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
bogdanm	0:9b334a45a8ff	350	#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
bogdanm	0:9b334a45a8ff	351	/**
bogdanm	0:9b334a45a8ff	352	* @}
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
bogdanm	0:9b334a45a8ff	356	* @{
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	359	#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
bogdanm	0:9b334a45a8ff	360	#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
bogdanm	0:9b334a45a8ff	361	#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
bogdanm	0:9b334a45a8ff	362	/**
bogdanm	0:9b334a45a8ff	363	* @}
bogdanm	0:9b334a45a8ff	364	*/
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
bogdanm	0:9b334a45a8ff	367	* @{
bogdanm	0:9b334a45a8ff	368	*/
bogdanm	0:9b334a45a8ff	369	#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	370	#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
bogdanm	0:9b334a45a8ff	371	#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
bogdanm	0:9b334a45a8ff	372	#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
bogdanm	0:9b334a45a8ff	373	/**
bogdanm	0:9b334a45a8ff	374	* @}
bogdanm	0:9b334a45a8ff	375	*/
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
bogdanm	0:9b334a45a8ff	378	* @{
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380	#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	381	#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
bogdanm	0:9b334a45a8ff	382	#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
bogdanm	0:9b334a45a8ff	383	#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
bogdanm	0:9b334a45a8ff	384	/**
bogdanm	0:9b334a45a8ff	385	* @}
bogdanm	0:9b334a45a8ff	386	*/
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
bogdanm	0:9b334a45a8ff	389	* @{
bogdanm	0:9b334a45a8ff	390	*/
bogdanm	0:9b334a45a8ff	391	#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	392	#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
bogdanm	0:9b334a45a8ff	393	#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
bogdanm	0:9b334a45a8ff	394	#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
bogdanm	0:9b334a45a8ff	395	/**
bogdanm	0:9b334a45a8ff	396	* @}
bogdanm	0:9b334a45a8ff	397	*/
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
bogdanm	0:9b334a45a8ff	400	* @{
bogdanm	0:9b334a45a8ff	401	*/
bogdanm	0:9b334a45a8ff	402	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	403	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
bogdanm	0:9b334a45a8ff	404	#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
bogdanm	0:9b334a45a8ff	405	/**
bogdanm	0:9b334a45a8ff	406	* @}
bogdanm	0:9b334a45a8ff	407	*/
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
bogdanm	0:9b334a45a8ff	410	* @{
bogdanm	0:9b334a45a8ff	411	*/
bogdanm	0:9b334a45a8ff	412	#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	413	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
bogdanm	0:9b334a45a8ff	414	#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/**
bogdanm	0:9b334a45a8ff	417	* @}
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
bogdanm	0:9b334a45a8ff	421	* @{
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	424	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
bogdanm	0:9b334a45a8ff	425	#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
bogdanm	0:9b334a45a8ff	426	/**
bogdanm	0:9b334a45a8ff	427	* @}
bogdanm	0:9b334a45a8ff	428	*/
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
bogdanm	0:9b334a45a8ff	431	* @{
bogdanm	0:9b334a45a8ff	432	*/
bogdanm	0:9b334a45a8ff	433	#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	434	#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
bogdanm	0:9b334a45a8ff	435	#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
bogdanm	0:9b334a45a8ff	436	/**
bogdanm	0:9b334a45a8ff	437	* @}
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
bogdanm	0:9b334a45a8ff	441	* @{
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	444	#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
bogdanm	0:9b334a45a8ff	445	#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
bogdanm	0:9b334a45a8ff	446	#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/**
bogdanm	0:9b334a45a8ff	449	* @}
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
bogdanm	0:9b334a45a8ff	453	* @{
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455	#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	456	#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
bogdanm	0:9b334a45a8ff	457	/**
bogdanm	0:9b334a45a8ff	458	* @}
bogdanm	0:9b334a45a8ff	459	*/
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
bogdanm	0:9b334a45a8ff	462	* @{
bogdanm	0:9b334a45a8ff	463	*/
bogdanm	0:9b334a45a8ff	464	#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	465	#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
mbed_official	83:a036322b8637	466	/**
mbed_official	83:a036322b8637	467	* @}
mbed_official	83:a036322b8637	468	*/
bogdanm	0:9b334a45a8ff	469
mbed_official	83:a036322b8637	470	/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
mbed_official	83:a036322b8637	471	* @{
mbed_official	83:a036322b8637	472	*/
mbed_official	83:a036322b8637	473	#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
mbed_official	83:a036322b8637	474	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
bogdanm	0:9b334a45a8ff	475	/**
bogdanm	0:9b334a45a8ff	476	* @}
bogdanm	0:9b334a45a8ff	477	*/
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/**
bogdanm	0:9b334a45a8ff	480	* @}
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482
bogdanm	0:9b334a45a8ff	483	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	484	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	0:9b334a45a8ff	485	* @{
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm	0:9b334a45a8ff	488	* @brief Enables or disables the AHB/APB peripheral clock.
bogdanm	0:9b334a45a8ff	489	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	490	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	491	* using it.
bogdanm	0:9b334a45a8ff	492	* @{
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	496	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	497	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	498	* using it.
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	501	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	502	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
bogdanm	0:9b334a45a8ff	503	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	504	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
bogdanm	0:9b334a45a8ff	505	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	506	} while(0)
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	509	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	510	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
bogdanm	0:9b334a45a8ff	511	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	512	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
bogdanm	0:9b334a45a8ff	513	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	514	} while(0)
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	517	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	518	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
bogdanm	0:9b334a45a8ff	519	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	520	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
bogdanm	0:9b334a45a8ff	521	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	522	} while(0)
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	525	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	526	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
bogdanm	0:9b334a45a8ff	527	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	528	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
bogdanm	0:9b334a45a8ff	529	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	530	} while(0)
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	533	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	534	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	535	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	536	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	537	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	538	} while(0)
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	541	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	542	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	543	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	544	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	545	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	546	} while(0)
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	549	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	550	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	551	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	552	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	553	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	554	} while(0)
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	557	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	558	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	559	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	560	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	561	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	562	} while(0)
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	565	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	566	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	567	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	568	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	569	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	570	} while(0)
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	573	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	574	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	575	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	576	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	577	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	578	} while(0)
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	581	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	582	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	583	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	584	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	585	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	586	} while(0)
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	589	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	591	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	593	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	594	} while(0)
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	597	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	599	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	601	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	602	} while(0)
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	605	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	606	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	607	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	608	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	609	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	610	} while(0)
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	613	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	614	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	615	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	616	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	617	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	618	} while(0)
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	621	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	622	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
bogdanm	0:9b334a45a8ff	623	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	624	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
bogdanm	0:9b334a45a8ff	625	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	626	} while(0)
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	629	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	630	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
bogdanm	0:9b334a45a8ff	631	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	632	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
bogdanm	0:9b334a45a8ff	633	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	634	} while(0)
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
bogdanm	0:9b334a45a8ff	637	#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
bogdanm	0:9b334a45a8ff	638	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
bogdanm	0:9b334a45a8ff	639	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	0:9b334a45a8ff	641	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	0:9b334a45a8ff	642	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
bogdanm	0:9b334a45a8ff	643	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
bogdanm	0:9b334a45a8ff	644	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
bogdanm	0:9b334a45a8ff	645	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
bogdanm	0:9b334a45a8ff	646	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
bogdanm	0:9b334a45a8ff	647	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	0:9b334a45a8ff	648	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	0:9b334a45a8ff	649	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
bogdanm	0:9b334a45a8ff	650	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm	0:9b334a45a8ff	651	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
bogdanm	0:9b334a45a8ff	652	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
bogdanm	0:9b334a45a8ff	653	/**
bogdanm	0:9b334a45a8ff	654	* @brief Enable ETHERNET clock.
bogdanm	0:9b334a45a8ff	655	*/
bogdanm	0:9b334a45a8ff	656	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	657	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	658	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	659	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	660	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	661	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	662	} while(0)
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	665	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	666	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	667	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	668	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	669	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	670	} while(0)
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	673	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	674	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	675	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	676	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	677	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	678	} while(0)
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	681	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	682	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	683	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	684	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	685	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	686	} while(0)
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	689	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	690	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	691	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	692	} while(0)
bogdanm	0:9b334a45a8ff	693	/**
bogdanm	0:9b334a45a8ff	694	* @brief Disable ETHERNET clock.
bogdanm	0:9b334a45a8ff	695	*/
bogdanm	0:9b334a45a8ff	696	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm	0:9b334a45a8ff	697	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm	0:9b334a45a8ff	698	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm	0:9b334a45a8ff	699	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	0:9b334a45a8ff	700	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
bogdanm	0:9b334a45a8ff	701	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	702	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	703	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	704	} while(0)
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	707	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	708	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	709	* using it.
bogdanm	0:9b334a45a8ff	710	*/
bogdanm	0:9b334a45a8ff	711	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	712	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	713	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	714	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	715	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	716	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	717	} while(0)
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	720	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	721	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
bogdanm	0:9b334a45a8ff	722	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	723	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
bogdanm	0:9b334a45a8ff	724	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	725	} while(0)
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	728	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	729	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
bogdanm	0:9b334a45a8ff	730	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	731	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
bogdanm	0:9b334a45a8ff	732	UNUSED(tmpreg); \
mbed_official	83:a036322b8637	733	__HAL_RCC_SYSCFG_CLK_ENABLE();\
bogdanm	0:9b334a45a8ff	734	} while(0)
bogdanm	0:9b334a45a8ff	735
mbed_official	83:a036322b8637	736	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	0:9b334a45a8ff	737	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
bogdanm	0:9b334a45a8ff	738
mbed_official	83:a036322b8637	739	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
bogdanm	0:9b334a45a8ff	740	#if defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	741	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	742	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	743	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	744	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	745	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	746	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	747	} while(0)
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	750	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	751	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	752	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	753	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	754	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	755	} while(0)
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm	0:9b334a45a8ff	758	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	0:9b334a45a8ff	759	#endif /* STM32F756x */
mbed_official	83:a036322b8637	760
bogdanm	0:9b334a45a8ff	761	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	762	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	763	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	764	* using it.
bogdanm	0:9b334a45a8ff	765	*/
bogdanm	0:9b334a45a8ff	766	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	767	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	768	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	769	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	770	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	771	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	772	} while(0)
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	775	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	776	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
bogdanm	0:9b334a45a8ff	777	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	778	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
bogdanm	0:9b334a45a8ff	779	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	780	} while(0)
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm	0:9b334a45a8ff	783	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	786	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	787	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	788	* using it.
bogdanm	0:9b334a45a8ff	789	*/
bogdanm	0:9b334a45a8ff	790	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	791	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	792	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	793	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	794	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	795	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	796	} while(0)
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	799	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	800	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	801	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	802	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	803	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	804	} while(0)
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	807	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
bogdanm	0:9b334a45a8ff	809	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
bogdanm	0:9b334a45a8ff	811	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	812	} while(0)
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	815	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	816	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
bogdanm	0:9b334a45a8ff	817	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	818	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
bogdanm	0:9b334a45a8ff	819	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	820	} while(0)
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	823	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	824	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	825	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	826	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	827	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	828	} while(0)
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	831	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	832	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	833	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	834	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	835	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	836	} while(0)
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	839	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	840	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	841	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	842	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	843	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	844	} while(0)
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	847	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	848	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	849	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	850	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	851	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	852	} while(0)
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	855	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	856	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	857	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	858	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	859	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	860	} while(0)
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	863	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	864	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
bogdanm	0:9b334a45a8ff	865	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	866	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
bogdanm	0:9b334a45a8ff	867	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	868	} while(0)
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	871	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	872	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm	0:9b334a45a8ff	873	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	874	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm	0:9b334a45a8ff	875	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	876	} while(0)
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	879	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	880	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
bogdanm	0:9b334a45a8ff	881	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	882	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
bogdanm	0:9b334a45a8ff	883	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	884	} while(0)
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	887	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	888	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
bogdanm	0:9b334a45a8ff	889	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	890	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
bogdanm	0:9b334a45a8ff	891	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	892	} while(0)
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	895	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	896	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	897	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	898	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	899	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	900	} while(0)
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	903	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	904	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	905	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	906	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	907	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	908	} while(0)
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	911	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	912	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	913	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	914	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	915	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	916	} while(0)
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	919	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	920	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	921	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	922	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	923	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	924	} while(0)
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	927	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	928	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	929	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	930	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	931	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	932	} while(0)
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	935	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm	0:9b334a45a8ff	937	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm	0:9b334a45a8ff	939	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	940	} while(0)
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	943	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
bogdanm	0:9b334a45a8ff	945	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
bogdanm	0:9b334a45a8ff	947	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	948	} while(0)
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	951	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	952	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
bogdanm	0:9b334a45a8ff	953	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	954	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
bogdanm	0:9b334a45a8ff	955	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	956	} while(0)
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	959	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	960	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	961	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	962	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	963	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	964	} while(0)
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	967	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	968	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	969	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	970	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	971	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	972	} while(0)
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	975	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	976	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	977	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	978	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	979	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	980	} while(0)
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	983	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	984	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	985	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	986	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	987	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	988	} while(0)
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	991	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	992	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
bogdanm	0:9b334a45a8ff	993	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	994	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
bogdanm	0:9b334a45a8ff	995	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	996	} while(0)
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	999	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
bogdanm	0:9b334a45a8ff	1001	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
bogdanm	0:9b334a45a8ff	1003	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1004	} while(0)
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	1007	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	1008	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm	0:9b334a45a8ff	1009	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm	0:9b334a45a8ff	1010	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	1011	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	1012	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	0:9b334a45a8ff	1013	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	0:9b334a45a8ff	1014	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	0:9b334a45a8ff	1015	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	1016	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	1017	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	0:9b334a45a8ff	1018	#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
bogdanm	0:9b334a45a8ff	1019	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	1020	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	0:9b334a45a8ff	1021	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	0:9b334a45a8ff	1022	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	0:9b334a45a8ff	1023	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	1024	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	1025	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm	0:9b334a45a8ff	1026	#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
bogdanm	0:9b334a45a8ff	1027	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	0:9b334a45a8ff	1028	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	0:9b334a45a8ff	1029	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	0:9b334a45a8ff	1030	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	1031	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
bogdanm	0:9b334a45a8ff	1032	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	1035	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1036	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1037	* using it.
bogdanm	0:9b334a45a8ff	1038	*/
bogdanm	0:9b334a45a8ff	1039	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1040	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1041	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	1042	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1043	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	1044	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1045	} while(0)
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1048	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1049	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1050	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1051	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1052	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1053	} while(0)
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1056	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1057	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	1058	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1059	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	1060	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1061	} while(0)
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1064	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1065	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm	0:9b334a45a8ff	1066	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1067	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm	0:9b334a45a8ff	1068	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1069	} while(0)
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1072	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1073	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	1074	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1075	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	1076	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1077	} while(0)
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1080	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1081	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1082	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1083	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1084	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1085	} while(0)
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1088	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1089	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1090	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1091	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1092	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1093	} while(0)
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1096	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1097	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
bogdanm	0:9b334a45a8ff	1098	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1099	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
bogdanm	0:9b334a45a8ff	1100	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1101	} while(0)
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1104	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1105	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	1106	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1107	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	1108	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1109	} while(0)
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1112	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1113	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
bogdanm	0:9b334a45a8ff	1114	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1115	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
bogdanm	0:9b334a45a8ff	1116	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1117	} while(0)
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1120	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1121	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
bogdanm	0:9b334a45a8ff	1122	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1123	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
bogdanm	0:9b334a45a8ff	1124	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1125	} while(0)
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1128	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1129	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
bogdanm	0:9b334a45a8ff	1130	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1131	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
bogdanm	0:9b334a45a8ff	1132	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1133	} while(0)
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1136	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1137	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
bogdanm	0:9b334a45a8ff	1138	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1139	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
bogdanm	0:9b334a45a8ff	1140	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1141	} while(0)
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1144	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1145	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	1146	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1147	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	1148	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1149	} while(0)
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1152	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1153	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
bogdanm	0:9b334a45a8ff	1154	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1155	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
bogdanm	0:9b334a45a8ff	1156	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1157	} while(0)
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1160	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1161	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	1162	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1163	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	1164	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1165	} while(0)
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1168	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1169	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
bogdanm	0:9b334a45a8ff	1170	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1171	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
bogdanm	0:9b334a45a8ff	1172	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1173	} while(0)
bogdanm	0:9b334a45a8ff	1174
mbed_official	83:a036322b8637	1175	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1176	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
mbed_official	83:a036322b8637	1177	__IO uint32_t tmpreg = 0x00; \
bogdanm	0:9b334a45a8ff	1178	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
bogdanm	0:9b334a45a8ff	1179	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1180	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
bogdanm	0:9b334a45a8ff	1181	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1182	} while(0)
mbed_official	83:a036322b8637	1183	#endif /* STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	1184
bogdanm	0:9b334a45a8ff	1185	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	0:9b334a45a8ff	1186	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	0:9b334a45a8ff	1187	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	1188	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm	0:9b334a45a8ff	1189	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	1190	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	0:9b334a45a8ff	1191	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	83:a036322b8637	1192	#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
bogdanm	0:9b334a45a8ff	1193	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	1194	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm	0:9b334a45a8ff	1195	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
bogdanm	0:9b334a45a8ff	1196	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
bogdanm	0:9b334a45a8ff	1197	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
bogdanm	0:9b334a45a8ff	1198	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm	0:9b334a45a8ff	1199	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
bogdanm	0:9b334a45a8ff	1200	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm	0:9b334a45a8ff	1201	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
mbed_official	83:a036322b8637	1202	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1203	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official	83:a036322b8637	1204	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1205	/**
bogdanm	0:9b334a45a8ff	1206	* @}
bogdanm	0:9b334a45a8ff	1207	*/
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	1211	* @brief Get the enable or disable status of the AHB/APB peripheral clock.
bogdanm	0:9b334a45a8ff	1212	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1213	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1214	* using it.
bogdanm	0:9b334a45a8ff	1215	* @{
bogdanm	0:9b334a45a8ff	1216	*/
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/** @brief Get the enable or disable status of the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	1219	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1220	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1221	* using it.
bogdanm	0:9b334a45a8ff	1222	*/
bogdanm	0:9b334a45a8ff	1223	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
bogdanm	0:9b334a45a8ff	1224	#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
bogdanm	0:9b334a45a8ff	1225	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1226	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
bogdanm	0:9b334a45a8ff	1227	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
bogdanm	0:9b334a45a8ff	1228	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
bogdanm	0:9b334a45a8ff	1229	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
bogdanm	0:9b334a45a8ff	1230	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
bogdanm	0:9b334a45a8ff	1231	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
bogdanm	0:9b334a45a8ff	1232	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
bogdanm	0:9b334a45a8ff	1233	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
bogdanm	0:9b334a45a8ff	1234	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
bogdanm	0:9b334a45a8ff	1235	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
bogdanm	0:9b334a45a8ff	1236	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
bogdanm	0:9b334a45a8ff	1237	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
bogdanm	0:9b334a45a8ff	1238	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
bogdanm	0:9b334a45a8ff	1239	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
bogdanm	0:9b334a45a8ff	1242	#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
bogdanm	0:9b334a45a8ff	1243	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1244	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
bogdanm	0:9b334a45a8ff	1245	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
bogdanm	0:9b334a45a8ff	1246	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
bogdanm	0:9b334a45a8ff	1247	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
bogdanm	0:9b334a45a8ff	1248	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
bogdanm	0:9b334a45a8ff	1249	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
bogdanm	0:9b334a45a8ff	1250	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
bogdanm	0:9b334a45a8ff	1251	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
bogdanm	0:9b334a45a8ff	1252	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
bogdanm	0:9b334a45a8ff	1253	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
bogdanm	0:9b334a45a8ff	1254	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
bogdanm	0:9b334a45a8ff	1255	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
bogdanm	0:9b334a45a8ff	1256	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
bogdanm	0:9b334a45a8ff	1257	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
bogdanm	0:9b334a45a8ff	1258	/**
bogdanm	0:9b334a45a8ff	1259	* @brief Enable ETHERNET clock.
bogdanm	0:9b334a45a8ff	1260	*/
bogdanm	0:9b334a45a8ff	1261	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
bogdanm	0:9b334a45a8ff	1262	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
bogdanm	0:9b334a45a8ff	1263	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
bogdanm	0:9b334a45a8ff	1264	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1265	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
bogdanm	0:9b334a45a8ff	1266	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
bogdanm	0:9b334a45a8ff	1267	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/**
bogdanm	0:9b334a45a8ff	1270	* @brief Disable ETHERNET clock.
bogdanm	0:9b334a45a8ff	1271	*/
bogdanm	0:9b334a45a8ff	1272	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
bogdanm	0:9b334a45a8ff	1273	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
bogdanm	0:9b334a45a8ff	1274	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
bogdanm	0:9b334a45a8ff	1275	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1276	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
bogdanm	0:9b334a45a8ff	1277	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
bogdanm	0:9b334a45a8ff	1278	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/** @brief Get the enable or disable status of the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	1281	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1282	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1283	* using it.
bogdanm	0:9b334a45a8ff	1284	*/
bogdanm	0:9b334a45a8ff	1285	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
bogdanm	0:9b334a45a8ff	1286	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
bogdanm	0:9b334a45a8ff	1287	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
mbed_official	83:a036322b8637	1288
bogdanm	0:9b334a45a8ff	1289	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
bogdanm	0:9b334a45a8ff	1290	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
bogdanm	0:9b334a45a8ff	1291	#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	#if defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	1294	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1295	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
bogdanm	0:9b334a45a8ff	1296	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1297	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
mbed_official	83:a036322b8637	1298	#endif /* STM32F756xx */
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/** @brief Get the enable or disable status of the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	1301	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1302	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1303	* using it.
bogdanm	0:9b334a45a8ff	1304	*/
bogdanm	0:9b334a45a8ff	1305	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
bogdanm	0:9b334a45a8ff	1306	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
bogdanm	0:9b334a45a8ff	1309	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/** @brief Get the enable or disable status of the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	1312	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1313	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1314	* using it.
bogdanm	0:9b334a45a8ff	1315	*/
bogdanm	0:9b334a45a8ff	1316	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1317	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1318	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
bogdanm	0:9b334a45a8ff	1319	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
bogdanm	0:9b334a45a8ff	1320	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
bogdanm	0:9b334a45a8ff	1321	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
bogdanm	0:9b334a45a8ff	1322	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
bogdanm	0:9b334a45a8ff	1323	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
bogdanm	0:9b334a45a8ff	1324	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
bogdanm	0:9b334a45a8ff	1325	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1326	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1327	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1328	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
bogdanm	0:9b334a45a8ff	1329	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1330	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1331	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
bogdanm	0:9b334a45a8ff	1332	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
bogdanm	0:9b334a45a8ff	1333	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1334	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1335	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1336	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
bogdanm	0:9b334a45a8ff	1337	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1338	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1339	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
bogdanm	0:9b334a45a8ff	1340	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
bogdanm	0:9b334a45a8ff	1341	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
bogdanm	0:9b334a45a8ff	1342	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
bogdanm	0:9b334a45a8ff	1343
bogdanm	0:9b334a45a8ff	1344	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1345	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1346	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
bogdanm	0:9b334a45a8ff	1347	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
bogdanm	0:9b334a45a8ff	1348	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
bogdanm	0:9b334a45a8ff	1349	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
bogdanm	0:9b334a45a8ff	1350	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
bogdanm	0:9b334a45a8ff	1351	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
bogdanm	0:9b334a45a8ff	1352	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
bogdanm	0:9b334a45a8ff	1353	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1354	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1355	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1356	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
bogdanm	0:9b334a45a8ff	1357	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1358	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1359	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
bogdanm	0:9b334a45a8ff	1360	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
bogdanm	0:9b334a45a8ff	1361	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1362	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1363	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1364	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
bogdanm	0:9b334a45a8ff	1365	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1366	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1367	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
bogdanm	0:9b334a45a8ff	1368	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
bogdanm	0:9b334a45a8ff	1369	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
bogdanm	0:9b334a45a8ff	1370	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/** @brief Get the enable or disable status of the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	1373	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1374	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1375	* using it.
bogdanm	0:9b334a45a8ff	1376	*/
bogdanm	0:9b334a45a8ff	1377	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1378	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
bogdanm	0:9b334a45a8ff	1379	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1380	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
bogdanm	0:9b334a45a8ff	1381	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1382	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1383	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1384	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1385	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1386	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
bogdanm	0:9b334a45a8ff	1387	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
bogdanm	0:9b334a45a8ff	1388	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
bogdanm	0:9b334a45a8ff	1389	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
bogdanm	0:9b334a45a8ff	1390	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
bogdanm	0:9b334a45a8ff	1391	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
bogdanm	0:9b334a45a8ff	1392	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1393	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
mbed_official	83:a036322b8637	1394	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1395	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
mbed_official	83:a036322b8637	1396	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1397	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1398	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
bogdanm	0:9b334a45a8ff	1399	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1400	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
bogdanm	0:9b334a45a8ff	1401	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1402	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1403	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1404	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1405	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1406	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
bogdanm	0:9b334a45a8ff	1407	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
bogdanm	0:9b334a45a8ff	1408	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
bogdanm	0:9b334a45a8ff	1409	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
bogdanm	0:9b334a45a8ff	1410	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
bogdanm	0:9b334a45a8ff	1411	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
bogdanm	0:9b334a45a8ff	1412	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1413	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
mbed_official	83:a036322b8637	1414	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1415	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
mbed_official	83:a036322b8637	1416	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1417	/**
bogdanm	0:9b334a45a8ff	1418	* @}
bogdanm	0:9b334a45a8ff	1419	*/
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm	0:9b334a45a8ff	1422	* @brief Forces or releases AHB/APB peripheral reset.
bogdanm	0:9b334a45a8ff	1423	* @{
bogdanm	0:9b334a45a8ff	1424	*/
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/** @brief Force or release AHB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1427	*/
bogdanm	0:9b334a45a8ff	1428	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
bogdanm	0:9b334a45a8ff	1429	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
bogdanm	0:9b334a45a8ff	1430	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	1431	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1432	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	1433	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	1434	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	1435	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	1436	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	1437	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1438	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1439	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	1440	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	1441	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
bogdanm	0:9b334a45a8ff	1442	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
bogdanm	0:9b334a45a8ff	1445	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
bogdanm	0:9b334a45a8ff	1446	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	1447	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1448	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	1449	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	1450	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	1451	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	1452	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	1453	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1454	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1455	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	1456	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	1457	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
bogdanm	0:9b334a45a8ff	1458	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/** @brief Force or release AHB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1461	*/
bogdanm	0:9b334a45a8ff	1462	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1463	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1464	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
bogdanm	0:9b334a45a8ff	1465	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
bogdanm	0:9b334a45a8ff	1468	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1469	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
bogdanm	0:9b334a45a8ff	1470	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	#if defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	1473	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	1474	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	1475	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	1476	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	1477	#endif /* STM32F756xx */
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/** @brief Force or release AHB3 peripheral reset
bogdanm	0:9b334a45a8ff	1480	*/
bogdanm	0:9b334a45a8ff	1481	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	1482	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	1483	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
bogdanm	0:9b334a45a8ff	1486	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	1487	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1490	*/
bogdanm	0:9b334a45a8ff	1491	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	1492	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	1493	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
bogdanm	0:9b334a45a8ff	1494	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
bogdanm	0:9b334a45a8ff	1495	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1496	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1497	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1498	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1499	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1500	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	1501	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	1502	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	0:9b334a45a8ff	1503	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
bogdanm	0:9b334a45a8ff	1504	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	1505	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1506	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1507	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1508	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	1509	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	1510	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	0:9b334a45a8ff	1511	#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C4RST))
bogdanm	0:9b334a45a8ff	1512	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1513	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1514	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1515	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1516	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
bogdanm	0:9b334a45a8ff	1517	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	1520	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	1521	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm	0:9b334a45a8ff	1522	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm	0:9b334a45a8ff	1523	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1524	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1525	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1526	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1527	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1528	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	1529	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	1530	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	0:9b334a45a8ff	1531	#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
bogdanm	0:9b334a45a8ff	1532	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	1533	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1534	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1535	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1536	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	1537	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	1538	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm	0:9b334a45a8ff	1539	#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
bogdanm	0:9b334a45a8ff	1540	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1541	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1542	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1543	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1544	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
bogdanm	0:9b334a45a8ff	1545	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1548	*/
bogdanm	0:9b334a45a8ff	1549	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	1550	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1551	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	1552	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
bogdanm	0:9b334a45a8ff	1553	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
bogdanm	0:9b334a45a8ff	1554	#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC1RST))
bogdanm	0:9b334a45a8ff	1555	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	1556	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
bogdanm	0:9b334a45a8ff	1557	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
bogdanm	0:9b334a45a8ff	1558	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
bogdanm	0:9b334a45a8ff	1559	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
bogdanm	0:9b334a45a8ff	1560	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	1561	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
bogdanm	0:9b334a45a8ff	1562	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	1563	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
mbed_official	83:a036322b8637	1564	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1565	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
mbed_official	83:a036322b8637	1566	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	1569	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1570	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	1571	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm	0:9b334a45a8ff	1572	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
bogdanm	0:9b334a45a8ff	1573	#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
bogdanm	0:9b334a45a8ff	1574	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	1575	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm	0:9b334a45a8ff	1576	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
bogdanm	0:9b334a45a8ff	1577	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
bogdanm	0:9b334a45a8ff	1578	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
bogdanm	0:9b334a45a8ff	1579	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	1580	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
bogdanm	0:9b334a45a8ff	1581	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	1582	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
mbed_official	83:a036322b8637	1583	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1584	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official	83:a036322b8637	1585	#endif /* STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	1586
bogdanm	0:9b334a45a8ff	1587	/**
bogdanm	0:9b334a45a8ff	1588	* @}
bogdanm	0:9b334a45a8ff	1589	*/
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
bogdanm	0:9b334a45a8ff	1592	* @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1593	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1594	* power consumption.
bogdanm	0:9b334a45a8ff	1595	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1596	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1597	* @{
bogdanm	0:9b334a45a8ff	1598	*/
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1601	*/
bogdanm	0:9b334a45a8ff	1602	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
bogdanm	0:9b334a45a8ff	1603	#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_AXILPEN))
bogdanm	0:9b334a45a8ff	1604	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	0:9b334a45a8ff	1605	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1606	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	0:9b334a45a8ff	1607	#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DTCMLPEN))
bogdanm	0:9b334a45a8ff	1608	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm	0:9b334a45a8ff	1609	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	0:9b334a45a8ff	1610	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	1611	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	1612	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	1613	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	1614	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1615	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1616	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
bogdanm	0:9b334a45a8ff	1617	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	0:9b334a45a8ff	1618	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	0:9b334a45a8ff	1619	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
bogdanm	0:9b334a45a8ff	1620	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
bogdanm	0:9b334a45a8ff	1621	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1622	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1623	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	0:9b334a45a8ff	1624	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	1625	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	0:9b334a45a8ff	1626	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
bogdanm	0:9b334a45a8ff	1629	#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
bogdanm	0:9b334a45a8ff	1630	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	0:9b334a45a8ff	1631	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1632	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	0:9b334a45a8ff	1633	#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
bogdanm	0:9b334a45a8ff	1634	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
bogdanm	0:9b334a45a8ff	1635	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	0:9b334a45a8ff	1636	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	1637	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	1638	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	1639	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	1640	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1641	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1642	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
bogdanm	0:9b334a45a8ff	1643	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	0:9b334a45a8ff	1644	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	0:9b334a45a8ff	1645	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
bogdanm	0:9b334a45a8ff	1646	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
bogdanm	0:9b334a45a8ff	1647	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1648	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1649	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	0:9b334a45a8ff	1650	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	1651	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	0:9b334a45a8ff	1652	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1655	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1656	* power consumption.
bogdanm	0:9b334a45a8ff	1657	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1658	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1659	*/
bogdanm	0:9b334a45a8ff	1660	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1661	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official	83:a036322b8637	1662
bogdanm	0:9b334a45a8ff	1663	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
bogdanm	0:9b334a45a8ff	1664	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	0:9b334a45a8ff	1667	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	0:9b334a45a8ff	1668
bogdanm	0:9b334a45a8ff	1669	#if defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	1670	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1671	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1674	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1675	#endif /* STM32F756xx */
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1678	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1679	* power consumption.
bogdanm	0:9b334a45a8ff	1680	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1681	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1682	*/
bogdanm	0:9b334a45a8ff	1683	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1684	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
bogdanm	0:9b334a45a8ff	1687	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1690	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1691	* power consumption.
bogdanm	0:9b334a45a8ff	1692	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1693	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1694	*/
bogdanm	0:9b334a45a8ff	1695	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
bogdanm	0:9b334a45a8ff	1696	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
bogdanm	0:9b334a45a8ff	1697	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
bogdanm	0:9b334a45a8ff	1698	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
bogdanm	0:9b334a45a8ff	1699	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1700	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1701	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1702	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1703	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1704	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
bogdanm	0:9b334a45a8ff	1705	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
bogdanm	0:9b334a45a8ff	1706	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
bogdanm	0:9b334a45a8ff	1707	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
bogdanm	0:9b334a45a8ff	1708	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
bogdanm	0:9b334a45a8ff	1709	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1710	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1711	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1712	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
bogdanm	0:9b334a45a8ff	1713	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
bogdanm	0:9b334a45a8ff	1714	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
bogdanm	0:9b334a45a8ff	1715	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C4LPEN))
bogdanm	0:9b334a45a8ff	1716	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1717	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1718	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
bogdanm	0:9b334a45a8ff	1719	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1720	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
bogdanm	0:9b334a45a8ff	1721	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
bogdanm	0:9b334a45a8ff	1724	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
bogdanm	0:9b334a45a8ff	1725	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
bogdanm	0:9b334a45a8ff	1726	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
bogdanm	0:9b334a45a8ff	1727	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1728	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1729	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1730	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1731	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1732	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
bogdanm	0:9b334a45a8ff	1733	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
bogdanm	0:9b334a45a8ff	1734	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
bogdanm	0:9b334a45a8ff	1735	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
bogdanm	0:9b334a45a8ff	1736	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
bogdanm	0:9b334a45a8ff	1737	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1738	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1739	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1740	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
bogdanm	0:9b334a45a8ff	1741	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
bogdanm	0:9b334a45a8ff	1742	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
bogdanm	0:9b334a45a8ff	1743	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
bogdanm	0:9b334a45a8ff	1744	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1745	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1746	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
bogdanm	0:9b334a45a8ff	1747	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	83:a036322b8637	1748	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official	83:a036322b8637	1749	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1752	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1753	* power consumption.
bogdanm	0:9b334a45a8ff	1754	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1755	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1756	*/
bogdanm	0:9b334a45a8ff	1757	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
bogdanm	0:9b334a45a8ff	1758	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1759	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
bogdanm	0:9b334a45a8ff	1760	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
bogdanm	0:9b334a45a8ff	1761	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
bogdanm	0:9b334a45a8ff	1762	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1763	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1764	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC1LPEN))
bogdanm	0:9b334a45a8ff	1765	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
bogdanm	0:9b334a45a8ff	1766	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
bogdanm	0:9b334a45a8ff	1767	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
bogdanm	0:9b334a45a8ff	1768	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
bogdanm	0:9b334a45a8ff	1769	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
bogdanm	0:9b334a45a8ff	1770	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1771	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
bogdanm	0:9b334a45a8ff	1772	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1773	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
mbed_official	83:a036322b8637	1774	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1775	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
mbed_official	83:a036322b8637	1776	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
bogdanm	0:9b334a45a8ff	1779	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1780	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
bogdanm	0:9b334a45a8ff	1781	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
bogdanm	0:9b334a45a8ff	1782	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
bogdanm	0:9b334a45a8ff	1783	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1784	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1785	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
bogdanm	0:9b334a45a8ff	1786	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
bogdanm	0:9b334a45a8ff	1787	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
bogdanm	0:9b334a45a8ff	1788	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
bogdanm	0:9b334a45a8ff	1789	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
bogdanm	0:9b334a45a8ff	1790	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
bogdanm	0:9b334a45a8ff	1791	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1792	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
bogdanm	0:9b334a45a8ff	1793	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1794	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
mbed_official	83:a036322b8637	1795	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1796	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official	83:a036322b8637	1797	#endif /* STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	1798
bogdanm	0:9b334a45a8ff	1799	/**
bogdanm	0:9b334a45a8ff	1800	* @}
bogdanm	0:9b334a45a8ff	1801	*/
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
bogdanm	0:9b334a45a8ff	1804	* @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1805	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1806	* power consumption.
bogdanm	0:9b334a45a8ff	1807	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1808	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1809	* @{
bogdanm	0:9b334a45a8ff	1810	*/
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1813	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1814	* power consumption.
bogdanm	0:9b334a45a8ff	1815	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1816	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1817	*/
bogdanm	0:9b334a45a8ff	1818	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1819	#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1820	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1821	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1822	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1823	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1824	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1825	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1826	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1827	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1828	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1829	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1830	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1831	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1832	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1833	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1834	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1835	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1836	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1837	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1838	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1839	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1840	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1841	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1842	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1845	#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1846	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1847	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1848	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1849	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1850	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1851	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1852	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1853	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1854	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1855	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1856	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1857	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1858	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1859	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1860	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1861	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1862	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1863	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1864	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1865	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1866	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1867	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1868	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1869
bogdanm	0:9b334a45a8ff	1870	/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1871	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1872	* power consumption.
bogdanm	0:9b334a45a8ff	1873	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1874	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1875	*/
bogdanm	0:9b334a45a8ff	1876	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1877	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
mbed_official	83:a036322b8637	1878
bogdanm	0:9b334a45a8ff	1879	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1880	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1881
bogdanm	0:9b334a45a8ff	1882	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1883	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1884
bogdanm	0:9b334a45a8ff	1885	#if defined(STM32F756xx)
bogdanm	0:9b334a45a8ff	1886	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1887	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1888
bogdanm	0:9b334a45a8ff	1889	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1890	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1891	#endif /* STM32F756xx */
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1894	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1895	* power consumption.
bogdanm	0:9b334a45a8ff	1896	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1897	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1898	*/
bogdanm	0:9b334a45a8ff	1899	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1900	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1903	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1906	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1907	* power consumption.
bogdanm	0:9b334a45a8ff	1908	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1909	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1910	*/
bogdanm	0:9b334a45a8ff	1911	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1912	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1913	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1914	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1915	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1916	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1917	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1918	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1919	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1920	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1921	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1922	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1923	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1924	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1925	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1926	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1927	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1928	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1929	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1930	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1931	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1932	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1933	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1934	#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1935	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1936	#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1937	#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1938
bogdanm	0:9b334a45a8ff	1939	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1940	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1941	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1942	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1943	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1944	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1945	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1946	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1947	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1948	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1949	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1950	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1951	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1952	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1953	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1954	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1955	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1956	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1957	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1958	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1959	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1960	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1961	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1962	#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1963	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1964	#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1965	#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1968	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1969	* power consumption.
bogdanm	0:9b334a45a8ff	1970	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1971	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1972	*/
bogdanm	0:9b334a45a8ff	1973	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1974	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1975	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1976	#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1977	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1978	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1979	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1980	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1981	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1982	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1983	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1984	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1985	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1986	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1987	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1988	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
bogdanm	0:9b334a45a8ff	1989	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
mbed_official	83:a036322b8637	1990	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	1991	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
mbed_official	83:a036322b8637	1992	#endif /* STM32F746xx \|\| STM32F756xx */
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1995	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1996	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1997	#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1998	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	1999	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2000	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2001	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2002	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2003	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2004	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2005	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2006	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2007	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2008	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2009	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
bogdanm	0:9b334a45a8ff	2010	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
mbed_official	83:a036322b8637	2011	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
bogdanm	0:9b334a45a8ff	2012	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
mbed_official	83:a036322b8637	2013	#endif /* STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	2014
bogdanm	0:9b334a45a8ff	2015	/**
bogdanm	0:9b334a45a8ff	2016	* @}
bogdanm	0:9b334a45a8ff	2017	*/
mbed_official	83:a036322b8637	2018
bogdanm	0:9b334a45a8ff	2019	/---------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	/** @brief Macro to configure the Timers clocks prescalers
bogdanm	0:9b334a45a8ff	2022	* @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm	0:9b334a45a8ff	2023	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2024	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm	0:9b334a45a8ff	2025	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm	0:9b334a45a8ff	2026	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm	0:9b334a45a8ff	2027	* division by 4 or more.
bogdanm	0:9b334a45a8ff	2028	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm	0:9b334a45a8ff	2029	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm	0:9b334a45a8ff	2030	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm	0:9b334a45a8ff	2031	* to division by 8 or more.
bogdanm	0:9b334a45a8ff	2032	*/
bogdanm	0:9b334a45a8ff	2033	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
mbed_official	83:a036322b8637	2034	RCC->DCKCFGR1 \|= (__PRESC__); \
mbed_official	83:a036322b8637	2035	}while(0)
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	/** @brief Macros to Enable or Disable the PLLISAI.
bogdanm	0:9b334a45a8ff	2038	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2039	*/
bogdanm	0:9b334a45a8ff	2040	#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR \|= (RCC_CR_PLLSAION))
bogdanm	0:9b334a45a8ff	2041	#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
bogdanm	0:9b334a45a8ff	2042
bogdanm	0:9b334a45a8ff	2043	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm	0:9b334a45a8ff	2044	* @note This function must be used only when the PLLSAI is disabled.
bogdanm	0:9b334a45a8ff	2045	* @note PLLSAI clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2046	* RCC_PLLConfig function )
bogdanm	0:9b334a45a8ff	2047	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official	83:a036322b8637	2048	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2049	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official	83:a036322b8637	2050	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
mbed_official	83:a036322b8637	2051	* @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
mbed_official	83:a036322b8637	2052	* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
bogdanm	0:9b334a45a8ff	2053	* @param __PLLSAIQ__: specifies the division factor for SAI clock
bogdanm	0:9b334a45a8ff	2054	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2055	* @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm	0:9b334a45a8ff	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2057	*/
mbed_official	83:a036322b8637	2058	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
mbed_official	83:a036322b8637	2059	(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
mbed_official	83:a036322b8637	2060	((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
mbed_official	83:a036322b8637	2061	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
mbed_official	83:a036322b8637	2062	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
bogdanm	0:9b334a45a8ff	2063
mbed_official	83:a036322b8637	2064	/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
bogdanm	0:9b334a45a8ff	2065	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2066	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2067	* HAL_RCC_ClockConfig() API)
bogdanm	0:9b334a45a8ff	2068	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	83:a036322b8637	2069	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2070	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	83:a036322b8637	2071	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
mbed_official	83:a036322b8637	2072	* @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
mbed_official	83:a036322b8637	2073	* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
bogdanm	0:9b334a45a8ff	2074	* @param __PLLI2SQ__: specifies the division factor for SAI clock.
bogdanm	0:9b334a45a8ff	2075	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2076	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	0:9b334a45a8ff	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2078	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	83:a036322b8637	2079	* on the I2S clock frequency.
bogdanm	0:9b334a45a8ff	2080	*/
mbed_official	83:a036322b8637	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
mbed_official	83:a036322b8637	2082	(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
mbed_official	83:a036322b8637	2083	((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
mbed_official	83:a036322b8637	2084	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
mbed_official	83:a036322b8637	2085	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
bogdanm	0:9b334a45a8ff	2086
bogdanm	0:9b334a45a8ff	2087	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
bogdanm	0:9b334a45a8ff	2088	* @note This function must be called before enabling the PLLI2S.
bogdanm	0:9b334a45a8ff	2089	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
bogdanm	0:9b334a45a8ff	2090	* This parameter must be a number between 1 and 32.
bogdanm	0:9b334a45a8ff	2091	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
bogdanm	0:9b334a45a8ff	2092	*/
bogdanm	0:9b334a45a8ff	2093	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
bogdanm	0:9b334a45a8ff	2096	* @note This function must be called before enabling the PLLSAI.
bogdanm	0:9b334a45a8ff	2097	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
bogdanm	0:9b334a45a8ff	2098	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
bogdanm	0:9b334a45a8ff	2099	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
bogdanm	0:9b334a45a8ff	2100	*/
bogdanm	0:9b334a45a8ff	2101	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
bogdanm	0:9b334a45a8ff	2104	*
bogdanm	0:9b334a45a8ff	2105	* @note This function must be called before enabling the PLLSAI.
bogdanm	0:9b334a45a8ff	2106	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official	83:a036322b8637	2107	* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
bogdanm	0:9b334a45a8ff	2108	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
bogdanm	0:9b334a45a8ff	2109	*/
bogdanm	0:9b334a45a8ff	2110	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
bogdanm	0:9b334a45a8ff	2111	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
bogdanm	0:9b334a45a8ff	2112
bogdanm	0:9b334a45a8ff	2113	/** @brief Macro to configure SAI1 clock source selection.
bogdanm	0:9b334a45a8ff	2114	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2115	* the SAI clock.
bogdanm	0:9b334a45a8ff	2116	* @param __SOURCE__: specifies the SAI1 clock source.
bogdanm	0:9b334a45a8ff	2117	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2118	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2119	* as SAI1 clock.
bogdanm	0:9b334a45a8ff	2120	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2121	* as SAI1 clock.
bogdanm	0:9b334a45a8ff	2122	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2123	* used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2124	*/
bogdanm	0:9b334a45a8ff	2125	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
bogdanm	0:9b334a45a8ff	2126	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
bogdanm	0:9b334a45a8ff	2127
bogdanm	0:9b334a45a8ff	2128	/** @brief Macro to get the SAI1 clock source.
bogdanm	0:9b334a45a8ff	2129	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2130	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2131	* as SAI1 clock.
bogdanm	0:9b334a45a8ff	2132	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2133	* as SAI1 clock.
bogdanm	0:9b334a45a8ff	2134	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2135	* used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2136	*/
bogdanm	0:9b334a45a8ff	2137	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
bogdanm	0:9b334a45a8ff	2138
bogdanm	0:9b334a45a8ff	2139
bogdanm	0:9b334a45a8ff	2140	/** @brief Macro to configure SAI2 clock source selection.
bogdanm	0:9b334a45a8ff	2141	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2142	* the SAI clock.
bogdanm	0:9b334a45a8ff	2143	* @param __SOURCE__: specifies the SAI2 clock source.
bogdanm	0:9b334a45a8ff	2144	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2145	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2146	* as SAI2 clock.
bogdanm	0:9b334a45a8ff	2147	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2148	* as SAI2 clock.
bogdanm	0:9b334a45a8ff	2149	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2150	* used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2151	*/
bogdanm	0:9b334a45a8ff	2152	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
bogdanm	0:9b334a45a8ff	2153	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
bogdanm	0:9b334a45a8ff	2154
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	/** @brief Macro to get the SAI2 clock source.
bogdanm	0:9b334a45a8ff	2157	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2158	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2159	* as SAI2 clock.
bogdanm	0:9b334a45a8ff	2160	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2161	* as SAI2 clock.
bogdanm	0:9b334a45a8ff	2162	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2163	* used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2164	*/
bogdanm	0:9b334a45a8ff	2165	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167
bogdanm	0:9b334a45a8ff	2168	/** @brief Enable PLLSAI_RDY interrupt.
bogdanm	0:9b334a45a8ff	2169	*/
bogdanm	0:9b334a45a8ff	2170	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/** @brief Disable PLLSAI_RDY interrupt.
bogdanm	0:9b334a45a8ff	2173	*/
bogdanm	0:9b334a45a8ff	2174	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2175
bogdanm	0:9b334a45a8ff	2176	/** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm	0:9b334a45a8ff	2177	*/
bogdanm	0:9b334a45a8ff	2178	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
bogdanm	0:9b334a45a8ff	2179
bogdanm	0:9b334a45a8ff	2180	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	2181	* @retval The new state (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2182	*/
bogdanm	0:9b334a45a8ff	2183	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2184
bogdanm	0:9b334a45a8ff	2185	/** @brief Check PLLSAI RDY flag is set or not.
bogdanm	0:9b334a45a8ff	2186	* @retval The new state (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2187	*/
bogdanm	0:9b334a45a8ff	2188	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm	0:9b334a45a8ff	2189
bogdanm	0:9b334a45a8ff	2190	/** @brief Macro to Get I2S clock source selection.
bogdanm	0:9b334a45a8ff	2191	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2192	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
bogdanm	0:9b334a45a8ff	2193	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
bogdanm	0:9b334a45a8ff	2194	*/
bogdanm	0:9b334a45a8ff	2195	#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	0:9b334a45a8ff	2198	*
bogdanm	0:9b334a45a8ff	2199	* @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
bogdanm	0:9b334a45a8ff	2200	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2201	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2202	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2203	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2204	*/
bogdanm	0:9b334a45a8ff	2205	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2206	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/** @brief Macro to get the I2C1 clock source.
bogdanm	0:9b334a45a8ff	2209	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2210	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2211	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2212	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	2213	*/
bogdanm	0:9b334a45a8ff	2214	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
bogdanm	0:9b334a45a8ff	2215
bogdanm	0:9b334a45a8ff	2216	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm	0:9b334a45a8ff	2217	*
bogdanm	0:9b334a45a8ff	2218	* @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
bogdanm	0:9b334a45a8ff	2219	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2220	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2221	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2222	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2223	*/
bogdanm	0:9b334a45a8ff	2224	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2225	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/** @brief Macro to get the I2C2 clock source.
bogdanm	0:9b334a45a8ff	2228	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2229	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2230	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2231	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	0:9b334a45a8ff	2232	*/
bogdanm	0:9b334a45a8ff	2233	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
bogdanm	0:9b334a45a8ff	2234
bogdanm	0:9b334a45a8ff	2235	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
bogdanm	0:9b334a45a8ff	2236	*
bogdanm	0:9b334a45a8ff	2237	* @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
bogdanm	0:9b334a45a8ff	2238	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2239	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2240	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2241	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2242	*/
bogdanm	0:9b334a45a8ff	2243	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2244	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	/** @brief macro to get the I2C3 clock source.
bogdanm	0:9b334a45a8ff	2247	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2248	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2249	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2250	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	0:9b334a45a8ff	2251	*/
bogdanm	0:9b334a45a8ff	2252	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
bogdanm	0:9b334a45a8ff	2253
bogdanm	0:9b334a45a8ff	2254	/** @brief Macro to configure the I2C4 clock (I2C4CLK).
bogdanm	0:9b334a45a8ff	2255	*
bogdanm	0:9b334a45a8ff	2256	* @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
bogdanm	0:9b334a45a8ff	2257	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2258	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2259	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2260	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2261	*/
bogdanm	0:9b334a45a8ff	2262	#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2263	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	/** @brief macro to get the I2C4 clock source.
bogdanm	0:9b334a45a8ff	2266	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2267	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2268	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2269	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
bogdanm	0:9b334a45a8ff	2270	*/
bogdanm	0:9b334a45a8ff	2271	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	0:9b334a45a8ff	2274	*
bogdanm	0:9b334a45a8ff	2275	* @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
bogdanm	0:9b334a45a8ff	2276	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2277	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	2278	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	2279	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	2280	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	2281	*/
bogdanm	0:9b334a45a8ff	2282	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2283	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285	/** @brief macro to get the USART1 clock source.
bogdanm	0:9b334a45a8ff	2286	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2287	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	2288	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	2289	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	2290	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	2291	*/
bogdanm	0:9b334a45a8ff	2292	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	/** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm	0:9b334a45a8ff	2295	*
bogdanm	0:9b334a45a8ff	2296	* @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
bogdanm	0:9b334a45a8ff	2297	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2298	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	2299	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	2300	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	2301	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	2302	*/
bogdanm	0:9b334a45a8ff	2303	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2304	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2305
bogdanm	0:9b334a45a8ff	2306	/** @brief macro to get the USART2 clock source.
bogdanm	0:9b334a45a8ff	2307	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2308	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	2309	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	2310	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	2311	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	2312	*/
bogdanm	0:9b334a45a8ff	2313	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
bogdanm	0:9b334a45a8ff	2314
bogdanm	0:9b334a45a8ff	2315	/** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm	0:9b334a45a8ff	2316	*
bogdanm	0:9b334a45a8ff	2317	* @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
bogdanm	0:9b334a45a8ff	2318	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2319	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	0:9b334a45a8ff	2320	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	0:9b334a45a8ff	2321	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	0:9b334a45a8ff	2322	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	0:9b334a45a8ff	2323	*/
bogdanm	0:9b334a45a8ff	2324	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2325	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	/** @brief macro to get the USART3 clock source.
bogdanm	0:9b334a45a8ff	2328	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2329	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	0:9b334a45a8ff	2330	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	0:9b334a45a8ff	2331	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	0:9b334a45a8ff	2332	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	0:9b334a45a8ff	2333	*/
bogdanm	0:9b334a45a8ff	2334	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
bogdanm	0:9b334a45a8ff	2335
bogdanm	0:9b334a45a8ff	2336	/** @brief Macro to configure the UART4 clock (UART4CLK).
bogdanm	0:9b334a45a8ff	2337	*
bogdanm	0:9b334a45a8ff	2338	* @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
bogdanm	0:9b334a45a8ff	2339	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2340	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm	0:9b334a45a8ff	2341	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm	0:9b334a45a8ff	2342	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm	0:9b334a45a8ff	2343	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm	0:9b334a45a8ff	2344	*/
bogdanm	0:9b334a45a8ff	2345	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2346	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2347
bogdanm	0:9b334a45a8ff	2348	/** @brief macro to get the UART4 clock source.
bogdanm	0:9b334a45a8ff	2349	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2350	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm	0:9b334a45a8ff	2351	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm	0:9b334a45a8ff	2352	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm	0:9b334a45a8ff	2353	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm	0:9b334a45a8ff	2354	*/
bogdanm	0:9b334a45a8ff	2355	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
bogdanm	0:9b334a45a8ff	2356
bogdanm	0:9b334a45a8ff	2357	/** @brief Macro to configure the UART5 clock (UART5CLK).
bogdanm	0:9b334a45a8ff	2358	*
bogdanm	0:9b334a45a8ff	2359	* @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
bogdanm	0:9b334a45a8ff	2360	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2361	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm	0:9b334a45a8ff	2362	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm	0:9b334a45a8ff	2363	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm	0:9b334a45a8ff	2364	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm	0:9b334a45a8ff	2365	*/
bogdanm	0:9b334a45a8ff	2366	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2367	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2368
bogdanm	0:9b334a45a8ff	2369	/** @brief macro to get the UART5 clock source.
bogdanm	0:9b334a45a8ff	2370	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2371	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm	0:9b334a45a8ff	2372	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm	0:9b334a45a8ff	2373	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm	0:9b334a45a8ff	2374	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm	0:9b334a45a8ff	2375	*/
bogdanm	0:9b334a45a8ff	2376	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
bogdanm	0:9b334a45a8ff	2377
bogdanm	0:9b334a45a8ff	2378	/** @brief Macro to configure the USART6 clock (USART6CLK).
bogdanm	0:9b334a45a8ff	2379	*
bogdanm	0:9b334a45a8ff	2380	* @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
bogdanm	0:9b334a45a8ff	2381	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2382	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
bogdanm	0:9b334a45a8ff	2383	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
bogdanm	0:9b334a45a8ff	2384	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
bogdanm	0:9b334a45a8ff	2385	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
bogdanm	0:9b334a45a8ff	2386	*/
bogdanm	0:9b334a45a8ff	2387	#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2388	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2389
bogdanm	0:9b334a45a8ff	2390	/** @brief macro to get the USART6 clock source.
bogdanm	0:9b334a45a8ff	2391	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2392	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
bogdanm	0:9b334a45a8ff	2393	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
bogdanm	0:9b334a45a8ff	2394	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
bogdanm	0:9b334a45a8ff	2395	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
bogdanm	0:9b334a45a8ff	2396	*/
bogdanm	0:9b334a45a8ff	2397	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
bogdanm	0:9b334a45a8ff	2398
bogdanm	0:9b334a45a8ff	2399	/** @brief Macro to configure the UART7 clock (UART7CLK).
bogdanm	0:9b334a45a8ff	2400	*
bogdanm	0:9b334a45a8ff	2401	* @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
bogdanm	0:9b334a45a8ff	2402	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2403	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
bogdanm	0:9b334a45a8ff	2404	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
bogdanm	0:9b334a45a8ff	2405	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
bogdanm	0:9b334a45a8ff	2406	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
bogdanm	0:9b334a45a8ff	2407	*/
bogdanm	0:9b334a45a8ff	2408	#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2409	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2410
bogdanm	0:9b334a45a8ff	2411	/** @brief macro to get the UART7 clock source.
bogdanm	0:9b334a45a8ff	2412	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2413	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
bogdanm	0:9b334a45a8ff	2414	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
bogdanm	0:9b334a45a8ff	2415	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
bogdanm	0:9b334a45a8ff	2416	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
bogdanm	0:9b334a45a8ff	2417	*/
bogdanm	0:9b334a45a8ff	2418	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
bogdanm	0:9b334a45a8ff	2419
bogdanm	0:9b334a45a8ff	2420	/** @brief Macro to configure the UART8 clock (UART8CLK).
bogdanm	0:9b334a45a8ff	2421	*
bogdanm	0:9b334a45a8ff	2422	* @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
bogdanm	0:9b334a45a8ff	2423	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2424	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
bogdanm	0:9b334a45a8ff	2425	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
bogdanm	0:9b334a45a8ff	2426	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
bogdanm	0:9b334a45a8ff	2427	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
bogdanm	0:9b334a45a8ff	2428	*/
bogdanm	0:9b334a45a8ff	2429	#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2430	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2431
bogdanm	0:9b334a45a8ff	2432	/** @brief macro to get the UART8 clock source.
bogdanm	0:9b334a45a8ff	2433	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2434	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
bogdanm	0:9b334a45a8ff	2435	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
bogdanm	0:9b334a45a8ff	2436	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
bogdanm	0:9b334a45a8ff	2437	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
bogdanm	0:9b334a45a8ff	2438	*/
bogdanm	0:9b334a45a8ff	2439	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
bogdanm	0:9b334a45a8ff	2440
bogdanm	0:9b334a45a8ff	2441	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
bogdanm	0:9b334a45a8ff	2442	*
bogdanm	0:9b334a45a8ff	2443	* @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	2444	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2445	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2446	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2447	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2448	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2449	*/
bogdanm	0:9b334a45a8ff	2450	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2451	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2452
bogdanm	0:9b334a45a8ff	2453	/** @brief macro to get the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	2454	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2455	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2456	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2457	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2458	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	2459	*/
bogdanm	0:9b334a45a8ff	2460	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	/** @brief Macro to configure the CEC clock (CECCLK).
bogdanm	0:9b334a45a8ff	2463	*
bogdanm	0:9b334a45a8ff	2464	* @param __CEC_CLKSOURCE__: specifies the CEC clock source.
bogdanm	0:9b334a45a8ff	2465	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2466	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	83:a036322b8637	2467	* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
bogdanm	0:9b334a45a8ff	2468	*/
bogdanm	0:9b334a45a8ff	2469	#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2470	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2471
bogdanm	0:9b334a45a8ff	2472	/** @brief macro to get the CEC clock source.
bogdanm	0:9b334a45a8ff	2473	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2474	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	0:9b334a45a8ff	2475	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	2476	*/
bogdanm	0:9b334a45a8ff	2477	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
bogdanm	0:9b334a45a8ff	2478
bogdanm	0:9b334a45a8ff	2479	/** @brief Macro to configure the CLK48 source (CLK48CLK).
bogdanm	0:9b334a45a8ff	2480	*
bogdanm	0:9b334a45a8ff	2481	* @param __CLK48_SOURCE__: specifies the CLK48 clock source.
bogdanm	0:9b334a45a8ff	2482	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2483	* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
mbed_official	83:a036322b8637	2484	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
bogdanm	0:9b334a45a8ff	2485	*/
bogdanm	0:9b334a45a8ff	2486	#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
bogdanm	0:9b334a45a8ff	2487	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
bogdanm	0:9b334a45a8ff	2488
bogdanm	0:9b334a45a8ff	2489	/** @brief macro to get the CLK48 source.
bogdanm	0:9b334a45a8ff	2490	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2491	* @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
mbed_official	83:a036322b8637	2492	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
bogdanm	0:9b334a45a8ff	2493	*/
bogdanm	0:9b334a45a8ff	2494	#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
bogdanm	0:9b334a45a8ff	2495
bogdanm	0:9b334a45a8ff	2496	/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
bogdanm	0:9b334a45a8ff	2497	*
bogdanm	0:9b334a45a8ff	2498	* @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
bogdanm	0:9b334a45a8ff	2499	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2500	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
bogdanm	0:9b334a45a8ff	2501	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
bogdanm	0:9b334a45a8ff	2502	*/
bogdanm	0:9b334a45a8ff	2503	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
bogdanm	0:9b334a45a8ff	2504	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	2505
bogdanm	0:9b334a45a8ff	2506	/** @brief macro to get the SDMMC1 clock source.
bogdanm	0:9b334a45a8ff	2507	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2508	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
bogdanm	0:9b334a45a8ff	2509	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
bogdanm	0:9b334a45a8ff	2510	*/
bogdanm	0:9b334a45a8ff	2511	#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	/**
bogdanm	0:9b334a45a8ff	2514	* @}
bogdanm	0:9b334a45a8ff	2515	*/
mbed_official	83:a036322b8637	2516
bogdanm	0:9b334a45a8ff	2517	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2518	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	2519	* @{
bogdanm	0:9b334a45a8ff	2520	*/
bogdanm	0:9b334a45a8ff	2521	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2522	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2523	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	0:9b334a45a8ff	2524
bogdanm	0:9b334a45a8ff	2525	/**
bogdanm	0:9b334a45a8ff	2526	* @}
bogdanm	0:9b334a45a8ff	2527	*/
bogdanm	0:9b334a45a8ff	2528	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2529	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm	0:9b334a45a8ff	2530	* @{
bogdanm	0:9b334a45a8ff	2531	*/
bogdanm	0:9b334a45a8ff	2532	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
bogdanm	0:9b334a45a8ff	2533	* @{
bogdanm	0:9b334a45a8ff	2534	*/
bogdanm	0:9b334a45a8ff	2535	#if defined(STM32F756xx) \|\| defined(STM32F746xx)
bogdanm	0:9b334a45a8ff	2536	#define IS_RCC_PERIPHCLOCK(SELECTION) \
mbed_official	83:a036322b8637	2537	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
bogdanm	0:9b334a45a8ff	2538	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
bogdanm	0:9b334a45a8ff	2539	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
bogdanm	0:9b334a45a8ff	2540	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
bogdanm	0:9b334a45a8ff	2541	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
bogdanm	0:9b334a45a8ff	2542	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
bogdanm	0:9b334a45a8ff	2543	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
bogdanm	0:9b334a45a8ff	2544	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
bogdanm	0:9b334a45a8ff	2545	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
bogdanm	0:9b334a45a8ff	2546	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
bogdanm	0:9b334a45a8ff	2547	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
bogdanm	0:9b334a45a8ff	2548	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
bogdanm	0:9b334a45a8ff	2549	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
bogdanm	0:9b334a45a8ff	2550	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
bogdanm	0:9b334a45a8ff	2551	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
bogdanm	0:9b334a45a8ff	2552	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
bogdanm	0:9b334a45a8ff	2553	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
bogdanm	0:9b334a45a8ff	2554	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
bogdanm	0:9b334a45a8ff	2555	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
bogdanm	0:9b334a45a8ff	2556	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
mbed_official	83:a036322b8637	2557	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
mbed_official	83:a036322b8637	2558	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
bogdanm	0:9b334a45a8ff	2559	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	2560	#elif defined(STM32F745xx)
bogdanm	0:9b334a45a8ff	2561	#define IS_RCC_PERIPHCLOCK(SELECTION) \
mbed_official	83:a036322b8637	2562	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
bogdanm	0:9b334a45a8ff	2563	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
bogdanm	0:9b334a45a8ff	2564	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
bogdanm	0:9b334a45a8ff	2565	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
bogdanm	0:9b334a45a8ff	2566	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
bogdanm	0:9b334a45a8ff	2567	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
bogdanm	0:9b334a45a8ff	2568	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
bogdanm	0:9b334a45a8ff	2569	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
bogdanm	0:9b334a45a8ff	2570	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
bogdanm	0:9b334a45a8ff	2571	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
bogdanm	0:9b334a45a8ff	2572	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
bogdanm	0:9b334a45a8ff	2573	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
bogdanm	0:9b334a45a8ff	2574	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
bogdanm	0:9b334a45a8ff	2575	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
bogdanm	0:9b334a45a8ff	2576	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
bogdanm	0:9b334a45a8ff	2577	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
bogdanm	0:9b334a45a8ff	2578	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
bogdanm	0:9b334a45a8ff	2579	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
bogdanm	0:9b334a45a8ff	2580	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
mbed_official	83:a036322b8637	2581	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
mbed_official	83:a036322b8637	2582	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
bogdanm	0:9b334a45a8ff	2583	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
mbed_official	83:a036322b8637	2584	#endif /* STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	2585	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	83:a036322b8637	2586	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
mbed_official	83:a036322b8637	2587	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
mbed_official	83:a036322b8637	2588	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
mbed_official	83:a036322b8637	2589	((VALUE) == RCC_PLLI2SP_DIV8))
bogdanm	0:9b334a45a8ff	2590	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	0:9b334a45a8ff	2591	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	0:9b334a45a8ff	2592
mbed_official	83:a036322b8637	2593	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	83:a036322b8637	2594	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
mbed_official	83:a036322b8637	2595	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
mbed_official	83:a036322b8637	2596	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
mbed_official	83:a036322b8637	2597	((VALUE) == RCC_PLLSAIP_DIV8))
bogdanm	0:9b334a45a8ff	2598	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	0:9b334a45a8ff	2599	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	0:9b334a45a8ff	2600
bogdanm	0:9b334a45a8ff	2601	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	0:9b334a45a8ff	2602
bogdanm	0:9b334a45a8ff	2603	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	0:9b334a45a8ff	2604
bogdanm	0:9b334a45a8ff	2605	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
mbed_official	83:a036322b8637	2606	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
mbed_official	83:a036322b8637	2607	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
bogdanm	0:9b334a45a8ff	2608	((VALUE) == RCC_PLLSAIDIVR_16))
bogdanm	0:9b334a45a8ff	2609	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) \|\| \
mbed_official	83:a036322b8637	2610	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm	0:9b334a45a8ff	2611
mbed_official	83:a036322b8637	2612	#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) \|\| \
mbed_official	83:a036322b8637	2613	((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
bogdanm	0:9b334a45a8ff	2614
bogdanm	0:9b334a45a8ff	2615	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2616	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	0:9b334a45a8ff	2617	#define IS_RCC_USART1CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2618	(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	0:9b334a45a8ff	2619	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2620	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2621	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2622
bogdanm	0:9b334a45a8ff	2623	#define IS_RCC_USART2CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2624	(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2625	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2626	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2627	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2628	#define IS_RCC_USART3CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2629	(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2630	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2631	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2632	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2633
bogdanm	0:9b334a45a8ff	2634	#define IS_RCC_UART4CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2635	(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2636	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2637	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2638	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2639
bogdanm	0:9b334a45a8ff	2640	#define IS_RCC_UART5CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2641	(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2642	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2643	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2644	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2645
bogdanm	0:9b334a45a8ff	2646	#define IS_RCC_USART6CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2647	(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) \|\| \
bogdanm	0:9b334a45a8ff	2648	((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2649	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2650	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2651
bogdanm	0:9b334a45a8ff	2652	#define IS_RCC_UART7CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2653	(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2654	((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2655	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2656	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2657
bogdanm	0:9b334a45a8ff	2658	#define IS_RCC_UART8CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2659	(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2660	((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	2661	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	2662	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2663	#define IS_RCC_I2C1CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2664	(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2665	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	2666	((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2667	#define IS_RCC_I2C2CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2668	(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2669	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	2670	((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2671
bogdanm	0:9b334a45a8ff	2672	#define IS_RCC_I2C3CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2673	(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2674	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	2675	((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2676	#define IS_RCC_I2C4CLKSOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2677	(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	2678	((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	2679	((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2680	#define IS_RCC_LPTIM1CLK(SOURCE) \
bogdanm	0:9b334a45a8ff	2681	(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
bogdanm	0:9b334a45a8ff	2682	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	2683	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	2684	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
bogdanm	0:9b334a45a8ff	2685	#define IS_RCC_CLK48SOURCE(SOURCE) \
bogdanm	0:9b334a45a8ff	2686	(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) \|\| \
bogdanm	0:9b334a45a8ff	2687	((SOURCE) == RCC_CLK48SOURCE_PLL))
bogdanm	0:9b334a45a8ff	2688	#define IS_RCC_TIMPRES(VALUE) \
bogdanm	0:9b334a45a8ff	2689	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
bogdanm	0:9b334a45a8ff	2690	((VALUE) == RCC_TIMPRES_ACTIVATED))
mbed_official	83:a036322b8637	2691
mbed_official	83:a036322b8637	2692	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx)
mbed_official	83:a036322b8637	2693	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
mbed_official	83:a036322b8637	2694	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
mbed_official	83:a036322b8637	2695	((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
mbed_official	83:a036322b8637	2696	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
mbed_official	83:a036322b8637	2697	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
mbed_official	83:a036322b8637	2698	((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
mbed_official	83:a036322b8637	2699	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx */
mbed_official	83:a036322b8637	2700
bogdanm	0:9b334a45a8ff	2701	/**
bogdanm	0:9b334a45a8ff	2702	* @}
bogdanm	0:9b334a45a8ff	2703	*/
bogdanm	0:9b334a45a8ff	2704
bogdanm	0:9b334a45a8ff	2705	/**
bogdanm	0:9b334a45a8ff	2706	* @}
bogdanm	0:9b334a45a8ff	2707	*/
bogdanm	0:9b334a45a8ff	2708
bogdanm	0:9b334a45a8ff	2709	/**
bogdanm	0:9b334a45a8ff	2710	* @}
bogdanm	0:9b334a45a8ff	2711	*/
bogdanm	0:9b334a45a8ff	2712
bogdanm	0:9b334a45a8ff	2713	/**
bogdanm	0:9b334a45a8ff	2714	* @}
bogdanm	0:9b334a45a8ff	2715	*/
mbed_official	83:a036322b8637	2716
bogdanm	0:9b334a45a8ff	2717	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2718	}
bogdanm	0:9b334a45a8ff	2719	#endif
bogdanm	0:9b334a45a8ff	2720
bogdanm	0:9b334a45a8ff	2721	#endif /* __STM32F7xx_HAL_RCC_EX_H */
bogdanm	0:9b334a45a8ff	2722
bogdanm	0:9b334a45a8ff	2723	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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