mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_i2s.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief I2S HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Integrated Interchip Sound (I2S) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	===============================================================================
bogdanm	0:9b334a45a8ff	15	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	16	===============================================================================
bogdanm	0:9b334a45a8ff	17	[..]
bogdanm	0:9b334a45a8ff	18	The I2S HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	19
bogdanm	0:9b334a45a8ff	20	(#) Declare a I2S_HandleTypeDef handle structure.
bogdanm	0:9b334a45a8ff	21	(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
bogdanm	0:9b334a45a8ff	22	(##) Enable the SPIx interface clock.
bogdanm	0:9b334a45a8ff	23	(##) I2S pins configuration:
bogdanm	0:9b334a45a8ff	24	(+++) Enable the clock for the I2S GPIOs.
bogdanm	0:9b334a45a8ff	25	(+++) Configure these I2S pins as alternate function pull-up.
bogdanm	0:9b334a45a8ff	26	(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	27	and HAL_I2S_Receive_IT() APIs).
bogdanm	0:9b334a45a8ff	28	(+++) Configure the I2Sx interrupt priority.
bogdanm	0:9b334a45a8ff	29	(+++) Enable the NVIC I2S IRQ handle.
bogdanm	0:9b334a45a8ff	30	(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	31	and HAL_I2S_Receive_DMA() APIs:
bogdanm	0:9b334a45a8ff	32	(+++) Declare a DMA handle structure for the Tx/Rx channel.
bogdanm	0:9b334a45a8ff	33	(+++) Enable the DMAx interface clock.
bogdanm	0:9b334a45a8ff	34	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA Tx/Rx Channel.
bogdanm	0:9b334a45a8ff	36	(+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
bogdanm	0:9b334a45a8ff	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
bogdanm	0:9b334a45a8ff	38	DMA Tx/Rx Channel.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
bogdanm	0:9b334a45a8ff	41	using HAL_I2S_Init() function.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	-@- The specific I2S interrupts (Transmission complete interrupt,
bogdanm	0:9b334a45a8ff	44	RXNE interrupt and Error Interrupts) will be managed using the macros
bogdanm	0:9b334a45a8ff	45	__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
bogdanm	0:9b334a45a8ff	46	-@- Make sure that either:
bogdanm	0:9b334a45a8ff	47	(+@) I2S clock is configured based on SYSCLK or
bogdanm	0:9b334a45a8ff	48	(+@) External clock source is configured after setting correctly
bogdanm	0:9b334a45a8ff	49	the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	(#) Three mode of operations are available within this driver :
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	54	=================================
bogdanm	0:9b334a45a8ff	55	[..]
bogdanm	0:9b334a45a8ff	56	(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	57	(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	60	===================================
bogdanm	0:9b334a45a8ff	61	[..]
bogdanm	0:9b334a45a8ff	62	(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	63	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	64	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	65	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	66	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	67	(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	68	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	69	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	70	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	71	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	72	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	73	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	76	==============================
bogdanm	0:9b334a45a8ff	77	[..]
bogdanm	0:9b334a45a8ff	78	(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	79	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	80	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	81	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	82	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	83	(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	84	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	85	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	86	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	87	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	88	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	89	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	90	(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm	0:9b334a45a8ff	91	(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm	0:9b334a45a8ff	92	(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	* I2S HAL driver macros list *
bogdanm	0:9b334a45a8ff	95	=============================================
bogdanm	0:9b334a45a8ff	96	[..]
bogdanm	0:9b334a45a8ff	97	Below the list of most used macros in I2S HAL driver.
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	100	(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	101	(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	102	(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	103	(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	[..]
bogdanm	0:9b334a45a8ff	106	(@) You can refer to the I2S HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	@endverbatim
bogdanm	0:9b334a45a8ff	109	******************************************************************************
bogdanm	0:9b334a45a8ff	110	* @attention
bogdanm	0:9b334a45a8ff	111	*
bogdanm	0:9b334a45a8ff	112	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	115	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	116	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	117	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	118	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	119	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	120	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	121	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	122	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	123	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	126	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	127	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	128	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	129	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	130	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	131	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	132	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	133	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	134	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	135	*
bogdanm	0:9b334a45a8ff	136	******************************************************************************
bogdanm	0:9b334a45a8ff	137	*/
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	140	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	143	* @{
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/** @defgroup I2S I2S
bogdanm	0:9b334a45a8ff	147	* @brief I2S HAL module driver
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	#ifdef HAL_I2S_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	154	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	155	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	158	/** @defgroup I2S_Private_Functions I2S Private Functions
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	162	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	163	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	164	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	165	static void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	166	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
bogdanm	0:9b334a45a8ff	167	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
bogdanm	0:9b334a45a8ff	168	static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
bogdanm	0:9b334a45a8ff	169	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	170	/**
bogdanm	0:9b334a45a8ff	171	* @}
bogdanm	0:9b334a45a8ff	172	*/
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/** @defgroup I2S_Exported_Functions I2S Exported Functions
bogdanm	0:9b334a45a8ff	177	* @{
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	181	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	182	*
bogdanm	0:9b334a45a8ff	183	@verbatim
bogdanm	0:9b334a45a8ff	184	===============================================================================
bogdanm	0:9b334a45a8ff	185	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	186	===============================================================================
bogdanm	0:9b334a45a8ff	187	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	188	de-initialize the I2Sx peripheral in simplex mode:
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	(+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	191	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	(+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	194	the selected configuration:
bogdanm	0:9b334a45a8ff	195	(++) Mode
bogdanm	0:9b334a45a8ff	196	(++) Standard
bogdanm	0:9b334a45a8ff	197	(++) Data Format
bogdanm	0:9b334a45a8ff	198	(++) MCLK Output
bogdanm	0:9b334a45a8ff	199	(++) Audio frequency
bogdanm	0:9b334a45a8ff	200	(++) Polarity
bogdanm	0:9b334a45a8ff	201	(++) Full duplex mode
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	(+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	204	of the selected I2Sx peripheral.
bogdanm	0:9b334a45a8ff	205	@endverbatim
bogdanm	0:9b334a45a8ff	206	* @{
bogdanm	0:9b334a45a8ff	207	*/
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/**
bogdanm	0:9b334a45a8ff	210	* @brief Initializes the I2S according to the specified parameters
bogdanm	0:9b334a45a8ff	211	* in the I2S_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	212	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	213	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	214	* @retval HAL status
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216	HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	217	{
bogdanm	0:9b334a45a8ff	218	uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm	0:9b334a45a8ff	219	uint32_t tmp = 0, i2sclk = 0;
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	222	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	223	{
bogdanm	0:9b334a45a8ff	224	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	225	}
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/* Check the parameters */
bogdanm	0:9b334a45a8ff	228	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm	0:9b334a45a8ff	229	assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm	0:9b334a45a8ff	230	assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm	0:9b334a45a8ff	231	assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm	0:9b334a45a8ff	232	assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	233	assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm	0:9b334a45a8ff	234	assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm	0:9b334a45a8ff	235	assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm	0:9b334a45a8ff	238	{
bogdanm	0:9b334a45a8ff	239	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	240	hi2s->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	241	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm	0:9b334a45a8ff	242	HAL_I2S_MspInit(hi2s);
bogdanm	0:9b334a45a8ff	243	}
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------/
bogdanm	0:9b334a45a8ff	248	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm	0:9b334a45a8ff	249	hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CKPOL \| \
bogdanm	0:9b334a45a8ff	250	SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \| \
bogdanm	0:9b334a45a8ff	251	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD);
bogdanm	0:9b334a45a8ff	252	hi2s->Instance->I2SPR = 0x0002;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/* Get the I2SCFGR register value */
bogdanm	0:9b334a45a8ff	255	tmpreg = hi2s->Instance->I2SCFGR;
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm	0:9b334a45a8ff	258	if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	i2sodd = (uint16_t)0;
bogdanm	0:9b334a45a8ff	261	i2sdiv = (uint16_t)2;
bogdanm	0:9b334a45a8ff	262	}
bogdanm	0:9b334a45a8ff	263	/* If the requested audio frequency is not the default, compute the prescaler */
bogdanm	0:9b334a45a8ff	264	else
bogdanm	0:9b334a45a8ff	265	{
bogdanm	0:9b334a45a8ff	266	/* Check the frame length (For the Prescaler computing) *******************/
bogdanm	0:9b334a45a8ff	267	if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
bogdanm	0:9b334a45a8ff	268	{
bogdanm	0:9b334a45a8ff	269	/* Packet length is 16 bits */
bogdanm	0:9b334a45a8ff	270	packetlength = 1;
bogdanm	0:9b334a45a8ff	271	}
bogdanm	0:9b334a45a8ff	272	else
bogdanm	0:9b334a45a8ff	273	{
bogdanm	0:9b334a45a8ff	274	/* Packet length is 32 bits */
bogdanm	0:9b334a45a8ff	275	packetlength = 2;
bogdanm	0:9b334a45a8ff	276	}
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Get I2S source Clock frequency ****************************************/
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	/* If an external I2S clock has to be used, the specific define should be set
bogdanm	0:9b334a45a8ff	281	in the project configuration or in the stm32f3xx_conf.h file */
bogdanm	0:9b334a45a8ff	282	if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
bogdanm	0:9b334a45a8ff	283	{
bogdanm	0:9b334a45a8ff	284	/* Set the I2S clock to the external clock value */
bogdanm	0:9b334a45a8ff	285	i2sclk = EXTERNAL_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	286	}
bogdanm	0:9b334a45a8ff	287	else
bogdanm	0:9b334a45a8ff	288	{
bogdanm	0:9b334a45a8ff	289	/* Get the I2S source clock value */
bogdanm	0:9b334a45a8ff	290	i2sclk = I2S_GetClockFreq(hi2s);
bogdanm	0:9b334a45a8ff	291	}
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	/* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm	0:9b334a45a8ff	294	if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm	0:9b334a45a8ff	295	{
bogdanm	0:9b334a45a8ff	296	/* MCLK output is enabled */
bogdanm	0:9b334a45a8ff	297	tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	298	}
bogdanm	0:9b334a45a8ff	299	else
bogdanm	0:9b334a45a8ff	300	{
bogdanm	0:9b334a45a8ff	301	/* MCLK output is disabled */
bogdanm	0:9b334a45a8ff	302	tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	303	}
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Remove the flatting point */
bogdanm	0:9b334a45a8ff	306	tmp = tmp / 10;
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/* Check the parity of the divider */
bogdanm	0:9b334a45a8ff	309	i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/* Compute the i2sdiv prescaler */
bogdanm	0:9b334a45a8ff	312	i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm	0:9b334a45a8ff	315	i2sodd = (uint16_t) (i2sodd << 8);
bogdanm	0:9b334a45a8ff	316	}
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm	0:9b334a45a8ff	319	if((i2sdiv < 2) \|\| (i2sdiv > 0xFF))
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	/* Set the default values */
bogdanm	0:9b334a45a8ff	322	i2sdiv = 2;
bogdanm	0:9b334a45a8ff	323	i2sodd = 0;
bogdanm	0:9b334a45a8ff	324	}
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/* Write to SPIx I2SPR register the computed value */
bogdanm	0:9b334a45a8ff	327	hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv \| (uint16_t)(i2sodd \| (uint16_t)hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/* Configure the I2S with the I2S_InitStruct values */
bogdanm	0:9b334a45a8ff	330	tmpreg \|= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD \| (uint16_t)(hi2s->Init.Mode \| \
bogdanm	0:9b334a45a8ff	331	(uint16_t)(hi2s->Init.Standard \| (uint16_t)(hi2s->Init.DataFormat \| \
bogdanm	0:9b334a45a8ff	332	(uint16_t)hi2s->Init.CPOL))));
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	335	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	338	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	return HAL_OK;
bogdanm	0:9b334a45a8ff	341	}
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/**
bogdanm	0:9b334a45a8ff	344	* @brief DeInitializes the I2S peripheral
bogdanm	0:9b334a45a8ff	345	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	346	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	347	* @retval HAL status
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349	HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	350	{
bogdanm	0:9b334a45a8ff	351	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	352	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	353	{
bogdanm	0:9b334a45a8ff	354	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	355	}
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* Check the parameters */
bogdanm	0:9b334a45a8ff	358	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	363	HAL_I2S_MspDeInit(hi2s);
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	366	hi2s->State = HAL_I2S_STATE_RESET;
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* Release Lock */
bogdanm	0:9b334a45a8ff	369	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	return HAL_OK;
bogdanm	0:9b334a45a8ff	372	}
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/**
bogdanm	0:9b334a45a8ff	375	* @brief I2S MSP Init
bogdanm	0:9b334a45a8ff	376	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	377	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	378	* @retval None
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380	__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	381	{
mbed_official	83:a036322b8637	382	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	383	UNUSED(hi2s);
mbed_official	83:a036322b8637	384
bogdanm	0:9b334a45a8ff	385	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	386	the HAL_I2S_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388	}
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	/**
bogdanm	0:9b334a45a8ff	391	* @brief I2S MSP DeInit
bogdanm	0:9b334a45a8ff	392	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	393	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	394	* @retval None
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	397	{
mbed_official	83:a036322b8637	398	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	399	UNUSED(hi2s);
mbed_official	83:a036322b8637	400
bogdanm	0:9b334a45a8ff	401	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	402	the HAL_I2S_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	403	*/
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/**
bogdanm	0:9b334a45a8ff	407	* @}
bogdanm	0:9b334a45a8ff	408	*/
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions
bogdanm	0:9b334a45a8ff	411	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	412	*
bogdanm	0:9b334a45a8ff	413	@verbatim
bogdanm	0:9b334a45a8ff	414	===============================================================================
bogdanm	0:9b334a45a8ff	415	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	416	===============================================================================
bogdanm	0:9b334a45a8ff	417	[..]
bogdanm	0:9b334a45a8ff	418	This subsection provides a set of functions allowing to manage the I2S data
bogdanm	0:9b334a45a8ff	419	transfers.
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	422	(++) Blocking mode : The communication is performed in the polling mode.
bogdanm	0:9b334a45a8ff	423	The status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	424	after finishing transfer.
bogdanm	0:9b334a45a8ff	425	(++) No-Blocking mode : The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	426	or DMA. These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	427	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	428	dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	429	using DMA mode.
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	(#) Blocking mode functions are :
bogdanm	0:9b334a45a8ff	432	(++) HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	433	(++) HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	(#) No-Blocking mode functions with Interrupt are :
bogdanm	0:9b334a45a8ff	436	(++) HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	437	(++) HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	(#) No-Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	440	(++) HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	441	(++) HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	444	(++) HAL_I2S_TxCpltCallback()
bogdanm	0:9b334a45a8ff	445	(++) HAL_I2S_RxCpltCallback()
bogdanm	0:9b334a45a8ff	446	(++) HAL_I2S_ErrorCallback()
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	@endverbatim
bogdanm	0:9b334a45a8ff	449	* @{
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	454	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	455	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	456	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	457	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	458	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	459	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	460	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	461	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	462	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	463	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	464	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	465	* @retval HAL status
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467	HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	470	{
bogdanm	0:9b334a45a8ff	471	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	472	}
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	477	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	478	{
bogdanm	0:9b334a45a8ff	479	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	480	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	481	}
bogdanm	0:9b334a45a8ff	482	else
bogdanm	0:9b334a45a8ff	483	{
bogdanm	0:9b334a45a8ff	484	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	485	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/* Process Locked */
bogdanm	0:9b334a45a8ff	489	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	492	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	495	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	498	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	while(hi2s->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	502	{
bogdanm	0:9b334a45a8ff	503	hi2s->Instance->DR = (*pData++);
bogdanm	0:9b334a45a8ff	504	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	505	/* Wait until TXE flag is set */
bogdanm	0:9b334a45a8ff	506	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	507	{
bogdanm	0:9b334a45a8ff	508	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	509	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	510	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	511	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	512	}
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	/* Check if an underrun occurs */
bogdanm	0:9b334a45a8ff	515	if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	518	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	521	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	524	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	525	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	528	}
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/* Check if Slave mode is selected */
bogdanm	0:9b334a45a8ff	532	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
bogdanm	0:9b334a45a8ff	533	{
bogdanm	0:9b334a45a8ff	534	/* Wait until Busy flag is reset */
mbed_official	83:a036322b8637	535	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	536	{
bogdanm	0:9b334a45a8ff	537	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	538	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	539	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	540	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	547	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	return HAL_OK;
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551	else
bogdanm	0:9b334a45a8ff	552	{
bogdanm	0:9b334a45a8ff	553	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	554	}
bogdanm	0:9b334a45a8ff	555	}
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/**
bogdanm	0:9b334a45a8ff	558	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	559	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	560	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	561	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	562	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	563	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	564	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	565	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	566	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	567	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	568	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	569	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	570	* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
bogdanm	0:9b334a45a8ff	571	* in continuous way and as the I2S is not disabled at the end of the I2S transaction.
bogdanm	0:9b334a45a8ff	572	* @retval HAL status
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574	HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	575	{
bogdanm	0:9b334a45a8ff	576	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	579	}
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	584	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	587	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	588	}
bogdanm	0:9b334a45a8ff	589	else
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	592	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	593	}
bogdanm	0:9b334a45a8ff	594	/* Process Locked */
bogdanm	0:9b334a45a8ff	595	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	598	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	601	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	602	{
bogdanm	0:9b334a45a8ff	603	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	604	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	608	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	609	{
bogdanm	0:9b334a45a8ff	610	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	611	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	612	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	613	}
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/* Receive data */
bogdanm	0:9b334a45a8ff	616	while(hi2s->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	617	{
bogdanm	0:9b334a45a8ff	618	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	619	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	620	{
bogdanm	0:9b334a45a8ff	621	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	622	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	623	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	624	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	625	}
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Check if an overrun occurs */
bogdanm	0:9b334a45a8ff	628	if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
bogdanm	0:9b334a45a8ff	629	{
bogdanm	0:9b334a45a8ff	630	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	631	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	634	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	637	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	638	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	(*pData++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	644	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	645	}
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	650	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	return HAL_OK;
bogdanm	0:9b334a45a8ff	653	}
bogdanm	0:9b334a45a8ff	654	else
bogdanm	0:9b334a45a8ff	655	{
bogdanm	0:9b334a45a8ff	656	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	657	}
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/**
bogdanm	0:9b334a45a8ff	661	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	662	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	663	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	664	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	665	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	666	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	667	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	668	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	669	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	670	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	671	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	672	* @retval HAL status
bogdanm	0:9b334a45a8ff	673	*/
bogdanm	0:9b334a45a8ff	674	HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	677	{
bogdanm	0:9b334a45a8ff	678	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	679	{
bogdanm	0:9b334a45a8ff	680	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	681	}
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	684	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	685	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	688	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	689	}
bogdanm	0:9b334a45a8ff	690	else
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	693	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	694	}
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/* Process Locked */
bogdanm	0:9b334a45a8ff	697	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	700	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	703	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	706	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	707	{
bogdanm	0:9b334a45a8ff	708	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	709	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	710	}
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	713	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	return HAL_OK;
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717	else
bogdanm	0:9b334a45a8ff	718	{
bogdanm	0:9b334a45a8ff	719	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721	}
bogdanm	0:9b334a45a8ff	722
bogdanm	0:9b334a45a8ff	723	/**
bogdanm	0:9b334a45a8ff	724	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	725	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	726	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	727	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	728	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	729	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	730	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	731	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	732	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	733	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	734	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	735	* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
bogdanm	0:9b334a45a8ff	736	* between Master and Slave otherwise the I2S interrupt should be optimized.
bogdanm	0:9b334a45a8ff	737	* @retval HAL status
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739	HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	742	{
bogdanm	0:9b334a45a8ff	743	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	744	{
bogdanm	0:9b334a45a8ff	745	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	746	}
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	749	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	750	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	753	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755	else
bogdanm	0:9b334a45a8ff	756	{
bogdanm	0:9b334a45a8ff	757	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	758	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	759	}
bogdanm	0:9b334a45a8ff	760	/* Process Locked */
bogdanm	0:9b334a45a8ff	761	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	764	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	767	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	770	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	773	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	777	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	return HAL_OK;
bogdanm	0:9b334a45a8ff	780	}
bogdanm	0:9b334a45a8ff	781	else
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	784	}
bogdanm	0:9b334a45a8ff	785	}
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/**
bogdanm	0:9b334a45a8ff	788	* @brief Transmit an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	789	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	790	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	791	* @param pData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	792	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	793	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	794	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	795	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	796	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	797	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	798	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	799	* @retval HAL status
bogdanm	0:9b334a45a8ff	800	*/
bogdanm	0:9b334a45a8ff	801	HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	808	}
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	813	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	814	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	815	{
bogdanm	0:9b334a45a8ff	816	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	817	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	818	}
bogdanm	0:9b334a45a8ff	819	else
bogdanm	0:9b334a45a8ff	820	{
bogdanm	0:9b334a45a8ff	821	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	822	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	823	}
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/* Process Locked */
bogdanm	0:9b334a45a8ff	826	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	829	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	/* Set the I2S Tx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	832	hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	833
bogdanm	0:9b334a45a8ff	834	/* Set the I2S TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	835	hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	838	hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	841	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	842	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	845	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	848	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	849	}
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	852	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	855	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	return HAL_OK;
bogdanm	0:9b334a45a8ff	858	}
bogdanm	0:9b334a45a8ff	859	else
bogdanm	0:9b334a45a8ff	860	{
bogdanm	0:9b334a45a8ff	861	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	}
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/**
bogdanm	0:9b334a45a8ff	866	* @brief Receive an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	867	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	868	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	869	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	870	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	871	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	872	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	873	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	874	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	875	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	876	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	877	* @retval HAL status
bogdanm	0:9b334a45a8ff	878	*/
bogdanm	0:9b334a45a8ff	879	HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	884	{
bogdanm	0:9b334a45a8ff	885	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	886	}
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	889	{
bogdanm	0:9b334a45a8ff	890	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	891	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	892	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	895	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	else
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	900	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902	/* Process Locked */
bogdanm	0:9b334a45a8ff	903	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	906	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	/* Set the I2S Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	909	hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/* Set the I2S Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	912	hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	915	hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	918	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	921	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	922	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	926	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	927	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)tmp, hi2s->RxXferSize);
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	930	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	933	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	937	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	940	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	return HAL_OK;
bogdanm	0:9b334a45a8ff	943	}
bogdanm	0:9b334a45a8ff	944	else
bogdanm	0:9b334a45a8ff	945	{
bogdanm	0:9b334a45a8ff	946	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	947	}
bogdanm	0:9b334a45a8ff	948	}
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/**
bogdanm	0:9b334a45a8ff	951	* @brief Pauses the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	952	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	953	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	954	* @retval HAL status
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956	HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	957	{
bogdanm	0:9b334a45a8ff	958	/* Process Locked */
bogdanm	0:9b334a45a8ff	959	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	962	{
bogdanm	0:9b334a45a8ff	963	/* Disable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	964	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	965	}
bogdanm	0:9b334a45a8ff	966	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	967	{
bogdanm	0:9b334a45a8ff	968	/* Disable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	969	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	970	}
bogdanm	0:9b334a45a8ff	971	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	972	{
bogdanm	0:9b334a45a8ff	973	if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)\|\|(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
bogdanm	0:9b334a45a8ff	974	{
bogdanm	0:9b334a45a8ff	975	/* Disable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	976	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	977	}
bogdanm	0:9b334a45a8ff	978	else
bogdanm	0:9b334a45a8ff	979	{
bogdanm	0:9b334a45a8ff	980	/* Disable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	981	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	982	}
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	986	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	return HAL_OK;
bogdanm	0:9b334a45a8ff	989	}
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/**
bogdanm	0:9b334a45a8ff	992	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	993	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	994	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	995	* @retval HAL status
bogdanm	0:9b334a45a8ff	996	*/
bogdanm	0:9b334a45a8ff	997	HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	/* Process Locked */
bogdanm	0:9b334a45a8ff	1000	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1003	{
bogdanm	0:9b334a45a8ff	1004	/* Enable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	1005	SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	/* Enable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	1010	SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1011	}
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/* If the I2S peripheral is still not enabled, enable it */
bogdanm	0:9b334a45a8ff	1014	if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm	0:9b334a45a8ff	1015	{
bogdanm	0:9b334a45a8ff	1016	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	1017	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1021	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	return HAL_OK;
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/**
bogdanm	0:9b334a45a8ff	1027	* @brief Stops the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	1028	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1029	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1030	* @retval HAL status
bogdanm	0:9b334a45a8ff	1031	*/
bogdanm	0:9b334a45a8ff	1032	HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1033	{
bogdanm	0:9b334a45a8ff	1034	/* Process Locked */
bogdanm	0:9b334a45a8ff	1035	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/* Disable the I2S Tx/Rx DMA requests */
bogdanm	0:9b334a45a8ff	1038	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1039	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/* Abort the I2S DMA Channel tx */
bogdanm	0:9b334a45a8ff	1042	if(hi2s->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	/* Disable the I2S DMA channel */
bogdanm	0:9b334a45a8ff	1045	__HAL_DMA_DISABLE(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	1046	HAL_DMA_Abort(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	1047	}
bogdanm	0:9b334a45a8ff	1048	/* Abort the I2S DMA Channel rx */
bogdanm	0:9b334a45a8ff	1049	if(hi2s->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1050	{
bogdanm	0:9b334a45a8ff	1051	/* Disable the I2S DMA channel */
bogdanm	0:9b334a45a8ff	1052	__HAL_DMA_DISABLE(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	1053	HAL_DMA_Abort(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	1054	}
bogdanm	0:9b334a45a8ff	1055
bogdanm	0:9b334a45a8ff	1056	/* Disable I2S peripheral */
bogdanm	0:9b334a45a8ff	1057	__HAL_I2S_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1062	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	return HAL_OK;
bogdanm	0:9b334a45a8ff	1065	}
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/**
bogdanm	0:9b334a45a8ff	1068	* @brief This function handles I2S interrupt request.
bogdanm	0:9b334a45a8ff	1069	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1070	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1071	* @retval HAL status
bogdanm	0:9b334a45a8ff	1072	*/
bogdanm	0:9b334a45a8ff	1073	void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	__IO uint32_t i2ssr = hi2s->Instance->SR;
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1078	{
bogdanm	0:9b334a45a8ff	1079	/* I2S in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1080	if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	1081	{
bogdanm	0:9b334a45a8ff	1082	I2S_Receive_IT(hi2s);
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	/* I2S Overrun error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1086	if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	1087	{
bogdanm	0:9b334a45a8ff	1088	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1089	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1092	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1095	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1096	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1100	{
bogdanm	0:9b334a45a8ff	1101	/* I2S in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1102	if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	I2S_Transmit_IT(hi2s);
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/* I2S Underrun error interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	1108	if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	1109	{
bogdanm	0:9b334a45a8ff	1110	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1111	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1114	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1117	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	1118	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1119	}
bogdanm	0:9b334a45a8ff	1120	}
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/**
bogdanm	0:9b334a45a8ff	1124	* @}
bogdanm	0:9b334a45a8ff	1125	*/
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/**
bogdanm	0:9b334a45a8ff	1128	* @}
bogdanm	0:9b334a45a8ff	1129	*/
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/** @addtogroup I2S_Private_Functions I2S Private Functions
bogdanm	0:9b334a45a8ff	1132	* @{
bogdanm	0:9b334a45a8ff	1133	*/
bogdanm	0:9b334a45a8ff	1134	/**
bogdanm	0:9b334a45a8ff	1135	* @brief This function handles I2S Communication Timeout.
bogdanm	0:9b334a45a8ff	1136	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1137	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1138	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1139	* @param State: Value of the flag expected
bogdanm	0:9b334a45a8ff	1140	* @param Timeout: Duration of the timeout
bogdanm	0:9b334a45a8ff	1141	* @retval HAL status
bogdanm	0:9b334a45a8ff	1142	*/
bogdanm	0:9b334a45a8ff	1143	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
bogdanm	0:9b334a45a8ff	1144	uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1145	{
bogdanm	0:9b334a45a8ff	1146	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/* Get tick */
bogdanm	0:9b334a45a8ff	1149	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	1152	if(State == RESET)
bogdanm	0:9b334a45a8ff	1153	{
bogdanm	0:9b334a45a8ff	1154	while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
bogdanm	0:9b334a45a8ff	1155	{
bogdanm	0:9b334a45a8ff	1156	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1157	{
bogdanm	0:9b334a45a8ff	1158	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1161	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1164	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1167	}
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169	}
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171	else
bogdanm	0:9b334a45a8ff	1172	{
bogdanm	0:9b334a45a8ff	1173	while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
bogdanm	0:9b334a45a8ff	1174	{
bogdanm	0:9b334a45a8ff	1175	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1176	{
bogdanm	0:9b334a45a8ff	1177	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1178	{
bogdanm	0:9b334a45a8ff	1179	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1180	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1183	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1186	}
bogdanm	0:9b334a45a8ff	1187	}
bogdanm	0:9b334a45a8ff	1188	}
bogdanm	0:9b334a45a8ff	1189	}
bogdanm	0:9b334a45a8ff	1190	return HAL_OK;
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192	/**
bogdanm	0:9b334a45a8ff	1193	* @}
bogdanm	0:9b334a45a8ff	1194	*/
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/** @addtogroup I2S_Exported_Functions I2S Exported Functions
bogdanm	0:9b334a45a8ff	1197	* @{
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
bogdanm	0:9b334a45a8ff	1201	* @{
bogdanm	0:9b334a45a8ff	1202	*/
bogdanm	0:9b334a45a8ff	1203	/**
bogdanm	0:9b334a45a8ff	1204	* @brief Tx Transfer Half completed callbacks
bogdanm	0:9b334a45a8ff	1205	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1206	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1207	* @retval None
bogdanm	0:9b334a45a8ff	1208	*/
bogdanm	0:9b334a45a8ff	1209	__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1210	{
mbed_official	83:a036322b8637	1211	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1212	UNUSED(hi2s);
mbed_official	83:a036322b8637	1213
bogdanm	0:9b334a45a8ff	1214	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1215	the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1216	*/
bogdanm	0:9b334a45a8ff	1217	}
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/**
bogdanm	0:9b334a45a8ff	1220	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1221	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1222	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1223	* @retval None
bogdanm	0:9b334a45a8ff	1224	*/
bogdanm	0:9b334a45a8ff	1225	__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1226	{
mbed_official	83:a036322b8637	1227	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1228	UNUSED(hi2s);
mbed_official	83:a036322b8637	1229
bogdanm	0:9b334a45a8ff	1230	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1231	the HAL_I2S_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1232	*/
bogdanm	0:9b334a45a8ff	1233	}
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	/**
bogdanm	0:9b334a45a8ff	1236	* @brief Rx Transfer half completed callbacks
bogdanm	0:9b334a45a8ff	1237	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1238	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1239	* @retval None
bogdanm	0:9b334a45a8ff	1240	*/
bogdanm	0:9b334a45a8ff	1241	__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1242	{
mbed_official	83:a036322b8637	1243	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1244	UNUSED(hi2s);
mbed_official	83:a036322b8637	1245
bogdanm	0:9b334a45a8ff	1246	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1247	the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1248	*/
bogdanm	0:9b334a45a8ff	1249	}
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/**
bogdanm	0:9b334a45a8ff	1252	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1253	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1254	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1255	* @retval None
bogdanm	0:9b334a45a8ff	1256	*/
bogdanm	0:9b334a45a8ff	1257	__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1258	{
mbed_official	83:a036322b8637	1259	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1260	UNUSED(hi2s);
mbed_official	83:a036322b8637	1261
bogdanm	0:9b334a45a8ff	1262	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1263	the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1264	*/
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/**
bogdanm	0:9b334a45a8ff	1268	* @brief I2S error callbacks
bogdanm	0:9b334a45a8ff	1269	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1270	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1271	* @retval None
bogdanm	0:9b334a45a8ff	1272	*/
bogdanm	0:9b334a45a8ff	1273	__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1274	{
mbed_official	83:a036322b8637	1275	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1276	UNUSED(hi2s);
mbed_official	83:a036322b8637	1277
bogdanm	0:9b334a45a8ff	1278	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1279	the HAL_I2S_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1280	*/
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/**
bogdanm	0:9b334a45a8ff	1284	* @}
bogdanm	0:9b334a45a8ff	1285	*/
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1288	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1289	*
bogdanm	0:9b334a45a8ff	1290	@verbatim
bogdanm	0:9b334a45a8ff	1291	===============================================================================
bogdanm	0:9b334a45a8ff	1292	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1293	===============================================================================
bogdanm	0:9b334a45a8ff	1294	[..]
bogdanm	0:9b334a45a8ff	1295	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1296	and the data flow.
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	@endverbatim
bogdanm	0:9b334a45a8ff	1299	* @{
bogdanm	0:9b334a45a8ff	1300	*/
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/**
bogdanm	0:9b334a45a8ff	1303	* @brief Return the I2S state
bogdanm	0:9b334a45a8ff	1304	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1305	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1306	* @retval HAL state
bogdanm	0:9b334a45a8ff	1307	*/
bogdanm	0:9b334a45a8ff	1308	HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1309	{
bogdanm	0:9b334a45a8ff	1310	return hi2s->State;
bogdanm	0:9b334a45a8ff	1311	}
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	/**
bogdanm	0:9b334a45a8ff	1314	* @brief Return the I2S error code
bogdanm	0:9b334a45a8ff	1315	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1316	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1317	* @retval I2S Error Code
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319	uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1320	{
bogdanm	0:9b334a45a8ff	1321	return hi2s->ErrorCode;
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323	/**
bogdanm	0:9b334a45a8ff	1324	* @}
bogdanm	0:9b334a45a8ff	1325	*/
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/**
bogdanm	0:9b334a45a8ff	1328	* @}
bogdanm	0:9b334a45a8ff	1329	*/
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/**
bogdanm	0:9b334a45a8ff	1332	* @brief Get I2S Input Clock based on I2S source clock selection
bogdanm	0:9b334a45a8ff	1333	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1334	* the configuration information for I2S module.
bogdanm	0:9b334a45a8ff	1335	* @retval I2S Clock Input
bogdanm	0:9b334a45a8ff	1336	*/
bogdanm	0:9b334a45a8ff	1337	static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1340	/* This variable used to store the VCO Input (value in Hz) */
bogdanm	0:9b334a45a8ff	1341	uint32_t vcoinput = 0;
bogdanm	0:9b334a45a8ff	1342	/* This variable used to store the I2S_CK_x (value in Hz) */
bogdanm	0:9b334a45a8ff	1343	uint32_t i2sclocksource = 0;
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Configure I2S Clock based on I2S source clock selection */
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
bogdanm	0:9b334a45a8ff	1348	switch(hi2s->Init.ClockSource)
bogdanm	0:9b334a45a8ff	1349	{
bogdanm	0:9b334a45a8ff	1350	case I2S_CLOCK_SYSCLK :
bogdanm	0:9b334a45a8ff	1351	{
bogdanm	0:9b334a45a8ff	1352	/* Configure the PLLI2S division factor */
bogdanm	0:9b334a45a8ff	1353	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm	0:9b334a45a8ff	1354	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	1355	{
bogdanm	0:9b334a45a8ff	1356	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	1357	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359	else
bogdanm	0:9b334a45a8ff	1360	{
bogdanm	0:9b334a45a8ff	1361	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	1362	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
bogdanm	0:9b334a45a8ff	1363	}
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	1366	/* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
bogdanm	0:9b334a45a8ff	1367	tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
bogdanm	0:9b334a45a8ff	1368	i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	break;
bogdanm	0:9b334a45a8ff	1371	}
bogdanm	0:9b334a45a8ff	1372	case I2S_CLOCK_EXTERNAL :
bogdanm	0:9b334a45a8ff	1373	{
bogdanm	0:9b334a45a8ff	1374	i2sclocksource = EXTERNAL_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	1375	break;
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377	default :
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	break;
bogdanm	0:9b334a45a8ff	1380	}
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/* the return result is the value of I2S clock */
bogdanm	0:9b334a45a8ff	1384	return i2sclocksource;
bogdanm	0:9b334a45a8ff	1385	}
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/** @addtogroup I2S_Private_Functions I2S Private Functions
bogdanm	0:9b334a45a8ff	1388	* @{
bogdanm	0:9b334a45a8ff	1389	*/
bogdanm	0:9b334a45a8ff	1390	/**
bogdanm	0:9b334a45a8ff	1391	* @brief DMA I2S transmit process complete callback
bogdanm	0:9b334a45a8ff	1392	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1393	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1394	* @retval None
bogdanm	0:9b334a45a8ff	1395	*/
bogdanm	0:9b334a45a8ff	1396	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1397	{
bogdanm	0:9b334a45a8ff	1398	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1401	{
bogdanm	0:9b334a45a8ff	1402	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1405	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1408	{
bogdanm	0:9b334a45a8ff	1409	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1412	}
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414	else
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1417	}
bogdanm	0:9b334a45a8ff	1418	}
bogdanm	0:9b334a45a8ff	1419	HAL_I2S_TxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/**
bogdanm	0:9b334a45a8ff	1423	* @brief DMA I2S transmit process half complete callback
bogdanm	0:9b334a45a8ff	1424	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1425	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1426	* @retval None
bogdanm	0:9b334a45a8ff	1427	*/
bogdanm	0:9b334a45a8ff	1428	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1429	{
bogdanm	0:9b334a45a8ff	1430	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	HAL_I2S_TxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1433	}
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/**
bogdanm	0:9b334a45a8ff	1436	* @brief DMA I2S receive process complete callback
bogdanm	0:9b334a45a8ff	1437	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1438	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1439	* @retval None
bogdanm	0:9b334a45a8ff	1440	*/
bogdanm	0:9b334a45a8ff	1441	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1442	{
bogdanm	0:9b334a45a8ff	1443	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1446	{
bogdanm	0:9b334a45a8ff	1447	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1448	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1451	if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1452	{
bogdanm	0:9b334a45a8ff	1453	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1454	{
bogdanm	0:9b334a45a8ff	1455	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457	}
bogdanm	0:9b334a45a8ff	1458	else
bogdanm	0:9b334a45a8ff	1459	{
bogdanm	0:9b334a45a8ff	1460	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1461	}
bogdanm	0:9b334a45a8ff	1462	}
bogdanm	0:9b334a45a8ff	1463	HAL_I2S_RxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1464	}
bogdanm	0:9b334a45a8ff	1465
bogdanm	0:9b334a45a8ff	1466	/**
bogdanm	0:9b334a45a8ff	1467	* @brief DMA I2S receive process half complete callback
bogdanm	0:9b334a45a8ff	1468	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1469	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1470	* @retval None
bogdanm	0:9b334a45a8ff	1471	*/
bogdanm	0:9b334a45a8ff	1472	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1475
bogdanm	0:9b334a45a8ff	1476	HAL_I2S_RxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1477	}
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/**
bogdanm	0:9b334a45a8ff	1480	* @brief DMA I2S communication error callback
bogdanm	0:9b334a45a8ff	1481	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1482	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1483	* @retval None
bogdanm	0:9b334a45a8ff	1484	*/
bogdanm	0:9b334a45a8ff	1485	static void I2S_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1486	{
bogdanm	0:9b334a45a8ff	1487	I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/* Disable Rx and Tx DMA Request */
bogdanm	0:9b334a45a8ff	1490	hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	1491	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1492	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1497	hi2s->ErrorCode \|= HAL_I2S_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1498	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1499	}
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/**
bogdanm	0:9b334a45a8ff	1502	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1503	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1504	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1505	* @retval None
bogdanm	0:9b334a45a8ff	1506	*/
bogdanm	0:9b334a45a8ff	1507	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1508	{
bogdanm	0:9b334a45a8ff	1509	/* Transmit data */
bogdanm	0:9b334a45a8ff	1510	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1511	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1514	{
bogdanm	0:9b334a45a8ff	1515	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1516	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1517
bogdanm	0:9b334a45a8ff	1518	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1519	HAL_I2S_TxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1520	}
bogdanm	0:9b334a45a8ff	1521	}
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	/**
bogdanm	0:9b334a45a8ff	1524	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1525	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1526	* @retval None
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1529	{
bogdanm	0:9b334a45a8ff	1530	/* Receive data */
bogdanm	0:9b334a45a8ff	1531	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	1532	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1535	{
bogdanm	0:9b334a45a8ff	1536	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1537	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1540	HAL_I2S_RxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1541	}
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543	/**
bogdanm	0:9b334a45a8ff	1544	* @}
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	#endif /* HAL_I2S_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1548	/**
bogdanm	0:9b334a45a8ff	1549	* @}
bogdanm	0:9b334a45a8ff	1550	*/
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/**
bogdanm	0:9b334a45a8ff	1553	* @}
bogdanm	0:9b334a45a8ff	1554	*/
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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