mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_eth.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief ETH HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Ethernet (ETH) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	(#)Declare a ETH_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	21	ETH_HandleTypeDef heth;
bogdanm	0:9b334a45a8ff	22
bogdanm	0:9b334a45a8ff	23	(#)Fill parameters of Init structure in heth handle
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
bogdanm	0:9b334a45a8ff	26
bogdanm	0:9b334a45a8ff	27	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
bogdanm	0:9b334a45a8ff	28	(##) Enable the Ethernet interface clock using
bogdanm	0:9b334a45a8ff	29	(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	30	(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	31	(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	(##) Initialize the related GPIO clocks
bogdanm	0:9b334a45a8ff	34	(##) Configure Ethernet pin-out
bogdanm	0:9b334a45a8ff	35	(##) Configure Ethernet NVIC interrupt (IT mode)
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
bogdanm	0:9b334a45a8ff	38	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
bogdanm	0:9b334a45a8ff	39	(##) HAL_ETH_DMARxDescListInit(); for Reception process
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#)Enable MAC and DMA transmission and reception:
bogdanm	0:9b334a45a8ff	42	(##) HAL_ETH_Start();
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
bogdanm	0:9b334a45a8ff	45	the frame to MAC TX FIFO:
bogdanm	0:9b334a45a8ff	46	(##) HAL_ETH_TransmitFrame();
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
bogdanm	0:9b334a45a8ff	49	frame parameters
bogdanm	0:9b334a45a8ff	50	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	(#) Get a received frame when an ETH RX interrupt occurs:
bogdanm	0:9b334a45a8ff	53	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	(#) Communicate with external PHY device:
bogdanm	0:9b334a45a8ff	56	(##) Read a specific register from the PHY
bogdanm	0:9b334a45a8ff	57	HAL_ETH_ReadPHYRegister();
bogdanm	0:9b334a45a8ff	58	(##) Write data to a specific RHY register:
bogdanm	0:9b334a45a8ff	59	HAL_ETH_WritePHYRegister();
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	(#) Configure the Ethernet MAC after ETH peripheral initialization
bogdanm	0:9b334a45a8ff	62	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	(#) Configure the Ethernet DMA after ETH peripheral initialization
bogdanm	0:9b334a45a8ff	65	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	@endverbatim
bogdanm	0:9b334a45a8ff	68	******************************************************************************
bogdanm	0:9b334a45a8ff	69	* @attention
bogdanm	0:9b334a45a8ff	70	*
bogdanm	0:9b334a45a8ff	71	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	72	*
bogdanm	0:9b334a45a8ff	73	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	74	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	75	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	76	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	77	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	78	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	79	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	80	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	81	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	82	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	83	*
bogdanm	0:9b334a45a8ff	84	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	85	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	86	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	87	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	88	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	89	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	90	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	91	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	92	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	93	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	94	*
bogdanm	0:9b334a45a8ff	95	******************************************************************************
bogdanm	0:9b334a45a8ff	96	*/
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	99	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	102	* @{
bogdanm	0:9b334a45a8ff	103	*/
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	/** @defgroup ETH ETH
bogdanm	0:9b334a45a8ff	106	* @brief ETH HAL module driver
bogdanm	0:9b334a45a8ff	107	* @{
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	#ifdef HAL_ETH_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	113	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	114	/** @defgroup ETH_Private_Constants ETH Private Constants
bogdanm	0:9b334a45a8ff	115	* @{
bogdanm	0:9b334a45a8ff	116	*/
mbed_official	83:a036322b8637	117	#define ETH_TIMEOUT_SWRESET ((uint32_t)500)
mbed_official	83:a036322b8637	118	#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
mbed_official	83:a036322b8637	119	#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	/**
bogdanm	0:9b334a45a8ff	122	* @}
bogdanm	0:9b334a45a8ff	123	*/
bogdanm	0:9b334a45a8ff	124	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	125	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	126	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	127	/** @defgroup ETH_Private_Functions ETH Private Functions
bogdanm	0:9b334a45a8ff	128	* @{
bogdanm	0:9b334a45a8ff	129	*/
bogdanm	0:9b334a45a8ff	130	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
bogdanm	0:9b334a45a8ff	131	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
bogdanm	0:9b334a45a8ff	132	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	133	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	134	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	135	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	136	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	137	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	138	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	139	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	140	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/**
bogdanm	0:9b334a45a8ff	143	* @}
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/** @defgroup ETH_Exported_Functions ETH Exported Functions
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	152	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	153	*
bogdanm	0:9b334a45a8ff	154	@verbatim
bogdanm	0:9b334a45a8ff	155	===============================================================================
bogdanm	0:9b334a45a8ff	156	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	157	===============================================================================
bogdanm	0:9b334a45a8ff	158	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	159	(+) Initialize and configure the Ethernet peripheral
bogdanm	0:9b334a45a8ff	160	(+) De-initialize the Ethernet peripheral
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	@endverbatim
bogdanm	0:9b334a45a8ff	163	* @{
bogdanm	0:9b334a45a8ff	164	*/
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/**
bogdanm	0:9b334a45a8ff	167	* @brief Initializes the Ethernet MAC and DMA according to default
bogdanm	0:9b334a45a8ff	168	* parameters.
bogdanm	0:9b334a45a8ff	169	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	170	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	171	* @retval HAL status
bogdanm	0:9b334a45a8ff	172	*/
bogdanm	0:9b334a45a8ff	173	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	174	{
bogdanm	0:9b334a45a8ff	175	uint32_t tempreg = 0, phyreg = 0;
bogdanm	0:9b334a45a8ff	176	uint32_t hclk = 60000000;
bogdanm	0:9b334a45a8ff	177	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	178	uint32_t err = ETH_SUCCESS;
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	181	if(heth == NULL)
bogdanm	0:9b334a45a8ff	182	{
bogdanm	0:9b334a45a8ff	183	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	184	}
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/* Check parameters */
bogdanm	0:9b334a45a8ff	187	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
bogdanm	0:9b334a45a8ff	188	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
bogdanm	0:9b334a45a8ff	189	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
bogdanm	0:9b334a45a8ff	190	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	if(heth->State == HAL_ETH_STATE_RESET)
bogdanm	0:9b334a45a8ff	193	{
bogdanm	0:9b334a45a8ff	194	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	195	heth->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	196	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm	0:9b334a45a8ff	197	HAL_ETH_MspInit(heth);
bogdanm	0:9b334a45a8ff	198	}
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/* Enable SYSCFG Clock */
bogdanm	0:9b334a45a8ff	201	__HAL_RCC_SYSCFG_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/* Select MII or RMII Mode*/
bogdanm	0:9b334a45a8ff	204	SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
bogdanm	0:9b334a45a8ff	205	SYSCFG->PMC \|= (uint32_t)heth->Init.MediaInterface;
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/* Ethernet Software reset */
bogdanm	0:9b334a45a8ff	208	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
bogdanm	0:9b334a45a8ff	209	/* After reset all the registers holds their respective reset values */
bogdanm	0:9b334a45a8ff	210	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
bogdanm	0:9b334a45a8ff	211
mbed_official	83:a036322b8637	212	/* Get tick */
mbed_official	83:a036322b8637	213	tickstart = HAL_GetTick();
mbed_official	83:a036322b8637	214
bogdanm	0:9b334a45a8ff	215	/* Wait for software reset */
bogdanm	0:9b334a45a8ff	216	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	217	{
mbed_official	83:a036322b8637	218	/* Check for the Timeout */
mbed_official	83:a036322b8637	219	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
mbed_official	83:a036322b8637	220	{
mbed_official	83:a036322b8637	221	heth->State= HAL_ETH_STATE_TIMEOUT;
mbed_official	83:a036322b8637	222
mbed_official	83:a036322b8637	223	/* Process Unlocked */
mbed_official	83:a036322b8637	224	__HAL_UNLOCK(heth);
mbed_official	83:a036322b8637	225
mbed_official	83:a036322b8637	226	/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
mbed_official	83:a036322b8637	227	not available, please check your external PHY or the IO configuration */
mbed_official	83:a036322b8637	228
mbed_official	83:a036322b8637	229	return HAL_TIMEOUT;
mbed_official	83:a036322b8637	230	}
bogdanm	0:9b334a45a8ff	231	}
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/-------------------------------- MAC Initialization ----------------------/
bogdanm	0:9b334a45a8ff	234	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	235	tempreg = (heth->Instance)->MACMIIAR;
bogdanm	0:9b334a45a8ff	236	/* Clear CSR Clock Range CR[2:0] bits */
bogdanm	0:9b334a45a8ff	237	tempreg &= ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/* Get hclk frequency value */
bogdanm	0:9b334a45a8ff	240	hclk = HAL_RCC_GetHCLKFreq();
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/* Set CR bits depending on hclk value */
bogdanm	0:9b334a45a8ff	243	if((hclk >= 20000000)&&(hclk < 35000000))
bogdanm	0:9b334a45a8ff	244	{
bogdanm	0:9b334a45a8ff	245	/* CSR Clock Range between 20-35 MHz */
bogdanm	0:9b334a45a8ff	246	tempreg \|= (uint32_t)ETH_MACMIIAR_CR_Div16;
bogdanm	0:9b334a45a8ff	247	}
bogdanm	0:9b334a45a8ff	248	else if((hclk >= 35000000)&&(hclk < 60000000))
bogdanm	0:9b334a45a8ff	249	{
bogdanm	0:9b334a45a8ff	250	/* CSR Clock Range between 35-60 MHz */
bogdanm	0:9b334a45a8ff	251	tempreg \|= (uint32_t)ETH_MACMIIAR_CR_Div26;
bogdanm	0:9b334a45a8ff	252	}
bogdanm	0:9b334a45a8ff	253	else if((hclk >= 60000000)&&(hclk < 100000000))
bogdanm	0:9b334a45a8ff	254	{
bogdanm	0:9b334a45a8ff	255	/* CSR Clock Range between 60-100 MHz */
bogdanm	0:9b334a45a8ff	256	tempreg \|= (uint32_t)ETH_MACMIIAR_CR_Div42;
bogdanm	0:9b334a45a8ff	257	}
bogdanm	0:9b334a45a8ff	258	else if((hclk >= 100000000)&&(hclk < 150000000))
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	/* CSR Clock Range between 100-150 MHz */
bogdanm	0:9b334a45a8ff	261	tempreg \|= (uint32_t)ETH_MACMIIAR_CR_Div62;
bogdanm	0:9b334a45a8ff	262	}
mbed_official	83:a036322b8637	263	else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	/* CSR Clock Range between 150-216 MHz */
bogdanm	0:9b334a45a8ff	266	tempreg \|= (uint32_t)ETH_MACMIIAR_CR_Div102;
bogdanm	0:9b334a45a8ff	267	}
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
bogdanm	0:9b334a45a8ff	270	(heth->Instance)->MACMIIAR = (uint32_t)tempreg;
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/-------------------- PHY initialization and configuration ----------------/
bogdanm	0:9b334a45a8ff	273	/* Put the PHY in reset mode */
bogdanm	0:9b334a45a8ff	274	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	277	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	280	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	283	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	286	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	287	}
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Delay to assure PHY reset */
bogdanm	0:9b334a45a8ff	290	HAL_Delay(PHY_RESET_DELAY);
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
bogdanm	0:9b334a45a8ff	293	{
bogdanm	0:9b334a45a8ff	294	/* Get tick */
bogdanm	0:9b334a45a8ff	295	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* We wait for linked status */
bogdanm	0:9b334a45a8ff	298	do
bogdanm	0:9b334a45a8ff	299	{
bogdanm	0:9b334a45a8ff	300	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/* Check for the Timeout */
mbed_official	83:a036322b8637	303	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	306	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	309	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	314	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	317	}
bogdanm	0:9b334a45a8ff	318	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Enable Auto-Negotiation */
bogdanm	0:9b334a45a8ff	322	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
bogdanm	0:9b334a45a8ff	323	{
bogdanm	0:9b334a45a8ff	324	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	325	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	328	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	331	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	334	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	335	}
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/* Get tick */
bogdanm	0:9b334a45a8ff	338	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* Wait until the auto-negotiation will be completed */
bogdanm	0:9b334a45a8ff	341	do
bogdanm	0:9b334a45a8ff	342	{
bogdanm	0:9b334a45a8ff	343	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/* Check for the Timeout */
mbed_official	83:a036322b8637	346	if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
bogdanm	0:9b334a45a8ff	347	{
bogdanm	0:9b334a45a8ff	348	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	349	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	352	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	357	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	360	}
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/* Read the result of the auto-negotiation */
bogdanm	0:9b334a45a8ff	365	if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
bogdanm	0:9b334a45a8ff	366	{
bogdanm	0:9b334a45a8ff	367	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	368	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	371	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	374	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	377	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	378	}
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
bogdanm	0:9b334a45a8ff	381	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	382	{
bogdanm	0:9b334a45a8ff	383	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
bogdanm	0:9b334a45a8ff	384	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386	else
bogdanm	0:9b334a45a8ff	387	{
bogdanm	0:9b334a45a8ff	388	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
bogdanm	0:9b334a45a8ff	389	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
bogdanm	0:9b334a45a8ff	390	}
bogdanm	0:9b334a45a8ff	391	/* Configure the MAC with the speed fixed by the auto-negotiation process */
bogdanm	0:9b334a45a8ff	392	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
bogdanm	0:9b334a45a8ff	393	{
bogdanm	0:9b334a45a8ff	394	/* Set Ethernet speed to 10M following the auto-negotiation */
bogdanm	0:9b334a45a8ff	395	(heth->Init).Speed = ETH_SPEED_10M;
bogdanm	0:9b334a45a8ff	396	}
bogdanm	0:9b334a45a8ff	397	else
bogdanm	0:9b334a45a8ff	398	{
bogdanm	0:9b334a45a8ff	399	/* Set Ethernet speed to 100M following the auto-negotiation */
bogdanm	0:9b334a45a8ff	400	(heth->Init).Speed = ETH_SPEED_100M;
bogdanm	0:9b334a45a8ff	401	}
bogdanm	0:9b334a45a8ff	402	}
bogdanm	0:9b334a45a8ff	403	else /* AutoNegotiation Disable */
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	/* Check parameters */
bogdanm	0:9b334a45a8ff	406	assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm	0:9b334a45a8ff	407	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/* Set MAC Speed and Duplex Mode */
bogdanm	0:9b334a45a8ff	410	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) \|
bogdanm	0:9b334a45a8ff	411	(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
bogdanm	0:9b334a45a8ff	412	{
bogdanm	0:9b334a45a8ff	413	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	414	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	417	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	420	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	423	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	424	}
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/* Delay to assure PHY configuration */
bogdanm	0:9b334a45a8ff	427	HAL_Delay(PHY_CONFIG_DELAY);
bogdanm	0:9b334a45a8ff	428	}
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	431	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	434	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	/* Return function status */
bogdanm	0:9b334a45a8ff	437	return HAL_OK;
bogdanm	0:9b334a45a8ff	438	}
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/**
bogdanm	0:9b334a45a8ff	441	* @brief De-Initializes the ETH peripheral.
bogdanm	0:9b334a45a8ff	442	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	443	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	444	* @retval HAL status
bogdanm	0:9b334a45a8ff	445	*/
bogdanm	0:9b334a45a8ff	446	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	449	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm	0:9b334a45a8ff	452	HAL_ETH_MspDeInit(heth);
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* Set ETH HAL state to Disabled */
bogdanm	0:9b334a45a8ff	455	heth->State= HAL_ETH_STATE_RESET;
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/* Release Lock */
bogdanm	0:9b334a45a8ff	458	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	/* Return function status */
bogdanm	0:9b334a45a8ff	461	return HAL_OK;
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @brief Initializes the DMA Tx descriptors in chain mode.
bogdanm	0:9b334a45a8ff	466	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	467	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	468	* @param DMATxDescTab: Pointer to the first Tx desc list
bogdanm	0:9b334a45a8ff	469	* @param TxBuff: Pointer to the first TxBuffer list
bogdanm	0:9b334a45a8ff	470	* @param TxBuffCount: Number of the used Tx desc in the list
bogdanm	0:9b334a45a8ff	471	* @retval HAL status
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
bogdanm	0:9b334a45a8ff	474	{
bogdanm	0:9b334a45a8ff	475	uint32_t i = 0;
bogdanm	0:9b334a45a8ff	476	ETH_DMADescTypeDef *dmatxdesc;
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	/* Process Locked */
bogdanm	0:9b334a45a8ff	479	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	482	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
bogdanm	0:9b334a45a8ff	485	heth->TxDesc = DMATxDescTab;
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	/* Fill each DMATxDesc descriptor with the right values */
bogdanm	0:9b334a45a8ff	488	for(i=0; i < TxBuffCount; i++)
bogdanm	0:9b334a45a8ff	489	{
bogdanm	0:9b334a45a8ff	490	/* Get the pointer on the ith member of the Tx Desc list */
bogdanm	0:9b334a45a8ff	491	dmatxdesc = DMATxDescTab + i;
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/* Set Second Address Chained bit */
bogdanm	0:9b334a45a8ff	494	dmatxdesc->Status = ETH_DMATXDESC_TCH;
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/* Set Buffer1 address pointer */
bogdanm	0:9b334a45a8ff	497	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	/* Set the DMA Tx descriptors checksum insertion */
bogdanm	0:9b334a45a8ff	502	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm	0:9b334a45a8ff	506	if(i < (TxBuffCount-1))
bogdanm	0:9b334a45a8ff	507	{
bogdanm	0:9b334a45a8ff	508	/* Set next descriptor address register with next descriptor base address */
bogdanm	0:9b334a45a8ff	509	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
bogdanm	0:9b334a45a8ff	510	}
bogdanm	0:9b334a45a8ff	511	else
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm	0:9b334a45a8ff	514	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516	}
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/* Set Transmit Descriptor List Address Register */
bogdanm	0:9b334a45a8ff	519	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	522	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	525	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* Return function status */
bogdanm	0:9b334a45a8ff	528	return HAL_OK;
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/**
bogdanm	0:9b334a45a8ff	532	* @brief Initializes the DMA Rx descriptors in chain mode.
bogdanm	0:9b334a45a8ff	533	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	534	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	535	* @param DMARxDescTab: Pointer to the first Rx desc list
bogdanm	0:9b334a45a8ff	536	* @param RxBuff: Pointer to the first RxBuffer list
bogdanm	0:9b334a45a8ff	537	* @param RxBuffCount: Number of the used Rx desc in the list
bogdanm	0:9b334a45a8ff	538	* @retval HAL status
bogdanm	0:9b334a45a8ff	539	*/
bogdanm	0:9b334a45a8ff	540	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
bogdanm	0:9b334a45a8ff	541	{
bogdanm	0:9b334a45a8ff	542	uint32_t i = 0;
bogdanm	0:9b334a45a8ff	543	ETH_DMADescTypeDef *DMARxDesc;
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/* Process Locked */
bogdanm	0:9b334a45a8ff	546	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	549	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
bogdanm	0:9b334a45a8ff	552	heth->RxDesc = DMARxDescTab;
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	/* Fill each DMARxDesc descriptor with the right values */
bogdanm	0:9b334a45a8ff	555	for(i=0; i < RxBuffCount; i++)
bogdanm	0:9b334a45a8ff	556	{
bogdanm	0:9b334a45a8ff	557	/* Get the pointer on the ith member of the Rx Desc list */
bogdanm	0:9b334a45a8ff	558	DMARxDesc = DMARxDescTab+i;
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/* Set Own bit of the Rx descriptor Status */
bogdanm	0:9b334a45a8ff	561	DMARxDesc->Status = ETH_DMARXDESC_OWN;
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Set Buffer1 size and Second Address Chained bit */
bogdanm	0:9b334a45a8ff	564	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/* Set Buffer1 address pointer */
bogdanm	0:9b334a45a8ff	567	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm	0:9b334a45a8ff	570	{
bogdanm	0:9b334a45a8ff	571	/* Enable Ethernet DMA Rx Descriptor interrupt */
bogdanm	0:9b334a45a8ff	572	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
bogdanm	0:9b334a45a8ff	573	}
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm	0:9b334a45a8ff	576	if(i < (RxBuffCount-1))
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	/* Set next descriptor address register with next descriptor base address */
bogdanm	0:9b334a45a8ff	579	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
bogdanm	0:9b334a45a8ff	580	}
bogdanm	0:9b334a45a8ff	581	else
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm	0:9b334a45a8ff	584	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
bogdanm	0:9b334a45a8ff	585	}
bogdanm	0:9b334a45a8ff	586	}
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	/* Set Receive Descriptor List Address Register */
bogdanm	0:9b334a45a8ff	589	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	592	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	595	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	/* Return function status */
bogdanm	0:9b334a45a8ff	598	return HAL_OK;
bogdanm	0:9b334a45a8ff	599	}
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/**
bogdanm	0:9b334a45a8ff	602	* @brief Initializes the ETH MSP.
bogdanm	0:9b334a45a8ff	603	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	604	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	605	* @retval None
bogdanm	0:9b334a45a8ff	606	*/
bogdanm	0:9b334a45a8ff	607	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	608	{
mbed_official	83:a036322b8637	609	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	610	UNUSED(heth);
mbed_official	83:a036322b8637	611
bogdanm	0:9b334a45a8ff	612	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	613	the HAL_ETH_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	614	*/
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/**
bogdanm	0:9b334a45a8ff	618	* @brief DeInitializes ETH MSP.
bogdanm	0:9b334a45a8ff	619	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	620	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	621	* @retval None
bogdanm	0:9b334a45a8ff	622	*/
bogdanm	0:9b334a45a8ff	623	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	624	{
mbed_official	83:a036322b8637	625	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	626	UNUSED(heth);
mbed_official	83:a036322b8637	627
bogdanm	0:9b334a45a8ff	628	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	629	the HAL_ETH_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	630	*/
bogdanm	0:9b334a45a8ff	631	}
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	/**
bogdanm	0:9b334a45a8ff	634	* @}
bogdanm	0:9b334a45a8ff	635	*/
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	638	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	639	*
bogdanm	0:9b334a45a8ff	640	@verbatim
bogdanm	0:9b334a45a8ff	641	==============================================================================
bogdanm	0:9b334a45a8ff	642	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	643	==============================================================================
bogdanm	0:9b334a45a8ff	644	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	645	(+) Transmit a frame
bogdanm	0:9b334a45a8ff	646	HAL_ETH_TransmitFrame();
bogdanm	0:9b334a45a8ff	647	(+) Receive a frame
bogdanm	0:9b334a45a8ff	648	HAL_ETH_GetReceivedFrame();
bogdanm	0:9b334a45a8ff	649	HAL_ETH_GetReceivedFrame_IT();
bogdanm	0:9b334a45a8ff	650	(+) Read from an External PHY register
bogdanm	0:9b334a45a8ff	651	HAL_ETH_ReadPHYRegister();
bogdanm	0:9b334a45a8ff	652	(+) Write to an External PHY register
bogdanm	0:9b334a45a8ff	653	HAL_ETH_WritePHYRegister();
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	@endverbatim
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	* @{
bogdanm	0:9b334a45a8ff	658	*/
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/**
bogdanm	0:9b334a45a8ff	661	* @brief Sends an Ethernet frame.
bogdanm	0:9b334a45a8ff	662	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	663	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	664	* @param FrameLength: Amount of data to be sent
bogdanm	0:9b334a45a8ff	665	* @retval HAL status
bogdanm	0:9b334a45a8ff	666	*/
bogdanm	0:9b334a45a8ff	667	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
bogdanm	0:9b334a45a8ff	668	{
bogdanm	0:9b334a45a8ff	669	uint32_t bufcount = 0, size = 0, i = 0;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Process Locked */
bogdanm	0:9b334a45a8ff	672	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	675	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	if (FrameLength == 0)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	/* Set ETH HAL state to READY */
bogdanm	0:9b334a45a8ff	680	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	683	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
bogdanm	0:9b334a45a8ff	689	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	690	{
bogdanm	0:9b334a45a8ff	691	/* OWN bit set */
bogdanm	0:9b334a45a8ff	692	heth->State = HAL_ETH_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	695	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Get the number of needed Tx buffers for the current frame */
bogdanm	0:9b334a45a8ff	701	if (FrameLength > ETH_TX_BUF_SIZE)
bogdanm	0:9b334a45a8ff	702	{
bogdanm	0:9b334a45a8ff	703	bufcount = FrameLength/ETH_TX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	704	if (FrameLength % ETH_TX_BUF_SIZE)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	bufcount++;
bogdanm	0:9b334a45a8ff	707	}
bogdanm	0:9b334a45a8ff	708	}
bogdanm	0:9b334a45a8ff	709	else
bogdanm	0:9b334a45a8ff	710	{
bogdanm	0:9b334a45a8ff	711	bufcount = 1;
bogdanm	0:9b334a45a8ff	712	}
bogdanm	0:9b334a45a8ff	713	if (bufcount == 1)
bogdanm	0:9b334a45a8ff	714	{
bogdanm	0:9b334a45a8ff	715	/* Set LAST and FIRST segment */
bogdanm	0:9b334a45a8ff	716	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
bogdanm	0:9b334a45a8ff	717	/* Set frame size */
bogdanm	0:9b334a45a8ff	718	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	719	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm	0:9b334a45a8ff	720	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
bogdanm	0:9b334a45a8ff	721	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	722	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724	else
bogdanm	0:9b334a45a8ff	725	{
bogdanm	0:9b334a45a8ff	726	for (i=0; i< bufcount; i++)
bogdanm	0:9b334a45a8ff	727	{
bogdanm	0:9b334a45a8ff	728	/* Clear FIRST and LAST segment bits */
bogdanm	0:9b334a45a8ff	729	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	if (i == 0)
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	/* Setting the first segment bit */
bogdanm	0:9b334a45a8ff	734	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Program size */
bogdanm	0:9b334a45a8ff	738	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	if (i == (bufcount-1))
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	/* Setting the last segment bit */
bogdanm	0:9b334a45a8ff	743	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
bogdanm	0:9b334a45a8ff	744	size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	745	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	746	}
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm	0:9b334a45a8ff	749	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
bogdanm	0:9b334a45a8ff	750	/* point to next descriptor */
bogdanm	0:9b334a45a8ff	751	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	752	}
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
bogdanm	0:9b334a45a8ff	756	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	/* Clear TBUS ETHERNET DMA flag */
bogdanm	0:9b334a45a8ff	759	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
bogdanm	0:9b334a45a8ff	760	/* Resume DMA transmission*/
bogdanm	0:9b334a45a8ff	761	(heth->Instance)->DMATPDR = 0;
bogdanm	0:9b334a45a8ff	762	}
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	765	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	768	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/* Return function status */
bogdanm	0:9b334a45a8ff	771	return HAL_OK;
bogdanm	0:9b334a45a8ff	772	}
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	/**
bogdanm	0:9b334a45a8ff	775	* @brief Checks for received frames.
bogdanm	0:9b334a45a8ff	776	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	777	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	778	* @retval HAL status
bogdanm	0:9b334a45a8ff	779	*/
bogdanm	0:9b334a45a8ff	780	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	781	{
bogdanm	0:9b334a45a8ff	782	uint32_t framelength = 0;
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/* Process Locked */
bogdanm	0:9b334a45a8ff	785	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* Check the ETH state to BUSY */
bogdanm	0:9b334a45a8ff	788	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	/* Check if segment is not owned by DMA */
bogdanm	0:9b334a45a8ff	791	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	792	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	/* Check if last segment */
bogdanm	0:9b334a45a8ff	795	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
bogdanm	0:9b334a45a8ff	796	{
bogdanm	0:9b334a45a8ff	797	/* increment segment count */
bogdanm	0:9b334a45a8ff	798	(heth->RxFrameInfos).SegCount++;
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Check if last segment is first segment: one segment contains the frame */
bogdanm	0:9b334a45a8ff	801	if ((heth->RxFrameInfos).SegCount == 1)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
bogdanm	0:9b334a45a8ff	804	}
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm	0:9b334a45a8ff	809	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm	0:9b334a45a8ff	810	heth->RxFrameInfos.length = framelength;
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* Get the address of the buffer start address */
bogdanm	0:9b334a45a8ff	813	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm	0:9b334a45a8ff	814	/* point to next descriptor */
bogdanm	0:9b334a45a8ff	815	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	818	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	821	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Return function status */
bogdanm	0:9b334a45a8ff	824	return HAL_OK;
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826	/* Check if first segment */
bogdanm	0:9b334a45a8ff	827	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	828	{
bogdanm	0:9b334a45a8ff	829	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	830	(heth->RxFrameInfos).LSRxDesc = NULL;
bogdanm	0:9b334a45a8ff	831	(heth->RxFrameInfos).SegCount = 1;
bogdanm	0:9b334a45a8ff	832	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	833	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	/* Check if intermediate segment */
bogdanm	0:9b334a45a8ff	836	else
bogdanm	0:9b334a45a8ff	837	{
bogdanm	0:9b334a45a8ff	838	(heth->RxFrameInfos).SegCount++;
bogdanm	0:9b334a45a8ff	839	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	840	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	841	}
bogdanm	0:9b334a45a8ff	842	}
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	845	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	848	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/* Return function status */
bogdanm	0:9b334a45a8ff	851	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/**
bogdanm	0:9b334a45a8ff	855	* @brief Gets the Received frame in interrupt mode.
bogdanm	0:9b334a45a8ff	856	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	857	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	858	* @retval HAL status
bogdanm	0:9b334a45a8ff	859	*/
bogdanm	0:9b334a45a8ff	860	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	uint32_t descriptorscancounter = 0;
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Process Locked */
bogdanm	0:9b334a45a8ff	865	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/* Set ETH HAL State to BUSY */
bogdanm	0:9b334a45a8ff	868	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/* Scan descriptors owned by CPU */
bogdanm	0:9b334a45a8ff	871	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
bogdanm	0:9b334a45a8ff	872	{
bogdanm	0:9b334a45a8ff	873	/* Just for security */
bogdanm	0:9b334a45a8ff	874	descriptorscancounter++;
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/* Check if first segment in frame */
bogdanm	0:9b334a45a8ff	877	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	878	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	881	heth->RxFrameInfos.SegCount = 1;
bogdanm	0:9b334a45a8ff	882	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	883	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	884	}
bogdanm	0:9b334a45a8ff	885	/* Check if intermediate segment */
bogdanm	0:9b334a45a8ff	886	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	887	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	888	{
bogdanm	0:9b334a45a8ff	889	/* Increment segment count */
bogdanm	0:9b334a45a8ff	890	(heth->RxFrameInfos.SegCount)++;
bogdanm	0:9b334a45a8ff	891	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	892	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	893	}
bogdanm	0:9b334a45a8ff	894	/* Should be last segment */
bogdanm	0:9b334a45a8ff	895	else
bogdanm	0:9b334a45a8ff	896	{
bogdanm	0:9b334a45a8ff	897	/* Last segment */
bogdanm	0:9b334a45a8ff	898	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	/* Increment segment count */
bogdanm	0:9b334a45a8ff	901	(heth->RxFrameInfos.SegCount)++;
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/* Check if last segment is first segment: one segment contains the frame */
bogdanm	0:9b334a45a8ff	904	if ((heth->RxFrameInfos.SegCount) == 1)
bogdanm	0:9b334a45a8ff	905	{
bogdanm	0:9b334a45a8ff	906	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm	0:9b334a45a8ff	910	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	/* Get the address of the buffer start address */
bogdanm	0:9b334a45a8ff	913	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	916	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	919	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	922	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* Return function status */
bogdanm	0:9b334a45a8ff	925	return HAL_OK;
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927	}
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	930	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	933	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Return function status */
bogdanm	0:9b334a45a8ff	936	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	937	}
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/**
bogdanm	0:9b334a45a8ff	940	* @brief This function handles ETH interrupt request.
bogdanm	0:9b334a45a8ff	941	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	942	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	943	* @retval HAL status
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	946	{
bogdanm	0:9b334a45a8ff	947	/* Frame received */
bogdanm	0:9b334a45a8ff	948	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
bogdanm	0:9b334a45a8ff	949	{
bogdanm	0:9b334a45a8ff	950	/* Receive complete callback */
bogdanm	0:9b334a45a8ff	951	HAL_ETH_RxCpltCallback(heth);
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	/* Clear the Eth DMA Rx IT pending bits */
bogdanm	0:9b334a45a8ff	954	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	957	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	960	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	}
bogdanm	0:9b334a45a8ff	963	/* Frame transmitted */
bogdanm	0:9b334a45a8ff	964	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
bogdanm	0:9b334a45a8ff	965	{
bogdanm	0:9b334a45a8ff	966	/* Transfer complete callback */
bogdanm	0:9b334a45a8ff	967	HAL_ETH_TxCpltCallback(heth);
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/* Clear the Eth DMA Tx IT pending bits */
bogdanm	0:9b334a45a8ff	970	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	973	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	976	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	977	}
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/* Clear the interrupt flags */
bogdanm	0:9b334a45a8ff	980	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/* ETH DMA Error */
bogdanm	0:9b334a45a8ff	983	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
bogdanm	0:9b334a45a8ff	984	{
bogdanm	0:9b334a45a8ff	985	/* Ethernet Error callback */
bogdanm	0:9b334a45a8ff	986	HAL_ETH_ErrorCallback(heth);
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* Clear the interrupt flags */
bogdanm	0:9b334a45a8ff	989	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	992	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	995	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	996	}
bogdanm	0:9b334a45a8ff	997	}
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/**
bogdanm	0:9b334a45a8ff	1000	* @brief Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1001	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1002	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1003	* @retval None
bogdanm	0:9b334a45a8ff	1004	*/
bogdanm	0:9b334a45a8ff	1005	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1006	{
mbed_official	83:a036322b8637	1007	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1008	UNUSED(heth);
mbed_official	83:a036322b8637	1009
bogdanm	0:9b334a45a8ff	1010	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1011	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1012	*/
bogdanm	0:9b334a45a8ff	1013	}
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	/**
bogdanm	0:9b334a45a8ff	1016	* @brief Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1017	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1018	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1019	* @retval None
bogdanm	0:9b334a45a8ff	1020	*/
bogdanm	0:9b334a45a8ff	1021	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1022	{
mbed_official	83:a036322b8637	1023	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1024	UNUSED(heth);
mbed_official	83:a036322b8637	1025
bogdanm	0:9b334a45a8ff	1026	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1027	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029	}
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/**
bogdanm	0:9b334a45a8ff	1032	* @brief Ethernet transfer error callbacks
bogdanm	0:9b334a45a8ff	1033	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1034	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1035	* @retval None
bogdanm	0:9b334a45a8ff	1036	*/
bogdanm	0:9b334a45a8ff	1037	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1038	{
mbed_official	83:a036322b8637	1039	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1040	UNUSED(heth);
mbed_official	83:a036322b8637	1041
bogdanm	0:9b334a45a8ff	1042	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1043	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1044	*/
bogdanm	0:9b334a45a8ff	1045	}
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/**
bogdanm	0:9b334a45a8ff	1048	* @brief Reads a PHY register
bogdanm	0:9b334a45a8ff	1049	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1050	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1051	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm	0:9b334a45a8ff	1052	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1053	* PHY_BCR: Transceiver Basic Control Register,
bogdanm	0:9b334a45a8ff	1054	* PHY_BSR: Transceiver Basic Status Register.
bogdanm	0:9b334a45a8ff	1055	* More PHY register could be read depending on the used PHY
bogdanm	0:9b334a45a8ff	1056	* @param RegValue: PHY register value
bogdanm	0:9b334a45a8ff	1057	* @retval HAL status
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1062	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* Check parameters */
bogdanm	0:9b334a45a8ff	1065	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	1068	if(heth->State == HAL_ETH_STATE_BUSY_RD)
bogdanm	0:9b334a45a8ff	1069	{
bogdanm	0:9b334a45a8ff	1070	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1071	}
bogdanm	0:9b334a45a8ff	1072	/* Set ETH HAL State to BUSY_RD */
bogdanm	0:9b334a45a8ff	1073	heth->State = HAL_ETH_STATE_BUSY_RD;
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	1076	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm	0:9b334a45a8ff	1079	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/* Prepare the MII address register value */
bogdanm	0:9b334a45a8ff	1082	tmpreg \|=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm	0:9b334a45a8ff	1083	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm	0:9b334a45a8ff	1084	tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
bogdanm	0:9b334a45a8ff	1085	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/* Write the result value into the MII Address register */
bogdanm	0:9b334a45a8ff	1088	heth->Instance->MACMIIAR = tmpreg;
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/* Get tick */
bogdanm	0:9b334a45a8ff	1091	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	/* Check for the Busy flag */
bogdanm	0:9b334a45a8ff	1094	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1097	if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
bogdanm	0:9b334a45a8ff	1098	{
bogdanm	0:9b334a45a8ff	1099	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1102	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1108	}
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/* Get MACMIIDR value */
bogdanm	0:9b334a45a8ff	1111	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* Set ETH HAL State to READY */
bogdanm	0:9b334a45a8ff	1114	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/* Return function status */
bogdanm	0:9b334a45a8ff	1117	return HAL_OK;
bogdanm	0:9b334a45a8ff	1118	}
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/**
bogdanm	0:9b334a45a8ff	1121	* @brief Writes to a PHY register.
bogdanm	0:9b334a45a8ff	1122	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1123	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1124	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm	0:9b334a45a8ff	1125	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1126	* PHY_BCR: Transceiver Control Register.
bogdanm	0:9b334a45a8ff	1127	* More PHY register could be written depending on the used PHY
bogdanm	0:9b334a45a8ff	1128	* @param RegValue: the value to write
bogdanm	0:9b334a45a8ff	1129	* @retval HAL status
bogdanm	0:9b334a45a8ff	1130	*/
bogdanm	0:9b334a45a8ff	1131	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm	0:9b334a45a8ff	1132	{
bogdanm	0:9b334a45a8ff	1133	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1134	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	/* Check parameters */
bogdanm	0:9b334a45a8ff	1137	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	1140	if(heth->State == HAL_ETH_STATE_BUSY_WR)
bogdanm	0:9b334a45a8ff	1141	{
bogdanm	0:9b334a45a8ff	1142	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144	/* Set ETH HAL State to BUSY_WR */
bogdanm	0:9b334a45a8ff	1145	heth->State = HAL_ETH_STATE_BUSY_WR;
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	1148	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm	0:9b334a45a8ff	1151	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/* Prepare the MII register address value */
bogdanm	0:9b334a45a8ff	1154	tmpreg \|=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm	0:9b334a45a8ff	1155	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm	0:9b334a45a8ff	1156	tmpreg \|= ETH_MACMIIAR_MW; /* Set the write mode */
bogdanm	0:9b334a45a8ff	1157	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	/* Give the value to the MII data register */
bogdanm	0:9b334a45a8ff	1160	heth->Instance->MACMIIDR = (uint16_t)RegValue;
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/* Write the result value into the MII Address register */
bogdanm	0:9b334a45a8ff	1163	heth->Instance->MACMIIAR = tmpreg;
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Get tick */
bogdanm	0:9b334a45a8ff	1166	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Check for the Busy flag */
bogdanm	0:9b334a45a8ff	1169	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1172	if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
bogdanm	0:9b334a45a8ff	1173	{
bogdanm	0:9b334a45a8ff	1174	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1177	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1183	}
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/* Set ETH HAL State to READY */
bogdanm	0:9b334a45a8ff	1186	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/* Return function status */
bogdanm	0:9b334a45a8ff	1189	return HAL_OK;
bogdanm	0:9b334a45a8ff	1190	}
bogdanm	0:9b334a45a8ff	1191
bogdanm	0:9b334a45a8ff	1192	/**
bogdanm	0:9b334a45a8ff	1193	* @}
bogdanm	0:9b334a45a8ff	1194	*/
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1197	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1198	*
bogdanm	0:9b334a45a8ff	1199	@verbatim
bogdanm	0:9b334a45a8ff	1200	===============================================================================
bogdanm	0:9b334a45a8ff	1201	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1202	===============================================================================
bogdanm	0:9b334a45a8ff	1203	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1204	(+) Enable MAC and DMA transmission and reception.
bogdanm	0:9b334a45a8ff	1205	HAL_ETH_Start();
bogdanm	0:9b334a45a8ff	1206	(+) Disable MAC and DMA transmission and reception.
bogdanm	0:9b334a45a8ff	1207	HAL_ETH_Stop();
bogdanm	0:9b334a45a8ff	1208	(+) Set the MAC configuration in runtime mode
bogdanm	0:9b334a45a8ff	1209	HAL_ETH_ConfigMAC();
bogdanm	0:9b334a45a8ff	1210	(+) Set the DMA configuration in runtime mode
bogdanm	0:9b334a45a8ff	1211	HAL_ETH_ConfigDMA();
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	@endverbatim
bogdanm	0:9b334a45a8ff	1214	* @{
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/**
bogdanm	0:9b334a45a8ff	1218	* @brief Enables Ethernet MAC and DMA reception/transmission
bogdanm	0:9b334a45a8ff	1219	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1220	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1221	* @retval HAL status
bogdanm	0:9b334a45a8ff	1222	*/
bogdanm	0:9b334a45a8ff	1223	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1224	{
bogdanm	0:9b334a45a8ff	1225	/* Process Locked */
bogdanm	0:9b334a45a8ff	1226	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1229	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/* Enable transmit state machine of the MAC for transmission on the MII */
bogdanm	0:9b334a45a8ff	1232	ETH_MACTransmissionEnable(heth);
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* Enable receive state machine of the MAC for reception from the MII */
bogdanm	0:9b334a45a8ff	1235	ETH_MACReceptionEnable(heth);
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/* Flush Transmit FIFO */
bogdanm	0:9b334a45a8ff	1238	ETH_FlushTransmitFIFO(heth);
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Start DMA transmission */
bogdanm	0:9b334a45a8ff	1241	ETH_DMATransmissionEnable(heth);
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	/* Start DMA reception */
bogdanm	0:9b334a45a8ff	1244	ETH_DMAReceptionEnable(heth);
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* Set the ETH state to READY*/
bogdanm	0:9b334a45a8ff	1247	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1250	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Return function status */
bogdanm	0:9b334a45a8ff	1253	return HAL_OK;
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/**
bogdanm	0:9b334a45a8ff	1257	* @brief Stop Ethernet MAC and DMA reception/transmission
bogdanm	0:9b334a45a8ff	1258	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1259	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1260	* @retval HAL status
bogdanm	0:9b334a45a8ff	1261	*/
bogdanm	0:9b334a45a8ff	1262	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1263	{
bogdanm	0:9b334a45a8ff	1264	/* Process Locked */
bogdanm	0:9b334a45a8ff	1265	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1268	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Stop DMA transmission */
bogdanm	0:9b334a45a8ff	1271	ETH_DMATransmissionDisable(heth);
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Stop DMA reception */
bogdanm	0:9b334a45a8ff	1274	ETH_DMAReceptionDisable(heth);
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/* Disable receive state machine of the MAC for reception from the MII */
bogdanm	0:9b334a45a8ff	1277	ETH_MACReceptionDisable(heth);
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/* Flush Transmit FIFO */
bogdanm	0:9b334a45a8ff	1280	ETH_FlushTransmitFIFO(heth);
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	/* Disable transmit state machine of the MAC for transmission on the MII */
bogdanm	0:9b334a45a8ff	1283	ETH_MACTransmissionDisable(heth);
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	/* Set the ETH state*/
bogdanm	0:9b334a45a8ff	1286	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1287
bogdanm	0:9b334a45a8ff	1288	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1289	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/* Return function status */
bogdanm	0:9b334a45a8ff	1292	return HAL_OK;
bogdanm	0:9b334a45a8ff	1293	}
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/**
bogdanm	0:9b334a45a8ff	1296	* @brief Set ETH MAC Configuration.
bogdanm	0:9b334a45a8ff	1297	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1298	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1299	* @param macconf: MAC Configuration structure
bogdanm	0:9b334a45a8ff	1300	* @retval HAL status
bogdanm	0:9b334a45a8ff	1301	*/
bogdanm	0:9b334a45a8ff	1302	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
bogdanm	0:9b334a45a8ff	1303	{
bogdanm	0:9b334a45a8ff	1304	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	/* Process Locked */
bogdanm	0:9b334a45a8ff	1307	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1310	heth->State= HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm	0:9b334a45a8ff	1313	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	if (macconf != NULL)
bogdanm	0:9b334a45a8ff	1316	{
bogdanm	0:9b334a45a8ff	1317	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1318	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
bogdanm	0:9b334a45a8ff	1319	assert_param(IS_ETH_JABBER(macconf->Jabber));
bogdanm	0:9b334a45a8ff	1320	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
bogdanm	0:9b334a45a8ff	1321	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
bogdanm	0:9b334a45a8ff	1322	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
bogdanm	0:9b334a45a8ff	1323	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
bogdanm	0:9b334a45a8ff	1324	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
bogdanm	0:9b334a45a8ff	1325	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
bogdanm	0:9b334a45a8ff	1326	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
bogdanm	0:9b334a45a8ff	1327	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
bogdanm	0:9b334a45a8ff	1328	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
bogdanm	0:9b334a45a8ff	1329	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
bogdanm	0:9b334a45a8ff	1330	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
bogdanm	0:9b334a45a8ff	1331	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
bogdanm	0:9b334a45a8ff	1332	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
bogdanm	0:9b334a45a8ff	1333	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
bogdanm	0:9b334a45a8ff	1334	assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
bogdanm	0:9b334a45a8ff	1335	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
bogdanm	0:9b334a45a8ff	1336	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
bogdanm	0:9b334a45a8ff	1337	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
bogdanm	0:9b334a45a8ff	1338	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
bogdanm	0:9b334a45a8ff	1339	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
bogdanm	0:9b334a45a8ff	1340	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
bogdanm	0:9b334a45a8ff	1341	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
bogdanm	0:9b334a45a8ff	1342	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
bogdanm	0:9b334a45a8ff	1343	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
bogdanm	0:9b334a45a8ff	1344	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1347	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1348	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1349	/* Clear WD, PCE, PS, TE and RE bits */
bogdanm	0:9b334a45a8ff	1350	tmpreg &= ETH_MACCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	tmpreg \|= (uint32_t)(macconf->Watchdog \|
bogdanm	0:9b334a45a8ff	1353	macconf->Jabber \|
bogdanm	0:9b334a45a8ff	1354	macconf->InterFrameGap \|
bogdanm	0:9b334a45a8ff	1355	macconf->CarrierSense \|
bogdanm	0:9b334a45a8ff	1356	(heth->Init).Speed \|
bogdanm	0:9b334a45a8ff	1357	macconf->ReceiveOwn \|
bogdanm	0:9b334a45a8ff	1358	macconf->LoopbackMode \|
bogdanm	0:9b334a45a8ff	1359	(heth->Init).DuplexMode \|
bogdanm	0:9b334a45a8ff	1360	macconf->ChecksumOffload \|
bogdanm	0:9b334a45a8ff	1361	macconf->RetryTransmission \|
bogdanm	0:9b334a45a8ff	1362	macconf->AutomaticPadCRCStrip \|
bogdanm	0:9b334a45a8ff	1363	macconf->BackOffLimit \|
bogdanm	0:9b334a45a8ff	1364	macconf->DeferralCheck);
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1367	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1370	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1371	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1372	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1373	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/----------------------- ETHERNET MACFFR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1376	/* Write to ETHERNET MACFFR */
bogdanm	0:9b334a45a8ff	1377	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
bogdanm	0:9b334a45a8ff	1378	macconf->SourceAddrFilter \|
bogdanm	0:9b334a45a8ff	1379	macconf->PassControlFrames \|
bogdanm	0:9b334a45a8ff	1380	macconf->BroadcastFramesReception \|
bogdanm	0:9b334a45a8ff	1381	macconf->DestinationAddrFilter \|
bogdanm	0:9b334a45a8ff	1382	macconf->PromiscuousMode \|
bogdanm	0:9b334a45a8ff	1383	macconf->MulticastFramesFilter \|
bogdanm	0:9b334a45a8ff	1384	macconf->UnicastFramesFilter);
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1387	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1388	tmpreg = (heth->Instance)->MACFFR;
bogdanm	0:9b334a45a8ff	1389	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1390	(heth->Instance)->MACFFR = tmpreg;
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
bogdanm	0:9b334a45a8ff	1393	/* Write to ETHERNET MACHTHR */
bogdanm	0:9b334a45a8ff	1394	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Write to ETHERNET MACHTLR */
bogdanm	0:9b334a45a8ff	1397	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
bogdanm	0:9b334a45a8ff	1398	/----------------------- ETHERNET MACFCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	/* Get the ETHERNET MACFCR value */
bogdanm	0:9b334a45a8ff	1401	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1402	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1403	tmpreg &= ETH_MACFCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	tmpreg \|= (uint32_t)((macconf->PauseTime << 16) \|
bogdanm	0:9b334a45a8ff	1406	macconf->ZeroQuantaPause \|
bogdanm	0:9b334a45a8ff	1407	macconf->PauseLowThreshold \|
bogdanm	0:9b334a45a8ff	1408	macconf->UnicastPauseFrameDetect \|
bogdanm	0:9b334a45a8ff	1409	macconf->ReceiveFlowControl \|
bogdanm	0:9b334a45a8ff	1410	macconf->TransmitFlowControl);
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Write to ETHERNET MACFCR */
bogdanm	0:9b334a45a8ff	1413	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1416	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1417	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1418	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1419	(heth->Instance)->MACFCR = tmpreg;
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
bogdanm	0:9b334a45a8ff	1422	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
bogdanm	0:9b334a45a8ff	1423	macconf->VLANTagIdentifier);
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1426	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1427	tmpreg = (heth->Instance)->MACVLANTR;
bogdanm	0:9b334a45a8ff	1428	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1429	(heth->Instance)->MACVLANTR = tmpreg;
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431	else /* macconf == NULL : here we just configure Speed and Duplex mode */
bogdanm	0:9b334a45a8ff	1432	{
bogdanm	0:9b334a45a8ff	1433	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1434	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1435	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/* Clear FES and DM bits */
bogdanm	0:9b334a45a8ff	1438	tmpreg &= ~((uint32_t)0x00004800);
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	tmpreg \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1443	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1446	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1447	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1448	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1449	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* Set the ETH state to Ready */
bogdanm	0:9b334a45a8ff	1453	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1456	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/* Return function status */
bogdanm	0:9b334a45a8ff	1459	return HAL_OK;
bogdanm	0:9b334a45a8ff	1460	}
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/**
bogdanm	0:9b334a45a8ff	1463	* @brief Sets ETH DMA Configuration.
bogdanm	0:9b334a45a8ff	1464	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1465	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1466	* @param dmaconf: DMA Configuration structure
bogdanm	0:9b334a45a8ff	1467	* @retval HAL status
bogdanm	0:9b334a45a8ff	1468	*/
bogdanm	0:9b334a45a8ff	1469	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
bogdanm	0:9b334a45a8ff	1470	{
bogdanm	0:9b334a45a8ff	1471	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/* Process Locked */
bogdanm	0:9b334a45a8ff	1474	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1475
bogdanm	0:9b334a45a8ff	1476	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1477	heth->State= HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/* Check parameters */
bogdanm	0:9b334a45a8ff	1480	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
bogdanm	0:9b334a45a8ff	1481	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
bogdanm	0:9b334a45a8ff	1482	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
bogdanm	0:9b334a45a8ff	1483	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
bogdanm	0:9b334a45a8ff	1484	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
bogdanm	0:9b334a45a8ff	1485	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
bogdanm	0:9b334a45a8ff	1486	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
bogdanm	0:9b334a45a8ff	1487	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
bogdanm	0:9b334a45a8ff	1488	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
bogdanm	0:9b334a45a8ff	1489	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
bogdanm	0:9b334a45a8ff	1490	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
bogdanm	0:9b334a45a8ff	1491	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
bogdanm	0:9b334a45a8ff	1492	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
bogdanm	0:9b334a45a8ff	1493	assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
bogdanm	0:9b334a45a8ff	1494	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
bogdanm	0:9b334a45a8ff	1495	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	/----------------------- ETHERNET DMAOMR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1498	/* Get the ETHERNET DMAOMR value */
bogdanm	0:9b334a45a8ff	1499	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1500	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1501	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	tmpreg \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
bogdanm	0:9b334a45a8ff	1504	dmaconf->ReceiveStoreForward \|
bogdanm	0:9b334a45a8ff	1505	dmaconf->FlushReceivedFrame \|
bogdanm	0:9b334a45a8ff	1506	dmaconf->TransmitStoreForward \|
bogdanm	0:9b334a45a8ff	1507	dmaconf->TransmitThresholdControl \|
bogdanm	0:9b334a45a8ff	1508	dmaconf->ForwardErrorFrames \|
bogdanm	0:9b334a45a8ff	1509	dmaconf->ForwardUndersizedGoodFrames \|
bogdanm	0:9b334a45a8ff	1510	dmaconf->ReceiveThresholdControl \|
bogdanm	0:9b334a45a8ff	1511	dmaconf->SecondFrameOperate);
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	/* Write to ETHERNET DMAOMR */
bogdanm	0:9b334a45a8ff	1514	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1517	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1518	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1519	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1520	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/----------------------- ETHERNET DMABMR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1523	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
bogdanm	0:9b334a45a8ff	1524	dmaconf->FixedBurst \|
bogdanm	0:9b334a45a8ff	1525	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm	0:9b334a45a8ff	1526	dmaconf->TxDMABurstLength \|
bogdanm	0:9b334a45a8ff	1527	dmaconf->EnhancedDescriptorFormat \|
bogdanm	0:9b334a45a8ff	1528	(dmaconf->DescriptorSkipLength << 2) \|
bogdanm	0:9b334a45a8ff	1529	dmaconf->DMAArbitration \|
bogdanm	0:9b334a45a8ff	1530	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1533	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1534	tmpreg = (heth->Instance)->DMABMR;
bogdanm	0:9b334a45a8ff	1535	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1536	(heth->Instance)->DMABMR = tmpreg;
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Set the ETH state to Ready */
bogdanm	0:9b334a45a8ff	1539	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1542	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* Return function status */
bogdanm	0:9b334a45a8ff	1545	return HAL_OK;
bogdanm	0:9b334a45a8ff	1546	}
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/**
bogdanm	0:9b334a45a8ff	1549	* @}
bogdanm	0:9b334a45a8ff	1550	*/
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	1553	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1554	*
bogdanm	0:9b334a45a8ff	1555	@verbatim
bogdanm	0:9b334a45a8ff	1556	===============================================================================
bogdanm	0:9b334a45a8ff	1557	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	1558	===============================================================================
bogdanm	0:9b334a45a8ff	1559	[..]
bogdanm	0:9b334a45a8ff	1560	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1561	and the data flow.
bogdanm	0:9b334a45a8ff	1562	(+) Get the ETH handle state:
bogdanm	0:9b334a45a8ff	1563	HAL_ETH_GetState();
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	@endverbatim
bogdanm	0:9b334a45a8ff	1567	* @{
bogdanm	0:9b334a45a8ff	1568	*/
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	/**
bogdanm	0:9b334a45a8ff	1571	* @brief Return the ETH HAL state
bogdanm	0:9b334a45a8ff	1572	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1573	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1574	* @retval HAL state
bogdanm	0:9b334a45a8ff	1575	*/
bogdanm	0:9b334a45a8ff	1576	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1577	{
bogdanm	0:9b334a45a8ff	1578	/* Return ETH state */
bogdanm	0:9b334a45a8ff	1579	return heth->State;
bogdanm	0:9b334a45a8ff	1580	}
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/**
bogdanm	0:9b334a45a8ff	1583	* @}
bogdanm	0:9b334a45a8ff	1584	*/
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/**
bogdanm	0:9b334a45a8ff	1587	* @}
bogdanm	0:9b334a45a8ff	1588	*/
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/** @addtogroup ETH_Private_Functions
bogdanm	0:9b334a45a8ff	1591	* @{
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/**
bogdanm	0:9b334a45a8ff	1595	* @brief Configures Ethernet MAC and DMA with default parameters.
bogdanm	0:9b334a45a8ff	1596	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1597	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1598	* @param err: Ethernet Init error
bogdanm	0:9b334a45a8ff	1599	* @retval HAL status
bogdanm	0:9b334a45a8ff	1600	*/
bogdanm	0:9b334a45a8ff	1601	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
bogdanm	0:9b334a45a8ff	1602	{
bogdanm	0:9b334a45a8ff	1603	ETH_MACInitTypeDef macinit;
bogdanm	0:9b334a45a8ff	1604	ETH_DMAInitTypeDef dmainit;
bogdanm	0:9b334a45a8ff	1605	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
bogdanm	0:9b334a45a8ff	1608	{
bogdanm	0:9b334a45a8ff	1609	/* Set Ethernet duplex mode to Full-duplex */
bogdanm	0:9b334a45a8ff	1610	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	/* Set Ethernet speed to 100M */
bogdanm	0:9b334a45a8ff	1613	(heth->Init).Speed = ETH_SPEED_100M;
bogdanm	0:9b334a45a8ff	1614	}
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/* Ethernet MAC default initialization **************************************/
bogdanm	0:9b334a45a8ff	1617	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
bogdanm	0:9b334a45a8ff	1618	macinit.Jabber = ETH_JABBER_ENABLE;
bogdanm	0:9b334a45a8ff	1619	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
bogdanm	0:9b334a45a8ff	1620	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
bogdanm	0:9b334a45a8ff	1621	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
bogdanm	0:9b334a45a8ff	1622	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
bogdanm	0:9b334a45a8ff	1623	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm	0:9b334a45a8ff	1624	{
bogdanm	0:9b334a45a8ff	1625	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
bogdanm	0:9b334a45a8ff	1626	}
bogdanm	0:9b334a45a8ff	1627	else
bogdanm	0:9b334a45a8ff	1628	{
bogdanm	0:9b334a45a8ff	1629	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
bogdanm	0:9b334a45a8ff	1630	}
bogdanm	0:9b334a45a8ff	1631	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
bogdanm	0:9b334a45a8ff	1632	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
bogdanm	0:9b334a45a8ff	1633	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
bogdanm	0:9b334a45a8ff	1634	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
bogdanm	0:9b334a45a8ff	1635	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
bogdanm	0:9b334a45a8ff	1636	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
bogdanm	0:9b334a45a8ff	1637	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
bogdanm	0:9b334a45a8ff	1638	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
bogdanm	0:9b334a45a8ff	1639	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
bogdanm	0:9b334a45a8ff	1640	macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
bogdanm	0:9b334a45a8ff	1641	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
bogdanm	0:9b334a45a8ff	1642	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
bogdanm	0:9b334a45a8ff	1643	macinit.HashTableHigh = 0x0;
bogdanm	0:9b334a45a8ff	1644	macinit.HashTableLow = 0x0;
bogdanm	0:9b334a45a8ff	1645	macinit.PauseTime = 0x0;
bogdanm	0:9b334a45a8ff	1646	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
bogdanm	0:9b334a45a8ff	1647	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
bogdanm	0:9b334a45a8ff	1648	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
bogdanm	0:9b334a45a8ff	1649	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
bogdanm	0:9b334a45a8ff	1650	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
bogdanm	0:9b334a45a8ff	1651	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
bogdanm	0:9b334a45a8ff	1652	macinit.VLANTagIdentifier = 0x0;
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1655	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1656	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1657	/* Clear WD, PCE, PS, TE and RE bits */
bogdanm	0:9b334a45a8ff	1658	tmpreg &= ETH_MACCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1659	/* Set the WD bit according to ETH Watchdog value */
bogdanm	0:9b334a45a8ff	1660	/* Set the JD: bit according to ETH Jabber value */
bogdanm	0:9b334a45a8ff	1661	/* Set the IFG bit according to ETH InterFrameGap value */
bogdanm	0:9b334a45a8ff	1662	/* Set the DCRS bit according to ETH CarrierSense value */
bogdanm	0:9b334a45a8ff	1663	/* Set the FES bit according to ETH Speed value */
bogdanm	0:9b334a45a8ff	1664	/* Set the DO bit according to ETH ReceiveOwn value */
bogdanm	0:9b334a45a8ff	1665	/* Set the LM bit according to ETH LoopbackMode value */
bogdanm	0:9b334a45a8ff	1666	/* Set the DM bit according to ETH Mode value */
bogdanm	0:9b334a45a8ff	1667	/* Set the IPCO bit according to ETH ChecksumOffload value */
bogdanm	0:9b334a45a8ff	1668	/* Set the DR bit according to ETH RetryTransmission value */
bogdanm	0:9b334a45a8ff	1669	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
bogdanm	0:9b334a45a8ff	1670	/* Set the BL bit according to ETH BackOffLimit value */
bogdanm	0:9b334a45a8ff	1671	/* Set the DC bit according to ETH DeferralCheck value */
bogdanm	0:9b334a45a8ff	1672	tmpreg \|= (uint32_t)(macinit.Watchdog \|
bogdanm	0:9b334a45a8ff	1673	macinit.Jabber \|
bogdanm	0:9b334a45a8ff	1674	macinit.InterFrameGap \|
bogdanm	0:9b334a45a8ff	1675	macinit.CarrierSense \|
bogdanm	0:9b334a45a8ff	1676	(heth->Init).Speed \|
bogdanm	0:9b334a45a8ff	1677	macinit.ReceiveOwn \|
bogdanm	0:9b334a45a8ff	1678	macinit.LoopbackMode \|
bogdanm	0:9b334a45a8ff	1679	(heth->Init).DuplexMode \|
bogdanm	0:9b334a45a8ff	1680	macinit.ChecksumOffload \|
bogdanm	0:9b334a45a8ff	1681	macinit.RetryTransmission \|
bogdanm	0:9b334a45a8ff	1682	macinit.AutomaticPadCRCStrip \|
bogdanm	0:9b334a45a8ff	1683	macinit.BackOffLimit \|
bogdanm	0:9b334a45a8ff	1684	macinit.DeferralCheck);
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1687	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1690	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1691	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1692	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1693	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1694
bogdanm	0:9b334a45a8ff	1695	/----------------------- ETHERNET MACFFR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1696	/* Set the RA bit according to ETH ReceiveAll value */
bogdanm	0:9b334a45a8ff	1697	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
bogdanm	0:9b334a45a8ff	1698	/* Set the PCF bit according to ETH PassControlFrames value */
bogdanm	0:9b334a45a8ff	1699	/* Set the DBF bit according to ETH BroadcastFramesReception value */
bogdanm	0:9b334a45a8ff	1700	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
bogdanm	0:9b334a45a8ff	1701	/* Set the PR bit according to ETH PromiscuousMode value */
bogdanm	0:9b334a45a8ff	1702	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
bogdanm	0:9b334a45a8ff	1703	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
bogdanm	0:9b334a45a8ff	1704	/* Write to ETHERNET MACFFR */
bogdanm	0:9b334a45a8ff	1705	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
bogdanm	0:9b334a45a8ff	1706	macinit.SourceAddrFilter \|
bogdanm	0:9b334a45a8ff	1707	macinit.PassControlFrames \|
bogdanm	0:9b334a45a8ff	1708	macinit.BroadcastFramesReception \|
bogdanm	0:9b334a45a8ff	1709	macinit.DestinationAddrFilter \|
bogdanm	0:9b334a45a8ff	1710	macinit.PromiscuousMode \|
bogdanm	0:9b334a45a8ff	1711	macinit.MulticastFramesFilter \|
bogdanm	0:9b334a45a8ff	1712	macinit.UnicastFramesFilter);
bogdanm	0:9b334a45a8ff	1713
bogdanm	0:9b334a45a8ff	1714	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1715	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1716	tmpreg = (heth->Instance)->MACFFR;
bogdanm	0:9b334a45a8ff	1717	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1718	(heth->Instance)->MACFFR = tmpreg;
bogdanm	0:9b334a45a8ff	1719
bogdanm	0:9b334a45a8ff	1720	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
bogdanm	0:9b334a45a8ff	1721	/* Write to ETHERNET MACHTHR */
bogdanm	0:9b334a45a8ff	1722	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/* Write to ETHERNET MACHTLR */
bogdanm	0:9b334a45a8ff	1725	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
bogdanm	0:9b334a45a8ff	1726	/----------------------- ETHERNET MACFCR Configuration -------------------/
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	/* Get the ETHERNET MACFCR value */
bogdanm	0:9b334a45a8ff	1729	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1730	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1731	tmpreg &= ETH_MACFCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/* Set the PT bit according to ETH PauseTime value */
bogdanm	0:9b334a45a8ff	1734	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
bogdanm	0:9b334a45a8ff	1735	/* Set the PLT bit according to ETH PauseLowThreshold value */
bogdanm	0:9b334a45a8ff	1736	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
bogdanm	0:9b334a45a8ff	1737	/* Set the RFE bit according to ETH ReceiveFlowControl value */
bogdanm	0:9b334a45a8ff	1738	/* Set the TFE bit according to ETH TransmitFlowControl value */
bogdanm	0:9b334a45a8ff	1739	tmpreg \|= (uint32_t)((macinit.PauseTime << 16) \|
bogdanm	0:9b334a45a8ff	1740	macinit.ZeroQuantaPause \|
bogdanm	0:9b334a45a8ff	1741	macinit.PauseLowThreshold \|
bogdanm	0:9b334a45a8ff	1742	macinit.UnicastPauseFrameDetect \|
bogdanm	0:9b334a45a8ff	1743	macinit.ReceiveFlowControl \|
bogdanm	0:9b334a45a8ff	1744	macinit.TransmitFlowControl);
bogdanm	0:9b334a45a8ff	1745
bogdanm	0:9b334a45a8ff	1746	/* Write to ETHERNET MACFCR */
bogdanm	0:9b334a45a8ff	1747	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1750	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1751	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1752	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1753	(heth->Instance)->MACFCR = tmpreg;
bogdanm	0:9b334a45a8ff	1754
bogdanm	0:9b334a45a8ff	1755	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
bogdanm	0:9b334a45a8ff	1756	/* Set the ETV bit according to ETH VLANTagComparison value */
bogdanm	0:9b334a45a8ff	1757	/* Set the VL bit according to ETH VLANTagIdentifier value */
bogdanm	0:9b334a45a8ff	1758	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
bogdanm	0:9b334a45a8ff	1759	macinit.VLANTagIdentifier);
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1762	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1763	tmpreg = (heth->Instance)->MACVLANTR;
bogdanm	0:9b334a45a8ff	1764	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1765	(heth->Instance)->MACVLANTR = tmpreg;
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	/* Ethernet DMA default initialization ************************************/
bogdanm	0:9b334a45a8ff	1768	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
bogdanm	0:9b334a45a8ff	1769	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
bogdanm	0:9b334a45a8ff	1770	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
bogdanm	0:9b334a45a8ff	1771	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
bogdanm	0:9b334a45a8ff	1772	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
bogdanm	0:9b334a45a8ff	1773	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
bogdanm	0:9b334a45a8ff	1774	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
bogdanm	0:9b334a45a8ff	1775	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
bogdanm	0:9b334a45a8ff	1776	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
bogdanm	0:9b334a45a8ff	1777	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
bogdanm	0:9b334a45a8ff	1778	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
bogdanm	0:9b334a45a8ff	1779	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
bogdanm	0:9b334a45a8ff	1780	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
bogdanm	0:9b334a45a8ff	1781	dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
bogdanm	0:9b334a45a8ff	1782	dmainit.DescriptorSkipLength = 0x0;
bogdanm	0:9b334a45a8ff	1783	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	/* Get the ETHERNET DMAOMR value */
bogdanm	0:9b334a45a8ff	1786	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1787	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1788	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1789
bogdanm	0:9b334a45a8ff	1790	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
bogdanm	0:9b334a45a8ff	1791	/* Set the RSF bit according to ETH ReceiveStoreForward value */
bogdanm	0:9b334a45a8ff	1792	/* Set the DFF bit according to ETH FlushReceivedFrame value */
bogdanm	0:9b334a45a8ff	1793	/* Set the TSF bit according to ETH TransmitStoreForward value */
bogdanm	0:9b334a45a8ff	1794	/* Set the TTC bit according to ETH TransmitThresholdControl value */
bogdanm	0:9b334a45a8ff	1795	/* Set the FEF bit according to ETH ForwardErrorFrames value */
bogdanm	0:9b334a45a8ff	1796	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
bogdanm	0:9b334a45a8ff	1797	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
bogdanm	0:9b334a45a8ff	1798	/* Set the OSF bit according to ETH SecondFrameOperate value */
bogdanm	0:9b334a45a8ff	1799	tmpreg \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
bogdanm	0:9b334a45a8ff	1800	dmainit.ReceiveStoreForward \|
bogdanm	0:9b334a45a8ff	1801	dmainit.FlushReceivedFrame \|
bogdanm	0:9b334a45a8ff	1802	dmainit.TransmitStoreForward \|
bogdanm	0:9b334a45a8ff	1803	dmainit.TransmitThresholdControl \|
bogdanm	0:9b334a45a8ff	1804	dmainit.ForwardErrorFrames \|
bogdanm	0:9b334a45a8ff	1805	dmainit.ForwardUndersizedGoodFrames \|
bogdanm	0:9b334a45a8ff	1806	dmainit.ReceiveThresholdControl \|
bogdanm	0:9b334a45a8ff	1807	dmainit.SecondFrameOperate);
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/* Write to ETHERNET DMAOMR */
bogdanm	0:9b334a45a8ff	1810	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1813	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1814	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1815	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1816	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	/----------------------- ETHERNET DMABMR Configuration ------------------/
bogdanm	0:9b334a45a8ff	1819	/* Set the AAL bit according to ETH AddressAlignedBeats value */
bogdanm	0:9b334a45a8ff	1820	/* Set the FB bit according to ETH FixedBurst value */
bogdanm	0:9b334a45a8ff	1821	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
bogdanm	0:9b334a45a8ff	1822	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
bogdanm	0:9b334a45a8ff	1823	/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
bogdanm	0:9b334a45a8ff	1824	/* Set the DSL bit according to ETH DesciptorSkipLength value */
bogdanm	0:9b334a45a8ff	1825	/* Set the PR and DA bits according to ETH DMAArbitration value */
bogdanm	0:9b334a45a8ff	1826	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
bogdanm	0:9b334a45a8ff	1827	dmainit.FixedBurst \|
bogdanm	0:9b334a45a8ff	1828	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm	0:9b334a45a8ff	1829	dmainit.TxDMABurstLength \|
bogdanm	0:9b334a45a8ff	1830	dmainit.EnhancedDescriptorFormat \|
bogdanm	0:9b334a45a8ff	1831	(dmainit.DescriptorSkipLength << 2) \|
bogdanm	0:9b334a45a8ff	1832	dmainit.DMAArbitration \|
bogdanm	0:9b334a45a8ff	1833	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1836	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1837	tmpreg = (heth->Instance)->DMABMR;
bogdanm	0:9b334a45a8ff	1838	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1839	(heth->Instance)->DMABMR = tmpreg;
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/* Enable the Ethernet Rx Interrupt */
bogdanm	0:9b334a45a8ff	1844	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
bogdanm	0:9b334a45a8ff	1845	}
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/* Initialize MAC address in ethernet MAC */
bogdanm	0:9b334a45a8ff	1848	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
bogdanm	0:9b334a45a8ff	1849	}
bogdanm	0:9b334a45a8ff	1850
bogdanm	0:9b334a45a8ff	1851	/**
bogdanm	0:9b334a45a8ff	1852	* @brief Configures the selected MAC address.
bogdanm	0:9b334a45a8ff	1853	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1854	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1855	* @param MacAddr: The MAC address to configure
bogdanm	0:9b334a45a8ff	1856	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1857	* @arg ETH_MAC_Address0: MAC Address0
bogdanm	0:9b334a45a8ff	1858	* @arg ETH_MAC_Address1: MAC Address1
bogdanm	0:9b334a45a8ff	1859	* @arg ETH_MAC_Address2: MAC Address2
bogdanm	0:9b334a45a8ff	1860	* @arg ETH_MAC_Address3: MAC Address3
bogdanm	0:9b334a45a8ff	1861	* @param Addr: Pointer to MAC address buffer data (6 bytes)
bogdanm	0:9b334a45a8ff	1862	* @retval HAL status
bogdanm	0:9b334a45a8ff	1863	*/
bogdanm	0:9b334a45a8ff	1864	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	uint32_t tmpreg;
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1869	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	/* Calculate the selected MAC address high register */
bogdanm	0:9b334a45a8ff	1872	tmpreg = ((uint32_t)Addr[5] << 8) \| (uint32_t)Addr[4];
bogdanm	0:9b334a45a8ff	1873	/* Load the selected MAC address high register */
bogdanm	0:9b334a45a8ff	1874	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
bogdanm	0:9b334a45a8ff	1875	/* Calculate the selected MAC address low register */
bogdanm	0:9b334a45a8ff	1876	tmpreg = ((uint32_t)Addr[3] << 24) \| ((uint32_t)Addr[2] << 16) \| ((uint32_t)Addr[1] << 8) \| Addr[0];
bogdanm	0:9b334a45a8ff	1877
bogdanm	0:9b334a45a8ff	1878	/* Load the selected MAC address low register */
bogdanm	0:9b334a45a8ff	1879	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
bogdanm	0:9b334a45a8ff	1880	}
bogdanm	0:9b334a45a8ff	1881
bogdanm	0:9b334a45a8ff	1882	/**
bogdanm	0:9b334a45a8ff	1883	* @brief Enables the MAC transmission.
bogdanm	0:9b334a45a8ff	1884	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1885	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1886	* @retval None
bogdanm	0:9b334a45a8ff	1887	*/
bogdanm	0:9b334a45a8ff	1888	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1889	{
bogdanm	0:9b334a45a8ff	1890	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1891
bogdanm	0:9b334a45a8ff	1892	/* Enable the MAC transmission */
bogdanm	0:9b334a45a8ff	1893	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
bogdanm	0:9b334a45a8ff	1894
bogdanm	0:9b334a45a8ff	1895	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1896	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1897	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1898	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1899	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1900	}
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	/**
bogdanm	0:9b334a45a8ff	1903	* @brief Disables the MAC transmission.
bogdanm	0:9b334a45a8ff	1904	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1905	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1906	* @retval None
bogdanm	0:9b334a45a8ff	1907	*/
bogdanm	0:9b334a45a8ff	1908	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1909	{
bogdanm	0:9b334a45a8ff	1910	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	/* Disable the MAC transmission */
bogdanm	0:9b334a45a8ff	1913	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1916	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1917	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1918	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1919	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1920	}
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	/**
bogdanm	0:9b334a45a8ff	1923	* @brief Enables the MAC reception.
bogdanm	0:9b334a45a8ff	1924	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1925	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1926	* @retval None
bogdanm	0:9b334a45a8ff	1927	*/
bogdanm	0:9b334a45a8ff	1928	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1929	{
bogdanm	0:9b334a45a8ff	1930	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	/* Enable the MAC reception */
bogdanm	0:9b334a45a8ff	1933	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1936	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1937	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1938	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1939	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/**
bogdanm	0:9b334a45a8ff	1943	* @brief Disables the MAC reception.
bogdanm	0:9b334a45a8ff	1944	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1945	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1946	* @retval None
bogdanm	0:9b334a45a8ff	1947	*/
bogdanm	0:9b334a45a8ff	1948	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1949	{
bogdanm	0:9b334a45a8ff	1950	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1951
bogdanm	0:9b334a45a8ff	1952	/* Disable the MAC reception */
bogdanm	0:9b334a45a8ff	1953	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
bogdanm	0:9b334a45a8ff	1954
bogdanm	0:9b334a45a8ff	1955	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1956	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1957	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1958	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1959	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1960	}
bogdanm	0:9b334a45a8ff	1961
bogdanm	0:9b334a45a8ff	1962	/**
bogdanm	0:9b334a45a8ff	1963	* @brief Enables the DMA transmission.
bogdanm	0:9b334a45a8ff	1964	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1965	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1966	* @retval None
bogdanm	0:9b334a45a8ff	1967	*/
bogdanm	0:9b334a45a8ff	1968	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1969	{
bogdanm	0:9b334a45a8ff	1970	/* Enable the DMA transmission */
bogdanm	0:9b334a45a8ff	1971	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
bogdanm	0:9b334a45a8ff	1972	}
bogdanm	0:9b334a45a8ff	1973
bogdanm	0:9b334a45a8ff	1974	/**
bogdanm	0:9b334a45a8ff	1975	* @brief Disables the DMA transmission.
bogdanm	0:9b334a45a8ff	1976	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1977	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1978	* @retval None
bogdanm	0:9b334a45a8ff	1979	*/
bogdanm	0:9b334a45a8ff	1980	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1981	{
bogdanm	0:9b334a45a8ff	1982	/* Disable the DMA transmission */
bogdanm	0:9b334a45a8ff	1983	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
bogdanm	0:9b334a45a8ff	1984	}
bogdanm	0:9b334a45a8ff	1985
bogdanm	0:9b334a45a8ff	1986	/**
bogdanm	0:9b334a45a8ff	1987	* @brief Enables the DMA reception.
bogdanm	0:9b334a45a8ff	1988	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1989	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1990	* @retval None
bogdanm	0:9b334a45a8ff	1991	*/
bogdanm	0:9b334a45a8ff	1992	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1993	{
bogdanm	0:9b334a45a8ff	1994	/* Enable the DMA reception */
bogdanm	0:9b334a45a8ff	1995	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
bogdanm	0:9b334a45a8ff	1996	}
bogdanm	0:9b334a45a8ff	1997
bogdanm	0:9b334a45a8ff	1998	/**
bogdanm	0:9b334a45a8ff	1999	* @brief Disables the DMA reception.
bogdanm	0:9b334a45a8ff	2000	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2001	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	2002	* @retval None
bogdanm	0:9b334a45a8ff	2003	*/
bogdanm	0:9b334a45a8ff	2004	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	2005	{
bogdanm	0:9b334a45a8ff	2006	/* Disable the DMA reception */
bogdanm	0:9b334a45a8ff	2007	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
bogdanm	0:9b334a45a8ff	2008	}
bogdanm	0:9b334a45a8ff	2009
bogdanm	0:9b334a45a8ff	2010	/**
bogdanm	0:9b334a45a8ff	2011	* @brief Clears the ETHERNET transmit FIFO.
bogdanm	0:9b334a45a8ff	2012	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2013	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	2014	* @retval None
bogdanm	0:9b334a45a8ff	2015	*/
bogdanm	0:9b334a45a8ff	2016	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	2017	{
bogdanm	0:9b334a45a8ff	2018	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2019
bogdanm	0:9b334a45a8ff	2020	/* Set the Flush Transmit FIFO bit */
bogdanm	0:9b334a45a8ff	2021	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
bogdanm	0:9b334a45a8ff	2022
bogdanm	0:9b334a45a8ff	2023	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	2024	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	2025	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	2026	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	2027	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	2028	}
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	/**
bogdanm	0:9b334a45a8ff	2031	* @}
bogdanm	0:9b334a45a8ff	2032	*/
bogdanm	0:9b334a45a8ff	2033
bogdanm	0:9b334a45a8ff	2034	#endif /* HAL_ETH_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2035	/**
bogdanm	0:9b334a45a8ff	2036	* @}
bogdanm	0:9b334a45a8ff	2037	*/
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/**
bogdanm	0:9b334a45a8ff	2040	* @}
bogdanm	0:9b334a45a8ff	2041	*/
bogdanm	0:9b334a45a8ff	2042
bogdanm	0:9b334a45a8ff	2043	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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