mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_adc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of ADC HAL extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F7xx_ADC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F7xx_ADC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f7xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup ADC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup ADC_Exported_Types ADC Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
mbed_official	83:a036322b8637	63	* @brief Structure definition of ADC and regular group initialization
mbed_official	83:a036322b8637	64	* @note Parameters of this structure are shared within 2 scopes:
mbed_official	83:a036322b8637	65	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
mbed_official	83:a036322b8637	66	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
mbed_official	83:a036322b8637	67	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
mbed_official	83:a036322b8637	68	* ADC state can be either:
mbed_official	83:a036322b8637	69	* - For all parameters: ADC disabled
mbed_official	83:a036322b8637	70	* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
mbed_official	83:a036322b8637	71	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
mbed_official	83:a036322b8637	72	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
mbed_official	83:a036322b8637	73	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
mbed_official	83:a036322b8637	74	*/
bogdanm	0:9b334a45a8ff	75	typedef struct
bogdanm	0:9b334a45a8ff	76	{
mbed_official	83:a036322b8637	77	uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
bogdanm	0:9b334a45a8ff	78	all the ADCs.
bogdanm	0:9b334a45a8ff	79	This parameter can be a value of @ref ADC_ClockPrescaler */
mbed_official	83:a036322b8637	80	uint32_t Resolution; /*!< Configures the ADC resolution.
bogdanm	0:9b334a45a8ff	81	This parameter can be a value of @ref ADC_Resolution */
mbed_official	83:a036322b8637	82	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
mbed_official	83:a036322b8637	83	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
bogdanm	0:9b334a45a8ff	84	This parameter can be a value of @ref ADC_data_align */
mbed_official	83:a036322b8637	85	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
mbed_official	83:a036322b8637	86	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
mbed_official	83:a036322b8637	87	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
mbed_official	83:a036322b8637	88	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
mbed_official	83:a036322b8637	89	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
mbed_official	83:a036322b8637	90	Scan direction is upward: from rank1 to rank 'n'. */
mbed_official	83:a036322b8637	91	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
mbed_official	83:a036322b8637	92	This parameter can be a value of @ref ADC_EOCSelection.
mbed_official	83:a036322b8637	93	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
mbed_official	83:a036322b8637	94	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
mbed_official	83:a036322b8637	95	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
mbed_official	83:a036322b8637	96	Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
mbed_official	83:a036322b8637	97	If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
mbed_official	83:a036322b8637	98	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
mbed_official	83:a036322b8637	99	after the selected trigger occurred (software start or external trigger).
bogdanm	0:9b334a45a8ff	100	This parameter can be set to ENABLE or DISABLE. */
mbed_official	83:a036322b8637	101	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
mbed_official	83:a036322b8637	102	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
bogdanm	0:9b334a45a8ff	103	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
mbed_official	83:a036322b8637	104	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
mbed_official	83:a036322b8637	105	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
mbed_official	83:a036322b8637	106	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
bogdanm	0:9b334a45a8ff	107	This parameter can be set to ENABLE or DISABLE. */
mbed_official	83:a036322b8637	108	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
mbed_official	83:a036322b8637	109	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
bogdanm	0:9b334a45a8ff	110	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
bogdanm	0:9b334a45a8ff	111	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
bogdanm	0:9b334a45a8ff	112	If set to ADC_SOFTWARE_START, external triggers are disabled.
mbed_official	83:a036322b8637	113	If set to external trigger source, triggering is on event rising edge by default.
mbed_official	83:a036322b8637	114	This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
bogdanm	0:9b334a45a8ff	115	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
bogdanm	0:9b334a45a8ff	116	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
mbed_official	83:a036322b8637	117	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
mbed_official	83:a036322b8637	118	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
mbed_official	83:a036322b8637	119	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
mbed_official	83:a036322b8637	120	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
mbed_official	83:a036322b8637	121	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
mbed_official	83:a036322b8637	122	This parameter can be set to ENABLE or DISABLE. */
bogdanm	0:9b334a45a8ff	123	}ADC_InitTypeDef;
bogdanm	0:9b334a45a8ff	124
mbed_official	83:a036322b8637	125
mbed_official	83:a036322b8637	126
bogdanm	0:9b334a45a8ff	127	/**
mbed_official	83:a036322b8637	128	* @brief Structure definition of ADC channel for regular group
mbed_official	83:a036322b8637	129	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
mbed_official	83:a036322b8637	130	* ADC can be either disabled or enabled without conversion on going on regular group.
bogdanm	0:9b334a45a8ff	131	*/
bogdanm	0:9b334a45a8ff	132	typedef struct
bogdanm	0:9b334a45a8ff	133	{
mbed_official	83:a036322b8637	134	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
mbed_official	83:a036322b8637	135	This parameter can be a value of @ref ADC_channels */
mbed_official	83:a036322b8637	136	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
mbed_official	83:a036322b8637	137	This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
mbed_official	83:a036322b8637	138	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
mbed_official	83:a036322b8637	139	Unit: ADC clock cycles
mbed_official	83:a036322b8637	140	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
mbed_official	83:a036322b8637	141	This parameter can be a value of @ref ADC_sampling_times
mbed_official	83:a036322b8637	142	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
mbed_official	83:a036322b8637	143	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
mbed_official	83:a036322b8637	144	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
mbed_official	83:a036322b8637	145	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
mbed_official	83:a036322b8637	146	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
mbed_official	83:a036322b8637	147	uint32_t Offset; /!< Reserved for future use, can be set to 0 /
bogdanm	0:9b334a45a8ff	148	}ADC_ChannelConfTypeDef;
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	/**
mbed_official	83:a036322b8637	151	* @brief ADC Configuration multi-mode structure definition
bogdanm	0:9b334a45a8ff	152	*/
bogdanm	0:9b334a45a8ff	153	typedef struct
bogdanm	0:9b334a45a8ff	154	{
bogdanm	0:9b334a45a8ff	155	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
bogdanm	0:9b334a45a8ff	156	This parameter can be a value of @ref ADC_analog_watchdog_selection */
bogdanm	0:9b334a45a8ff	157	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	158	This parameter must be a 12-bit value. */
bogdanm	0:9b334a45a8ff	159	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	160	This parameter must be a 12-bit value. */
bogdanm	0:9b334a45a8ff	161	uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
bogdanm	0:9b334a45a8ff	162	This parameter has an effect only if watchdog mode is configured on single channel
bogdanm	0:9b334a45a8ff	163	This parameter can be a value of @ref ADC_channels */
bogdanm	0:9b334a45a8ff	164	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
bogdanm	0:9b334a45a8ff	165	is interrupt mode or in polling mode.
bogdanm	0:9b334a45a8ff	166	This parameter can be set to ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	167	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
bogdanm	0:9b334a45a8ff	168	}ADC_AnalogWDGConfTypeDef;
mbed_official	83:a036322b8637	169
mbed_official	83:a036322b8637	170	/**
mbed_official	83:a036322b8637	171	* @brief HAL ADC state machine: ADC states definition (bitfields)
mbed_official	83:a036322b8637	172	*/
mbed_official	83:a036322b8637	173	/* States of ADC global scope */
mbed_official	83:a036322b8637	174	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
mbed_official	83:a036322b8637	175	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
mbed_official	83:a036322b8637	176	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy to internal process (initialization, calibration) /
mbed_official	83:a036322b8637	177	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
mbed_official	83:a036322b8637	178
mbed_official	83:a036322b8637	179	/* States of ADC errors */
mbed_official	83:a036322b8637	180	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
mbed_official	83:a036322b8637	181	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
mbed_official	83:a036322b8637	182	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
mbed_official	83:a036322b8637	183
mbed_official	83:a036322b8637	184	/* States of ADC group regular */
mbed_official	83:a036322b8637	185	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
mbed_official	83:a036322b8637	186	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
mbed_official	83:a036322b8637	187	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
mbed_official	83:a036322b8637	188	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
mbed_official	83:a036322b8637	189
mbed_official	83:a036322b8637	190	/* States of ADC group injected */
mbed_official	83:a036322b8637	191	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
mbed_official	83:a036322b8637	192	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
mbed_official	83:a036322b8637	193	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Conversion data available on group injected /
mbed_official	83:a036322b8637	194
mbed_official	83:a036322b8637	195	/* States of ADC analog watchdogs */
mbed_official	83:a036322b8637	196	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of analog watchdog 1 /
mbed_official	83:a036322b8637	197	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 /
mbed_official	83:a036322b8637	198	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 /
mbed_official	83:a036322b8637	199
mbed_official	83:a036322b8637	200	/* States of ADC multi-mode */
mbed_official	83:a036322b8637	201	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( /
mbed_official	83:a036322b8637	202
mbed_official	83:a036322b8637	203
mbed_official	83:a036322b8637	204	/**
mbed_official	83:a036322b8637	205	* @brief ADC handle Structure definition
mbed_official	83:a036322b8637	206	*/
mbed_official	83:a036322b8637	207	typedef struct
mbed_official	83:a036322b8637	208	{
mbed_official	83:a036322b8637	209	ADC_TypeDef Instance; /!< Register base address */
mbed_official	83:a036322b8637	210
mbed_official	83:a036322b8637	211	ADC_InitTypeDef Init; /!< ADC required parameters /
mbed_official	83:a036322b8637	212
mbed_official	83:a036322b8637	213	__IO uint32_t NbrOfCurrentConversionRank; /!< ADC number of current conversion rank /
mbed_official	83:a036322b8637	214
mbed_official	83:a036322b8637	215	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
mbed_official	83:a036322b8637	216
mbed_official	83:a036322b8637	217	HAL_LockTypeDef Lock; /!< ADC locking object /
mbed_official	83:a036322b8637	218
mbed_official	83:a036322b8637	219	__IO uint32_t State; /!< ADC communication state /
mbed_official	83:a036322b8637	220
mbed_official	83:a036322b8637	221	__IO uint32_t ErrorCode; /!< ADC Error code /
mbed_official	83:a036322b8637	222	}ADC_HandleTypeDef;
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @}
bogdanm	0:9b334a45a8ff	225	*/
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	228	/** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm	0:9b334a45a8ff	229	* @{
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/** @defgroup ADC_Error_Code ADC Error Code
bogdanm	0:9b334a45a8ff	233	* @{
mbed_official	83:a036322b8637	234	*/
mbed_official	83:a036322b8637	235	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
mbed_official	83:a036322b8637	236	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
mbed_official	83:a036322b8637	237	enable/disable, erroneous state */
mbed_official	83:a036322b8637	238	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
mbed_official	83:a036322b8637	239	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
bogdanm	0:9b334a45a8ff	240	/**
bogdanm	0:9b334a45a8ff	241	* @}
mbed_official	83:a036322b8637	242	*/
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244
mbed_official	83:a036322b8637	245	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
bogdanm	0:9b334a45a8ff	246	* @{
bogdanm	0:9b334a45a8ff	247	*/
bogdanm	0:9b334a45a8ff	248	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	249	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
bogdanm	0:9b334a45a8ff	250	#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
bogdanm	0:9b334a45a8ff	251	#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
bogdanm	0:9b334a45a8ff	252	/**
bogdanm	0:9b334a45a8ff	253	* @}
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
bogdanm	0:9b334a45a8ff	257	* @{
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	260	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
bogdanm	0:9b334a45a8ff	261	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
bogdanm	0:9b334a45a8ff	262	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	263	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
bogdanm	0:9b334a45a8ff	264	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	265	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
bogdanm	0:9b334a45a8ff	266	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	267	#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
bogdanm	0:9b334a45a8ff	268	#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	269	#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1))
bogdanm	0:9b334a45a8ff	270	#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	271	#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2))
bogdanm	0:9b334a45a8ff	272	#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
bogdanm	0:9b334a45a8ff	273	#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
bogdanm	0:9b334a45a8ff	274	#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
bogdanm	0:9b334a45a8ff	275	/**
bogdanm	0:9b334a45a8ff	276	* @}
bogdanm	0:9b334a45a8ff	277	*/
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/** @defgroup ADC_Resolution ADC Resolution
bogdanm	0:9b334a45a8ff	280	* @{
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	283	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
bogdanm	0:9b334a45a8ff	284	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
bogdanm	0:9b334a45a8ff	285	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
bogdanm	0:9b334a45a8ff	286	/**
bogdanm	0:9b334a45a8ff	287	* @}
bogdanm	0:9b334a45a8ff	288	*/
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
bogdanm	0:9b334a45a8ff	291	* @{
bogdanm	0:9b334a45a8ff	292	*/
bogdanm	0:9b334a45a8ff	293	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	294	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
bogdanm	0:9b334a45a8ff	295	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
bogdanm	0:9b334a45a8ff	296	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
bogdanm	0:9b334a45a8ff	297	/**
bogdanm	0:9b334a45a8ff	298	* @}
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
bogdanm	0:9b334a45a8ff	302	* @{
bogdanm	0:9b334a45a8ff	303	*/
bogdanm	0:9b334a45a8ff	304	/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
bogdanm	0:9b334a45a8ff	305	/* compatibility with other STM32 devices. */
mbed_official	83:a036322b8637	306
mbed_official	83:a036322b8637	307
bogdanm	0:9b334a45a8ff	308	#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	309	#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
bogdanm	0:9b334a45a8ff	310	#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
bogdanm	0:9b334a45a8ff	311	#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	312	#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
bogdanm	0:9b334a45a8ff	313	#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	314	#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
bogdanm	0:9b334a45a8ff	315	#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	316	#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
bogdanm	0:9b334a45a8ff	317	#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	318	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1))
bogdanm	0:9b334a45a8ff	319	#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	320	#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2))
bogdanm	0:9b334a45a8ff	321	#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
bogdanm	0:9b334a45a8ff	324	#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
mbed_official	83:a036322b8637	325
bogdanm	0:9b334a45a8ff	326	/**
bogdanm	0:9b334a45a8ff	327	* @}
bogdanm	0:9b334a45a8ff	328	*/
bogdanm	0:9b334a45a8ff	329
mbed_official	83:a036322b8637	330	/** @defgroup ADC_data_align ADC Data Align
bogdanm	0:9b334a45a8ff	331	* @{
bogdanm	0:9b334a45a8ff	332	*/
bogdanm	0:9b334a45a8ff	333	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	334	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
bogdanm	0:9b334a45a8ff	335	/**
bogdanm	0:9b334a45a8ff	336	* @}
bogdanm	0:9b334a45a8ff	337	*/
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	/** @defgroup ADC_channels ADC Common Channels
bogdanm	0:9b334a45a8ff	340	* @{
bogdanm	0:9b334a45a8ff	341	*/
bogdanm	0:9b334a45a8ff	342	#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	343	#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	344	#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	345	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	346	#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
bogdanm	0:9b334a45a8ff	347	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	348	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
bogdanm	0:9b334a45a8ff	349	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	350	#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
bogdanm	0:9b334a45a8ff	351	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	352	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1))
bogdanm	0:9b334a45a8ff	353	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	354	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2))
bogdanm	0:9b334a45a8ff	355	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	356	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
bogdanm	0:9b334a45a8ff	357	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	358	#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
bogdanm	0:9b334a45a8ff	359	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0))
bogdanm	0:9b334a45a8ff	360	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1))
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
bogdanm	0:9b334a45a8ff	363	#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @}
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/** @defgroup ADC_sampling_times ADC Sampling Times
bogdanm	0:9b334a45a8ff	369	* @{
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	372	#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
bogdanm	0:9b334a45a8ff	373	#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
bogdanm	0:9b334a45a8ff	374	#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0))
bogdanm	0:9b334a45a8ff	375	#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
bogdanm	0:9b334a45a8ff	376	#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0))
bogdanm	0:9b334a45a8ff	377	#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1))
bogdanm	0:9b334a45a8ff	378	#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
bogdanm	0:9b334a45a8ff	379	/**
bogdanm	0:9b334a45a8ff	380	* @}
bogdanm	0:9b334a45a8ff	381	*/
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/** @defgroup ADC_EOCSelection ADC EOC Selection
bogdanm	0:9b334a45a8ff	384	* @{
bogdanm	0:9b334a45a8ff	385	*/
bogdanm	0:9b334a45a8ff	386	#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	387	#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	388	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /!< reserved for future use /
bogdanm	0:9b334a45a8ff	389	/**
bogdanm	0:9b334a45a8ff	390	* @}
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	/** @defgroup ADC_Event_type ADC Event Type
bogdanm	0:9b334a45a8ff	394	* @{
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
bogdanm	0:9b334a45a8ff	397	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm	0:9b334a45a8ff	398	/**
bogdanm	0:9b334a45a8ff	399	* @}
bogdanm	0:9b334a45a8ff	400	*/
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
bogdanm	0:9b334a45a8ff	403	* @{
bogdanm	0:9b334a45a8ff	404	*/
bogdanm	0:9b334a45a8ff	405	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
bogdanm	0:9b334a45a8ff	406	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	407	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	408	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
bogdanm	0:9b334a45a8ff	409	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
bogdanm	0:9b334a45a8ff	410	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	411	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	412	/**
bogdanm	0:9b334a45a8ff	413	* @}
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
bogdanm	0:9b334a45a8ff	417	* @{
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419	#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
bogdanm	0:9b334a45a8ff	420	#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
bogdanm	0:9b334a45a8ff	421	#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
bogdanm	0:9b334a45a8ff	422	#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
bogdanm	0:9b334a45a8ff	423	/**
bogdanm	0:9b334a45a8ff	424	* @}
bogdanm	0:9b334a45a8ff	425	*/
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/** @defgroup ADC_flags_definition ADC Flags Definition
bogdanm	0:9b334a45a8ff	428	* @{
bogdanm	0:9b334a45a8ff	429	*/
bogdanm	0:9b334a45a8ff	430	#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
bogdanm	0:9b334a45a8ff	431	#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
bogdanm	0:9b334a45a8ff	432	#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
bogdanm	0:9b334a45a8ff	433	#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
bogdanm	0:9b334a45a8ff	434	#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
bogdanm	0:9b334a45a8ff	435	#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
bogdanm	0:9b334a45a8ff	436	/**
bogdanm	0:9b334a45a8ff	437	* @}
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/** @defgroup ADC_channels_type ADC Channels Type
bogdanm	0:9b334a45a8ff	441	* @{
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443	#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	444	#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /!< reserved for future use /
bogdanm	0:9b334a45a8ff	445	#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /!< reserved for future use /
bogdanm	0:9b334a45a8ff	446	/**
bogdanm	0:9b334a45a8ff	447	* @}
bogdanm	0:9b334a45a8ff	448	*/
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/**
bogdanm	0:9b334a45a8ff	451	* @}
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	455	/** @defgroup ADC_Exported_Macros ADC Exported Macros
bogdanm	0:9b334a45a8ff	456	* @{
bogdanm	0:9b334a45a8ff	457	*/
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/** @brief Reset ADC handle state
bogdanm	0:9b334a45a8ff	460	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	461	* @retval None
bogdanm	0:9b334a45a8ff	462	*/
bogdanm	0:9b334a45a8ff	463	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/**
bogdanm	0:9b334a45a8ff	466	* @brief Enable the ADC peripheral.
bogdanm	0:9b334a45a8ff	467	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	468	* @retval None
bogdanm	0:9b334a45a8ff	469	*/
bogdanm	0:9b334a45a8ff	470	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON)
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/**
bogdanm	0:9b334a45a8ff	473	* @brief Disable the ADC peripheral.
bogdanm	0:9b334a45a8ff	474	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	475	* @retval None
bogdanm	0:9b334a45a8ff	476	*/
bogdanm	0:9b334a45a8ff	477	#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/**
bogdanm	0:9b334a45a8ff	480	* @brief Enable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	481	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	482	* @param __INTERRUPT__: ADC Interrupt.
bogdanm	0:9b334a45a8ff	483	* @retval None
bogdanm	0:9b334a45a8ff	484	*/
bogdanm	0:9b334a45a8ff	485	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	/**
bogdanm	0:9b334a45a8ff	488	* @brief Disable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	489	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	490	* @param __INTERRUPT__: ADC interrupt.
bogdanm	0:9b334a45a8ff	491	* @retval None
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/** @brief Check if the specified ADC interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	496	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	497	* @param __INTERRUPT__: specifies the ADC interrupt source to check.
bogdanm	0:9b334a45a8ff	498	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/**
bogdanm	0:9b334a45a8ff	503	* @brief Clear the ADC's pending flags.
bogdanm	0:9b334a45a8ff	504	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	505	* @param __FLAG__: ADC flag.
bogdanm	0:9b334a45a8ff	506	* @retval None
bogdanm	0:9b334a45a8ff	507	*/
bogdanm	0:9b334a45a8ff	508	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/**
bogdanm	0:9b334a45a8ff	511	* @brief Get the selected ADC's flag status.
bogdanm	0:9b334a45a8ff	512	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	513	* @param __FLAG__: ADC flag.
bogdanm	0:9b334a45a8ff	514	* @retval None
bogdanm	0:9b334a45a8ff	515	*/
bogdanm	0:9b334a45a8ff	516	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/**
bogdanm	0:9b334a45a8ff	519	* @}
bogdanm	0:9b334a45a8ff	520	*/
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	/* Include ADC HAL Extension module */
bogdanm	0:9b334a45a8ff	523	#include "stm32f7xx_hal_adc_ex.h"
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	526	/** @addtogroup ADC_Exported_Functions
bogdanm	0:9b334a45a8ff	527	* @{
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/** @addtogroup ADC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	531	* @{
bogdanm	0:9b334a45a8ff	532	*/
bogdanm	0:9b334a45a8ff	533	/* Initialization/de-initialization functions ***********************************/
bogdanm	0:9b334a45a8ff	534	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	535	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	536	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	537	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	538	/**
bogdanm	0:9b334a45a8ff	539	* @}
bogdanm	0:9b334a45a8ff	540	*/
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/** @addtogroup ADC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	543	* @{
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545	/* I/O operation functions ******************************************************/
bogdanm	0:9b334a45a8ff	546	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	547	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	548	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	553	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm	0:9b334a45a8ff	558	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	563	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	564	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	565	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	566	/**
bogdanm	0:9b334a45a8ff	567	* @}
bogdanm	0:9b334a45a8ff	568	*/
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/** @addtogroup ADC_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	571	* @{
bogdanm	0:9b334a45a8ff	572	*/
bogdanm	0:9b334a45a8ff	573	/* Peripheral Control functions *************************************************/
bogdanm	0:9b334a45a8ff	574	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm	0:9b334a45a8ff	575	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
bogdanm	0:9b334a45a8ff	576	/**
bogdanm	0:9b334a45a8ff	577	* @}
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/** @addtogroup ADC_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	581	* @{
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583	/* Peripheral State functions ***************************************************/
mbed_official	83:a036322b8637	584	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
mbed_official	83:a036322b8637	585	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	586	/**
bogdanm	0:9b334a45a8ff	587	* @}
bogdanm	0:9b334a45a8ff	588	*/
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	/**
bogdanm	0:9b334a45a8ff	591	* @}
bogdanm	0:9b334a45a8ff	592	*/
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/* Private types -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	595	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	596	/* Private constants ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	597	/** @defgroup ADC_Private_Constants ADC Private Constants
bogdanm	0:9b334a45a8ff	598	* @{
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600	/* Delay for ADC stabilization time. */
bogdanm	0:9b334a45a8ff	601	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
bogdanm	0:9b334a45a8ff	602	/* Unit: us */
bogdanm	0:9b334a45a8ff	603	#define ADC_STAB_DELAY_US ((uint32_t) 3)
bogdanm	0:9b334a45a8ff	604	/* Delay for temperature sensor stabilization time. */
bogdanm	0:9b334a45a8ff	605	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
bogdanm	0:9b334a45a8ff	606	/* Unit: us */
bogdanm	0:9b334a45a8ff	607	#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
bogdanm	0:9b334a45a8ff	608	/**
bogdanm	0:9b334a45a8ff	609	* @}
bogdanm	0:9b334a45a8ff	610	*/
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	613	/** @defgroup ADC_Private_Macros ADC Private Macros
bogdanm	0:9b334a45a8ff	614	* @{
bogdanm	0:9b334a45a8ff	615	*/
mbed_official	83:a036322b8637	616	/* Macro reserved for internal HAL driver usage, not intended to be used in
mbed_official	83:a036322b8637	617	code of final user */
mbed_official	83:a036322b8637	618
mbed_official	83:a036322b8637	619	/**
mbed_official	83:a036322b8637	620	* @brief Verification of ADC state: enabled or disabled
mbed_official	83:a036322b8637	621	* @param __HANDLE__: ADC handle
mbed_official	83:a036322b8637	622	* @retval SET (ADC enabled) or RESET (ADC disabled)
mbed_official	83:a036322b8637	623	*/
mbed_official	83:a036322b8637	624	#define ADC_IS_ENABLE(__HANDLE__) \
mbed_official	83:a036322b8637	625	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
mbed_official	83:a036322b8637	626	) ? SET : RESET)
mbed_official	83:a036322b8637	627
mbed_official	83:a036322b8637	628	/**
mbed_official	83:a036322b8637	629	* @brief Test if conversion trigger of regular group is software start
mbed_official	83:a036322b8637	630	* or external trigger.
mbed_official	83:a036322b8637	631	* @param __HANDLE__: ADC handle
mbed_official	83:a036322b8637	632	* @retval SET (software start) or RESET (external trigger)
mbed_official	83:a036322b8637	633	*/
mbed_official	83:a036322b8637	634	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
mbed_official	83:a036322b8637	635	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
mbed_official	83:a036322b8637	636
mbed_official	83:a036322b8637	637	/**
mbed_official	83:a036322b8637	638	* @brief Test if conversion trigger of injected group is software start
mbed_official	83:a036322b8637	639	* or external trigger.
mbed_official	83:a036322b8637	640	* @param __HANDLE__: ADC handle
mbed_official	83:a036322b8637	641	* @retval SET (software start) or RESET (external trigger)
mbed_official	83:a036322b8637	642	*/
mbed_official	83:a036322b8637	643	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
mbed_official	83:a036322b8637	644	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
mbed_official	83:a036322b8637	645
mbed_official	83:a036322b8637	646	/**
mbed_official	83:a036322b8637	647	* @brief Simultaneously clears and sets specific bits of the handle State
mbed_official	83:a036322b8637	648	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
mbed_official	83:a036322b8637	649	* the first parameter is the ADC handle State, the second parameter is the
mbed_official	83:a036322b8637	650	* bit field to clear, the third and last parameter is the bit field to set.
mbed_official	83:a036322b8637	651	* @retval None
mbed_official	83:a036322b8637	652	*/
mbed_official	83:a036322b8637	653	#define ADC_STATE_CLR_SET MODIFY_REG
mbed_official	83:a036322b8637	654
mbed_official	83:a036322b8637	655	/**
mbed_official	83:a036322b8637	656	* @brief Clear ADC error code (set it to error code: "no error")
mbed_official	83:a036322b8637	657	* @param __HANDLE__: ADC handle
mbed_official	83:a036322b8637	658	* @retval None
mbed_official	83:a036322b8637	659	*/
mbed_official	83:a036322b8637	660	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
mbed_official	83:a036322b8637	661	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
bogdanm	0:9b334a45a8ff	662	#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	663	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	664	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) \|\| \
bogdanm	0:9b334a45a8ff	665	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
bogdanm	0:9b334a45a8ff	666	#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	667	((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	668	((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	669	((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	670	((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	671	((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	672	((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	673	((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	674	((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	675	((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	676	((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	677	((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	678	((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	679	((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	680	((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	681	((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
bogdanm	0:9b334a45a8ff	682	#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) \|\| \
bogdanm	0:9b334a45a8ff	683	((__RESOLUTION__) == ADC_RESOLUTION_10B) \|\| \
bogdanm	0:9b334a45a8ff	684	((__RESOLUTION__) == ADC_RESOLUTION_8B) \|\| \
bogdanm	0:9b334a45a8ff	685	((__RESOLUTION__) == ADC_RESOLUTION_6B))
bogdanm	0:9b334a45a8ff	686	#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	687	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
bogdanm	0:9b334a45a8ff	688	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	689	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
bogdanm	0:9b334a45a8ff	690	#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
bogdanm	0:9b334a45a8ff	691	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
bogdanm	0:9b334a45a8ff	692	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
bogdanm	0:9b334a45a8ff	693	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
bogdanm	0:9b334a45a8ff	694	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	695	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
bogdanm	0:9b334a45a8ff	696	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
bogdanm	0:9b334a45a8ff	697	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	698	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) \|\| \
bogdanm	0:9b334a45a8ff	699	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	700	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
bogdanm	0:9b334a45a8ff	701	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	702	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	703	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	704	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
bogdanm	0:9b334a45a8ff	705	((__REGTRIG__) == ADC_SOFTWARE_START))
bogdanm	0:9b334a45a8ff	706	#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) \|\| \
bogdanm	0:9b334a45a8ff	707	((__ALIGN__) == ADC_DATAALIGN_LEFT))
bogdanm	0:9b334a45a8ff	708
bogdanm	0:9b334a45a8ff	709	#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	710	((__TIME__) == ADC_SAMPLETIME_15CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	711	((__TIME__) == ADC_SAMPLETIME_28CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	712	((__TIME__) == ADC_SAMPLETIME_56CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	713	((__TIME__) == ADC_SAMPLETIME_84CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	714	((__TIME__) == ADC_SAMPLETIME_112CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	715	((__TIME__) == ADC_SAMPLETIME_144CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	716	((__TIME__) == ADC_SAMPLETIME_480CYCLES))
bogdanm	0:9b334a45a8ff	717	#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) \|\| \
bogdanm	0:9b334a45a8ff	718	((__EOCSelection__) == ADC_EOC_SEQ_CONV) \|\| \
bogdanm	0:9b334a45a8ff	719	((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
bogdanm	0:9b334a45a8ff	720	#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	721	((__EVENT__) == ADC_OVR_EVENT))
bogdanm	0:9b334a45a8ff	722	#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
bogdanm	0:9b334a45a8ff	723	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	724	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
bogdanm	0:9b334a45a8ff	725	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
bogdanm	0:9b334a45a8ff	726	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	727	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) \|\| \
bogdanm	0:9b334a45a8ff	728	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
bogdanm	0:9b334a45a8ff	729	#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) \|\| \
bogdanm	0:9b334a45a8ff	730	((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) \|\| \
bogdanm	0:9b334a45a8ff	731	((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
bogdanm	0:9b334a45a8ff	732	#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
bogdanm	0:9b334a45a8ff	733	#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
bogdanm	0:9b334a45a8ff	734	#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
bogdanm	0:9b334a45a8ff	735	#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
bogdanm	0:9b334a45a8ff	736	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
bogdanm	0:9b334a45a8ff	737	((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) \|\| \
bogdanm	0:9b334a45a8ff	738	(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) \|\| \
bogdanm	0:9b334a45a8ff	739	(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) \|\| \
bogdanm	0:9b334a45a8ff	740	(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	/**
bogdanm	0:9b334a45a8ff	743	* @brief Set ADC Regular channel sequence length.
bogdanm	0:9b334a45a8ff	744	* @param _NbrOfConversion_: Regular channel sequence length.
bogdanm	0:9b334a45a8ff	745	* @retval None
bogdanm	0:9b334a45a8ff	746	*/
bogdanm	0:9b334a45a8ff	747	#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/**
bogdanm	0:9b334a45a8ff	750	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
bogdanm	0:9b334a45a8ff	751	* @param _SAMPLETIME_: Sample time parameter.
bogdanm	0:9b334a45a8ff	752	* @param _CHANNELNB_: Channel number.
bogdanm	0:9b334a45a8ff	753	* @retval None
bogdanm	0:9b334a45a8ff	754	*/
bogdanm	0:9b334a45a8ff	755	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/**
bogdanm	0:9b334a45a8ff	758	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
bogdanm	0:9b334a45a8ff	759	* @param _SAMPLETIME_: Sample time parameter.
bogdanm	0:9b334a45a8ff	760	* @param _CHANNELNB_: Channel number.
bogdanm	0:9b334a45a8ff	761	* @retval None
bogdanm	0:9b334a45a8ff	762	*/
bogdanm	0:9b334a45a8ff	763	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/**
bogdanm	0:9b334a45a8ff	766	* @brief Set the selected regular channel rank for rank between 1 and 6.
bogdanm	0:9b334a45a8ff	767	* @param _CHANNELNB_: Channel number.
bogdanm	0:9b334a45a8ff	768	* @param _RANKNB_: Rank number.
bogdanm	0:9b334a45a8ff	769	* @retval None
bogdanm	0:9b334a45a8ff	770	*/
bogdanm	0:9b334a45a8ff	771	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/**
bogdanm	0:9b334a45a8ff	774	* @brief Set the selected regular channel rank for rank between 7 and 12.
bogdanm	0:9b334a45a8ff	775	* @param _CHANNELNB_: Channel number.
bogdanm	0:9b334a45a8ff	776	* @param _RANKNB_: Rank number.
bogdanm	0:9b334a45a8ff	777	* @retval None
bogdanm	0:9b334a45a8ff	778	*/
bogdanm	0:9b334a45a8ff	779	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/**
bogdanm	0:9b334a45a8ff	782	* @brief Set the selected regular channel rank for rank between 13 and 16.
bogdanm	0:9b334a45a8ff	783	* @param _CHANNELNB_: Channel number.
bogdanm	0:9b334a45a8ff	784	* @param _RANKNB_: Rank number.
bogdanm	0:9b334a45a8ff	785	* @retval None
bogdanm	0:9b334a45a8ff	786	*/
bogdanm	0:9b334a45a8ff	787	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/**
bogdanm	0:9b334a45a8ff	790	* @brief Enable ADC continuous conversion mode.
bogdanm	0:9b334a45a8ff	791	* @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm	0:9b334a45a8ff	792	* @retval None
bogdanm	0:9b334a45a8ff	793	*/
bogdanm	0:9b334a45a8ff	794	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	/**
bogdanm	0:9b334a45a8ff	797	* @brief Configures the number of discontinuous conversions for the regular group channels.
bogdanm	0:9b334a45a8ff	798	* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
bogdanm	0:9b334a45a8ff	799	* @retval None
bogdanm	0:9b334a45a8ff	800	*/
bogdanm	0:9b334a45a8ff	801	#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	/**
bogdanm	0:9b334a45a8ff	804	* @brief Enable ADC scan mode.
bogdanm	0:9b334a45a8ff	805	* @param _SCANCONV_MODE_: Scan conversion mode.
bogdanm	0:9b334a45a8ff	806	* @retval None
bogdanm	0:9b334a45a8ff	807	*/
bogdanm	0:9b334a45a8ff	808	#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	/**
bogdanm	0:9b334a45a8ff	811	* @brief Enable the ADC end of conversion selection.
bogdanm	0:9b334a45a8ff	812	* @param _EOCSelection_MODE_: End of conversion selection mode.
bogdanm	0:9b334a45a8ff	813	* @retval None
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815	#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/**
bogdanm	0:9b334a45a8ff	818	* @brief Enable the ADC DMA continuous request.
bogdanm	0:9b334a45a8ff	819	* @param _DMAContReq_MODE_: DMA continuous request mode.
bogdanm	0:9b334a45a8ff	820	* @retval None
bogdanm	0:9b334a45a8ff	821	*/
bogdanm	0:9b334a45a8ff	822	#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/**
bogdanm	0:9b334a45a8ff	825	* @brief Return resolution bits in CR1 register.
bogdanm	0:9b334a45a8ff	826	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	827	* @retval None
bogdanm	0:9b334a45a8ff	828	*/
bogdanm	0:9b334a45a8ff	829	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	/**
bogdanm	0:9b334a45a8ff	832	* @}
bogdanm	0:9b334a45a8ff	833	*/
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	836	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	837	* @{
bogdanm	0:9b334a45a8ff	838	*/
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/**
bogdanm	0:9b334a45a8ff	841	* @}
bogdanm	0:9b334a45a8ff	842	*/
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/**
bogdanm	0:9b334a45a8ff	845	* @}
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	/**
bogdanm	0:9b334a45a8ff	849	* @}
bogdanm	0:9b334a45a8ff	850	*/
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	853	}
bogdanm	0:9b334a45a8ff	854	#endif
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	#endif /__STM32F7xx_ADC_H /
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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