mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_ll_fmc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief FMC Low Layer HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
bogdanm	0:9b334a45a8ff	11	* + Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### FMC peripheral features #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..] The Flexible memory controller (FMC) includes three memory controllers:
bogdanm	0:9b334a45a8ff	20	(+) The NOR/PSRAM memory controller
bogdanm	0:9b334a45a8ff	21	(+) The NAND/PC Card memory controller
bogdanm	0:9b334a45a8ff	22	(+) The Synchronous DRAM (SDRAM) controller
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	[..] The FMC functional block makes the interface with synchronous and asynchronous static
bogdanm	0:9b334a45a8ff	25	memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
bogdanm	0:9b334a45a8ff	26	(+) to translate AHB transactions into the appropriate external device protocol
bogdanm	0:9b334a45a8ff	27	(+) to meet the access time requirements of the external memory devices
bogdanm	0:9b334a45a8ff	28
bogdanm	0:9b334a45a8ff	29	[..] All external memories share the addresses, data and control signals with the controller.
bogdanm	0:9b334a45a8ff	30	Each external device is accessed by means of a unique Chip Select. The FMC performs
bogdanm	0:9b334a45a8ff	31	only one access at a time to an external device.
bogdanm	0:9b334a45a8ff	32	The main features of the FMC controller are the following:
bogdanm	0:9b334a45a8ff	33	(+) Interface with static-memory mapped devices including:
bogdanm	0:9b334a45a8ff	34	(++) Static random access memory (SRAM)
bogdanm	0:9b334a45a8ff	35	(++) Read-only memory (ROM)
bogdanm	0:9b334a45a8ff	36	(++) NOR Flash memory/OneNAND Flash memory
bogdanm	0:9b334a45a8ff	37	(++) PSRAM (4 memory banks)
bogdanm	0:9b334a45a8ff	38	(++) 16-bit PC Card compatible devices
bogdanm	0:9b334a45a8ff	39	(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
bogdanm	0:9b334a45a8ff	40	data
bogdanm	0:9b334a45a8ff	41	(+) Interface with synchronous DRAM (SDRAM) memories
bogdanm	0:9b334a45a8ff	42	(+) Independent Chip Select control for each memory bank
bogdanm	0:9b334a45a8ff	43	(+) Independent configuration for each memory bank
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	@endverbatim
bogdanm	0:9b334a45a8ff	46	******************************************************************************
bogdanm	0:9b334a45a8ff	47	* @attention
bogdanm	0:9b334a45a8ff	48	*
bogdanm	0:9b334a45a8ff	49	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	50	*
bogdanm	0:9b334a45a8ff	51	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	52	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	53	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	54	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	55	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	56	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	57	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	58	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	59	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	60	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	61	*
bogdanm	0:9b334a45a8ff	62	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	63	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	64	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	65	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	66	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	67	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	68	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	69	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	70	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	71	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	72	*
bogdanm	0:9b334a45a8ff	73	******************************************************************************
bogdanm	0:9b334a45a8ff	74	*/
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	77	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	80	* @{
bogdanm	0:9b334a45a8ff	81	*/
bogdanm	0:9b334a45a8ff	82
bogdanm	0:9b334a45a8ff	83	/** @defgroup FMC_LL FMC Low Layer
bogdanm	0:9b334a45a8ff	84	* @brief FMC driver modules
bogdanm	0:9b334a45a8ff	85	* @{
bogdanm	0:9b334a45a8ff	86	*/
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	#if defined (HAL_SRAM_MODULE_ENABLED) \|\| defined(HAL_NOR_MODULE_ENABLED) \|\| defined(HAL_NAND_MODULE_ENABLED) \|\| defined(HAL_PCCARD_MODULE_ENABLED) \|\| defined(HAL_SDRAM_MODULE_ENABLED)
bogdanm	0:9b334a45a8ff	89
mbed_official	19:112740acecfa	90	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	93	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	94	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	95	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	96	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	97	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	98	/** @addtogroup FMC_LL_Private_Functions
bogdanm	0:9b334a45a8ff	99	* @{
bogdanm	0:9b334a45a8ff	100	*/
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	/** @addtogroup FMC_LL_NORSRAM
bogdanm	0:9b334a45a8ff	103	* @brief NORSRAM Controller functions
bogdanm	0:9b334a45a8ff	104	*
bogdanm	0:9b334a45a8ff	105	@verbatim
bogdanm	0:9b334a45a8ff	106	==============================================================================
bogdanm	0:9b334a45a8ff	107	##### How to use NORSRAM device driver #####
bogdanm	0:9b334a45a8ff	108	==============================================================================
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	[..]
bogdanm	0:9b334a45a8ff	111	This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
bogdanm	0:9b334a45a8ff	112	to run the NORSRAM external devices.
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
bogdanm	0:9b334a45a8ff	115	(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
bogdanm	0:9b334a45a8ff	116	(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
bogdanm	0:9b334a45a8ff	117	(+) FMC NORSRAM bank extended timing configuration using the function
bogdanm	0:9b334a45a8ff	118	FMC_NORSRAM_Extended_Timing_Init()
bogdanm	0:9b334a45a8ff	119	(+) FMC NORSRAM bank enable/disable write operation using the functions
bogdanm	0:9b334a45a8ff	120	FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	@endverbatim
bogdanm	0:9b334a45a8ff	124	* @{
bogdanm	0:9b334a45a8ff	125	*/
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
bogdanm	0:9b334a45a8ff	128	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	129	*
bogdanm	0:9b334a45a8ff	130	@verbatim
bogdanm	0:9b334a45a8ff	131	==============================================================================
bogdanm	0:9b334a45a8ff	132	##### Initialization and de_initialization functions #####
bogdanm	0:9b334a45a8ff	133	==============================================================================
bogdanm	0:9b334a45a8ff	134	[..]
bogdanm	0:9b334a45a8ff	135	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	136	(+) Initialize and configure the FMC NORSRAM interface
bogdanm	0:9b334a45a8ff	137	(+) De-initialize the FMC NORSRAM interface
bogdanm	0:9b334a45a8ff	138	(+) Configure the FMC clock and associated GPIOs
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	@endverbatim
bogdanm	0:9b334a45a8ff	141	* @{
bogdanm	0:9b334a45a8ff	142	*/
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	/**
bogdanm	0:9b334a45a8ff	145	* @brief Initialize the FMC_NORSRAM device according to the specified
bogdanm	0:9b334a45a8ff	146	* control parameters in the FMC_NORSRAM_InitTypeDef
bogdanm	0:9b334a45a8ff	147	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	148	* @param Init: Pointer to NORSRAM Initialization structure
bogdanm	0:9b334a45a8ff	149	* @retval HAL status
bogdanm	0:9b334a45a8ff	150	*/
bogdanm	0:9b334a45a8ff	151	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init)
bogdanm	0:9b334a45a8ff	152	{
bogdanm	0:9b334a45a8ff	153	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/* Check the parameters */
bogdanm	0:9b334a45a8ff	156	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	157	assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
bogdanm	0:9b334a45a8ff	158	assert_param(IS_FMC_MUX(Init->DataAddressMux));
bogdanm	0:9b334a45a8ff	159	assert_param(IS_FMC_MEMORY(Init->MemoryType));
bogdanm	0:9b334a45a8ff	160	assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm	0:9b334a45a8ff	161	assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
bogdanm	0:9b334a45a8ff	162	assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
mbed_official	19:112740acecfa	163	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	164	assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
mbed_official	19:112740acecfa	165	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	166	assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
bogdanm	0:9b334a45a8ff	167	assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
bogdanm	0:9b334a45a8ff	168	assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
bogdanm	0:9b334a45a8ff	169	assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
bogdanm	0:9b334a45a8ff	170	assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
bogdanm	0:9b334a45a8ff	171	assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
bogdanm	0:9b334a45a8ff	172	assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
mbed_official	19:112740acecfa	173	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	174	assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
bogdanm	0:9b334a45a8ff	175	assert_param(IS_FMC_PAGESIZE(Init->PageSize));
mbed_official	19:112740acecfa	176	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	/* Get the BTCR register value */
bogdanm	0:9b334a45a8ff	179	tmpr = Device->BTCR[Init->NSBank];
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	182	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
bogdanm	0:9b334a45a8ff	183	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
bogdanm	0:9b334a45a8ff	184	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
bogdanm	0:9b334a45a8ff	185	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
bogdanm	0:9b334a45a8ff	186	FMC_BCR1_WAITPOL \| FMC_BCR1_WRAPMOD \| FMC_BCR1_WAITCFG \| \
bogdanm	0:9b334a45a8ff	187	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
bogdanm	0:9b334a45a8ff	188	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN));
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	/* Set NORSRAM device control parameters */
bogdanm	0:9b334a45a8ff	191	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
bogdanm	0:9b334a45a8ff	192	Init->MemoryType \|\
bogdanm	0:9b334a45a8ff	193	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	194	Init->BurstAccessMode \|\
bogdanm	0:9b334a45a8ff	195	Init->WaitSignalPolarity \|\
bogdanm	0:9b334a45a8ff	196	Init->WrapMode \|\
bogdanm	0:9b334a45a8ff	197	Init->WaitSignalActive \|\
bogdanm	0:9b334a45a8ff	198	Init->WriteOperation \|\
bogdanm	0:9b334a45a8ff	199	Init->WaitSignal \|\
bogdanm	0:9b334a45a8ff	200	Init->ExtendedMode \|\
bogdanm	0:9b334a45a8ff	201	Init->AsynchronousWait \|\
bogdanm	0:9b334a45a8ff	202	Init->WriteBurst \|\
bogdanm	0:9b334a45a8ff	203	Init->ContinuousClock);
mbed_official	19:112740acecfa	204	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	0:9b334a45a8ff	205	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
bogdanm	0:9b334a45a8ff	206	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
bogdanm	0:9b334a45a8ff	207	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
bogdanm	0:9b334a45a8ff	208	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
bogdanm	0:9b334a45a8ff	209	FMC_BCR1_WAITPOL \| FMC_BCR1_WAITCFG \| FMC_BCR1_CPSIZE \| \
bogdanm	0:9b334a45a8ff	210	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
bogdanm	0:9b334a45a8ff	211	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN \| \
bogdanm	0:9b334a45a8ff	212	FMC_BCR1_WFDIS));
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* Set NORSRAM device control parameters */
bogdanm	0:9b334a45a8ff	215	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
bogdanm	0:9b334a45a8ff	216	Init->MemoryType \|\
bogdanm	0:9b334a45a8ff	217	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	218	Init->BurstAccessMode \|\
bogdanm	0:9b334a45a8ff	219	Init->WaitSignalPolarity \|\
bogdanm	0:9b334a45a8ff	220	Init->WaitSignalActive \|\
bogdanm	0:9b334a45a8ff	221	Init->WriteOperation \|\
bogdanm	0:9b334a45a8ff	222	Init->WaitSignal \|\
bogdanm	0:9b334a45a8ff	223	Init->ExtendedMode \|\
bogdanm	0:9b334a45a8ff	224	Init->AsynchronousWait \|\
bogdanm	0:9b334a45a8ff	225	Init->WriteBurst \|\
bogdanm	0:9b334a45a8ff	226	Init->ContinuousClock \|\
bogdanm	0:9b334a45a8ff	227	Init->PageSize \|\
bogdanm	0:9b334a45a8ff	228	Init->WriteFifo);
bogdanm	0:9b334a45a8ff	229	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	tmpr \|= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
bogdanm	0:9b334a45a8ff	234	}
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	Device->BTCR[Init->NSBank] = tmpr;
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
bogdanm	0:9b334a45a8ff	239	if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
bogdanm	0:9b334a45a8ff	242	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->BurstAccessMode \|\
bogdanm	0:9b334a45a8ff	243	Init->ContinuousClock);
bogdanm	0:9b334a45a8ff	244	}
bogdanm	0:9b334a45a8ff	245
mbed_official	19:112740acecfa	246	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	247	if(Init->NSBank != FMC_NORSRAM_BANK1)
bogdanm	0:9b334a45a8ff	248	{
bogdanm	0:9b334a45a8ff	249	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->WriteFifo);
bogdanm	0:9b334a45a8ff	250	}
mbed_official	19:112740acecfa	251	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	252
bogdanm	0:9b334a45a8ff	253	return HAL_OK;
bogdanm	0:9b334a45a8ff	254	}
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/**
bogdanm	0:9b334a45a8ff	257	* @brief DeInitialize the FMC_NORSRAM peripheral
bogdanm	0:9b334a45a8ff	258	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	259	* @param ExDevice: Pointer to NORSRAM extended mode device instance
bogdanm	0:9b334a45a8ff	260	* @param Bank: NORSRAM bank number
bogdanm	0:9b334a45a8ff	261	* @retval HAL status
bogdanm	0:9b334a45a8ff	262	*/
bogdanm	0:9b334a45a8ff	263	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank)
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	/* Check the parameters */
bogdanm	0:9b334a45a8ff	266	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	267	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
bogdanm	0:9b334a45a8ff	268	assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	269
bogdanm	0:9b334a45a8ff	270	/* Disable the FMC_NORSRAM device */
bogdanm	0:9b334a45a8ff	271	__FMC_NORSRAM_DISABLE(Device, Bank);
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* De-initialize the FMC_NORSRAM device */
bogdanm	0:9b334a45a8ff	274	/* FMC_NORSRAM_BANK1 */
bogdanm	0:9b334a45a8ff	275	if(Bank == FMC_NORSRAM_BANK1)
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	Device->BTCR[Bank] = 0x000030DB;
bogdanm	0:9b334a45a8ff	278	}
bogdanm	0:9b334a45a8ff	279	/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
bogdanm	0:9b334a45a8ff	280	else
bogdanm	0:9b334a45a8ff	281	{
bogdanm	0:9b334a45a8ff	282	Device->BTCR[Bank] = 0x000030D2;
bogdanm	0:9b334a45a8ff	283	}
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	Device->BTCR[Bank + 1] = 0x0FFFFFFF;
bogdanm	0:9b334a45a8ff	286	ExDevice->BWTR[Bank] = 0x0FFFFFFF;
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	return HAL_OK;
bogdanm	0:9b334a45a8ff	289	}
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/**
bogdanm	0:9b334a45a8ff	292	* @brief Initialize the FMC_NORSRAM Timing according to the specified
bogdanm	0:9b334a45a8ff	293	* parameters in the FMC_NORSRAM_TimingTypeDef
bogdanm	0:9b334a45a8ff	294	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	295	* @param Timing: Pointer to NORSRAM Timing structure
bogdanm	0:9b334a45a8ff	296	* @param Bank: NORSRAM bank number
bogdanm	0:9b334a45a8ff	297	* @retval HAL status
bogdanm	0:9b334a45a8ff	298	*/
bogdanm	0:9b334a45a8ff	299	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	300	{
bogdanm	0:9b334a45a8ff	301	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/* Check the parameters */
bogdanm	0:9b334a45a8ff	304	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	305	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm	0:9b334a45a8ff	306	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm	0:9b334a45a8ff	307	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm	0:9b334a45a8ff	308	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm	0:9b334a45a8ff	309	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
bogdanm	0:9b334a45a8ff	310	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
bogdanm	0:9b334a45a8ff	311	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
bogdanm	0:9b334a45a8ff	312	assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Get the BTCR register value */
bogdanm	0:9b334a45a8ff	315	tmpr = Device->BTCR[Bank + 1];
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
bogdanm	0:9b334a45a8ff	318	tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET \| FMC_BTR1_ADDHLD \| FMC_BTR1_DATAST \| \
bogdanm	0:9b334a45a8ff	319	FMC_BTR1_BUSTURN \| FMC_BTR1_CLKDIV \| FMC_BTR1_DATLAT \| \
bogdanm	0:9b334a45a8ff	320	FMC_BTR1_ACCMOD));
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/* Set FMC_NORSRAM device timing parameters */
bogdanm	0:9b334a45a8ff	323	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
bogdanm	0:9b334a45a8ff	324	((Timing->AddressHoldTime) << 4) \|\
bogdanm	0:9b334a45a8ff	325	((Timing->DataSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	326	((Timing->BusTurnAroundDuration) << 16) \|\
bogdanm	0:9b334a45a8ff	327	(((Timing->CLKDivision)-1) << 20) \|\
bogdanm	0:9b334a45a8ff	328	(((Timing->DataLatency)-2) << 24) \|\
bogdanm	0:9b334a45a8ff	329	(Timing->AccessMode));
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	Device->BTCR[Bank + 1] = tmpr;
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
bogdanm	0:9b334a45a8ff	334	if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
bogdanm	0:9b334a45a8ff	335	{
bogdanm	0:9b334a45a8ff	336	tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
bogdanm	0:9b334a45a8ff	337	tmpr \|= (uint32_t)(((Timing->CLKDivision)-1) << 20);
bogdanm	0:9b334a45a8ff	338	Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
bogdanm	0:9b334a45a8ff	339	}
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	return HAL_OK;
bogdanm	0:9b334a45a8ff	342	}
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/**
bogdanm	0:9b334a45a8ff	345	* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
bogdanm	0:9b334a45a8ff	346	* parameters in the FMC_NORSRAM_TimingTypeDef
bogdanm	0:9b334a45a8ff	347	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	348	* @param Timing: Pointer to NORSRAM Timing structure
bogdanm	0:9b334a45a8ff	349	* @param Bank: NORSRAM bank number
bogdanm	0:9b334a45a8ff	350	* @retval HAL status
bogdanm	0:9b334a45a8ff	351	*/
bogdanm	0:9b334a45a8ff	352	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode)
bogdanm	0:9b334a45a8ff	353	{
bogdanm	0:9b334a45a8ff	354	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/* Check the parameters */
bogdanm	0:9b334a45a8ff	357	assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
bogdanm	0:9b334a45a8ff	360	if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
bogdanm	0:9b334a45a8ff	361	{
bogdanm	0:9b334a45a8ff	362	/* Check the parameters */
bogdanm	0:9b334a45a8ff	363	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
bogdanm	0:9b334a45a8ff	364	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm	0:9b334a45a8ff	365	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm	0:9b334a45a8ff	366	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm	0:9b334a45a8ff	367	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official	19:112740acecfa	368	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	369	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
bogdanm	0:9b334a45a8ff	370	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official	19:112740acecfa	371	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	372	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
bogdanm	0:9b334a45a8ff	373	assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/* Get the BWTR register value */
bogdanm	0:9b334a45a8ff	376	tmpr = Device->BWTR[Bank];
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	379	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
bogdanm	0:9b334a45a8ff	380	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
bogdanm	0:9b334a45a8ff	381	FMC_BWTR1_BUSTURN \| FMC_BWTR1_CLKDIV \| FMC_BWTR1_DATLAT \| \
bogdanm	0:9b334a45a8ff	382	FMC_BWTR1_ACCMOD));
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
bogdanm	0:9b334a45a8ff	385	((Timing->AddressHoldTime) << 4) \|\
bogdanm	0:9b334a45a8ff	386	((Timing->DataSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	387	((Timing->BusTurnAroundDuration) << 16) \|\
bogdanm	0:9b334a45a8ff	388	(((Timing->CLKDivision)-1) << 20) \|\
bogdanm	0:9b334a45a8ff	389	(((Timing->DataLatency)-2) << 24) \|\
bogdanm	0:9b334a45a8ff	390	(Timing->AccessMode));
mbed_official	19:112740acecfa	391	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	0:9b334a45a8ff	392	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
bogdanm	0:9b334a45a8ff	393	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
bogdanm	0:9b334a45a8ff	394	FMC_BWTR1_BUSTURN \| FMC_BWTR1_ACCMOD));
bogdanm	0:9b334a45a8ff	395
bogdanm	0:9b334a45a8ff	396	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
bogdanm	0:9b334a45a8ff	397	((Timing->AddressHoldTime) << 4) \|\
bogdanm	0:9b334a45a8ff	398	((Timing->DataSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	399	((Timing->BusTurnAroundDuration) << 16) \|\
bogdanm	0:9b334a45a8ff	400	(Timing->AccessMode));
bogdanm	0:9b334a45a8ff	401	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	Device->BWTR[Bank] = tmpr;
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405	else
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	Device->BWTR[Bank] = 0x0FFFFFFF;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	return HAL_OK;
bogdanm	0:9b334a45a8ff	411	}
bogdanm	0:9b334a45a8ff	412	/**
bogdanm	0:9b334a45a8ff	413	* @}
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
bogdanm	0:9b334a45a8ff	417	* @brief management functions
bogdanm	0:9b334a45a8ff	418	*
bogdanm	0:9b334a45a8ff	419	@verbatim
bogdanm	0:9b334a45a8ff	420	==============================================================================
bogdanm	0:9b334a45a8ff	421	##### FMC_NORSRAM Control functions #####
bogdanm	0:9b334a45a8ff	422	==============================================================================
bogdanm	0:9b334a45a8ff	423	[..]
bogdanm	0:9b334a45a8ff	424	This subsection provides a set of functions allowing to control dynamically
bogdanm	0:9b334a45a8ff	425	the FMC NORSRAM interface.
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	@endverbatim
bogdanm	0:9b334a45a8ff	428	* @{
bogdanm	0:9b334a45a8ff	429	*/
bogdanm	0:9b334a45a8ff	430	/**
bogdanm	0:9b334a45a8ff	431	* @brief Enables dynamically FMC_NORSRAM write operation.
bogdanm	0:9b334a45a8ff	432	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	433	* @param Bank: NORSRAM bank number
bogdanm	0:9b334a45a8ff	434	* @retval HAL status
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	437	{
bogdanm	0:9b334a45a8ff	438	/* Check the parameters */
bogdanm	0:9b334a45a8ff	439	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	440	assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Enable write operation */
bogdanm	0:9b334a45a8ff	443	Device->BTCR[Bank] \|= FMC_WRITE_OPERATION_ENABLE;
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	return HAL_OK;
bogdanm	0:9b334a45a8ff	446	}
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/**
bogdanm	0:9b334a45a8ff	449	* @brief Disables dynamically FMC_NORSRAM write operation.
bogdanm	0:9b334a45a8ff	450	* @param Device: Pointer to NORSRAM device instance
bogdanm	0:9b334a45a8ff	451	* @param Bank: NORSRAM bank number
bogdanm	0:9b334a45a8ff	452	* @retval HAL status
bogdanm	0:9b334a45a8ff	453	*/
bogdanm	0:9b334a45a8ff	454	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	455	{
bogdanm	0:9b334a45a8ff	456	/* Check the parameters */
bogdanm	0:9b334a45a8ff	457	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	458	assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	/* Disable write operation */
bogdanm	0:9b334a45a8ff	461	Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	return HAL_OK;
bogdanm	0:9b334a45a8ff	464	}
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @}
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/**
bogdanm	0:9b334a45a8ff	471	* @}
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	/** @addtogroup FMC_LL_NAND
bogdanm	0:9b334a45a8ff	475	* @brief NAND Controller functions
bogdanm	0:9b334a45a8ff	476	*
bogdanm	0:9b334a45a8ff	477	@verbatim
bogdanm	0:9b334a45a8ff	478	==============================================================================
bogdanm	0:9b334a45a8ff	479	##### How to use NAND device driver #####
bogdanm	0:9b334a45a8ff	480	==============================================================================
bogdanm	0:9b334a45a8ff	481	[..]
bogdanm	0:9b334a45a8ff	482	This driver contains a set of APIs to interface with the FMC NAND banks in order
bogdanm	0:9b334a45a8ff	483	to run the NAND external devices.
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	(+) FMC NAND bank reset using the function FMC_NAND_DeInit()
bogdanm	0:9b334a45a8ff	486	(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
bogdanm	0:9b334a45a8ff	487	(+) FMC NAND bank common space timing configuration using the function
bogdanm	0:9b334a45a8ff	488	FMC_NAND_CommonSpace_Timing_Init()
bogdanm	0:9b334a45a8ff	489	(+) FMC NAND bank attribute space timing configuration using the function
bogdanm	0:9b334a45a8ff	490	FMC_NAND_AttributeSpace_Timing_Init()
bogdanm	0:9b334a45a8ff	491	(+) FMC NAND bank enable/disable ECC correction feature using the functions
bogdanm	0:9b334a45a8ff	492	FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
bogdanm	0:9b334a45a8ff	493	(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	@endverbatim
bogdanm	0:9b334a45a8ff	496	* @{
bogdanm	0:9b334a45a8ff	497	*/
bogdanm	0:9b334a45a8ff	498
mbed_official	19:112740acecfa	499	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	500	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	501	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	502	*
bogdanm	0:9b334a45a8ff	503	@verbatim
bogdanm	0:9b334a45a8ff	504	==============================================================================
bogdanm	0:9b334a45a8ff	505	##### Initialization and de_initialization functions #####
bogdanm	0:9b334a45a8ff	506	==============================================================================
bogdanm	0:9b334a45a8ff	507	[..]
bogdanm	0:9b334a45a8ff	508	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	509	(+) Initialize and configure the FMC NAND interface
bogdanm	0:9b334a45a8ff	510	(+) De-initialize the FMC NAND interface
bogdanm	0:9b334a45a8ff	511	(+) Configure the FMC clock and associated GPIOs
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	@endverbatim
bogdanm	0:9b334a45a8ff	514	* @{
bogdanm	0:9b334a45a8ff	515	*/
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/**
bogdanm	0:9b334a45a8ff	518	* @brief Initializes the FMC_NAND device according to the specified
bogdanm	0:9b334a45a8ff	519	* control parameters in the FMC_NAND_HandleTypeDef
bogdanm	0:9b334a45a8ff	520	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	521	* @param Init: Pointer to NAND Initialization structure
bogdanm	0:9b334a45a8ff	522	* @retval HAL status
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
bogdanm	0:9b334a45a8ff	525	{
bogdanm	0:9b334a45a8ff	526	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/* Check the parameters */
bogdanm	0:9b334a45a8ff	529	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	530	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
bogdanm	0:9b334a45a8ff	531	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm	0:9b334a45a8ff	532	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm	0:9b334a45a8ff	533	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
bogdanm	0:9b334a45a8ff	534	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
bogdanm	0:9b334a45a8ff	535	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm	0:9b334a45a8ff	536	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	/* Get the NAND bank register value */
bogdanm	0:9b334a45a8ff	539	tmpr = Device->PCR;
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
bogdanm	0:9b334a45a8ff	542	tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN \| FMC_PCR_PBKEN \| FMC_PCR_PTYP \| \
bogdanm	0:9b334a45a8ff	543	FMC_PCR_PWID \| FMC_PCR_ECCEN \| FMC_PCR_TCLR \| \
bogdanm	0:9b334a45a8ff	544	FMC_PCR_TAR \| FMC_PCR_ECCPS));
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/* Set NAND device control parameters */
bogdanm	0:9b334a45a8ff	547	tmpr \|= (uint32_t)(Init->Waitfeature \|\
bogdanm	0:9b334a45a8ff	548	FMC_PCR_MEMORY_TYPE_NAND \|\
bogdanm	0:9b334a45a8ff	549	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	550	Init->EccComputation \|\
bogdanm	0:9b334a45a8ff	551	Init->ECCPageSize \|\
bogdanm	0:9b334a45a8ff	552	((Init->TCLRSetupTime) << 9) \|\
bogdanm	0:9b334a45a8ff	553	((Init->TARSetupTime) << 13));
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/* NAND bank registers configuration */
bogdanm	0:9b334a45a8ff	556	Device->PCR = tmpr;
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	return HAL_OK;
bogdanm	0:9b334a45a8ff	559	}
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/**
bogdanm	0:9b334a45a8ff	562	* @brief Initializes the FMC_NAND Common space Timing according to the specified
bogdanm	0:9b334a45a8ff	563	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	564	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	565	* @param Timing: Pointer to NAND timing structure
bogdanm	0:9b334a45a8ff	566	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	567	* @retval HAL status
bogdanm	0:9b334a45a8ff	568	*/
bogdanm	0:9b334a45a8ff	569	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	570	{
bogdanm	0:9b334a45a8ff	571	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/* Check the parameters */
bogdanm	0:9b334a45a8ff	574	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	575	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	576	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	577	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	578	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	579	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Get the NAND bank 2 register value */
bogdanm	0:9b334a45a8ff	582	tmpr = Device->PMEM;
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
bogdanm	0:9b334a45a8ff	586	tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 \| FMC_PMEM_MEMWAIT2 \| FMC_PMEM_MEMHOLD2 \| \
bogdanm	0:9b334a45a8ff	587	FMC_PMEM_MEMHIZ2));
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Set FMC_NAND device timing parameters */
bogdanm	0:9b334a45a8ff	590	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	591	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	592	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	593	((Timing->HiZSetupTime) << 24)
bogdanm	0:9b334a45a8ff	594	);
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/* NAND bank registers configuration */
bogdanm	0:9b334a45a8ff	597	Device->PMEM = tmpr;
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	return HAL_OK;
bogdanm	0:9b334a45a8ff	600	}
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/**
bogdanm	0:9b334a45a8ff	603	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
bogdanm	0:9b334a45a8ff	604	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	605	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	606	* @param Timing: Pointer to NAND timing structure
bogdanm	0:9b334a45a8ff	607	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	608	* @retval HAL status
bogdanm	0:9b334a45a8ff	609	*/
bogdanm	0:9b334a45a8ff	610	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	611	{
bogdanm	0:9b334a45a8ff	612	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/* Check the parameters */
bogdanm	0:9b334a45a8ff	615	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	616	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	617	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	618	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	619	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	620	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/* Get the NAND bank register value */
bogdanm	0:9b334a45a8ff	623	tmpr = Device->PATT;
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
bogdanm	0:9b334a45a8ff	626	tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 \| FMC_PATT_ATTWAIT2 \| FMC_PATT_ATTHOLD2 \| \
bogdanm	0:9b334a45a8ff	627	FMC_PATT_ATTHIZ2));
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* Set FMC_NAND device timing parameters */
bogdanm	0:9b334a45a8ff	630	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	631	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	632	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	633	((Timing->HiZSetupTime) << 24));
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/* NAND bank registers configuration */
bogdanm	0:9b334a45a8ff	636	Device->PATT = tmpr;
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	return HAL_OK;
bogdanm	0:9b334a45a8ff	639	}
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/**
bogdanm	0:9b334a45a8ff	643	* @brief DeInitializes the FMC_NAND device
bogdanm	0:9b334a45a8ff	644	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	645	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	646	* @retval HAL status
bogdanm	0:9b334a45a8ff	647	*/
bogdanm	0:9b334a45a8ff	648	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	649	{
bogdanm	0:9b334a45a8ff	650	/* Check the parameters */
bogdanm	0:9b334a45a8ff	651	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	652	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	653
bogdanm	0:9b334a45a8ff	654	/* Disable the NAND Bank */
bogdanm	0:9b334a45a8ff	655	__FMC_NAND_DISABLE(Device, Bank);
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/* De-initialize the NAND Bank */
bogdanm	0:9b334a45a8ff	658	/* Set the FMC_NAND_BANK registers to their reset values */
bogdanm	0:9b334a45a8ff	659	Device->PCR = 0x00000018;
bogdanm	0:9b334a45a8ff	660	Device->SR = 0x00000040;
bogdanm	0:9b334a45a8ff	661	Device->PMEM = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	662	Device->PATT = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	return HAL_OK;
bogdanm	0:9b334a45a8ff	665	}
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	/**
bogdanm	0:9b334a45a8ff	668	* @}
bogdanm	0:9b334a45a8ff	669	*/
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	/** @defgroup HAL_FMC_NAND_Group2 Control functions
bogdanm	0:9b334a45a8ff	673	* @brief management functions
bogdanm	0:9b334a45a8ff	674	*
bogdanm	0:9b334a45a8ff	675	@verbatim
bogdanm	0:9b334a45a8ff	676	==============================================================================
bogdanm	0:9b334a45a8ff	677	##### FMC_NAND Control functions #####
bogdanm	0:9b334a45a8ff	678	==============================================================================
bogdanm	0:9b334a45a8ff	679	[..]
bogdanm	0:9b334a45a8ff	680	This subsection provides a set of functions allowing to control dynamically
bogdanm	0:9b334a45a8ff	681	the FMC NAND interface.
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	@endverbatim
bogdanm	0:9b334a45a8ff	684	* @{
bogdanm	0:9b334a45a8ff	685	*/
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/**
bogdanm	0:9b334a45a8ff	689	* @brief Enables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	690	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	691	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	692	* @retval HAL status
bogdanm	0:9b334a45a8ff	693	*/
bogdanm	0:9b334a45a8ff	694	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	695	{
bogdanm	0:9b334a45a8ff	696	/* Check the parameters */
bogdanm	0:9b334a45a8ff	697	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	698	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Enable ECC feature */
bogdanm	0:9b334a45a8ff	701	Device->PCR \|= FMC_PCR_ECCEN;
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	return HAL_OK;
bogdanm	0:9b334a45a8ff	704	}
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/**
bogdanm	0:9b334a45a8ff	708	* @brief Disables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	709	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	710	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	711	* @retval HAL status
bogdanm	0:9b334a45a8ff	712	*/
bogdanm	0:9b334a45a8ff	713	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	714	{
bogdanm	0:9b334a45a8ff	715	/* Check the parameters */
bogdanm	0:9b334a45a8ff	716	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	717	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	/* Disable ECC feature */
bogdanm	0:9b334a45a8ff	720	Device->PCR &= ~FMC_PCR_ECCEN;
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	return HAL_OK;
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/**
bogdanm	0:9b334a45a8ff	726	* @brief Disables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	727	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	728	* @param ECCval: Pointer to ECC value
bogdanm	0:9b334a45a8ff	729	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	730	* @param Timeout: Timeout wait value
bogdanm	0:9b334a45a8ff	731	* @retval HAL status
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	734	{
bogdanm	0:9b334a45a8ff	735	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Check the parameters */
bogdanm	0:9b334a45a8ff	738	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	739	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	740
bogdanm	0:9b334a45a8ff	741	/* Get tick */
bogdanm	0:9b334a45a8ff	742	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/* Wait until FIFO is empty */
bogdanm	0:9b334a45a8ff	745	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
bogdanm	0:9b334a45a8ff	746	{
bogdanm	0:9b334a45a8ff	747	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	748	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	749	{
bogdanm	0:9b334a45a8ff	750	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755	}
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/* Get the ECCR register value */
bogdanm	0:9b334a45a8ff	758	*ECCval = (uint32_t)Device->ECCR;
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	return HAL_OK;
bogdanm	0:9b334a45a8ff	761	}
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/**
bogdanm	0:9b334a45a8ff	764	* @}
bogdanm	0:9b334a45a8ff	765	*/
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	768	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	769	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	770	*
bogdanm	0:9b334a45a8ff	771	@verbatim
bogdanm	0:9b334a45a8ff	772	==============================================================================
bogdanm	0:9b334a45a8ff	773	##### Initialization and de_initialization functions #####
bogdanm	0:9b334a45a8ff	774	==============================================================================
bogdanm	0:9b334a45a8ff	775	[..]
bogdanm	0:9b334a45a8ff	776	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	777	(+) Initialize and configure the FMC NAND interface
bogdanm	0:9b334a45a8ff	778	(+) De-initialize the FMC NAND interface
bogdanm	0:9b334a45a8ff	779	(+) Configure the FMC clock and associated GPIOs
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	@endverbatim
bogdanm	0:9b334a45a8ff	782	* @{
bogdanm	0:9b334a45a8ff	783	*/
bogdanm	0:9b334a45a8ff	784	/**
bogdanm	0:9b334a45a8ff	785	* @brief Initializes the FMC_NAND device according to the specified
bogdanm	0:9b334a45a8ff	786	* control parameters in the FMC_NAND_HandleTypeDef
bogdanm	0:9b334a45a8ff	787	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	788	* @param Init: Pointer to NAND Initialization structure
bogdanm	0:9b334a45a8ff	789	* @retval HAL status
bogdanm	0:9b334a45a8ff	790	*/
bogdanm	0:9b334a45a8ff	791	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	/* Check the parameters */
bogdanm	0:9b334a45a8ff	796	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	797	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
bogdanm	0:9b334a45a8ff	798	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm	0:9b334a45a8ff	799	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm	0:9b334a45a8ff	800	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
bogdanm	0:9b334a45a8ff	801	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
bogdanm	0:9b334a45a8ff	802	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm	0:9b334a45a8ff	803	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	if(Init->NandBank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	/* Get the NAND bank 2 register value */
bogdanm	0:9b334a45a8ff	808	tmpr = Device->PCR2;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810	else
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	/* Get the NAND bank 3 register value */
bogdanm	0:9b334a45a8ff	813	tmpr = Device->PCR3;
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
bogdanm	0:9b334a45a8ff	817	tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN \| FMC_PCR2_PBKEN \| FMC_PCR2_PTYP \| \
bogdanm	0:9b334a45a8ff	818	FMC_PCR2_PWID \| FMC_PCR2_ECCEN \| FMC_PCR2_TCLR \| \
bogdanm	0:9b334a45a8ff	819	FMC_PCR2_TAR \| FMC_PCR2_ECCPS));
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/* Set NAND device control parameters */
bogdanm	0:9b334a45a8ff	822	tmpr \|= (uint32_t)(Init->Waitfeature \|\
bogdanm	0:9b334a45a8ff	823	FMC_PCR_MEMORY_TYPE_NAND \|\
bogdanm	0:9b334a45a8ff	824	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	825	Init->EccComputation \|\
bogdanm	0:9b334a45a8ff	826	Init->ECCPageSize \|\
bogdanm	0:9b334a45a8ff	827	((Init->TCLRSetupTime) << 9) \|\
bogdanm	0:9b334a45a8ff	828	((Init->TARSetupTime) << 13));
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	if(Init->NandBank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	/* NAND bank 2 registers configuration */
bogdanm	0:9b334a45a8ff	833	Device->PCR2 = tmpr;
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	else
bogdanm	0:9b334a45a8ff	836	{
bogdanm	0:9b334a45a8ff	837	/* NAND bank 3 registers configuration */
bogdanm	0:9b334a45a8ff	838	Device->PCR3 = tmpr;
bogdanm	0:9b334a45a8ff	839	}
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	return HAL_OK;
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	}
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/**
bogdanm	0:9b334a45a8ff	846	* @brief Initializes the FMC_NAND Common space Timing according to the specified
bogdanm	0:9b334a45a8ff	847	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	848	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	849	* @param Timing: Pointer to NAND timing structure
bogdanm	0:9b334a45a8ff	850	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	851	* @retval HAL status
bogdanm	0:9b334a45a8ff	852	*/
bogdanm	0:9b334a45a8ff	853	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	854	{
bogdanm	0:9b334a45a8ff	855	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Check the parameters */
bogdanm	0:9b334a45a8ff	858	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	859	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	860	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	861	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	862	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	863	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	866	{
bogdanm	0:9b334a45a8ff	867	/* Get the NAND bank 2 register value */
bogdanm	0:9b334a45a8ff	868	tmpr = Device->PMEM2;
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870	else
bogdanm	0:9b334a45a8ff	871	{
bogdanm	0:9b334a45a8ff	872	/* Get the NAND bank 3 register value */
bogdanm	0:9b334a45a8ff	873	tmpr = Device->PMEM3;
bogdanm	0:9b334a45a8ff	874	}
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
bogdanm	0:9b334a45a8ff	877	tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 \| FMC_PMEM2_MEMWAIT2 \| FMC_PMEM2_MEMHOLD2 \| \
bogdanm	0:9b334a45a8ff	878	FMC_PMEM2_MEMHIZ2));
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	/* Set FMC_NAND device timing parameters */
bogdanm	0:9b334a45a8ff	881	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	882	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	883	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	884	((Timing->HiZSetupTime) << 24)
bogdanm	0:9b334a45a8ff	885	);
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	888	{
bogdanm	0:9b334a45a8ff	889	/* NAND bank 2 registers configuration */
bogdanm	0:9b334a45a8ff	890	Device->PMEM2 = tmpr;
bogdanm	0:9b334a45a8ff	891	}
bogdanm	0:9b334a45a8ff	892	else
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	/* NAND bank 3 registers configuration */
bogdanm	0:9b334a45a8ff	895	Device->PMEM3 = tmpr;
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	return HAL_OK;
bogdanm	0:9b334a45a8ff	899	}
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/**
bogdanm	0:9b334a45a8ff	902	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
bogdanm	0:9b334a45a8ff	903	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	904	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	905	* @param Timing: Pointer to NAND timing structure
bogdanm	0:9b334a45a8ff	906	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	907	* @retval HAL status
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	910	{
bogdanm	0:9b334a45a8ff	911	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Check the parameters */
bogdanm	0:9b334a45a8ff	914	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	915	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	916	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	917	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	918	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	919	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	922	{
bogdanm	0:9b334a45a8ff	923	/* Get the NAND bank 2 register value */
bogdanm	0:9b334a45a8ff	924	tmpr = Device->PATT2;
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926	else
bogdanm	0:9b334a45a8ff	927	{
bogdanm	0:9b334a45a8ff	928	/* Get the NAND bank 3 register value */
bogdanm	0:9b334a45a8ff	929	tmpr = Device->PATT3;
bogdanm	0:9b334a45a8ff	930	}
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
bogdanm	0:9b334a45a8ff	933	tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 \| FMC_PATT2_ATTWAIT2 \| FMC_PATT2_ATTHOLD2 \| \
bogdanm	0:9b334a45a8ff	934	FMC_PATT2_ATTHIZ2));
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* Set FMC_NAND device timing parameters */
bogdanm	0:9b334a45a8ff	937	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	938	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	939	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	940	((Timing->HiZSetupTime) << 24));
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	943	{
bogdanm	0:9b334a45a8ff	944	/* NAND bank 2 registers configuration */
bogdanm	0:9b334a45a8ff	945	Device->PATT2 = tmpr;
bogdanm	0:9b334a45a8ff	946	}
bogdanm	0:9b334a45a8ff	947	else
bogdanm	0:9b334a45a8ff	948	{
bogdanm	0:9b334a45a8ff	949	/* NAND bank 3 registers configuration */
bogdanm	0:9b334a45a8ff	950	Device->PATT3 = tmpr;
bogdanm	0:9b334a45a8ff	951	}
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	return HAL_OK;
bogdanm	0:9b334a45a8ff	954	}
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/**
bogdanm	0:9b334a45a8ff	957	* @brief DeInitializes the FMC_NAND device
bogdanm	0:9b334a45a8ff	958	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	959	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	960	* @retval HAL status
bogdanm	0:9b334a45a8ff	961	*/
bogdanm	0:9b334a45a8ff	962	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	963	{
bogdanm	0:9b334a45a8ff	964	/* Check the parameters */
bogdanm	0:9b334a45a8ff	965	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	966	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/* Disable the NAND Bank */
bogdanm	0:9b334a45a8ff	969	__FMC_NAND_DISABLE(Device, Bank);
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	/* De-initialize the NAND Bank */
bogdanm	0:9b334a45a8ff	972	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	973	{
bogdanm	0:9b334a45a8ff	974	/* Set the FMC_NAND_BANK2 registers to their reset values */
bogdanm	0:9b334a45a8ff	975	Device->PCR2 = 0x00000018;
bogdanm	0:9b334a45a8ff	976	Device->SR2 = 0x00000040;
bogdanm	0:9b334a45a8ff	977	Device->PMEM2 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	978	Device->PATT2 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	979	}
bogdanm	0:9b334a45a8ff	980	/* FMC_Bank3_NAND */
bogdanm	0:9b334a45a8ff	981	else
bogdanm	0:9b334a45a8ff	982	{
bogdanm	0:9b334a45a8ff	983	/* Set the FMC_NAND_BANK3 registers to their reset values */
bogdanm	0:9b334a45a8ff	984	Device->PCR3 = 0x00000018;
bogdanm	0:9b334a45a8ff	985	Device->SR3 = 0x00000040;
bogdanm	0:9b334a45a8ff	986	Device->PMEM3 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	987	Device->PATT3 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	988	}
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	return HAL_OK;
bogdanm	0:9b334a45a8ff	991	}
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/**
bogdanm	0:9b334a45a8ff	994	* @}
bogdanm	0:9b334a45a8ff	995	*/
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
bogdanm	0:9b334a45a8ff	998	* @brief management functions
bogdanm	0:9b334a45a8ff	999	*
bogdanm	0:9b334a45a8ff	1000	@verbatim
bogdanm	0:9b334a45a8ff	1001	==============================================================================
bogdanm	0:9b334a45a8ff	1002	##### FMC_NAND Control functions #####
bogdanm	0:9b334a45a8ff	1003	==============================================================================
bogdanm	0:9b334a45a8ff	1004	[..]
bogdanm	0:9b334a45a8ff	1005	This subsection provides a set of functions allowing to control dynamically
bogdanm	0:9b334a45a8ff	1006	the FMC NAND interface.
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	@endverbatim
bogdanm	0:9b334a45a8ff	1009	* @{
bogdanm	0:9b334a45a8ff	1010	*/
bogdanm	0:9b334a45a8ff	1011	/**
bogdanm	0:9b334a45a8ff	1012	* @brief Enables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	1013	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	1014	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	1015	* @retval HAL status
bogdanm	0:9b334a45a8ff	1016	*/
bogdanm	0:9b334a45a8ff	1017	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1018	{
bogdanm	0:9b334a45a8ff	1019	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1020	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1021	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Enable ECC feature */
bogdanm	0:9b334a45a8ff	1024	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	1025	{
bogdanm	0:9b334a45a8ff	1026	Device->PCR2 \|= FMC_PCR2_ECCEN;
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028	else
bogdanm	0:9b334a45a8ff	1029	{
bogdanm	0:9b334a45a8ff	1030	Device->PCR3 \|= FMC_PCR3_ECCEN;
bogdanm	0:9b334a45a8ff	1031	}
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	return HAL_OK;
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	/**
bogdanm	0:9b334a45a8ff	1037	* @brief Disables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	1038	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	1039	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	1040	* @retval HAL status
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1045	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1046	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* Disable ECC feature */
bogdanm	0:9b334a45a8ff	1049	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	1050	{
bogdanm	0:9b334a45a8ff	1051	Device->PCR2 &= ~FMC_PCR2_ECCEN;
bogdanm	0:9b334a45a8ff	1052	}
bogdanm	0:9b334a45a8ff	1053	else
bogdanm	0:9b334a45a8ff	1054	{
bogdanm	0:9b334a45a8ff	1055	Device->PCR3 &= ~FMC_PCR3_ECCEN;
bogdanm	0:9b334a45a8ff	1056	}
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	return HAL_OK;
bogdanm	0:9b334a45a8ff	1059	}
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/**
bogdanm	0:9b334a45a8ff	1062	* @brief Disables dynamically FMC_NAND ECC feature.
bogdanm	0:9b334a45a8ff	1063	* @param Device: Pointer to NAND device instance
bogdanm	0:9b334a45a8ff	1064	* @param ECCval: Pointer to ECC value
bogdanm	0:9b334a45a8ff	1065	* @param Bank: NAND bank number
bogdanm	0:9b334a45a8ff	1066	* @param Timeout: Timeout wait value
bogdanm	0:9b334a45a8ff	1067	* @retval HAL status
bogdanm	0:9b334a45a8ff	1068	*/
bogdanm	0:9b334a45a8ff	1069	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1070	{
bogdanm	0:9b334a45a8ff	1071	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1074	assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1075	assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/* Get tick */
bogdanm	0:9b334a45a8ff	1078	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/* Wait until FIFO is empty */
bogdanm	0:9b334a45a8ff	1081	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
bogdanm	0:9b334a45a8ff	1082	{
bogdanm	0:9b334a45a8ff	1083	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1084	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1085	{
bogdanm	0:9b334a45a8ff	1086	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1087	{
bogdanm	0:9b334a45a8ff	1088	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1089	}
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091	}
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	if(Bank == FMC_NAND_BANK2)
bogdanm	0:9b334a45a8ff	1094	{
bogdanm	0:9b334a45a8ff	1095	/* Get the ECCR2 register value */
bogdanm	0:9b334a45a8ff	1096	*ECCval = (uint32_t)Device->ECCR2;
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098	else
bogdanm	0:9b334a45a8ff	1099	{
bogdanm	0:9b334a45a8ff	1100	/* Get the ECCR3 register value */
bogdanm	0:9b334a45a8ff	1101	*ECCval = (uint32_t)Device->ECCR3;
bogdanm	0:9b334a45a8ff	1102	}
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	return HAL_OK;
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/**
bogdanm	0:9b334a45a8ff	1108	* @}
bogdanm	0:9b334a45a8ff	1109	*/
bogdanm	0:9b334a45a8ff	1110
mbed_official	19:112740acecfa	1111	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	0:9b334a45a8ff	1112	/**
bogdanm	0:9b334a45a8ff	1113	* @}
bogdanm	0:9b334a45a8ff	1114	*/
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1117	/** @addtogroup FMC_LL_PCCARD
bogdanm	0:9b334a45a8ff	1118	* @brief PCCARD Controller functions
bogdanm	0:9b334a45a8ff	1119	*
bogdanm	0:9b334a45a8ff	1120	@verbatim
bogdanm	0:9b334a45a8ff	1121	==============================================================================
bogdanm	0:9b334a45a8ff	1122	##### How to use PCCARD device driver #####
bogdanm	0:9b334a45a8ff	1123	==============================================================================
bogdanm	0:9b334a45a8ff	1124	[..]
bogdanm	0:9b334a45a8ff	1125	This driver contains a set of APIs to interface with the FMC PCCARD bank in order
bogdanm	0:9b334a45a8ff	1126	to run the PCCARD/compact flash external devices.
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	(+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
bogdanm	0:9b334a45a8ff	1129	(+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
bogdanm	0:9b334a45a8ff	1130	(+) FMC PCCARD bank common space timing configuration using the function
bogdanm	0:9b334a45a8ff	1131	FMC_PCCARD_CommonSpace_Timing_Init()
bogdanm	0:9b334a45a8ff	1132	(+) FMC PCCARD bank attribute space timing configuration using the function
bogdanm	0:9b334a45a8ff	1133	FMC_PCCARD_AttributeSpace_Timing_Init()
bogdanm	0:9b334a45a8ff	1134	(+) FMC PCCARD bank IO space timing configuration using the function
bogdanm	0:9b334a45a8ff	1135	FMC_PCCARD_IOSpace_Timing_Init()
bogdanm	0:9b334a45a8ff	1136	@endverbatim
bogdanm	0:9b334a45a8ff	1137	* @{
bogdanm	0:9b334a45a8ff	1138	*/
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
bogdanm	0:9b334a45a8ff	1141	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	1142	*
bogdanm	0:9b334a45a8ff	1143	@verbatim
bogdanm	0:9b334a45a8ff	1144	==============================================================================
bogdanm	0:9b334a45a8ff	1145	##### Initialization and de_initialization functions #####
bogdanm	0:9b334a45a8ff	1146	==============================================================================
bogdanm	0:9b334a45a8ff	1147	[..]
bogdanm	0:9b334a45a8ff	1148	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1149	(+) Initialize and configure the FMC PCCARD interface
bogdanm	0:9b334a45a8ff	1150	(+) De-initialize the FMC PCCARD interface
bogdanm	0:9b334a45a8ff	1151	(+) Configure the FMC clock and associated GPIOs
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	@endverbatim
bogdanm	0:9b334a45a8ff	1154	* @{
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/**
bogdanm	0:9b334a45a8ff	1158	* @brief Initializes the FMC_PCCARD device according to the specified
bogdanm	0:9b334a45a8ff	1159	* control parameters in the FMC_PCCARD_HandleTypeDef
bogdanm	0:9b334a45a8ff	1160	* @param Device: Pointer to PCCARD device instance
bogdanm	0:9b334a45a8ff	1161	* @param Init: Pointer to PCCARD Initialization structure
bogdanm	0:9b334a45a8ff	1162	* @retval HAL status
bogdanm	0:9b334a45a8ff	1163	*/
bogdanm	0:9b334a45a8ff	1164	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init)
bogdanm	0:9b334a45a8ff	1165	{
bogdanm	0:9b334a45a8ff	1166	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1169	assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1170	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm	0:9b334a45a8ff	1171	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm	0:9b334a45a8ff	1172	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/* Get PCCARD control register value */
bogdanm	0:9b334a45a8ff	1175	tmpr = Device->PCR4;
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	/* Clear TAR, TCLR, PWAITEN and PWID bits */
bogdanm	0:9b334a45a8ff	1178	tmpr &= ((uint32_t)~(FMC_PCR4_TAR \| FMC_PCR4_TCLR \| FMC_PCR4_PWAITEN \| \
bogdanm	0:9b334a45a8ff	1179	FMC_PCR4_PWID));
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	/* Set FMC_PCCARD device control parameters */
bogdanm	0:9b334a45a8ff	1182	tmpr \|= (uint32_t)(Init->Waitfeature \|\
bogdanm	0:9b334a45a8ff	1183	FMC_NAND_PCC_MEM_BUS_WIDTH_16 \|\
bogdanm	0:9b334a45a8ff	1184	(Init->TCLRSetupTime << 9) \|\
bogdanm	0:9b334a45a8ff	1185	(Init->TARSetupTime << 13));
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	Device->PCR4 = tmpr;
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	return HAL_OK;
bogdanm	0:9b334a45a8ff	1190	}
bogdanm	0:9b334a45a8ff	1191
bogdanm	0:9b334a45a8ff	1192	/**
bogdanm	0:9b334a45a8ff	1193	* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
bogdanm	0:9b334a45a8ff	1194	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	1195	* @param Device: Pointer to PCCARD device instance
bogdanm	0:9b334a45a8ff	1196	* @param Timing: Pointer to PCCARD timing structure
bogdanm	0:9b334a45a8ff	1197	* @retval HAL status
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
bogdanm	0:9b334a45a8ff	1200	{
bogdanm	0:9b334a45a8ff	1201	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1204	assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1205	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	1206	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	1207	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	1208	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* Get PCCARD common space timing register value */
bogdanm	0:9b334a45a8ff	1211	tmpr = Device->PMEM4;
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
bogdanm	0:9b334a45a8ff	1214	tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 \| FMC_PMEM4_MEMWAIT4 \| FMC_PMEM4_MEMHOLD4 \| \
bogdanm	0:9b334a45a8ff	1215	FMC_PMEM4_MEMHIZ4));
bogdanm	0:9b334a45a8ff	1216	/* Set PCCARD timing parameters */
bogdanm	0:9b334a45a8ff	1217	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	1218	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	1219	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	1220	((Timing->HiZSetupTime) << 24));
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	Device->PMEM4 = tmpr;
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	return HAL_OK;
bogdanm	0:9b334a45a8ff	1225	}
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/**
bogdanm	0:9b334a45a8ff	1228	* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
bogdanm	0:9b334a45a8ff	1229	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	1230	* @param Device: Pointer to PCCARD device instance
bogdanm	0:9b334a45a8ff	1231	* @param Timing: Pointer to PCCARD timing structure
bogdanm	0:9b334a45a8ff	1232	* @retval HAL status
bogdanm	0:9b334a45a8ff	1233	*/
bogdanm	0:9b334a45a8ff	1234	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
bogdanm	0:9b334a45a8ff	1235	{
bogdanm	0:9b334a45a8ff	1236	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1239	assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1240	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	1241	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	1242	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	1243	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/* Get PCCARD timing parameters */
bogdanm	0:9b334a45a8ff	1246	tmpr = Device->PATT4;
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
bogdanm	0:9b334a45a8ff	1249	tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 \| FMC_PATT4_ATTWAIT4 \| FMC_PATT4_ATTHOLD4 \| \
bogdanm	0:9b334a45a8ff	1250	FMC_PATT4_ATTHIZ4));
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Set PCCARD timing parameters */
bogdanm	0:9b334a45a8ff	1253	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	1254	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	1255	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	1256	((Timing->HiZSetupTime) << 24));
bogdanm	0:9b334a45a8ff	1257	Device->PATT4 = tmpr;
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	return HAL_OK;
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/**
bogdanm	0:9b334a45a8ff	1263	* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
bogdanm	0:9b334a45a8ff	1264	* parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm	0:9b334a45a8ff	1265	* @param Device: Pointer to PCCARD device instance
bogdanm	0:9b334a45a8ff	1266	* @param Timing: Pointer to PCCARD timing structure
bogdanm	0:9b334a45a8ff	1267	* @retval HAL status
bogdanm	0:9b334a45a8ff	1268	*/
bogdanm	0:9b334a45a8ff	1269	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
bogdanm	0:9b334a45a8ff	1270	{
bogdanm	0:9b334a45a8ff	1271	uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1274	assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1275	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm	0:9b334a45a8ff	1276	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm	0:9b334a45a8ff	1277	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm	0:9b334a45a8ff	1278	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Get FMC_PCCARD device timing parameters */
bogdanm	0:9b334a45a8ff	1281	tmpr = Device->PIO4;
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
bogdanm	0:9b334a45a8ff	1284	tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 \| FMC_PIO4_IOWAIT4 \| FMC_PIO4_IOHOLD4 \| \
bogdanm	0:9b334a45a8ff	1285	FMC_PIO4_IOHIZ4));
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Set FMC_PCCARD device timing parameters */
bogdanm	0:9b334a45a8ff	1288	tmpr \|= (uint32_t)(Timing->SetupTime \|\
bogdanm	0:9b334a45a8ff	1289	((Timing->WaitSetupTime) << 8) \|\
bogdanm	0:9b334a45a8ff	1290	((Timing->HoldSetupTime) << 16) \|\
bogdanm	0:9b334a45a8ff	1291	((Timing->HiZSetupTime) << 24));
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	Device->PIO4 = tmpr;
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	return HAL_OK;
bogdanm	0:9b334a45a8ff	1296	}
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/**
bogdanm	0:9b334a45a8ff	1299	* @brief DeInitializes the FMC_PCCARD device
bogdanm	0:9b334a45a8ff	1300	* @param Device: Pointer to PCCARD device instance
bogdanm	0:9b334a45a8ff	1301	* @retval HAL status
bogdanm	0:9b334a45a8ff	1302	*/
bogdanm	0:9b334a45a8ff	1303	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
bogdanm	0:9b334a45a8ff	1304	{
bogdanm	0:9b334a45a8ff	1305	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1306	assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Disable the FMC_PCCARD device */
bogdanm	0:9b334a45a8ff	1309	__FMC_PCCARD_DISABLE(Device);
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/* De-initialize the FMC_PCCARD device */
bogdanm	0:9b334a45a8ff	1312	Device->PCR4 = 0x00000018;
bogdanm	0:9b334a45a8ff	1313	Device->SR4 = 0x00000000;
bogdanm	0:9b334a45a8ff	1314	Device->PMEM4 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	1315	Device->PATT4 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	1316	Device->PIO4 = 0xFCFCFCFC;
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	return HAL_OK;
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/**
bogdanm	0:9b334a45a8ff	1322	* @}
bogdanm	0:9b334a45a8ff	1323	*/
bogdanm	0:9b334a45a8ff	1324	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/** @addtogroup FMC_LL_SDRAM
bogdanm	0:9b334a45a8ff	1328	* @brief SDRAM Controller functions
bogdanm	0:9b334a45a8ff	1329	*
bogdanm	0:9b334a45a8ff	1330	@verbatim
bogdanm	0:9b334a45a8ff	1331	==============================================================================
bogdanm	0:9b334a45a8ff	1332	##### How to use SDRAM device driver #####
bogdanm	0:9b334a45a8ff	1333	==============================================================================
bogdanm	0:9b334a45a8ff	1334	[..]
bogdanm	0:9b334a45a8ff	1335	This driver contains a set of APIs to interface with the FMC SDRAM banks in order
bogdanm	0:9b334a45a8ff	1336	to run the SDRAM external devices.
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	(+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
bogdanm	0:9b334a45a8ff	1339	(+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
bogdanm	0:9b334a45a8ff	1340	(+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
bogdanm	0:9b334a45a8ff	1341	(+) FMC SDRAM bank enable/disable write operation using the functions
bogdanm	0:9b334a45a8ff	1342	FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
bogdanm	0:9b334a45a8ff	1343	(+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	@endverbatim
bogdanm	0:9b334a45a8ff	1346	* @{
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
bogdanm	0:9b334a45a8ff	1350	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	1351	*
bogdanm	0:9b334a45a8ff	1352	@verbatim
bogdanm	0:9b334a45a8ff	1353	==============================================================================
bogdanm	0:9b334a45a8ff	1354	##### Initialization and de_initialization functions #####
bogdanm	0:9b334a45a8ff	1355	==============================================================================
bogdanm	0:9b334a45a8ff	1356	[..]
bogdanm	0:9b334a45a8ff	1357	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1358	(+) Initialize and configure the FMC SDRAM interface
bogdanm	0:9b334a45a8ff	1359	(+) De-initialize the FMC SDRAM interface
bogdanm	0:9b334a45a8ff	1360	(+) Configure the FMC clock and associated GPIOs
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	@endverbatim
bogdanm	0:9b334a45a8ff	1363	* @{
bogdanm	0:9b334a45a8ff	1364	*/
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/**
bogdanm	0:9b334a45a8ff	1367	* @brief Initializes the FMC_SDRAM device according to the specified
bogdanm	0:9b334a45a8ff	1368	* control parameters in the FMC_SDRAM_InitTypeDef
bogdanm	0:9b334a45a8ff	1369	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1370	* @param Init: Pointer to SDRAM Initialization structure
bogdanm	0:9b334a45a8ff	1371	* @retval HAL status
bogdanm	0:9b334a45a8ff	1372	*/
bogdanm	0:9b334a45a8ff	1373	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init)
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	uint32_t tmpr1 = 0;
bogdanm	0:9b334a45a8ff	1376	uint32_t tmpr2 = 0;
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1379	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1380	assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
bogdanm	0:9b334a45a8ff	1381	assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
bogdanm	0:9b334a45a8ff	1382	assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
bogdanm	0:9b334a45a8ff	1383	assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm	0:9b334a45a8ff	1384	assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
bogdanm	0:9b334a45a8ff	1385	assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
bogdanm	0:9b334a45a8ff	1386	assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
bogdanm	0:9b334a45a8ff	1387	assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
bogdanm	0:9b334a45a8ff	1388	assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
bogdanm	0:9b334a45a8ff	1389	assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
bogdanm	0:9b334a45a8ff	1390
bogdanm	0:9b334a45a8ff	1391	/* Set SDRAM bank configuration parameters */
bogdanm	0:9b334a45a8ff	1392	if (Init->SDBank != FMC_SDRAM_BANK2)
bogdanm	0:9b334a45a8ff	1393	{
bogdanm	0:9b334a45a8ff	1394	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
bogdanm	0:9b334a45a8ff	1397	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
bogdanm	0:9b334a45a8ff	1398	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
bogdanm	0:9b334a45a8ff	1399	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	tmpr1 \|= (uint32_t)(Init->ColumnBitsNumber \|\
bogdanm	0:9b334a45a8ff	1403	Init->RowBitsNumber \|\
bogdanm	0:9b334a45a8ff	1404	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	1405	Init->InternalBankNumber \|\
bogdanm	0:9b334a45a8ff	1406	Init->CASLatency \|\
bogdanm	0:9b334a45a8ff	1407	Init->WriteProtection \|\
bogdanm	0:9b334a45a8ff	1408	Init->SDClockPeriod \|\
bogdanm	0:9b334a45a8ff	1409	Init->ReadBurst \|\
bogdanm	0:9b334a45a8ff	1410	Init->ReadPipeDelay
bogdanm	0:9b334a45a8ff	1411	);
bogdanm	0:9b334a45a8ff	1412	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414	else /* FMC_Bank2_SDRAM */
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
bogdanm	0:9b334a45a8ff	1419	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
bogdanm	0:9b334a45a8ff	1420	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
bogdanm	0:9b334a45a8ff	1421	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	tmpr1 \|= (uint32_t)(Init->SDClockPeriod \|\
bogdanm	0:9b334a45a8ff	1424	Init->ReadBurst \|\
bogdanm	0:9b334a45a8ff	1425	Init->ReadPipeDelay);
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
bogdanm	0:9b334a45a8ff	1430	tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
bogdanm	0:9b334a45a8ff	1431	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
bogdanm	0:9b334a45a8ff	1432	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	tmpr2 \|= (uint32_t)(Init->ColumnBitsNumber \|\
bogdanm	0:9b334a45a8ff	1435	Init->RowBitsNumber \|\
bogdanm	0:9b334a45a8ff	1436	Init->MemoryDataWidth \|\
bogdanm	0:9b334a45a8ff	1437	Init->InternalBankNumber \|\
bogdanm	0:9b334a45a8ff	1438	Init->CASLatency \|\
bogdanm	0:9b334a45a8ff	1439	Init->WriteProtection);
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
bogdanm	0:9b334a45a8ff	1442	Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
bogdanm	0:9b334a45a8ff	1443	}
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	return HAL_OK;
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	/**
bogdanm	0:9b334a45a8ff	1449	* @brief Initializes the FMC_SDRAM device timing according to the specified
bogdanm	0:9b334a45a8ff	1450	* parameters in the FMC_SDRAM_TimingTypeDef
bogdanm	0:9b334a45a8ff	1451	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1452	* @param Timing: Pointer to SDRAM Timing structure
bogdanm	0:9b334a45a8ff	1453	* @param Bank: SDRAM bank number
bogdanm	0:9b334a45a8ff	1454	* @retval HAL status
bogdanm	0:9b334a45a8ff	1455	*/
bogdanm	0:9b334a45a8ff	1456	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1457	{
bogdanm	0:9b334a45a8ff	1458	uint32_t tmpr1 = 0;
bogdanm	0:9b334a45a8ff	1459	uint32_t tmpr2 = 0;
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1462	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1463	assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
bogdanm	0:9b334a45a8ff	1464	assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
bogdanm	0:9b334a45a8ff	1465	assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
bogdanm	0:9b334a45a8ff	1466	assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
bogdanm	0:9b334a45a8ff	1467	assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
bogdanm	0:9b334a45a8ff	1468	assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
bogdanm	0:9b334a45a8ff	1469	assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
bogdanm	0:9b334a45a8ff	1470	assert_param(IS_FMC_SDRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	/* Set SDRAM device timing parameters */
bogdanm	0:9b334a45a8ff	1473	if (Bank != FMC_SDRAM_BANK2)
bogdanm	0:9b334a45a8ff	1474	{
bogdanm	0:9b334a45a8ff	1475	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
bogdanm	0:9b334a45a8ff	1478	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
bogdanm	0:9b334a45a8ff	1479	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
bogdanm	0:9b334a45a8ff	1480	FMC_SDTR1_TRCD));
bogdanm	0:9b334a45a8ff	1481
bogdanm	0:9b334a45a8ff	1482	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1) \|\
bogdanm	0:9b334a45a8ff	1483	(((Timing->ExitSelfRefreshDelay)-1) << 4) \|\
bogdanm	0:9b334a45a8ff	1484	(((Timing->SelfRefreshTime)-1) << 8) \|\
bogdanm	0:9b334a45a8ff	1485	(((Timing->RowCycleDelay)-1) << 12) \|\
bogdanm	0:9b334a45a8ff	1486	(((Timing->WriteRecoveryTime)-1) <<16) \|\
bogdanm	0:9b334a45a8ff	1487	(((Timing->RPDelay)-1) << 20) \|\
bogdanm	0:9b334a45a8ff	1488	(((Timing->RCDDelay)-1) << 24));
bogdanm	0:9b334a45a8ff	1489	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
bogdanm	0:9b334a45a8ff	1490	}
bogdanm	0:9b334a45a8ff	1491	else /* FMC_Bank2_SDRAM */
bogdanm	0:9b334a45a8ff	1492	{
bogdanm	0:9b334a45a8ff	1493	tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
bogdanm	0:9b334a45a8ff	1496	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
bogdanm	0:9b334a45a8ff	1497	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
bogdanm	0:9b334a45a8ff	1498	FMC_SDTR1_TRCD));
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1) \|\
bogdanm	0:9b334a45a8ff	1501	(((Timing->ExitSelfRefreshDelay)-1) << 4) \|\
bogdanm	0:9b334a45a8ff	1502	(((Timing->SelfRefreshTime)-1) << 8) \|\
bogdanm	0:9b334a45a8ff	1503	(((Timing->WriteRecoveryTime)-1) <<16) \|\
bogdanm	0:9b334a45a8ff	1504	(((Timing->RCDDelay)-1) << 24));
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
bogdanm	0:9b334a45a8ff	1509	tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
bogdanm	0:9b334a45a8ff	1510	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
bogdanm	0:9b334a45a8ff	1511	FMC_SDTR1_TRCD));
bogdanm	0:9b334a45a8ff	1512	tmpr2 \|= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) \|\
bogdanm	0:9b334a45a8ff	1513	(((Timing->RPDelay)-1) << 20));
bogdanm	0:9b334a45a8ff	1514
bogdanm	0:9b334a45a8ff	1515	Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
bogdanm	0:9b334a45a8ff	1516	Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
bogdanm	0:9b334a45a8ff	1517	}
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	return HAL_OK;
bogdanm	0:9b334a45a8ff	1520	}
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/**
bogdanm	0:9b334a45a8ff	1523	* @brief DeInitializes the FMC_SDRAM peripheral
bogdanm	0:9b334a45a8ff	1524	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1525	* @retval HAL status
bogdanm	0:9b334a45a8ff	1526	*/
bogdanm	0:9b334a45a8ff	1527	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1528	{
bogdanm	0:9b334a45a8ff	1529	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1530	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1531	assert_param(IS_FMC_SDRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/* De-initialize the SDRAM device */
bogdanm	0:9b334a45a8ff	1534	Device->SDCR[Bank] = 0x000002D0;
bogdanm	0:9b334a45a8ff	1535	Device->SDTR[Bank] = 0x0FFFFFFF;
bogdanm	0:9b334a45a8ff	1536	Device->SDCMR = 0x00000000;
bogdanm	0:9b334a45a8ff	1537	Device->SDRTR = 0x00000000;
bogdanm	0:9b334a45a8ff	1538	Device->SDSR = 0x00000000;
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	return HAL_OK;
bogdanm	0:9b334a45a8ff	1541	}
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	/**
bogdanm	0:9b334a45a8ff	1544	* @}
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
bogdanm	0:9b334a45a8ff	1548	* @brief management functions
bogdanm	0:9b334a45a8ff	1549	*
bogdanm	0:9b334a45a8ff	1550	@verbatim
bogdanm	0:9b334a45a8ff	1551	==============================================================================
bogdanm	0:9b334a45a8ff	1552	##### FMC_SDRAM Control functions #####
bogdanm	0:9b334a45a8ff	1553	==============================================================================
bogdanm	0:9b334a45a8ff	1554	[..]
bogdanm	0:9b334a45a8ff	1555	This subsection provides a set of functions allowing to control dynamically
bogdanm	0:9b334a45a8ff	1556	the FMC SDRAM interface.
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	@endverbatim
bogdanm	0:9b334a45a8ff	1559	* @{
bogdanm	0:9b334a45a8ff	1560	*/
bogdanm	0:9b334a45a8ff	1561	/**
bogdanm	0:9b334a45a8ff	1562	* @brief Enables dynamically FMC_SDRAM write protection.
bogdanm	0:9b334a45a8ff	1563	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1564	* @param Bank: SDRAM bank number
bogdanm	0:9b334a45a8ff	1565	* @retval HAL status
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1568	{
bogdanm	0:9b334a45a8ff	1569	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1570	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1571	assert_param(IS_FMC_SDRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/* Enable write protection */
bogdanm	0:9b334a45a8ff	1574	Device->SDCR[Bank] \|= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
bogdanm	0:9b334a45a8ff	1575
bogdanm	0:9b334a45a8ff	1576	return HAL_OK;
bogdanm	0:9b334a45a8ff	1577	}
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	/**
bogdanm	0:9b334a45a8ff	1580	* @brief Disables dynamically FMC_SDRAM write protection.
bogdanm	0:9b334a45a8ff	1581	* @param hsdram: FMC_SDRAM handle
bogdanm	0:9b334a45a8ff	1582	* @retval HAL status
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1585	{
bogdanm	0:9b334a45a8ff	1586	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1587	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1588	assert_param(IS_FMC_SDRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/* Disable write protection */
bogdanm	0:9b334a45a8ff	1591	Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
bogdanm	0:9b334a45a8ff	1592
bogdanm	0:9b334a45a8ff	1593	return HAL_OK;
bogdanm	0:9b334a45a8ff	1594	}
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/**
bogdanm	0:9b334a45a8ff	1597	* @brief Send Command to the FMC SDRAM bank
bogdanm	0:9b334a45a8ff	1598	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1599	* @param Command: Pointer to SDRAM command structure
bogdanm	0:9b334a45a8ff	1600	* @param Timing: Pointer to SDRAM Timing structure
bogdanm	0:9b334a45a8ff	1601	* @param Timeout: Timeout wait value
bogdanm	0:9b334a45a8ff	1602	* @retval HAL state
bogdanm	0:9b334a45a8ff	1603	*/
bogdanm	0:9b334a45a8ff	1604	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1605	{
bogdanm	0:9b334a45a8ff	1606	__IO uint32_t tmpr = 0;
bogdanm	0:9b334a45a8ff	1607	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1610	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1611	assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
bogdanm	0:9b334a45a8ff	1612	assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
bogdanm	0:9b334a45a8ff	1613	assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
bogdanm	0:9b334a45a8ff	1614	assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/* Set command register */
bogdanm	0:9b334a45a8ff	1617	tmpr = (uint32_t)((Command->CommandMode) \|\
bogdanm	0:9b334a45a8ff	1618	(Command->CommandTarget) \|\
bogdanm	0:9b334a45a8ff	1619	(((Command->AutoRefreshNumber)-1) << 5) \|\
bogdanm	0:9b334a45a8ff	1620	((Command->ModeRegisterDefinition) << 9)
bogdanm	0:9b334a45a8ff	1621	);
bogdanm	0:9b334a45a8ff	1622
bogdanm	0:9b334a45a8ff	1623	Device->SDCMR = tmpr;
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	/* Get tick */
bogdanm	0:9b334a45a8ff	1626	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/* Wait until command is send */
bogdanm	0:9b334a45a8ff	1629	while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
bogdanm	0:9b334a45a8ff	1630	{
bogdanm	0:9b334a45a8ff	1631	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1632	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1633	{
bogdanm	0:9b334a45a8ff	1634	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1635	{
bogdanm	0:9b334a45a8ff	1636	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1637	}
mbed_official	19:112740acecfa	1638	}
bogdanm	0:9b334a45a8ff	1639	}
mbed_official	19:112740acecfa	1640
mbed_official	19:112740acecfa	1641	return HAL_OK;
bogdanm	0:9b334a45a8ff	1642	}
bogdanm	0:9b334a45a8ff	1643
bogdanm	0:9b334a45a8ff	1644	/**
bogdanm	0:9b334a45a8ff	1645	* @brief Program the SDRAM Memory Refresh rate.
bogdanm	0:9b334a45a8ff	1646	* @param Device: Pointer to SDRAM device instance
mbed_official	19:112740acecfa	1647	* @param RefreshRate: The SDRAM refresh rate value.
bogdanm	0:9b334a45a8ff	1648	* @retval HAL state
bogdanm	0:9b334a45a8ff	1649	*/
bogdanm	0:9b334a45a8ff	1650	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
bogdanm	0:9b334a45a8ff	1651	{
bogdanm	0:9b334a45a8ff	1652	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1653	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1654	assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/* Set the refresh rate in command register */
bogdanm	0:9b334a45a8ff	1657	Device->SDRTR \|= (RefreshRate<<1);
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	return HAL_OK;
bogdanm	0:9b334a45a8ff	1660	}
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/**
bogdanm	0:9b334a45a8ff	1663	* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
bogdanm	0:9b334a45a8ff	1664	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1665	* @param AutoRefreshNumber: Specifies the auto Refresh number.
bogdanm	0:9b334a45a8ff	1666	* @retval None
bogdanm	0:9b334a45a8ff	1667	*/
bogdanm	0:9b334a45a8ff	1668	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
bogdanm	0:9b334a45a8ff	1669	{
bogdanm	0:9b334a45a8ff	1670	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1671	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1672	assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674	/* Set the Auto-refresh number in command register */
bogdanm	0:9b334a45a8ff	1675	Device->SDCMR \|= (AutoRefreshNumber << 5);
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	return HAL_OK;
bogdanm	0:9b334a45a8ff	1678	}
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	/**
bogdanm	0:9b334a45a8ff	1681	* @brief Returns the indicated FMC SDRAM bank mode status.
bogdanm	0:9b334a45a8ff	1682	* @param Device: Pointer to SDRAM device instance
bogdanm	0:9b334a45a8ff	1683	* @param Bank: Defines the FMC SDRAM bank. This parameter can be
bogdanm	0:9b334a45a8ff	1684	* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
bogdanm	0:9b334a45a8ff	1685	* @retval The FMC SDRAM bank mode status, could be on of the following values:
bogdanm	0:9b334a45a8ff	1686	* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
bogdanm	0:9b334a45a8ff	1687	* FMC_SDRAM_POWER_DOWN_MODE.
bogdanm	0:9b334a45a8ff	1688	*/
bogdanm	0:9b334a45a8ff	1689	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
bogdanm	0:9b334a45a8ff	1690	{
bogdanm	0:9b334a45a8ff	1691	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1694	assert_param(IS_FMC_SDRAM_DEVICE(Device));
bogdanm	0:9b334a45a8ff	1695	assert_param(IS_FMC_SDRAM_BANK(Bank));
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	/* Get the corresponding bank mode */
bogdanm	0:9b334a45a8ff	1698	if(Bank == FMC_SDRAM_BANK1)
bogdanm	0:9b334a45a8ff	1699	{
bogdanm	0:9b334a45a8ff	1700	tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702	else
bogdanm	0:9b334a45a8ff	1703	{
bogdanm	0:9b334a45a8ff	1704	tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
bogdanm	0:9b334a45a8ff	1705	}
bogdanm	0:9b334a45a8ff	1706
bogdanm	0:9b334a45a8ff	1707	/* Return the mode status */
bogdanm	0:9b334a45a8ff	1708	return tmpreg;
bogdanm	0:9b334a45a8ff	1709	}
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	/**
bogdanm	0:9b334a45a8ff	1712	* @}
bogdanm	0:9b334a45a8ff	1713	*/
bogdanm	0:9b334a45a8ff	1714
bogdanm	0:9b334a45a8ff	1715	/**
bogdanm	0:9b334a45a8ff	1716	* @}
bogdanm	0:9b334a45a8ff	1717	*/
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	/**
bogdanm	0:9b334a45a8ff	1720	* @}
bogdanm	0:9b334a45a8ff	1721	*/
mbed_official	19:112740acecfa	1722	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	1723	#endif /* HAL_SRAM_MODULE_ENABLED \|\| HAL_NOR_MODULE_ENABLED \|\| HAL_NAND_MODULE_ENABLED \|\| HAL_PCCARD_MODULE_ENABLED \|\| HAL_SDRAM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	/**
bogdanm	0:9b334a45a8ff	1726	* @}
bogdanm	0:9b334a45a8ff	1727	*/
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729	/**
bogdanm	0:9b334a45a8ff	1730	* @}
bogdanm	0:9b334a45a8ff	1731	*/
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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