mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F4xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F4xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	71	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	74	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	78	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	0:9b334a45a8ff	81	reaches zero, an update event is generated and counting restarts
bogdanm	0:9b334a45a8ff	82	from the RCR value (N).
bogdanm	0:9b334a45a8ff	83	This means in PWM mode that (N+1) corresponds to:
bogdanm	0:9b334a45a8ff	84	- the number of PWM periods in edge-aligned mode
bogdanm	0:9b334a45a8ff	85	- the number of half PWM period in center-aligned mode
bogdanm	0:9b334a45a8ff	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	0:9b334a45a8ff	87	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	88	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/**
bogdanm	0:9b334a45a8ff	91	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	92	*/
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	typedef struct
bogdanm	0:9b334a45a8ff	95	{
bogdanm	0:9b334a45a8ff	96	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	107	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	110	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	116	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	120	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	121	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	/**
bogdanm	0:9b334a45a8ff	124	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	125	*/
bogdanm	0:9b334a45a8ff	126	typedef struct
bogdanm	0:9b334a45a8ff	127	{
bogdanm	0:9b334a45a8ff	128	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	132	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	139	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	143	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	147	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	157	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	/**
bogdanm	0:9b334a45a8ff	161	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	162	*/
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	typedef struct
bogdanm	0:9b334a45a8ff	165	{
bogdanm	0:9b334a45a8ff	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	174
bogdanm	0:9b334a45a8ff	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	177	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	/**
bogdanm	0:9b334a45a8ff	180	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	181	*/
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	typedef struct
bogdanm	0:9b334a45a8ff	184	{
bogdanm	0:9b334a45a8ff	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	186	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	211	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	/**
bogdanm	0:9b334a45a8ff	214	* @brief Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216	typedef struct
bogdanm	0:9b334a45a8ff	217	{
bogdanm	0:9b334a45a8ff	218	uint32_t ClockSource; /*!< TIM clock sources.
bogdanm	0:9b334a45a8ff	219	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm	0:9b334a45a8ff	221	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm	0:9b334a45a8ff	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	224	uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm	0:9b334a45a8ff	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	226	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/**
bogdanm	0:9b334a45a8ff	229	* @brief Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231	typedef struct
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm	0:9b334a45a8ff	234	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm	0:9b334a45a8ff	236	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	0:9b334a45a8ff	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm	0:9b334a45a8ff	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm	0:9b334a45a8ff	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm	0:9b334a45a8ff	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	243	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/**
bogdanm	0:9b334a45a8ff	246	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	247	*/
bogdanm	0:9b334a45a8ff	248	typedef struct {
bogdanm	0:9b334a45a8ff	249	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	0:9b334a45a8ff	250	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	0:9b334a45a8ff	251	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	0:9b334a45a8ff	252	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	0:9b334a45a8ff	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	257	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	0:9b334a45a8ff	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	/**
bogdanm	0:9b334a45a8ff	263	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	264	*/
bogdanm	0:9b334a45a8ff	265	typedef enum
bogdanm	0:9b334a45a8ff	266	{
bogdanm	0:9b334a45a8ff	267	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	268	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	269	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	270	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	271	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	272	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/**
bogdanm	0:9b334a45a8ff	275	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	276	*/
bogdanm	0:9b334a45a8ff	277	typedef enum
bogdanm	0:9b334a45a8ff	278	{
bogdanm	0:9b334a45a8ff	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	284	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	/**
bogdanm	0:9b334a45a8ff	287	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	288	*/
bogdanm	0:9b334a45a8ff	289	typedef struct
bogdanm	0:9b334a45a8ff	290	{
bogdanm	0:9b334a45a8ff	291	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	295	This array is accessed by a @ref DMA_Handle_index */
bogdanm	0:9b334a45a8ff	296	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	298	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	299	/**
bogdanm	0:9b334a45a8ff	300	* @}
bogdanm	0:9b334a45a8ff	301	*/
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	305	* @{
bogdanm	0:9b334a45a8ff	306	*/
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
bogdanm	0:9b334a45a8ff	309	* @{
bogdanm	0:9b334a45a8ff	310	*/
bogdanm	0:9b334a45a8ff	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	314	/**
bogdanm	0:9b334a45a8ff	315	* @}
bogdanm	0:9b334a45a8ff	316	*/
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	0:9b334a45a8ff	319	* @{
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	323	/**
bogdanm	0:9b334a45a8ff	324	* @}
bogdanm	0:9b334a45a8ff	325	*/
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	0:9b334a45a8ff	328	* @{
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	334	/**
bogdanm	0:9b334a45a8ff	335	* @}
bogdanm	0:9b334a45a8ff	336	*/
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	0:9b334a45a8ff	339	* @{
bogdanm	0:9b334a45a8ff	340	*/
bogdanm	0:9b334a45a8ff	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	346	/**
bogdanm	0:9b334a45a8ff	347	* @}
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	0:9b334a45a8ff	351	* @{
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	356	/**
bogdanm	0:9b334a45a8ff	357	* @}
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
bogdanm	0:9b334a45a8ff	361	* @{
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	371
bogdanm	0:9b334a45a8ff	372	/**
bogdanm	0:9b334a45a8ff	373	* @}
bogdanm	0:9b334a45a8ff	374	*/
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	0:9b334a45a8ff	377	* @{
bogdanm	0:9b334a45a8ff	378	*/
bogdanm	0:9b334a45a8ff	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	381	/**
bogdanm	0:9b334a45a8ff	382	* @}
bogdanm	0:9b334a45a8ff	383	*/
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	0:9b334a45a8ff	386	* @{
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	390	/**
bogdanm	0:9b334a45a8ff	391	* @}
bogdanm	0:9b334a45a8ff	392	*/
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
bogdanm	0:9b334a45a8ff	395	* @{
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	0:9b334a45a8ff	399	/**
bogdanm	0:9b334a45a8ff	400	* @}
bogdanm	0:9b334a45a8ff	401	*/
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	0:9b334a45a8ff	404	* @{
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	0:9b334a45a8ff	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	408	/**
bogdanm	0:9b334a45a8ff	409	* @}
bogdanm	0:9b334a45a8ff	410	*/
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
bogdanm	0:9b334a45a8ff	413	* @{
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	0:9b334a45a8ff	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	417	/**
bogdanm	0:9b334a45a8ff	418	* @}
bogdanm	0:9b334a45a8ff	419	*/
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/** @defgroup TIM_Channel TIM Channel
bogdanm	0:9b334a45a8ff	422	* @{
bogdanm	0:9b334a45a8ff	423	*/
bogdanm	0:9b334a45a8ff	424	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	425	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	426	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	427	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	428	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/**
bogdanm	0:9b334a45a8ff	431	* @}
bogdanm	0:9b334a45a8ff	432	*/
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	0:9b334a45a8ff	435	* @{
bogdanm	0:9b334a45a8ff	436	*/
bogdanm	0:9b334a45a8ff	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	440	/**
bogdanm	0:9b334a45a8ff	441	* @}
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	0:9b334a45a8ff	445	* @{
bogdanm	0:9b334a45a8ff	446	*/
bogdanm	0:9b334a45a8ff	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	448	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	450	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/**
bogdanm	0:9b334a45a8ff	454	* @}
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	0:9b334a45a8ff	458	* @{
bogdanm	0:9b334a45a8ff	459	*/
bogdanm	0:9b334a45a8ff	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @}
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	473	/**
bogdanm	0:9b334a45a8ff	474	* @}
bogdanm	0:9b334a45a8ff	475	*/
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	0:9b334a45a8ff	478	* @{
bogdanm	0:9b334a45a8ff	479	*/
bogdanm	0:9b334a45a8ff	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/**
bogdanm	0:9b334a45a8ff	485	* @}
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
bogdanm	0:9b334a45a8ff	489	* @{
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	496	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	0:9b334a45a8ff	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	0:9b334a45a8ff	499	/**
bogdanm	0:9b334a45a8ff	500	* @}
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
bogdanm	0:9b334a45a8ff	504	* @{
bogdanm	0:9b334a45a8ff	505	*/
bogdanm	0:9b334a45a8ff	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	0:9b334a45a8ff	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	508	/**
bogdanm	0:9b334a45a8ff	509	* @}
bogdanm	0:9b334a45a8ff	510	*/
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	/** @defgroup TIM_DMA_sources TIM DMA sources
bogdanm	0:9b334a45a8ff	513	* @{
bogdanm	0:9b334a45a8ff	514	*/
bogdanm	0:9b334a45a8ff	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	0:9b334a45a8ff	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	522	/**
bogdanm	0:9b334a45a8ff	523	* @}
bogdanm	0:9b334a45a8ff	524	*/
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/** @defgroup TIM_Event_Source TIM Event Source
bogdanm	0:9b334a45a8ff	527	* @{
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
bogdanm	0:9b334a45a8ff	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
bogdanm	0:9b334a45a8ff	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
bogdanm	0:9b334a45a8ff	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
bogdanm	0:9b334a45a8ff	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
bogdanm	0:9b334a45a8ff	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
bogdanm	0:9b334a45a8ff	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
bogdanm	0:9b334a45a8ff	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	/**
bogdanm	0:9b334a45a8ff	539	* @}
bogdanm	0:9b334a45a8ff	540	*/
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/** @defgroup TIM_Flag_definition TIM Flag definition
bogdanm	0:9b334a45a8ff	543	* @{
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	0:9b334a45a8ff	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	0:9b334a45a8ff	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	557	/**
bogdanm	0:9b334a45a8ff	558	* @}
bogdanm	0:9b334a45a8ff	559	*/
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	0:9b334a45a8ff	562	* @{
bogdanm	0:9b334a45a8ff	563	*/
bogdanm	0:9b334a45a8ff	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	574	/**
bogdanm	0:9b334a45a8ff	575	* @}
bogdanm	0:9b334a45a8ff	576	*/
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	0:9b334a45a8ff	579	* @{
bogdanm	0:9b334a45a8ff	580	*/
bogdanm	0:9b334a45a8ff	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	586	/**
bogdanm	0:9b334a45a8ff	587	* @}
bogdanm	0:9b334a45a8ff	588	*/
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	0:9b334a45a8ff	591	* @{
bogdanm	0:9b334a45a8ff	592	*/
bogdanm	0:9b334a45a8ff	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	597	/**
bogdanm	0:9b334a45a8ff	598	* @}
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
bogdanm	0:9b334a45a8ff	602	* @{
bogdanm	0:9b334a45a8ff	603	*/
bogdanm	0:9b334a45a8ff	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	606	/**
bogdanm	0:9b334a45a8ff	607	* @}
bogdanm	0:9b334a45a8ff	608	*/
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	0:9b334a45a8ff	611	* @{
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @}
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	0:9b334a45a8ff	620	* @{
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	626	/**
bogdanm	0:9b334a45a8ff	627	* @}
bogdanm	0:9b334a45a8ff	628	*/
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
bogdanm	0:9b334a45a8ff	631	* @{
bogdanm	0:9b334a45a8ff	632	*/
bogdanm	0:9b334a45a8ff	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	0:9b334a45a8ff	634	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	635	/**
bogdanm	0:9b334a45a8ff	636	* @}
bogdanm	0:9b334a45a8ff	637	*/
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
bogdanm	0:9b334a45a8ff	640	* @{
bogdanm	0:9b334a45a8ff	641	*/
bogdanm	0:9b334a45a8ff	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	0:9b334a45a8ff	643	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	644	/**
bogdanm	0:9b334a45a8ff	645	* @}
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/** @defgroup TIM_Lock_level TIM Lock level
bogdanm	0:9b334a45a8ff	649	* @{
bogdanm	0:9b334a45a8ff	650	*/
bogdanm	0:9b334a45a8ff	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	0:9b334a45a8ff	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	0:9b334a45a8ff	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	0:9b334a45a8ff	655	/**
bogdanm	0:9b334a45a8ff	656	* @}
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
bogdanm	0:9b334a45a8ff	659	* @{
bogdanm	0:9b334a45a8ff	660	*/
bogdanm	0:9b334a45a8ff	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	0:9b334a45a8ff	662	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	663	/**
bogdanm	0:9b334a45a8ff	664	* @}
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
bogdanm	0:9b334a45a8ff	668	* @{
bogdanm	0:9b334a45a8ff	669	*/
bogdanm	0:9b334a45a8ff	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	0:9b334a45a8ff	672	/**
bogdanm	0:9b334a45a8ff	673	* @}
bogdanm	0:9b334a45a8ff	674	*/
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
bogdanm	0:9b334a45a8ff	677	* @{
bogdanm	0:9b334a45a8ff	678	*/
bogdanm	0:9b334a45a8ff	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	0:9b334a45a8ff	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	681	/**
bogdanm	0:9b334a45a8ff	682	* @}
bogdanm	0:9b334a45a8ff	683	*/
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	0:9b334a45a8ff	686	* @{
bogdanm	0:9b334a45a8ff	687	*/
bogdanm	0:9b334a45a8ff	688	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	696	/**
bogdanm	0:9b334a45a8ff	697	* @}
bogdanm	0:9b334a45a8ff	698	*/
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
bogdanm	0:9b334a45a8ff	701	* @{
bogdanm	0:9b334a45a8ff	702	*/
bogdanm	0:9b334a45a8ff	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	0:9b334a45a8ff	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	0:9b334a45a8ff	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	0:9b334a45a8ff	708	/**
bogdanm	0:9b334a45a8ff	709	* @}
bogdanm	0:9b334a45a8ff	710	*/
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
bogdanm	0:9b334a45a8ff	713	* @{
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	717	/**
bogdanm	0:9b334a45a8ff	718	* @}
bogdanm	0:9b334a45a8ff	719	*/
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	0:9b334a45a8ff	722	* @{
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	725	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	726	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	727	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	728	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	729	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	730	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	731	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	732	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	733	/**
bogdanm	0:9b334a45a8ff	734	* @}
bogdanm	0:9b334a45a8ff	735	*/
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	0:9b334a45a8ff	738	* @{
bogdanm	0:9b334a45a8ff	739	*/
bogdanm	0:9b334a45a8ff	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	745	/**
bogdanm	0:9b334a45a8ff	746	* @}
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	0:9b334a45a8ff	750	* @{
bogdanm	0:9b334a45a8ff	751	*/
bogdanm	0:9b334a45a8ff	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	756	/**
bogdanm	0:9b334a45a8ff	757	* @}
bogdanm	0:9b334a45a8ff	758	*/
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
bogdanm	0:9b334a45a8ff	762	* @{
bogdanm	0:9b334a45a8ff	763	*/
bogdanm	0:9b334a45a8ff	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	766	/**
bogdanm	0:9b334a45a8ff	767	* @}
bogdanm	0:9b334a45a8ff	768	*/
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
bogdanm	0:9b334a45a8ff	771	* @{
bogdanm	0:9b334a45a8ff	772	*/
bogdanm	0:9b334a45a8ff	773	#define TIM_DMABASE_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	774	#define TIM_DMABASE_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	775	#define TIM_DMABASE_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	776	#define TIM_DMABASE_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	777	#define TIM_DMABASE_SR (0x00000004)
bogdanm	0:9b334a45a8ff	778	#define TIM_DMABASE_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	779	#define TIM_DMABASE_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	780	#define TIM_DMABASE_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	781	#define TIM_DMABASE_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	782	#define TIM_DMABASE_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	783	#define TIM_DMABASE_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	784	#define TIM_DMABASE_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	785	#define TIM_DMABASE_RCR (0x0000000C)
bogdanm	0:9b334a45a8ff	786	#define TIM_DMABASE_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	787	#define TIM_DMABASE_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	788	#define TIM_DMABASE_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	789	#define TIM_DMABASE_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	790	#define TIM_DMABASE_BDTR (0x00000011)
bogdanm	0:9b334a45a8ff	791	#define TIM_DMABASE_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	792	#define TIM_DMABASE_OR (0x00000013)
bogdanm	0:9b334a45a8ff	793	/**
bogdanm	0:9b334a45a8ff	794	* @}
bogdanm	0:9b334a45a8ff	795	*/
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	0:9b334a45a8ff	798	* @{
bogdanm	0:9b334a45a8ff	799	*/
bogdanm	0:9b334a45a8ff	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
bogdanm	0:9b334a45a8ff	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
bogdanm	0:9b334a45a8ff	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
bogdanm	0:9b334a45a8ff	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
bogdanm	0:9b334a45a8ff	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
bogdanm	0:9b334a45a8ff	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
bogdanm	0:9b334a45a8ff	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
bogdanm	0:9b334a45a8ff	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
bogdanm	0:9b334a45a8ff	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
bogdanm	0:9b334a45a8ff	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
bogdanm	0:9b334a45a8ff	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
bogdanm	0:9b334a45a8ff	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
bogdanm	0:9b334a45a8ff	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
bogdanm	0:9b334a45a8ff	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
bogdanm	0:9b334a45a8ff	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
bogdanm	0:9b334a45a8ff	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
bogdanm	0:9b334a45a8ff	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
bogdanm	0:9b334a45a8ff	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm	0:9b334a45a8ff	818	/**
bogdanm	0:9b334a45a8ff	819	* @}
bogdanm	0:9b334a45a8ff	820	*/
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/** @defgroup DMA_Handle_index DMA Handle index
bogdanm	0:9b334a45a8ff	823	* @{
bogdanm	0:9b334a45a8ff	824	*/
bogdanm	0:9b334a45a8ff	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	0:9b334a45a8ff	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	832	/**
bogdanm	0:9b334a45a8ff	833	* @}
bogdanm	0:9b334a45a8ff	834	*/
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	/** @defgroup Channel_CC_State Channel CC State
bogdanm	0:9b334a45a8ff	837	* @{
bogdanm	0:9b334a45a8ff	838	*/
bogdanm	0:9b334a45a8ff	839	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	840	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	841	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	842	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	843	/**
bogdanm	0:9b334a45a8ff	844	* @}
bogdanm	0:9b334a45a8ff	845	*/
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/**
bogdanm	0:9b334a45a8ff	848	* @}
bogdanm	0:9b334a45a8ff	849	*/
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	0:9b334a45a8ff	853	* @{
bogdanm	0:9b334a45a8ff	854	*/
bogdanm	0:9b334a45a8ff	855	/** @brief Reset TIM handle state
bogdanm	0:9b334a45a8ff	856	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	857	* @retval None
bogdanm	0:9b334a45a8ff	858	*/
bogdanm	0:9b334a45a8ff	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/**
bogdanm	0:9b334a45a8ff	862	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	863	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	864	* @retval None
bogdanm	0:9b334a45a8ff	865	*/
bogdanm	0:9b334a45a8ff	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/**
bogdanm	0:9b334a45a8ff	869	* @brief Enable the TIM main Output.
bogdanm	0:9b334a45a8ff	870	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	871	* @retval None
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/**
bogdanm	0:9b334a45a8ff	877	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	878	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	879	* @retval None
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	882	do { \
bogdanm	0:9b334a45a8ff	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	884	{ \
bogdanm	0:9b334a45a8ff	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	886	{ \
bogdanm	0:9b334a45a8ff	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	888	} \
bogdanm	0:9b334a45a8ff	889	} \
bogdanm	0:9b334a45a8ff	890	} while(0)
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	893	channels have been disabled */
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @brief Disable the TIM main Output.
bogdanm	0:9b334a45a8ff	896	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	897	* @retval None
bogdanm	0:9b334a45a8ff	898	*/
bogdanm	0:9b334a45a8ff	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	900	do { \
bogdanm	0:9b334a45a8ff	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	902	{ \
bogdanm	0:9b334a45a8ff	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	904	{ \
bogdanm	0:9b334a45a8ff	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	0:9b334a45a8ff	906	} \
bogdanm	0:9b334a45a8ff	907	} \
bogdanm	0:9b334a45a8ff	908	} while(0)
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
bogdanm	0:9b334a45a8ff	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
bogdanm	0:9b334a45a8ff	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
bogdanm	0:9b334a45a8ff	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
bogdanm	0:9b334a45a8ff	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
bogdanm	0:9b334a45a8ff	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
bogdanm	0:9b334a45a8ff	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/**
bogdanm	0:9b334a45a8ff	948	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	949	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	950	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	951	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	952	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	957	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	958	* @retval None
bogdanm	0:9b334a45a8ff	959	*/
bogdanm	0:9b334a45a8ff	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/**
bogdanm	0:9b334a45a8ff	964	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	965	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	967	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	972	* @retval None
bogdanm	0:9b334a45a8ff	973	*/
bogdanm	0:9b334a45a8ff	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	/**
bogdanm	0:9b334a45a8ff	978	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	979	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	980	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	981	* @retval None
bogdanm	0:9b334a45a8ff	982	*/
bogdanm	0:9b334a45a8ff	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/**
bogdanm	0:9b334a45a8ff	986	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	987	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	988	* @retval None
bogdanm	0:9b334a45a8ff	989	*/
bogdanm	0:9b334a45a8ff	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	0:9b334a45a8ff	994	* another time any Init function.
bogdanm	0:9b334a45a8ff	995	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	996	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	997	* @retval None
bogdanm	0:9b334a45a8ff	998	*/
bogdanm	0:9b334a45a8ff	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1000	do{ \
bogdanm	0:9b334a45a8ff	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1003	} while(0)
bogdanm	0:9b334a45a8ff	1004	/**
bogdanm	0:9b334a45a8ff	1005	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	0:9b334a45a8ff	1006	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1007	* @retval None
bogdanm	0:9b334a45a8ff	1008	*/
bogdanm	0:9b334a45a8ff	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	/**
bogdanm	0:9b334a45a8ff	1012	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	0:9b334a45a8ff	1013	* another time any Init function.
bogdanm	0:9b334a45a8ff	1014	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1015	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1016	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1017	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1018	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1019	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1020	* @retval None
bogdanm	0:9b334a45a8ff	1021	*/
bogdanm	0:9b334a45a8ff	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1023	do{ \
bogdanm	0:9b334a45a8ff	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1027	} while(0)
bogdanm	0:9b334a45a8ff	1028	/**
bogdanm	0:9b334a45a8ff	1029	* @brief Gets the TIM Clock Division value on runtime
bogdanm	0:9b334a45a8ff	1030	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1031	* @retval None
bogdanm	0:9b334a45a8ff	1032	*/
bogdanm	0:9b334a45a8ff	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/**
bogdanm	0:9b334a45a8ff	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	0:9b334a45a8ff	1037	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1038	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1039	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1040	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1046	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1047	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1051	* @retval None
bogdanm	0:9b334a45a8ff	1052	*/
bogdanm	0:9b334a45a8ff	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1054	do{ \
bogdanm	0:9b334a45a8ff	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1057	} while(0)
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/**
bogdanm	0:9b334a45a8ff	1060	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	0:9b334a45a8ff	1061	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1062	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1063	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1068	* @retval None
bogdanm	0:9b334a45a8ff	1069	*/
bogdanm	0:9b334a45a8ff	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/**
bogdanm	0:9b334a45a8ff	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1078	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	0:9b334a45a8ff	1080	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1081	* enabled)
bogdanm	0:9b334a45a8ff	1082	* @retval None
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/**
bogdanm	0:9b334a45a8ff	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1089	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	0:9b334a45a8ff	1091	* following events generate an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1092	* enabled):
bogdanm	0:9b334a45a8ff	1093	* Counter overflow/underflow
bogdanm	0:9b334a45a8ff	1094	* Setting the UG bit
bogdanm	0:9b334a45a8ff	1095	* Update generation through the slave mode controller
bogdanm	0:9b334a45a8ff	1096	* @retval None
bogdanm	0:9b334a45a8ff	1097	*/
bogdanm	0:9b334a45a8ff	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/**
bogdanm	0:9b334a45a8ff	1102	* @brief Sets the TIM Capture x input polarity on runtime.
bogdanm	0:9b334a45a8ff	1103	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1104	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1105	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1110	* @param __POLARITY__: Polarity for TIx source
bogdanm	0:9b334a45a8ff	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
bogdanm	0:9b334a45a8ff	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
bogdanm	0:9b334a45a8ff	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
bogdanm	0:9b334a45a8ff	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
bogdanm	0:9b334a45a8ff	1115	* @retval None
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1118	do{ \
bogdanm	0:9b334a45a8ff	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
bogdanm	0:9b334a45a8ff	1121	}while(0)
bogdanm	0:9b334a45a8ff	1122	/**
bogdanm	0:9b334a45a8ff	1123	* @}
bogdanm	0:9b334a45a8ff	1124	*/
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/* Include TIM HAL Extension module */
bogdanm	0:9b334a45a8ff	1127	#include "stm32f4xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1130	/** @addtogroup TIM_Exported_Functions
bogdanm	0:9b334a45a8ff	1131	* @{
bogdanm	0:9b334a45a8ff	1132	*/
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1135	* @{
bogdanm	0:9b334a45a8ff	1136	*/
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1143	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1146	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1149	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1152	/**
bogdanm	0:9b334a45a8ff	1153	* @}
bogdanm	0:9b334a45a8ff	1154	*/
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1157	* @{
bogdanm	0:9b334a45a8ff	1158	*/
bogdanm	0:9b334a45a8ff	1159	/* Timer Output Compare functions **********************************************/
bogdanm	0:9b334a45a8ff	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1164	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1167	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1170	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/**
bogdanm	0:9b334a45a8ff	1175	* @}
bogdanm	0:9b334a45a8ff	1176	*/
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	1179	* @{
bogdanm	0:9b334a45a8ff	1180	*/
bogdanm	0:9b334a45a8ff	1181	/* Timer PWM functions *********************************************************/
bogdanm	0:9b334a45a8ff	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1186	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1189	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1192	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/**
bogdanm	0:9b334a45a8ff	1197	* @}
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	1201	* @{
bogdanm	0:9b334a45a8ff	1202	*/
bogdanm	0:9b334a45a8ff	1203	/* Timer Input Capture functions ***********************************************/
bogdanm	0:9b334a45a8ff	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1208	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1211	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1214	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/**
bogdanm	0:9b334a45a8ff	1219	* @}
bogdanm	0:9b334a45a8ff	1220	*/
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	0:9b334a45a8ff	1223	* @{
bogdanm	0:9b334a45a8ff	1224	*/
bogdanm	0:9b334a45a8ff	1225	/* Timer One Pulse functions ***************************************************/
bogdanm	0:9b334a45a8ff	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1230	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/**
bogdanm	0:9b334a45a8ff	1239	* @}
bogdanm	0:9b334a45a8ff	1240	*/
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	0:9b334a45a8ff	1243	* @{
bogdanm	0:9b334a45a8ff	1244	*/
bogdanm	0:9b334a45a8ff	1245	/* Timer Encoder functions *****************************************************/
bogdanm	0:9b334a45a8ff	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1250	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1253	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1256	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/**
bogdanm	0:9b334a45a8ff	1261	* @}
bogdanm	0:9b334a45a8ff	1262	*/
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	0:9b334a45a8ff	1265	* @{
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267	/* Interrupt Handler functions **********************************************/
bogdanm	0:9b334a45a8ff	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/**
bogdanm	0:9b334a45a8ff	1271	* @}
bogdanm	0:9b334a45a8ff	1272	*/
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	0:9b334a45a8ff	1275	* @{
bogdanm	0:9b334a45a8ff	1276	*/
bogdanm	0:9b334a45a8ff	1277	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/**
bogdanm	0:9b334a45a8ff	1297	* @}
bogdanm	0:9b334a45a8ff	1298	*/
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	0:9b334a45a8ff	1301	* @{
bogdanm	0:9b334a45a8ff	1302	*/
bogdanm	0:9b334a45a8ff	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/**
bogdanm	0:9b334a45a8ff	1312	* @}
bogdanm	0:9b334a45a8ff	1313	*/
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	0:9b334a45a8ff	1316	* @{
bogdanm	0:9b334a45a8ff	1317	*/
bogdanm	0:9b334a45a8ff	1318	/* Peripheral State functions **************************************************/
bogdanm	0:9b334a45a8ff	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	/**
bogdanm	0:9b334a45a8ff	1327	* @}
bogdanm	0:9b334a45a8ff	1328	*/
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/**
bogdanm	0:9b334a45a8ff	1331	* @}
bogdanm	0:9b334a45a8ff	1332	*/
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
bogdanm	0:9b334a45a8ff	1336	* @{
bogdanm	0:9b334a45a8ff	1337	*/
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
bogdanm	0:9b334a45a8ff	1340	* @{
bogdanm	0:9b334a45a8ff	1341	*/
bogdanm	0:9b334a45a8ff	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	1353	((MODE) == TIM_OCMODE_PWM2))
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1363	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	1372	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	1381	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1384	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1388	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	1396	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1401	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	1404	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	1410	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1452	((STATE) == TIM_OSSR_DISABLE))
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1455	((STATE) == TIM_OSSI_DISABLE))
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1460	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1463	((STATE) == TIM_BREAK_DISABLE))
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	1478	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	1496	((SELECTION) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1502	((SELECTION) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	1503	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	1504	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1505	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	1506	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	1507	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1510	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	1517	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
bogdanm	0:9b334a45a8ff	1520	((BASE) == TIM_DMABASE_CR2) \|\| \
bogdanm	0:9b334a45a8ff	1521	((BASE) == TIM_DMABASE_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	1522	((BASE) == TIM_DMABASE_DIER) \|\| \
bogdanm	0:9b334a45a8ff	1523	((BASE) == TIM_DMABASE_SR) \|\| \
bogdanm	0:9b334a45a8ff	1524	((BASE) == TIM_DMABASE_EGR) \|\| \
bogdanm	0:9b334a45a8ff	1525	((BASE) == TIM_DMABASE_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	1526	((BASE) == TIM_DMABASE_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	1527	((BASE) == TIM_DMABASE_CCER) \|\| \
bogdanm	0:9b334a45a8ff	1528	((BASE) == TIM_DMABASE_CNT) \|\| \
bogdanm	0:9b334a45a8ff	1529	((BASE) == TIM_DMABASE_PSC) \|\| \
bogdanm	0:9b334a45a8ff	1530	((BASE) == TIM_DMABASE_ARR) \|\| \
bogdanm	0:9b334a45a8ff	1531	((BASE) == TIM_DMABASE_RCR) \|\| \
bogdanm	0:9b334a45a8ff	1532	((BASE) == TIM_DMABASE_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	1533	((BASE) == TIM_DMABASE_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	1534	((BASE) == TIM_DMABASE_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	1535	((BASE) == TIM_DMABASE_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	1536	((BASE) == TIM_DMABASE_BDTR) \|\| \
bogdanm	0:9b334a45a8ff	1537	((BASE) == TIM_DMABASE_DCR) \|\| \
bogdanm	0:9b334a45a8ff	1538	((BASE) == TIM_DMABASE_OR))
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
bogdanm	0:9b334a45a8ff	1541	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1542	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1543	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1544	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1545	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1546	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1547	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1548	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1549	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1550	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1551	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1552	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1553	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1554	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1555	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1556	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1557	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1560	/**
bogdanm	0:9b334a45a8ff	1561	* @}
bogdanm	0:9b334a45a8ff	1562	*/
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
bogdanm	0:9b334a45a8ff	1565	* @{
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	1568	channels have been disabled */
bogdanm	0:9b334a45a8ff	1569	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	1570	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	0:9b334a45a8ff	1571	/**
bogdanm	0:9b334a45a8ff	1572	* @}
bogdanm	0:9b334a45a8ff	1573	*/
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	/**
bogdanm	0:9b334a45a8ff	1576	* @}
bogdanm	0:9b334a45a8ff	1577	*/
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1580	/** @defgroup TIM_Private_Functions TIM Private Functions
bogdanm	0:9b334a45a8ff	1581	* @{
bogdanm	0:9b334a45a8ff	1582	*/
bogdanm	0:9b334a45a8ff	1583	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	0:9b334a45a8ff	1584	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	1585	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1586	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1587	void TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1588	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1589	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	0:9b334a45a8ff	1590	/**
bogdanm	0:9b334a45a8ff	1591	* @}
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/**
bogdanm	0:9b334a45a8ff	1595	* @}
bogdanm	0:9b334a45a8ff	1596	*/
bogdanm	0:9b334a45a8ff	1597
bogdanm	0:9b334a45a8ff	1598	/**
bogdanm	0:9b334a45a8ff	1599	* @}
bogdanm	0:9b334a45a8ff	1600	*/
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604	#endif
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	#endif /* __STM32F4xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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