mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + IO operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx interface clock using
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx Stream
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customized HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	@endverbatim
bogdanm	0:9b334a45a8ff	59	******************************************************************************
bogdanm	0:9b334a45a8ff	60	* @attention
bogdanm	0:9b334a45a8ff	61	*
bogdanm	0:9b334a45a8ff	62	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	63	*
bogdanm	0:9b334a45a8ff	64	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	65	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	66	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	67	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	68	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	69	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	70	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	71	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	72	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	73	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	74	*
bogdanm	0:9b334a45a8ff	75	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	76	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	77	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	78	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	79	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	80	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	81	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	82	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	83	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	84	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	85	*
bogdanm	0:9b334a45a8ff	86	******************************************************************************
bogdanm	0:9b334a45a8ff	87	*/
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	90	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	93	* @{
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	97	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	98	* @{
bogdanm	0:9b334a45a8ff	99	*/
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	104	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	105	#define SPI_TIMEOUT_VALUE 10
bogdanm	0:9b334a45a8ff	106	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	107	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	108	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	109	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	110	* @{
bogdanm	0:9b334a45a8ff	111	*/
bogdanm	0:9b334a45a8ff	112	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	113	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	114	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	115	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	116	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	117	static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	118	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	119	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	120	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	121	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	122	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	123	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	124	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	125	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	126	/**
bogdanm	0:9b334a45a8ff	127	* @}
bogdanm	0:9b334a45a8ff	128	*/
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	131	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	136	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	137	*
bogdanm	0:9b334a45a8ff	138	@verbatim
bogdanm	0:9b334a45a8ff	139	===============================================================================
bogdanm	0:9b334a45a8ff	140	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	141	===============================================================================
bogdanm	0:9b334a45a8ff	142	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	143	de-initialize the SPIx peripheral:
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	146	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	149	the selected configuration:
bogdanm	0:9b334a45a8ff	150	(++) Mode
bogdanm	0:9b334a45a8ff	151	(++) Direction
bogdanm	0:9b334a45a8ff	152	(++) Data Size
bogdanm	0:9b334a45a8ff	153	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	154	(++) NSS Management
bogdanm	0:9b334a45a8ff	155	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	156	(++) FirstBit
bogdanm	0:9b334a45a8ff	157	(++) TIMode
bogdanm	0:9b334a45a8ff	158	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	159	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	162	of the selected SPIx peripheral.
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	@endverbatim
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	/**
bogdanm	0:9b334a45a8ff	169	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	170	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	171	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	172	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	173	* @retval HAL status
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	176	{
bogdanm	0:9b334a45a8ff	177	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	178	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	179	{
bogdanm	0:9b334a45a8ff	180	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	181	}
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	/* Check the parameters */
bogdanm	0:9b334a45a8ff	184	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	185	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	186	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	187	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	188	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	189	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	190	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	191	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	192	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	193	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	194	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	197	{
bogdanm	0:9b334a45a8ff	198	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	199	hspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	200	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	201	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	202	}
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/* Disable the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	207	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	210	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	211	Communication speed, First bit and CRC calculation state */
bogdanm	0:9b334a45a8ff	212	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
bogdanm	0:9b334a45a8ff	213	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	214	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	217	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/---------------------------- SPIx CRCPOLY Configuration ------------------/
bogdanm	0:9b334a45a8ff	220	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	221	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
bogdanm	0:9b334a45a8ff	224	hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	227	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	return HAL_OK;
bogdanm	0:9b334a45a8ff	230	}
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	234	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	235	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	236	* @retval HAL status
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	241	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	242	{
bogdanm	0:9b334a45a8ff	243	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	244	}
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	247	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	250	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	253	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	/* Release Lock */
bogdanm	0:9b334a45a8ff	256	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	return HAL_OK;
bogdanm	0:9b334a45a8ff	259	}
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/**
bogdanm	0:9b334a45a8ff	262	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	263	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	264	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	265	* @retval None
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	268	{
bogdanm	0:9b334a45a8ff	269	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	270	the HAL_SPI_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272	}
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/**
bogdanm	0:9b334a45a8ff	275	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	276	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	277	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	278	* @retval None
bogdanm	0:9b334a45a8ff	279	*/
bogdanm	0:9b334a45a8ff	280	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	281	{
bogdanm	0:9b334a45a8ff	282	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	283	the HAL_SPI_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	284	*/
bogdanm	0:9b334a45a8ff	285	}
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/**
bogdanm	0:9b334a45a8ff	288	* @}
bogdanm	0:9b334a45a8ff	289	*/
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	292	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	293	*
bogdanm	0:9b334a45a8ff	294	@verbatim
bogdanm	0:9b334a45a8ff	295	==============================================================================
bogdanm	0:9b334a45a8ff	296	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	297	===============================================================================
bogdanm	0:9b334a45a8ff	298	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	299	data transfers.
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	304	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	305	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	306	after finishing transfer.
bogdanm	0:9b334a45a8ff	307	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	308	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	309	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	310	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	311	using DMA mode.
bogdanm	0:9b334a45a8ff	312	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	313	will be executed respectively at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	314	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	317	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	@endverbatim
bogdanm	0:9b334a45a8ff	320	* @{
bogdanm	0:9b334a45a8ff	321	*/
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/**
bogdanm	0:9b334a45a8ff	324	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	325	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	326	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	327	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	328	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	329	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	330	* @retval HAL status
bogdanm	0:9b334a45a8ff	331	*/
bogdanm	0:9b334a45a8ff	332	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	333	{
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	336	{
bogdanm	0:9b334a45a8ff	337	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	338	{
bogdanm	0:9b334a45a8ff	339	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/* Check the parameters */
bogdanm	0:9b334a45a8ff	343	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/* Process Locked */
bogdanm	0:9b334a45a8ff	346	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/* Configure communication */
bogdanm	0:9b334a45a8ff	349	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	350	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	353	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	354	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	357	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	358	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	359	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	360	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	363	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	364	{
bogdanm	0:9b334a45a8ff	365	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	369	{
bogdanm	0:9b334a45a8ff	370	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	371	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	372	}
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	375	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	376	{
bogdanm	0:9b334a45a8ff	377	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	378	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	379	}
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	382	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	383	{
bogdanm	0:9b334a45a8ff	384	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	385	{
bogdanm	0:9b334a45a8ff	386	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	387	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	388	}
bogdanm	0:9b334a45a8ff	389	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	390	{
bogdanm	0:9b334a45a8ff	391	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	392	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	393	{
bogdanm	0:9b334a45a8ff	394	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	395	}
bogdanm	0:9b334a45a8ff	396	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	397	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	398	}
bogdanm	0:9b334a45a8ff	399	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	400	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	403	}
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	406	else
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	409	{
bogdanm	0:9b334a45a8ff	410	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	411	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	412	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	413	}
bogdanm	0:9b334a45a8ff	414	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	415	{
bogdanm	0:9b334a45a8ff	416	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	417	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	418	{
bogdanm	0:9b334a45a8ff	419	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	420	}
bogdanm	0:9b334a45a8ff	421	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	422	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	423	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	424	}
bogdanm	0:9b334a45a8ff	425	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	426	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	427	{
bogdanm	0:9b334a45a8ff	428	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	429	}
bogdanm	0:9b334a45a8ff	430	}
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	433	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	434	{
bogdanm	0:9b334a45a8ff	435	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	436	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	440	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	443	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	444	}
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	447	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	448	{
bogdanm	0:9b334a45a8ff	449	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	455	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	return HAL_OK;
bogdanm	0:9b334a45a8ff	458	}
bogdanm	0:9b334a45a8ff	459	else
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463	}
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/**
bogdanm	0:9b334a45a8ff	466	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	467	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	468	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	469	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	470	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	471	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	472	* @retval HAL status
bogdanm	0:9b334a45a8ff	473	*/
bogdanm	0:9b334a45a8ff	474	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	477	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	482	{
bogdanm	0:9b334a45a8ff	483	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	/* Process Locked */
bogdanm	0:9b334a45a8ff	487	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/* Configure communication */
bogdanm	0:9b334a45a8ff	490	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	491	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	494	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	495	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	498	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	499	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	500	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	501	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	504	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	505	{
bogdanm	0:9b334a45a8ff	506	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	507	}
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	510	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	511	{
bogdanm	0:9b334a45a8ff	512	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	513	}
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	518	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	521	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
bogdanm	0:9b334a45a8ff	522	}
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	525	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	526	{
bogdanm	0:9b334a45a8ff	527	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	528	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	532	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	533	{
bogdanm	0:9b334a45a8ff	534	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	537	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	538	{
bogdanm	0:9b334a45a8ff	539	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	543	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	544	}
bogdanm	0:9b334a45a8ff	545	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	546	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	547	{
bogdanm	0:9b334a45a8ff	548	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	549	}
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	552	else
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	555	{
bogdanm	0:9b334a45a8ff	556	/* Wait until RXNE flag is set to read data */
bogdanm	0:9b334a45a8ff	557	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	560	}
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	563	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	564	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	565	}
bogdanm	0:9b334a45a8ff	566	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	567	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	568	{
bogdanm	0:9b334a45a8ff	569	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	570	}
bogdanm	0:9b334a45a8ff	571	}
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	574	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	575	{
bogdanm	0:9b334a45a8ff	576	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	580	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	583	}
bogdanm	0:9b334a45a8ff	584	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	585	else
bogdanm	0:9b334a45a8ff	586	{
bogdanm	0:9b334a45a8ff	587	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	588	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* Wait until RXNE flag is set: CRC Received */
bogdanm	0:9b334a45a8ff	593	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	596	{
bogdanm	0:9b334a45a8ff	597	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	598	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	599	}
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Read CRC to Flush RXNE flag */
bogdanm	0:9b334a45a8ff	602	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	603	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	604	}
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	607	{
bogdanm	0:9b334a45a8ff	608	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	609	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	610	}
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
bogdanm	0:9b334a45a8ff	615	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	616	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
bogdanm	0:9b334a45a8ff	617	{
bogdanm	0:9b334a45a8ff	618	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	621	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	624	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	625
bogdanm	0:9b334a45a8ff	626	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	627	}
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	630	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	return HAL_OK;
bogdanm	0:9b334a45a8ff	633	}
bogdanm	0:9b334a45a8ff	634	else
bogdanm	0:9b334a45a8ff	635	{
bogdanm	0:9b334a45a8ff	636	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	637	}
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/**
bogdanm	0:9b334a45a8ff	641	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	642	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	643	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	644	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	645	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	646	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	647	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	648	* @retval HAL status
bogdanm	0:9b334a45a8ff	649	*/
bogdanm	0:9b334a45a8ff	650	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	653	uint32_t tmpstate = 0, tmp = 0;
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	tmpstate = hspi->State;
bogdanm	0:9b334a45a8ff	656	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
bogdanm	0:9b334a45a8ff	657	{
bogdanm	0:9b334a45a8ff	658	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	659	{
bogdanm	0:9b334a45a8ff	660	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	661	}
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	/* Check the parameters */
bogdanm	0:9b334a45a8ff	664	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	/* Process Locked */
bogdanm	0:9b334a45a8ff	667	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	670	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	671	{
bogdanm	0:9b334a45a8ff	672	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/* Configure communication */
bogdanm	0:9b334a45a8ff	676	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	679	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	680	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	683	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	684	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	687	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	688	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	691	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	692	{
bogdanm	0:9b334a45a8ff	693	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	694	}
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	697	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	698	{
bogdanm	0:9b334a45a8ff	699	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	700	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	704	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	707	{
bogdanm	0:9b334a45a8ff	708	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	709	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	710	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	711	}
bogdanm	0:9b334a45a8ff	712	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	713	{
bogdanm	0:9b334a45a8ff	714	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	715	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	716	{
bogdanm	0:9b334a45a8ff	717	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	718	}
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	721	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	727	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	728	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	729	}
bogdanm	0:9b334a45a8ff	730	else
bogdanm	0:9b334a45a8ff	731	{
bogdanm	0:9b334a45a8ff	732	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	733	{
bogdanm	0:9b334a45a8ff	734	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	735	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	736	{
bogdanm	0:9b334a45a8ff	737	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	738	}
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	741	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	742	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	745	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	746	{
bogdanm	0:9b334a45a8ff	747	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	748	}
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	751	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	752	{
bogdanm	0:9b334a45a8ff	753	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	757	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	758	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	759	}
bogdanm	0:9b334a45a8ff	760	/* Receive the last byte */
bogdanm	0:9b334a45a8ff	761	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	764	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	765	{
bogdanm	0:9b334a45a8ff	766	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	767	}
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	770	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	771	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	772	}
bogdanm	0:9b334a45a8ff	773	}
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	776	else
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	779	{
bogdanm	0:9b334a45a8ff	780	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	781	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	786	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	787	{
bogdanm	0:9b334a45a8ff	788	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	789	}
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	792	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	798	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	799	}
bogdanm	0:9b334a45a8ff	800	else
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	803	{
bogdanm	0:9b334a45a8ff	804	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	805	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	808	}
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	811	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	812
bogdanm	0:9b334a45a8ff	813	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	814	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	815	{
bogdanm	0:9b334a45a8ff	816	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	817	}
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	820	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	823	}
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	826	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	827	}
bogdanm	0:9b334a45a8ff	828	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	829	{
bogdanm	0:9b334a45a8ff	830	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	831	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	837	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	838	}
bogdanm	0:9b334a45a8ff	839	}
bogdanm	0:9b334a45a8ff	840	}
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	843	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	844	{
bogdanm	0:9b334a45a8ff	845	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	846	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	847	{
bogdanm	0:9b334a45a8ff	848	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	849	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851	/* Read CRC */
bogdanm	0:9b334a45a8ff	852	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	853	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	854	}
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	857	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	858	{
bogdanm	0:9b334a45a8ff	859	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	860	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
bogdanm	0:9b334a45a8ff	866	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	867	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
bogdanm	0:9b334a45a8ff	868	{
bogdanm	0:9b334a45a8ff	869	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	872	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	875	}
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	878	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	881	}
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	884	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	return HAL_OK;
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	else
bogdanm	0:9b334a45a8ff	889	{
bogdanm	0:9b334a45a8ff	890	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	891	}
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	896	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	897	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	898	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	899	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	900	* @retval HAL status
bogdanm	0:9b334a45a8ff	901	*/
bogdanm	0:9b334a45a8ff	902	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	903	{
bogdanm	0:9b334a45a8ff	904	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	905	{
bogdanm	0:9b334a45a8ff	906	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	907	{
bogdanm	0:9b334a45a8ff	908	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/* Check the parameters */
bogdanm	0:9b334a45a8ff	912	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	/* Process Locked */
bogdanm	0:9b334a45a8ff	915	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/* Configure communication */
bogdanm	0:9b334a45a8ff	918	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	919	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	922	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	923	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	924	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	927	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	928	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	929	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	932	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	933	{
bogdanm	0:9b334a45a8ff	934	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	935	}
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	938	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	939	{
bogdanm	0:9b334a45a8ff	940	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	941	}
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	946	}else
bogdanm	0:9b334a45a8ff	947	{
bogdanm	0:9b334a45a8ff	948	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	949	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	952	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	955	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	956	{
bogdanm	0:9b334a45a8ff	957	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	958	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	959	}
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	return HAL_OK;
bogdanm	0:9b334a45a8ff	962	}
bogdanm	0:9b334a45a8ff	963	else
bogdanm	0:9b334a45a8ff	964	{
bogdanm	0:9b334a45a8ff	965	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	966	}
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/**
bogdanm	0:9b334a45a8ff	970	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	971	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	972	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	973	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	974	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	975	* @retval HAL status
bogdanm	0:9b334a45a8ff	976	*/
bogdanm	0:9b334a45a8ff	977	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	982	{
bogdanm	0:9b334a45a8ff	983	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	984	}
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Process Locked */
bogdanm	0:9b334a45a8ff	987	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/* Configure communication */
bogdanm	0:9b334a45a8ff	990	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	991	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	hspi->RxISR = &SPI_RxISR;
bogdanm	0:9b334a45a8ff	994	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	995	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	996	hspi->RxXferCount = Size ;
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	999	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1000	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1001	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1004	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1005	{
bogdanm	0:9b334a45a8ff	1006	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1007	}
bogdanm	0:9b334a45a8ff	1008	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1009	{
bogdanm	0:9b334a45a8ff	1010	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1011	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1014	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1015	}
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1018	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1019	{
bogdanm	0:9b334a45a8ff	1020	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1021	}
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1024	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1027	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1030	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1031	process unlock */
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1034	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1035	{
bogdanm	0:9b334a45a8ff	1036	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1037	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1038	}
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	return HAL_OK;
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042	else
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1045	}
bogdanm	0:9b334a45a8ff	1046	}
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/**
bogdanm	0:9b334a45a8ff	1049	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1050	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1051	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1052	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1053	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	1054	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1055	* @retval HAL status
bogdanm	0:9b334a45a8ff	1056	*/
bogdanm	0:9b334a45a8ff	1057	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1058	{
bogdanm	0:9b334a45a8ff	1059	uint32_t tmpstate = 0;
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	tmpstate = hspi->State;
bogdanm	0:9b334a45a8ff	1062	if((tmpstate == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1063	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1064	{
bogdanm	0:9b334a45a8ff	1065	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1066	{
bogdanm	0:9b334a45a8ff	1067	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1068	}
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1071	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Process locked */
bogdanm	0:9b334a45a8ff	1074	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1077	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1078	{
bogdanm	0:9b334a45a8ff	1079	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1080	}
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/* Configure communication */
bogdanm	0:9b334a45a8ff	1083	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1086	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1087	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1088	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	hspi->RxISR = &SPI_2LinesRxISR;
bogdanm	0:9b334a45a8ff	1091	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1092	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1093	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1096	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1097	{
bogdanm	0:9b334a45a8ff	1098	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1099	}
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1102	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1105	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1108	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1109	{
bogdanm	0:9b334a45a8ff	1110	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1111	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1112	}
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	return HAL_OK;
bogdanm	0:9b334a45a8ff	1115	}
bogdanm	0:9b334a45a8ff	1116	else
bogdanm	0:9b334a45a8ff	1117	{
bogdanm	0:9b334a45a8ff	1118	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1119	}
bogdanm	0:9b334a45a8ff	1120	}
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	/**
bogdanm	0:9b334a45a8ff	1123	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1124	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1125	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1126	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1127	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1128	* @retval HAL status
bogdanm	0:9b334a45a8ff	1129	*/
bogdanm	0:9b334a45a8ff	1130	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1131	{
bogdanm	0:9b334a45a8ff	1132	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1133	{
bogdanm	0:9b334a45a8ff	1134	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1135	{
bogdanm	0:9b334a45a8ff	1136	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1137	}
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1140	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	/* Process Locked */
bogdanm	0:9b334a45a8ff	1143	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	/* Configure communication */
bogdanm	0:9b334a45a8ff	1146	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1147	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1150	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1151	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1154	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1155	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1156	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1157	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1160	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1161	{
bogdanm	0:9b334a45a8ff	1162	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1163	}
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1166	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1167	{
bogdanm	0:9b334a45a8ff	1168	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1169	}
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1172	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1175	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1178	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	/* Enable the Tx DMA Stream */
bogdanm	0:9b334a45a8ff	1181	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1184	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1187	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1190	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1194	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	return HAL_OK;
bogdanm	0:9b334a45a8ff	1197	}
bogdanm	0:9b334a45a8ff	1198	else
bogdanm	0:9b334a45a8ff	1199	{
bogdanm	0:9b334a45a8ff	1200	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1201	}
bogdanm	0:9b334a45a8ff	1202	}
bogdanm	0:9b334a45a8ff	1203
bogdanm	0:9b334a45a8ff	1204	/**
bogdanm	0:9b334a45a8ff	1205	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1206	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1207	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1208	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1209	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1210	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1211	* @retval HAL status
bogdanm	0:9b334a45a8ff	1212	*/
bogdanm	0:9b334a45a8ff	1213	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1214	{
bogdanm	0:9b334a45a8ff	1215	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1218	{
bogdanm	0:9b334a45a8ff	1219	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/* Process Locked */
bogdanm	0:9b334a45a8ff	1223	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/* Configure communication */
bogdanm	0:9b334a45a8ff	1226	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1227	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1230	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1231	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1234	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1235	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1236	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1237	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1240	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1245	{
bogdanm	0:9b334a45a8ff	1246	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1247	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1250	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1251	}
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1254	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1257	}
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1260	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1263	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1266	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Enable the Rx DMA Stream */
bogdanm	0:9b334a45a8ff	1269	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1272	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1275	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1276	{
bogdanm	0:9b334a45a8ff	1277	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1278	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1279	}
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1282	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	return HAL_OK;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	else
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1289	}
bogdanm	0:9b334a45a8ff	1290	}
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/**
bogdanm	0:9b334a45a8ff	1293	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1294	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1295	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1296	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1297	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1298	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1299	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1300	* @retval HAL status
bogdanm	0:9b334a45a8ff	1301	*/
bogdanm	0:9b334a45a8ff	1302	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1303	{
bogdanm	0:9b334a45a8ff	1304	uint32_t tmpstate = 0;
bogdanm	0:9b334a45a8ff	1305	tmpstate = hspi->State;
bogdanm	0:9b334a45a8ff	1306	if((tmpstate == HAL_SPI_STATE_READY) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && \
bogdanm	0:9b334a45a8ff	1307	(hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1308	{
bogdanm	0:9b334a45a8ff	1309	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1310	{
bogdanm	0:9b334a45a8ff	1311	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1312	}
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1315	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/* Process locked */
bogdanm	0:9b334a45a8ff	1318	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1321	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1322	{
bogdanm	0:9b334a45a8ff	1323	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1324	}
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	/* Configure communication */
bogdanm	0:9b334a45a8ff	1327	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	hspi->pTxBuffPtr = (uint8_t*)pTxData;
bogdanm	0:9b334a45a8ff	1330	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1331	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	hspi->pRxBuffPtr = (uint8_t*)pRxData;
bogdanm	0:9b334a45a8ff	1334	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1335	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1338	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1339	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1342	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1343	{
bogdanm	0:9b334a45a8ff	1344	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1345	}
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1348	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1349	{
bogdanm	0:9b334a45a8ff	1350	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1351	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355	else
bogdanm	0:9b334a45a8ff	1356	{
bogdanm	0:9b334a45a8ff	1357	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1358	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1361	}
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1364	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* Enable the Rx DMA Stream */
bogdanm	0:9b334a45a8ff	1367	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1370	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1373	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1374	hspi->hdmatx->XferCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1377	{
bogdanm	0:9b334a45a8ff	1378	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1379	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1380	}
bogdanm	0:9b334a45a8ff	1381	else
bogdanm	0:9b334a45a8ff	1382	{
bogdanm	0:9b334a45a8ff	1383	hspi->hdmatx->XferErrorCallback = NULL;
bogdanm	0:9b334a45a8ff	1384	}
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* Enable the Tx DMA Stream */
bogdanm	0:9b334a45a8ff	1387	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1390	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1393	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1396	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1400	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	return HAL_OK;
bogdanm	0:9b334a45a8ff	1403	}
bogdanm	0:9b334a45a8ff	1404	else
bogdanm	0:9b334a45a8ff	1405	{
bogdanm	0:9b334a45a8ff	1406	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1407	}
bogdanm	0:9b334a45a8ff	1408	}
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/**
bogdanm	0:9b334a45a8ff	1411	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1412	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1413	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1414	* @retval HAL status
bogdanm	0:9b334a45a8ff	1415	*/
bogdanm	0:9b334a45a8ff	1416	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1417	{
bogdanm	0:9b334a45a8ff	1418	/* Process Locked */
bogdanm	0:9b334a45a8ff	1419	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1422	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1423	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1426	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	return HAL_OK;
bogdanm	0:9b334a45a8ff	1429	}
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	/**
bogdanm	0:9b334a45a8ff	1432	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1433	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1434	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1435	* @retval HAL status
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1438	{
bogdanm	0:9b334a45a8ff	1439	/* Process Locked */
bogdanm	0:9b334a45a8ff	1440	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1443	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1444	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1447	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	return HAL_OK;
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/**
bogdanm	0:9b334a45a8ff	1453	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1454	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1455	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1456	* @retval HAL status
bogdanm	0:9b334a45a8ff	1457	*/
bogdanm	0:9b334a45a8ff	1458	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1459	{
bogdanm	0:9b334a45a8ff	1460	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1461	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1462	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1463	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1464	*/
bogdanm	0:9b334a45a8ff	1465
bogdanm	0:9b334a45a8ff	1466	/* Abort the SPI DMA tx Stream */
bogdanm	0:9b334a45a8ff	1467	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1470	}
bogdanm	0:9b334a45a8ff	1471	/* Abort the SPI DMA rx Stream */
bogdanm	0:9b334a45a8ff	1472	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1475	}
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1478	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1479	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	return HAL_OK;
bogdanm	0:9b334a45a8ff	1484	}
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	/**
bogdanm	0:9b334a45a8ff	1487	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1488	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1489	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1490	* @retval HAL status
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
bogdanm	0:9b334a45a8ff	1497	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	1498	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1499	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
bogdanm	0:9b334a45a8ff	1500	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
bogdanm	0:9b334a45a8ff	1501	{
bogdanm	0:9b334a45a8ff	1502	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1503	return;
bogdanm	0:9b334a45a8ff	1504	}
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
bogdanm	0:9b334a45a8ff	1507	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	1508	/* SPI in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1509	if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm	0:9b334a45a8ff	1510	{
bogdanm	0:9b334a45a8ff	1511	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1512	return;
bogdanm	0:9b334a45a8ff	1513	}
bogdanm	0:9b334a45a8ff	1514
bogdanm	0:9b334a45a8ff	1515	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1516	{
bogdanm	0:9b334a45a8ff	1517	/* SPI CRC error interrupt occurred ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1518	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1519	{
bogdanm	0:9b334a45a8ff	1520	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1521	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523	/* SPI Mode Fault error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1524	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1525	{
bogdanm	0:9b334a45a8ff	1526	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
bogdanm	0:9b334a45a8ff	1527	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/* SPI Overrun error interrupt occurred -----------------------------------*/
bogdanm	0:9b334a45a8ff	1531	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1532	{
bogdanm	0:9b334a45a8ff	1533	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1534	{
bogdanm	0:9b334a45a8ff	1535	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1536	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1537	}
bogdanm	0:9b334a45a8ff	1538	}
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/* SPI Frame error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1541	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1542	{
bogdanm	0:9b334a45a8ff	1543	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
bogdanm	0:9b334a45a8ff	1544	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1545	}
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1548	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1549	{
bogdanm	0:9b334a45a8ff	1550	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1551	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1552	}
bogdanm	0:9b334a45a8ff	1553	}
bogdanm	0:9b334a45a8ff	1554	}
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/**
bogdanm	0:9b334a45a8ff	1557	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1558	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1559	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1560	* @retval None
bogdanm	0:9b334a45a8ff	1561	*/
bogdanm	0:9b334a45a8ff	1562	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1563	{
bogdanm	0:9b334a45a8ff	1564	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1565	the HAL_SPI_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	}
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	/**
bogdanm	0:9b334a45a8ff	1570	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1571	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1572	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1573	* @retval None
bogdanm	0:9b334a45a8ff	1574	*/
bogdanm	0:9b334a45a8ff	1575	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1576	{
bogdanm	0:9b334a45a8ff	1577	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1578	the HAL_SPI_RxCpltCallback() could be implemented in the user file
bogdanm	0:9b334a45a8ff	1579	*/
bogdanm	0:9b334a45a8ff	1580	}
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/**
bogdanm	0:9b334a45a8ff	1583	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1584	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1585	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1586	* @retval None
bogdanm	0:9b334a45a8ff	1587	*/
bogdanm	0:9b334a45a8ff	1588	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1589	{
bogdanm	0:9b334a45a8ff	1590	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1591	the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593	}
bogdanm	0:9b334a45a8ff	1594
bogdanm	0:9b334a45a8ff	1595	/**
bogdanm	0:9b334a45a8ff	1596	* @brief Tx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1597	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1598	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1599	* @retval None
bogdanm	0:9b334a45a8ff	1600	*/
bogdanm	0:9b334a45a8ff	1601	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1602	{
bogdanm	0:9b334a45a8ff	1603	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1604	the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1605	*/
bogdanm	0:9b334a45a8ff	1606	}
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	/**
bogdanm	0:9b334a45a8ff	1609	* @brief Rx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1610	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1611	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1612	* @retval None
bogdanm	0:9b334a45a8ff	1613	*/
bogdanm	0:9b334a45a8ff	1614	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1615	{
bogdanm	0:9b334a45a8ff	1616	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1617	the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
bogdanm	0:9b334a45a8ff	1618	*/
bogdanm	0:9b334a45a8ff	1619	}
bogdanm	0:9b334a45a8ff	1620
bogdanm	0:9b334a45a8ff	1621	/**
bogdanm	0:9b334a45a8ff	1622	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1623	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1624	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1625	* @retval None
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1628	{
bogdanm	0:9b334a45a8ff	1629	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1630	the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
bogdanm	0:9b334a45a8ff	1631	*/
bogdanm	0:9b334a45a8ff	1632	}
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	/**
bogdanm	0:9b334a45a8ff	1635	* @brief SPI error callbacks
bogdanm	0:9b334a45a8ff	1636	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1637	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1638	* @retval None
bogdanm	0:9b334a45a8ff	1639	*/
bogdanm	0:9b334a45a8ff	1640	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1641	{
bogdanm	0:9b334a45a8ff	1642	/* NOTE : - This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1643	the HAL_SPI_ErrorCallback() could be implemented in the user file.
bogdanm	0:9b334a45a8ff	1644	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1645	and user can use HAL_SPI_GetError() API to check the latest error occurred.
bogdanm	0:9b334a45a8ff	1646	*/
bogdanm	0:9b334a45a8ff	1647	}
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/**
bogdanm	0:9b334a45a8ff	1650	* @}
bogdanm	0:9b334a45a8ff	1651	*/
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1654	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1655	*
bogdanm	0:9b334a45a8ff	1656	@verbatim
bogdanm	0:9b334a45a8ff	1657	===============================================================================
bogdanm	0:9b334a45a8ff	1658	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1659	===============================================================================
bogdanm	0:9b334a45a8ff	1660	[..]
bogdanm	0:9b334a45a8ff	1661	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1662	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1663	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1664	@endverbatim
bogdanm	0:9b334a45a8ff	1665	* @{
bogdanm	0:9b334a45a8ff	1666	*/
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/**
bogdanm	0:9b334a45a8ff	1669	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1670	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1671	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1672	* @retval HAL state
bogdanm	0:9b334a45a8ff	1673	*/
bogdanm	0:9b334a45a8ff	1674	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1675	{
bogdanm	0:9b334a45a8ff	1676	return hspi->State;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	/**
bogdanm	0:9b334a45a8ff	1680	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1681	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1682	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1683	* @retval SPI Error Code
bogdanm	0:9b334a45a8ff	1684	*/
bogdanm	0:9b334a45a8ff	1685	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1686	{
bogdanm	0:9b334a45a8ff	1687	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1688	}
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/**
bogdanm	0:9b334a45a8ff	1691	* @}
bogdanm	0:9b334a45a8ff	1692	*/
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	/**
bogdanm	0:9b334a45a8ff	1695	* @brief Interrupt Handler to close Tx transfer
bogdanm	0:9b334a45a8ff	1696	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1697	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1698	* @retval void
bogdanm	0:9b334a45a8ff	1699	*/
bogdanm	0:9b334a45a8ff	1700	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1701	{
bogdanm	0:9b334a45a8ff	1702	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1703	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1704	{
bogdanm	0:9b334a45a8ff	1705	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1706	}
bogdanm	0:9b334a45a8ff	1707
bogdanm	0:9b334a45a8ff	1708	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	1709	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	/* Disable ERR interrupt if Receive process is finished */
bogdanm	0:9b334a45a8ff	1712	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	1713	{
bogdanm	0:9b334a45a8ff	1714	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1715
bogdanm	0:9b334a45a8ff	1716	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1717	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1718	{
bogdanm	0:9b334a45a8ff	1719	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1720	}
bogdanm	0:9b334a45a8ff	1721
bogdanm	0:9b334a45a8ff	1722	/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1723	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1724	{
bogdanm	0:9b334a45a8ff	1725	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1726	}
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1729	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1730	{
bogdanm	0:9b334a45a8ff	1731	/* Check if we are in Tx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1732	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1733	{
bogdanm	0:9b334a45a8ff	1734	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1735	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1736	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738	else
bogdanm	0:9b334a45a8ff	1739	{
bogdanm	0:9b334a45a8ff	1740	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1741	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1742	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1743	}
bogdanm	0:9b334a45a8ff	1744	}
bogdanm	0:9b334a45a8ff	1745	else
bogdanm	0:9b334a45a8ff	1746	{
bogdanm	0:9b334a45a8ff	1747	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1748	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1749	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1750	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1751	}
bogdanm	0:9b334a45a8ff	1752	}
bogdanm	0:9b334a45a8ff	1753	}
bogdanm	0:9b334a45a8ff	1754
bogdanm	0:9b334a45a8ff	1755	/**
bogdanm	0:9b334a45a8ff	1756	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1757	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1758	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1759	* @retval void
bogdanm	0:9b334a45a8ff	1760	*/
bogdanm	0:9b334a45a8ff	1761	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1762	{
bogdanm	0:9b334a45a8ff	1763	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1764	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1767	}
bogdanm	0:9b334a45a8ff	1768	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1769	else
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	1772	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1773	}
bogdanm	0:9b334a45a8ff	1774	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	1775
bogdanm	0:9b334a45a8ff	1776	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1779	{
bogdanm	0:9b334a45a8ff	1780	/* calculate and transfer CRC on Tx line */
bogdanm	0:9b334a45a8ff	1781	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	1782	}
bogdanm	0:9b334a45a8ff	1783	SPI_TxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1784	}
bogdanm	0:9b334a45a8ff	1785	}
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	/**
bogdanm	0:9b334a45a8ff	1788	* @brief Interrupt Handler to close Rx transfer
bogdanm	0:9b334a45a8ff	1789	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1790	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1791	* @retval void
bogdanm	0:9b334a45a8ff	1792	*/
bogdanm	0:9b334a45a8ff	1793	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1794	{
bogdanm	0:9b334a45a8ff	1795	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1798	{
bogdanm	0:9b334a45a8ff	1799	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	1800	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1801	{
bogdanm	0:9b334a45a8ff	1802	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1803	}
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	/* Read CRC to reset RXNE flag */
bogdanm	0:9b334a45a8ff	1806	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1807	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	1810	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1811	{
bogdanm	0:9b334a45a8ff	1812	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1813	}
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1816	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1817	{
bogdanm	0:9b334a45a8ff	1818	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1821	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1822	}
bogdanm	0:9b334a45a8ff	1823	}
bogdanm	0:9b334a45a8ff	1824
bogdanm	0:9b334a45a8ff	1825	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1826	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
bogdanm	0:9b334a45a8ff	1827
bogdanm	0:9b334a45a8ff	1828	/* if Transmit process is finished */
bogdanm	0:9b334a45a8ff	1829	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
bogdanm	0:9b334a45a8ff	1830	{
bogdanm	0:9b334a45a8ff	1831	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1832	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1835	{
bogdanm	0:9b334a45a8ff	1836	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1837	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1838	}
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1841	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/* Check if we are in Rx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1844	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1845	{
bogdanm	0:9b334a45a8ff	1846	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1847	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1848	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1849	}
bogdanm	0:9b334a45a8ff	1850	else
bogdanm	0:9b334a45a8ff	1851	{
bogdanm	0:9b334a45a8ff	1852	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1853	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1854	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856	}
bogdanm	0:9b334a45a8ff	1857	else
bogdanm	0:9b334a45a8ff	1858	{
bogdanm	0:9b334a45a8ff	1859	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1860	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1861	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1862	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1863	}
bogdanm	0:9b334a45a8ff	1864	}
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @brief Interrupt Handler to receive amount of data in 2Lines mode
bogdanm	0:9b334a45a8ff	1869	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1870	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1871	* @retval void
bogdanm	0:9b334a45a8ff	1872	*/
bogdanm	0:9b334a45a8ff	1873	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1874	{
bogdanm	0:9b334a45a8ff	1875	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1876	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1877	{
bogdanm	0:9b334a45a8ff	1878	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1879	}
bogdanm	0:9b334a45a8ff	1880	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1881	else
bogdanm	0:9b334a45a8ff	1882	{
bogdanm	0:9b334a45a8ff	1883	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1884	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1885	}
bogdanm	0:9b334a45a8ff	1886	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	if(hspi->RxXferCount==0)
bogdanm	0:9b334a45a8ff	1889	{
bogdanm	0:9b334a45a8ff	1890	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1891	}
bogdanm	0:9b334a45a8ff	1892	}
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	/**
bogdanm	0:9b334a45a8ff	1895	* @brief Interrupt Handler to receive amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1896	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1897	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1898	* @retval void
bogdanm	0:9b334a45a8ff	1899	*/
bogdanm	0:9b334a45a8ff	1900	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1901	{
bogdanm	0:9b334a45a8ff	1902	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1903	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1904	{
bogdanm	0:9b334a45a8ff	1905	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1908	else
bogdanm	0:9b334a45a8ff	1909	{
bogdanm	0:9b334a45a8ff	1910	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1911	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1912	}
bogdanm	0:9b334a45a8ff	1913	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	1916	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	1917	{
bogdanm	0:9b334a45a8ff	1918	/* Set CRC Next to calculate CRC on Rx side */
bogdanm	0:9b334a45a8ff	1919	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	1920	}
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1923	{
bogdanm	0:9b334a45a8ff	1924	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	}
bogdanm	0:9b334a45a8ff	1927
bogdanm	0:9b334a45a8ff	1928	/**
bogdanm	0:9b334a45a8ff	1929	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	1930	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1931	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1932	* @retval None
bogdanm	0:9b334a45a8ff	1933	*/
bogdanm	0:9b334a45a8ff	1934	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1935	{
bogdanm	0:9b334a45a8ff	1936	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	1939	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1940	{
bogdanm	0:9b334a45a8ff	1941	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1942	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1943	{
bogdanm	0:9b334a45a8ff	1944	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1945	}
bogdanm	0:9b334a45a8ff	1946	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1947	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1948
bogdanm	0:9b334a45a8ff	1949	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1950	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1951	{
bogdanm	0:9b334a45a8ff	1952	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	1953	}
bogdanm	0:9b334a45a8ff	1954
bogdanm	0:9b334a45a8ff	1955	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1958	}
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	/* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1961	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1962	{
bogdanm	0:9b334a45a8ff	1963	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1964	}
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1967	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1968	{
bogdanm	0:9b334a45a8ff	1969	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1970	}
bogdanm	0:9b334a45a8ff	1971	else
bogdanm	0:9b334a45a8ff	1972	{
bogdanm	0:9b334a45a8ff	1973	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975	}
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	/**
bogdanm	0:9b334a45a8ff	1978	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	1979	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1980	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1981	* @retval None
bogdanm	0:9b334a45a8ff	1982	*/
bogdanm	0:9b334a45a8ff	1983	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1984	{
bogdanm	0:9b334a45a8ff	1985	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1988	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	1989	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1990	{
bogdanm	0:9b334a45a8ff	1991	if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1992	{
bogdanm	0:9b334a45a8ff	1993	SPI_DMAEndTransmitReceive(hspi);
bogdanm	0:9b334a45a8ff	1994	}
bogdanm	0:9b334a45a8ff	1995	/* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
bogdanm	0:9b334a45a8ff	1996	else
bogdanm	0:9b334a45a8ff	1997	{
bogdanm	0:9b334a45a8ff	1998	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1999	{
bogdanm	0:9b334a45a8ff	2000	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2001	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2002	}
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2005	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2008
bogdanm	0:9b334a45a8ff	2009	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2010	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2011	{
bogdanm	0:9b334a45a8ff	2012	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2013	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2014	{
bogdanm	0:9b334a45a8ff	2015	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2016	}
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	/* Read CRC */
bogdanm	0:9b334a45a8ff	2019	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2020	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2021
bogdanm	0:9b334a45a8ff	2022	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	2023	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2024	{
bogdanm	0:9b334a45a8ff	2025	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2026	}
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2029	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2030	{
bogdanm	0:9b334a45a8ff	2031	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2032	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2033	}
bogdanm	0:9b334a45a8ff	2034	}
bogdanm	0:9b334a45a8ff	2035	}
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2040	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2041	{
bogdanm	0:9b334a45a8ff	2042	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2043	}
bogdanm	0:9b334a45a8ff	2044	else
bogdanm	0:9b334a45a8ff	2045	{
bogdanm	0:9b334a45a8ff	2046	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2047	}
bogdanm	0:9b334a45a8ff	2048	}
bogdanm	0:9b334a45a8ff	2049	else
bogdanm	0:9b334a45a8ff	2050	{
bogdanm	0:9b334a45a8ff	2051	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2052	}
bogdanm	0:9b334a45a8ff	2053	}
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	/**
bogdanm	0:9b334a45a8ff	2056	* @brief End DMA SPI transmit receive process
bogdanm	0:9b334a45a8ff	2057	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2058	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2059	* @retval None
bogdanm	0:9b334a45a8ff	2060	*/
bogdanm	0:9b334a45a8ff	2061	static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2062	{
bogdanm	0:9b334a45a8ff	2063	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	2064
bogdanm	0:9b334a45a8ff	2065	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2066	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2067	{
bogdanm	0:9b334a45a8ff	2068	/* Check if CRC is done on going (RXNE flag set) */
bogdanm	0:9b334a45a8ff	2069	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
bogdanm	0:9b334a45a8ff	2070	{
bogdanm	0:9b334a45a8ff	2071	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2072	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2075	}
bogdanm	0:9b334a45a8ff	2076	}
bogdanm	0:9b334a45a8ff	2077	/* Read CRC */
bogdanm	0:9b334a45a8ff	2078	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2079	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2080
bogdanm	0:9b334a45a8ff	2081	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2082	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2083	{
bogdanm	0:9b334a45a8ff	2084	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2085	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2086	}
bogdanm	0:9b334a45a8ff	2087	}
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2090	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2091	{
bogdanm	0:9b334a45a8ff	2092	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2093	}
bogdanm	0:9b334a45a8ff	2094	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2095	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2096
bogdanm	0:9b334a45a8ff	2097	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2098	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2099	{
bogdanm	0:9b334a45a8ff	2100	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2101	}
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2104	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2107	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2108	}
bogdanm	0:9b334a45a8ff	2109
bogdanm	0:9b334a45a8ff	2110	/**
bogdanm	0:9b334a45a8ff	2111	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2112	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	19:112740acecfa	2113	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2114	* @retval None
bogdanm	0:9b334a45a8ff	2115	*/
bogdanm	0:9b334a45a8ff	2116	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2117	{
bogdanm	0:9b334a45a8ff	2118	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2119	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	2120	{ /**/
bogdanm	0:9b334a45a8ff	2121	SPI_DMAEndTransmitReceive(hspi);
bogdanm	0:9b334a45a8ff	2122
bogdanm	0:9b334a45a8ff	2123	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2124
bogdanm	0:9b334a45a8ff	2125	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2126	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2127	{
bogdanm	0:9b334a45a8ff	2128	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2129	}
bogdanm	0:9b334a45a8ff	2130	else
bogdanm	0:9b334a45a8ff	2131	{
bogdanm	0:9b334a45a8ff	2132	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2133	}
bogdanm	0:9b334a45a8ff	2134	}
bogdanm	0:9b334a45a8ff	2135	else
bogdanm	0:9b334a45a8ff	2136	{
bogdanm	0:9b334a45a8ff	2137	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2138	}
bogdanm	0:9b334a45a8ff	2139	}
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	/**
bogdanm	0:9b334a45a8ff	2142	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2143	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2144	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2145	* @retval None
bogdanm	0:9b334a45a8ff	2146	*/
bogdanm	0:9b334a45a8ff	2147	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2148	{
bogdanm	0:9b334a45a8ff	2149	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2150
bogdanm	0:9b334a45a8ff	2151	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2152	}
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	/**
bogdanm	0:9b334a45a8ff	2155	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2156	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2157	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2158	* @retval None
bogdanm	0:9b334a45a8ff	2159	*/
bogdanm	0:9b334a45a8ff	2160	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2161	{
bogdanm	0:9b334a45a8ff	2162	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2163
bogdanm	0:9b334a45a8ff	2164	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2165	}
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	/**
bogdanm	0:9b334a45a8ff	2168	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2169	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2170	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2171	* @retval None
bogdanm	0:9b334a45a8ff	2172	*/
bogdanm	0:9b334a45a8ff	2173	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2174	{
bogdanm	0:9b334a45a8ff	2175	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2176
bogdanm	0:9b334a45a8ff	2177	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2178	}
bogdanm	0:9b334a45a8ff	2179
bogdanm	0:9b334a45a8ff	2180	/**
bogdanm	0:9b334a45a8ff	2181	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2182	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2183	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2184	* @retval None
bogdanm	0:9b334a45a8ff	2185	*/
bogdanm	0:9b334a45a8ff	2186	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2187	{
bogdanm	0:9b334a45a8ff	2188	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2189	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2190	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2191	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2192	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	2193	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2194	}
bogdanm	0:9b334a45a8ff	2195
bogdanm	0:9b334a45a8ff	2196	/**
bogdanm	0:9b334a45a8ff	2197	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2198	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2199	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2200	* @param Flag: SPI flag to check
bogdanm	0:9b334a45a8ff	2201	* @param Status: Flag status to check: RESET or set
bogdanm	0:9b334a45a8ff	2202	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2203	* @retval HAL status
bogdanm	0:9b334a45a8ff	2204	*/
bogdanm	0:9b334a45a8ff	2205	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2206	{
bogdanm	0:9b334a45a8ff	2207	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	/* Get tick */
bogdanm	0:9b334a45a8ff	2210	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2211
bogdanm	0:9b334a45a8ff	2212	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	2213	if(Status == RESET)
bogdanm	0:9b334a45a8ff	2214	{
bogdanm	0:9b334a45a8ff	2215	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
bogdanm	0:9b334a45a8ff	2216	{
bogdanm	0:9b334a45a8ff	2217	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2218	{
bogdanm	0:9b334a45a8ff	2219	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2220	{
bogdanm	0:9b334a45a8ff	2221	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2222	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2223	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2224
bogdanm	0:9b334a45a8ff	2225	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2226	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2227
bogdanm	0:9b334a45a8ff	2228	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2229	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2230
bogdanm	0:9b334a45a8ff	2231	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2232	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2233	{
bogdanm	0:9b334a45a8ff	2234	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2235	}
bogdanm	0:9b334a45a8ff	2236
bogdanm	0:9b334a45a8ff	2237	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2238
bogdanm	0:9b334a45a8ff	2239	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2240	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2241
bogdanm	0:9b334a45a8ff	2242	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2243	}
bogdanm	0:9b334a45a8ff	2244	}
bogdanm	0:9b334a45a8ff	2245	}
bogdanm	0:9b334a45a8ff	2246	}
bogdanm	0:9b334a45a8ff	2247	else
bogdanm	0:9b334a45a8ff	2248	{
bogdanm	0:9b334a45a8ff	2249	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
bogdanm	0:9b334a45a8ff	2250	{
bogdanm	0:9b334a45a8ff	2251	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2252	{
bogdanm	0:9b334a45a8ff	2253	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2254	{
bogdanm	0:9b334a45a8ff	2255	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2256	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2257	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2258
bogdanm	0:9b334a45a8ff	2259	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2260	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2261
bogdanm	0:9b334a45a8ff	2262	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2263	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2266	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2267	{
bogdanm	0:9b334a45a8ff	2268	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2269	}
bogdanm	0:9b334a45a8ff	2270
bogdanm	0:9b334a45a8ff	2271	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2274	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2275
bogdanm	0:9b334a45a8ff	2276	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2277	}
bogdanm	0:9b334a45a8ff	2278	}
bogdanm	0:9b334a45a8ff	2279	}
bogdanm	0:9b334a45a8ff	2280	}
bogdanm	0:9b334a45a8ff	2281	return HAL_OK;
bogdanm	0:9b334a45a8ff	2282	}
bogdanm	0:9b334a45a8ff	2283
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285	/**
bogdanm	0:9b334a45a8ff	2286	* @}
bogdanm	0:9b334a45a8ff	2287	*/
bogdanm	0:9b334a45a8ff	2288
bogdanm	0:9b334a45a8ff	2289	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2290	/**
bogdanm	0:9b334a45a8ff	2291	* @}
bogdanm	0:9b334a45a8ff	2292	*/
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	/**
bogdanm	0:9b334a45a8ff	2295	* @}
bogdanm	0:9b334a45a8ff	2296	*/
bogdanm	0:9b334a45a8ff	2297
bogdanm	0:9b334a45a8ff	2298	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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