mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_qspi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief QSPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the QuadSPI interface (QSPI).
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + Indirect functional mode management
bogdanm	0:9b334a45a8ff	13	* + Memory-mapped functional mode management
bogdanm	0:9b334a45a8ff	14	* + Auto-polling functional mode management
bogdanm	0:9b334a45a8ff	15	* + Interrupts and flags management
bogdanm	0:9b334a45a8ff	16	* + DMA channel configuration for indirect functional mode
bogdanm	0:9b334a45a8ff	17	* + Errors management and abort functionality
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	@verbatim
bogdanm	0:9b334a45a8ff	20	===============================================================================
bogdanm	0:9b334a45a8ff	21	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	22	===============================================================================
bogdanm	0:9b334a45a8ff	23	[..]
bogdanm	0:9b334a45a8ff	24	* Initialization *
bogdanm	0:9b334a45a8ff	25	======================
bogdanm	0:9b334a45a8ff	26	[..]
bogdanm	0:9b334a45a8ff	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
bogdanm	0:9b334a45a8ff	28	(+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	29	(+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	30	(+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	31	(+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
bogdanm	0:9b334a45a8ff	32	(+) If interrupt mode is used, enable and configure QuadSPI global
bogdanm	0:9b334a45a8ff	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	34	(+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
bogdanm	0:9b334a45a8ff	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
bogdanm	0:9b334a45a8ff	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
bogdanm	0:9b334a45a8ff	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
bogdanm	0:9b334a45a8ff	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	* Indirect functional mode *
bogdanm	0:9b334a45a8ff	42	================================
bogdanm	0:9b334a45a8ff	43	[..]
bogdanm	0:9b334a45a8ff	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
bogdanm	0:9b334a45a8ff	45	functions :
bogdanm	0:9b334a45a8ff	46	(+) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	47	(+) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	48	(+) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	49	bytes values.
bogdanm	0:9b334a45a8ff	50	(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	51	(+) Data phase : the mode used and if present the number of bytes.
bogdanm	0:9b334a45a8ff	52	(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	53	if activated.
bogdanm	0:9b334a45a8ff	54	(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	55	(#) If no data is required for the command, it is sent directly to the memory :
bogdanm	0:9b334a45a8ff	56	(+) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	57	(+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
bogdanm	0:9b334a45a8ff	59	HAL_QSPI_Transmit_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	60	(+) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	61	(+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	63	(+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
bogdanm	0:9b334a45a8ff	66	HAL_QSPI_Receive_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	67	(+) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	68	(+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	70	(+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	* Auto-polling functional mode *
bogdanm	0:9b334a45a8ff	74	====================================
bogdanm	0:9b334a45a8ff	75	[..]
bogdanm	0:9b334a45a8ff	76	(#) Configure the command sequence and the auto-polling functional mode using the
bogdanm	0:9b334a45a8ff	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
bogdanm	0:9b334a45a8ff	78	(+) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	79	(+) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	80	(+) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	81	bytes values.
bogdanm	0:9b334a45a8ff	82	(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	83	(+) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	84	(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	85	if activated.
bogdanm	0:9b334a45a8ff	86	(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	87	(+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
bogdanm	0:9b334a45a8ff	88	the polling interval and the automatic stop activation.
bogdanm	0:9b334a45a8ff	89	(#) After the configuration :
bogdanm	0:9b334a45a8ff	90	(+) In polling mode, the output of the function is done when the status match is reached. The
bogdanm	0:9b334a45a8ff	91	automatic stop is activated to avoid an infinite loop.
bogdanm	0:9b334a45a8ff	92	(+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	* Memory-mapped functional mode *
bogdanm	0:9b334a45a8ff	95	=====================================
bogdanm	0:9b334a45a8ff	96	[..]
bogdanm	0:9b334a45a8ff	97	(#) Configure the command sequence and the memory-mapped functional mode using the
bogdanm	0:9b334a45a8ff	98	HAL_QSPI_MemoryMapped() functions :
bogdanm	0:9b334a45a8ff	99	(+) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	100	(+) Address phase : the mode used and the size.
bogdanm	0:9b334a45a8ff	101	(+) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	102	bytes values.
bogdanm	0:9b334a45a8ff	103	(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	104	(+) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	105	(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	106	if activated.
bogdanm	0:9b334a45a8ff	107	(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	108	(+) The timeout activation and the timeout period.
bogdanm	0:9b334a45a8ff	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
bogdanm	0:9b334a45a8ff	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	* Errors management and abort functionality *
bogdanm	0:9b334a45a8ff	113	==================================================
bogdanm	0:9b334a45a8ff	114	[..]
bogdanm	0:9b334a45a8ff	115	(#) HAL_QSPI_GetError() function gives the error rised during the last operation.
bogdanm	0:9b334a45a8ff	116	(#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
bogdanm	0:9b334a45a8ff	117	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	* Workarounds linked to Silicon Limitation *
bogdanm	0:9b334a45a8ff	120	====================================================
bogdanm	0:9b334a45a8ff	121	[..]
bogdanm	0:9b334a45a8ff	122	(#) Workarounds Implemented inside HAL Driver
bogdanm	0:9b334a45a8ff	123	(+) Extra data written in the FIFO at the end of a read transfer
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	@endverbatim
bogdanm	0:9b334a45a8ff	126	******************************************************************************
bogdanm	0:9b334a45a8ff	127	* @attention
bogdanm	0:9b334a45a8ff	128	*
bogdanm	0:9b334a45a8ff	129	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	130	*
bogdanm	0:9b334a45a8ff	131	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	132	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	133	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	134	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	136	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	137	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	139	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	140	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	141	*
bogdanm	0:9b334a45a8ff	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	152	*
bogdanm	0:9b334a45a8ff	153	******************************************************************************
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	160	* @{
bogdanm	0:9b334a45a8ff	161	*/
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/** @defgroup QSPI QSPI
bogdanm	0:9b334a45a8ff	164	* @brief HAL QSPI module driver
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167	#ifdef HAL_QSPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	168
mbed_official	19:112740acecfa	169	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	172	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	173	/** @addtogroup QSPI_Private_Constants
bogdanm	0:9b334a45a8ff	174	* @{
bogdanm	0:9b334a45a8ff	175	*/
bogdanm	0:9b334a45a8ff	176	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
bogdanm	0:9b334a45a8ff	177	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
bogdanm	0:9b334a45a8ff	178	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
bogdanm	0:9b334a45a8ff	179	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
bogdanm	0:9b334a45a8ff	180	/**
bogdanm	0:9b334a45a8ff	181	* @}
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	185	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
bogdanm	0:9b334a45a8ff	186	* @{
bogdanm	0:9b334a45a8ff	187	*/
bogdanm	0:9b334a45a8ff	188	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	189	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
bogdanm	0:9b334a45a8ff	190	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
bogdanm	0:9b334a45a8ff	191	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	192	/**
bogdanm	0:9b334a45a8ff	193	* @}
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	197	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	198	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
bogdanm	0:9b334a45a8ff	199	* @{
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	202	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	203	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	204	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	205	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	206	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	207	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @}
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
bogdanm	0:9b334a45a8ff	215	* @{
bogdanm	0:9b334a45a8ff	216	*/
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	219	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	220	*
bogdanm	0:9b334a45a8ff	221	@verbatim
bogdanm	0:9b334a45a8ff	222	===============================================================================
bogdanm	0:9b334a45a8ff	223	##### Initialization and Configuration functions #####
bogdanm	0:9b334a45a8ff	224	===============================================================================
bogdanm	0:9b334a45a8ff	225	[..]
bogdanm	0:9b334a45a8ff	226	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	227	(+) Initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	228	(+) De-initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	@endverbatim
bogdanm	0:9b334a45a8ff	231	* @{
bogdanm	0:9b334a45a8ff	232	*/
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/**
bogdanm	0:9b334a45a8ff	235	* @brief Initializes the QSPI mode according to the specified parameters
bogdanm	0:9b334a45a8ff	236	* in the QSPI_InitTypeDef and creates the associated handle.
bogdanm	0:9b334a45a8ff	237	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	238	* @retval HAL status
bogdanm	0:9b334a45a8ff	239	*/
bogdanm	0:9b334a45a8ff	240	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	241	{
bogdanm	0:9b334a45a8ff	242	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	245	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	248	}
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/* Check the parameters */
bogdanm	0:9b334a45a8ff	251	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
bogdanm	0:9b334a45a8ff	252	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	253	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
bogdanm	0:9b334a45a8ff	254	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
bogdanm	0:9b334a45a8ff	255	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
bogdanm	0:9b334a45a8ff	257	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	258	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
bogdanm	0:9b334a45a8ff	261	{
bogdanm	0:9b334a45a8ff	262	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
bogdanm	0:9b334a45a8ff	263	}
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	/* Process locked */
bogdanm	0:9b334a45a8ff	266	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	if(hqspi->State == HAL_QSPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	269	{
bogdanm	0:9b334a45a8ff	270	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	271	hqspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* Init the low level hardware : GPIO, CLOCK */
bogdanm	0:9b334a45a8ff	274	HAL_QSPI_MspInit(hqspi);
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/* Configure the default timeout for the QSPI memory access */
bogdanm	0:9b334a45a8ff	277	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
bogdanm	0:9b334a45a8ff	278	}
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	/* Configure QSPI FIFO Threshold */
bogdanm	0:9b334a45a8ff	281	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	284	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	287	{
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Configure QSPI Clock Prescaler and Sample Shift */
bogdanm	0:9b334a45a8ff	290	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
bogdanm	0:9b334a45a8ff	293	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
bogdanm	0:9b334a45a8ff	294	((hqspi->Init.FlashSize << 16) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	/* Enable the QSPI peripheral */
bogdanm	0:9b334a45a8ff	297	__HAL_QSPI_ENABLE(hqspi);
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	300	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	303	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	304	}
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Release Lock */
bogdanm	0:9b334a45a8ff	307	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* Return function status */
bogdanm	0:9b334a45a8ff	310	return status;
bogdanm	0:9b334a45a8ff	311	}
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/**
bogdanm	0:9b334a45a8ff	314	* @brief DeInitializes the QSPI peripheral
bogdanm	0:9b334a45a8ff	315	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	316	* @retval HAL status
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	319	{
bogdanm	0:9b334a45a8ff	320	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	321	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	322	{
bogdanm	0:9b334a45a8ff	323	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	324	}
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/* Process locked */
bogdanm	0:9b334a45a8ff	327	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/* Disable the QSPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	330	__HAL_QSPI_DISABLE(hqspi);
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	333	HAL_QSPI_MspDeInit(hqspi);
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	336	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	339	hqspi->State = HAL_QSPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	/* Release Lock */
bogdanm	0:9b334a45a8ff	342	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	return HAL_OK;
bogdanm	0:9b334a45a8ff	345	}
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	/**
bogdanm	0:9b334a45a8ff	348	* @brief QSPI MSP Init
bogdanm	0:9b334a45a8ff	349	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	350	* @retval None
bogdanm	0:9b334a45a8ff	351	*/
bogdanm	0:9b334a45a8ff	352	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	353	{
bogdanm	0:9b334a45a8ff	354	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	355	the HAL_QSPI_MspInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	356	*/
bogdanm	0:9b334a45a8ff	357	}
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/**
bogdanm	0:9b334a45a8ff	360	* @brief QSPI MSP DeInit
bogdanm	0:9b334a45a8ff	361	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	362	* @retval None
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	365	{
bogdanm	0:9b334a45a8ff	366	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	367	the HAL_QSPI_MspDeInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	368	*/
bogdanm	0:9b334a45a8ff	369	}
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	/**
bogdanm	0:9b334a45a8ff	372	* @}
bogdanm	0:9b334a45a8ff	373	*/
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	376	* @brief QSPI Transmit/Receive functions
bogdanm	0:9b334a45a8ff	377	*
bogdanm	0:9b334a45a8ff	378	@verbatim
bogdanm	0:9b334a45a8ff	379	===============================================================================
mbed_official	19:112740acecfa	380	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	381	===============================================================================
bogdanm	0:9b334a45a8ff	382	[..]
bogdanm	0:9b334a45a8ff	383	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	384	(+) Handle the interrupts.
bogdanm	0:9b334a45a8ff	385	(+) Handle the command sequence.
bogdanm	0:9b334a45a8ff	386	(+) Transmit data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	387	(+) Receive data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	388	(+) Manage the auto-polling functional mode.
bogdanm	0:9b334a45a8ff	389	(+) Manage the memory-mapped functional mode.
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	@endverbatim
bogdanm	0:9b334a45a8ff	392	* @{
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	/**
bogdanm	0:9b334a45a8ff	396	* @brief This function handles QSPI interrupt request.
bogdanm	0:9b334a45a8ff	397	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	398	* @retval None.
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	__IO uint32_t *data_reg;
bogdanm	0:9b334a45a8ff	403	uint32_t flag = 0, itsource = 0;
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	/* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	406	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
bogdanm	0:9b334a45a8ff	407	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	410	{
bogdanm	0:9b334a45a8ff	411	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	/* Transmission process */
bogdanm	0:9b334a45a8ff	416	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	417	{
bogdanm	0:9b334a45a8ff	418	if (hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	419	{
bogdanm	0:9b334a45a8ff	420	/* Fill the FIFO until it is full */
bogdanm	0:9b334a45a8ff	421	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	422	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	423	}
bogdanm	0:9b334a45a8ff	424	else
bogdanm	0:9b334a45a8ff	425	{
bogdanm	0:9b334a45a8ff	426	/* No more data available for the transfer */
bogdanm	0:9b334a45a8ff	427	break;
bogdanm	0:9b334a45a8ff	428	}
bogdanm	0:9b334a45a8ff	429	}
bogdanm	0:9b334a45a8ff	430	}
bogdanm	0:9b334a45a8ff	431	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	432	{
bogdanm	0:9b334a45a8ff	433	/* Receiving Process */
bogdanm	0:9b334a45a8ff	434	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	435	{
bogdanm	0:9b334a45a8ff	436	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	437	{
bogdanm	0:9b334a45a8ff	438	/* Read the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	439	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	440	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	441	}
bogdanm	0:9b334a45a8ff	442	else
bogdanm	0:9b334a45a8ff	443	{
bogdanm	0:9b334a45a8ff	444	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	445	break;
bogdanm	0:9b334a45a8ff	446	}
bogdanm	0:9b334a45a8ff	447	}
bogdanm	0:9b334a45a8ff	448	}
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/* FIFO Threshold callback */
bogdanm	0:9b334a45a8ff	451	HAL_QSPI_FifoThresholdCallback(hqspi);
bogdanm	0:9b334a45a8ff	452	}
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
bogdanm	0:9b334a45a8ff	455	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	456	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	459	{
bogdanm	0:9b334a45a8ff	460	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	461	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	464	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/* Transfer complete callback */
bogdanm	0:9b334a45a8ff	467	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	470	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/* TX Complete callback */
bogdanm	0:9b334a45a8ff	473	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	474	}
bogdanm	0:9b334a45a8ff	475	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	476	{
bogdanm	0:9b334a45a8ff	477	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	478	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	481	{
bogdanm	0:9b334a45a8ff	482	/* Read the last data received in the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	483	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	484	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	485	}
bogdanm	0:9b334a45a8ff	486	else
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	489	break;
bogdanm	0:9b334a45a8ff	490	}
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	494	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/* RX Complete callback */
bogdanm	0:9b334a45a8ff	497	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	498	}
bogdanm	0:9b334a45a8ff	499	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	/* Command Complete callback */
bogdanm	0:9b334a45a8ff	502	HAL_QSPI_CmdCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	506	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	507	}
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* QSPI Status Match interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	510	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	511	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	514	{
bogdanm	0:9b334a45a8ff	515	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	516	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/* Check if the automatic poll mode stop is activated */
bogdanm	0:9b334a45a8ff	519	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	/* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
bogdanm	0:9b334a45a8ff	522	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	525	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	526	}
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/* Status match callback */
bogdanm	0:9b334a45a8ff	529	HAL_QSPI_StatusMatchCallback(hqspi);
bogdanm	0:9b334a45a8ff	530	}
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	533	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	534	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	537	{
bogdanm	0:9b334a45a8ff	538	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	539	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/* Disable all the QSPI Interrupts */
bogdanm	0:9b334a45a8ff	542	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* Set error code */
bogdanm	0:9b334a45a8ff	545	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	548	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	/* Error callback */
bogdanm	0:9b334a45a8ff	551	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	552	}
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	/* QSPI Time out interrupt occurred -----------------------------------------*/
bogdanm	0:9b334a45a8ff	555	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	556	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	559	{
bogdanm	0:9b334a45a8ff	560	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	561	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Time out callback */
bogdanm	0:9b334a45a8ff	564	HAL_QSPI_TimeOutCallback(hqspi);
bogdanm	0:9b334a45a8ff	565	}
bogdanm	0:9b334a45a8ff	566	}
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	/**
bogdanm	0:9b334a45a8ff	569	* @brief Sets the command configuration.
bogdanm	0:9b334a45a8ff	570	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	571	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	572	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	573	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	574	* @retval HAL status
bogdanm	0:9b334a45a8ff	575	*/
bogdanm	0:9b334a45a8ff	576	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/* Check the parameters */
bogdanm	0:9b334a45a8ff	581	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	582	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	583	{
bogdanm	0:9b334a45a8ff	584	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	585	}
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	588	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	589	{
bogdanm	0:9b334a45a8ff	590	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	591	}
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	594	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	595	{
bogdanm	0:9b334a45a8ff	596	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	600	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	603	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	604	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/* Process locked */
bogdanm	0:9b334a45a8ff	607	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	614	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	617	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	620	{
bogdanm	0:9b334a45a8ff	621	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	622	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	625	{
bogdanm	0:9b334a45a8ff	626	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	627	so wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	628	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	629	{
bogdanm	0:9b334a45a8ff	630	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	631	}
bogdanm	0:9b334a45a8ff	632	else
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	637	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	}
bogdanm	0:9b334a45a8ff	641	else
bogdanm	0:9b334a45a8ff	642	{
bogdanm	0:9b334a45a8ff	643	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	644	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	645	}
bogdanm	0:9b334a45a8ff	646	}
bogdanm	0:9b334a45a8ff	647	}
bogdanm	0:9b334a45a8ff	648	else
bogdanm	0:9b334a45a8ff	649	{
bogdanm	0:9b334a45a8ff	650	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	651	}
bogdanm	0:9b334a45a8ff	652
bogdanm	0:9b334a45a8ff	653	/* Process unlocked */
bogdanm	0:9b334a45a8ff	654	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	/* Return function status */
bogdanm	0:9b334a45a8ff	657	return status;
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/**
bogdanm	0:9b334a45a8ff	661	* @brief Sets the command configuration in interrupt mode.
bogdanm	0:9b334a45a8ff	662	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	663	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	664	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	665	* @retval HAL status
bogdanm	0:9b334a45a8ff	666	*/
bogdanm	0:9b334a45a8ff	667	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
bogdanm	0:9b334a45a8ff	668	{
bogdanm	0:9b334a45a8ff	669	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Check the parameters */
bogdanm	0:9b334a45a8ff	672	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	673	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	674	{
bogdanm	0:9b334a45a8ff	675	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	679	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	685	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	688	}
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	691	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	692
bogdanm	0:9b334a45a8ff	693	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	694	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	695	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Process locked */
bogdanm	0:9b334a45a8ff	698	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	701	{
bogdanm	0:9b334a45a8ff	702	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	705	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	708	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	713	{
bogdanm	0:9b334a45a8ff	714	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	715	so activate TC and TE interrupts */
bogdanm	0:9b334a45a8ff	716	/* Enable the QSPI Transfer Error Interrupt */
bogdanm	0:9b334a45a8ff	717	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	718	}
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	721	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	722
bogdanm	0:9b334a45a8ff	723	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	724	{
bogdanm	0:9b334a45a8ff	725	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	726	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	727	}
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729	}
bogdanm	0:9b334a45a8ff	730	else
bogdanm	0:9b334a45a8ff	731	{
bogdanm	0:9b334a45a8ff	732	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	733	}
bogdanm	0:9b334a45a8ff	734
bogdanm	0:9b334a45a8ff	735	/* Process unlocked */
bogdanm	0:9b334a45a8ff	736	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	/* Return function status */
bogdanm	0:9b334a45a8ff	739	return status;
bogdanm	0:9b334a45a8ff	740	}
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	/**
bogdanm	0:9b334a45a8ff	743	* @brief Transmit an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	744	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	745	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	746	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	747	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	748	* @retval HAL status
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	753	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	/* Process locked */
bogdanm	0:9b334a45a8ff	756	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	if(pData != NULL )
bogdanm	0:9b334a45a8ff	761	{
bogdanm	0:9b334a45a8ff	762	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/* Update state */
bogdanm	0:9b334a45a8ff	765	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	768	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	769	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	770	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	773	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	while(hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	776	{
bogdanm	0:9b334a45a8ff	777	/* Wait until FT flag is set to send data */
bogdanm	0:9b334a45a8ff	778	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	779	{
bogdanm	0:9b334a45a8ff	780	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	781	break;
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	785	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	791	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	794	}
bogdanm	0:9b334a45a8ff	795	else
bogdanm	0:9b334a45a8ff	796	{
bogdanm	0:9b334a45a8ff	797	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	798	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	801	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803	}
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	806	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808	else
bogdanm	0:9b334a45a8ff	809	{
bogdanm	0:9b334a45a8ff	810	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	}
bogdanm	0:9b334a45a8ff	813	else
bogdanm	0:9b334a45a8ff	814	{
bogdanm	0:9b334a45a8ff	815	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	816	}
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818	/* Process unlocked */
bogdanm	0:9b334a45a8ff	819	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	return status;
bogdanm	0:9b334a45a8ff	822	}
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/**
bogdanm	0:9b334a45a8ff	826	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	827	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	828	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	829	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	830	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	831	* @retval HAL status
bogdanm	0:9b334a45a8ff	832	*/
bogdanm	0:9b334a45a8ff	833	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	834	{
bogdanm	0:9b334a45a8ff	835	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	836	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	837	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/* Process locked */
bogdanm	0:9b334a45a8ff	840	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	843	{
bogdanm	0:9b334a45a8ff	844	if(pData != NULL )
bogdanm	0:9b334a45a8ff	845	{
bogdanm	0:9b334a45a8ff	846	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	/* Update state */
bogdanm	0:9b334a45a8ff	849	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	852	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	853	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	854	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	857	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	860	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	while(hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	863	{
bogdanm	0:9b334a45a8ff	864	/* Wait until FT or TC flag is set to read received data */
bogdanm	0:9b334a45a8ff	865	if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	866	{
bogdanm	0:9b334a45a8ff	867	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	868	break;
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	872	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	873	}
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	876	{
bogdanm	0:9b334a45a8ff	877	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	878	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	881	}
bogdanm	0:9b334a45a8ff	882	else
bogdanm	0:9b334a45a8ff	883	{
bogdanm	0:9b334a45a8ff	884	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	885	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	888	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	889	}
bogdanm	0:9b334a45a8ff	890	}
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	893	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895	else
bogdanm	0:9b334a45a8ff	896	{
bogdanm	0:9b334a45a8ff	897	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899	}
bogdanm	0:9b334a45a8ff	900	else
bogdanm	0:9b334a45a8ff	901	{
bogdanm	0:9b334a45a8ff	902	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	903	}
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/* Process unlocked */
bogdanm	0:9b334a45a8ff	906	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	return status;
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/**
bogdanm	0:9b334a45a8ff	912	* @brief Send an amount of data in interrupt mode
bogdanm	0:9b334a45a8ff	913	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	914	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	915	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	916	* @retval HAL status
bogdanm	0:9b334a45a8ff	917	*/
bogdanm	0:9b334a45a8ff	918	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	/* Process locked */
bogdanm	0:9b334a45a8ff	923	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	926	{
bogdanm	0:9b334a45a8ff	927	if(pData != NULL )
bogdanm	0:9b334a45a8ff	928	{
bogdanm	0:9b334a45a8ff	929	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/* Update state */
bogdanm	0:9b334a45a8ff	932	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	935	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	936	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	937	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	940	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
bogdanm	0:9b334a45a8ff	943	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	944
bogdanm	0:9b334a45a8ff	945	}
bogdanm	0:9b334a45a8ff	946	else
bogdanm	0:9b334a45a8ff	947	{
bogdanm	0:9b334a45a8ff	948	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951	else
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	954	}
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/* Process unlocked */
bogdanm	0:9b334a45a8ff	957	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	return status;
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/**
bogdanm	0:9b334a45a8ff	963	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	964	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	965	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	966	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	967	* @retval HAL status
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	970	{
bogdanm	0:9b334a45a8ff	971	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	972	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/* Process locked */
bogdanm	0:9b334a45a8ff	975	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	if(pData != NULL )
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/* Update state */
bogdanm	0:9b334a45a8ff	984	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	987	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	988	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	989	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	992	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	995	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
bogdanm	0:9b334a45a8ff	998	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	999	}
bogdanm	0:9b334a45a8ff	1000	else
bogdanm	0:9b334a45a8ff	1001	{
bogdanm	0:9b334a45a8ff	1002	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1003	}
bogdanm	0:9b334a45a8ff	1004	}
bogdanm	0:9b334a45a8ff	1005	else
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1011	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	return status;
bogdanm	0:9b334a45a8ff	1014	}
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	/**
bogdanm	0:9b334a45a8ff	1017	* @brief Sends an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1018	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1019	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1020	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	1021	* @retval HAL status
bogdanm	0:9b334a45a8ff	1022	*/
bogdanm	0:9b334a45a8ff	1023	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1024	{
bogdanm	0:9b334a45a8ff	1025	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1026	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Process locked */
bogdanm	0:9b334a45a8ff	1029	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1034	{
bogdanm	0:9b334a45a8ff	1035	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/* Update state */
bogdanm	0:9b334a45a8ff	1038	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1041	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1042	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1043	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/* Configure QSPI: CCR register with functional mode as indirect write */
bogdanm	0:9b334a45a8ff	1046	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1049	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1052	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1055	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1058	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
bogdanm	0:9b334a45a8ff	1059	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/* Enable the QSPI transmit DMA Channel */
bogdanm	0:9b334a45a8ff	1062	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1063	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1066	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1067	}
bogdanm	0:9b334a45a8ff	1068	else
bogdanm	0:9b334a45a8ff	1069	{
bogdanm	0:9b334a45a8ff	1070	status = HAL_OK;
bogdanm	0:9b334a45a8ff	1071	}
bogdanm	0:9b334a45a8ff	1072	}
bogdanm	0:9b334a45a8ff	1073	else
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1079	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	return status;
bogdanm	0:9b334a45a8ff	1082	}
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	/**
bogdanm	0:9b334a45a8ff	1085	* @brief Receives an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1086	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1087	* @param pData: pointer to data buffer.
bogdanm	0:9b334a45a8ff	1088	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	1089	* @retval HAL status
bogdanm	0:9b334a45a8ff	1090	*/
bogdanm	0:9b334a45a8ff	1091	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1094	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1095	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/* Process locked */
bogdanm	0:9b334a45a8ff	1098	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1101	{
bogdanm	0:9b334a45a8ff	1102	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/* Update state */
bogdanm	0:9b334a45a8ff	1107	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1110	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1111	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1112	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1115	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1118	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1121	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1124	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
bogdanm	0:9b334a45a8ff	1125	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/* Enable the DMA Channel */
bogdanm	0:9b334a45a8ff	1128	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1129	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	1132	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	1135	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1138	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140	else
bogdanm	0:9b334a45a8ff	1141	{
bogdanm	0:9b334a45a8ff	1142	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144	}
bogdanm	0:9b334a45a8ff	1145	else
bogdanm	0:9b334a45a8ff	1146	{
bogdanm	0:9b334a45a8ff	1147	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1148	}
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1151	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	return status;
bogdanm	0:9b334a45a8ff	1154	}
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	/**
bogdanm	0:9b334a45a8ff	1157	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
bogdanm	0:9b334a45a8ff	1158	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1159	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1160	* @param cfg: structure that contains the polling configuration information.
bogdanm	0:9b334a45a8ff	1161	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	1162	* @note This function is used only in Automatic Polling Mode
bogdanm	0:9b334a45a8ff	1163	* @retval HAL status
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1170	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1171	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1172	{
bogdanm	0:9b334a45a8ff	1173	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1174	}
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1177	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1178	{
bogdanm	0:9b334a45a8ff	1179	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1183	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1184	{
bogdanm	0:9b334a45a8ff	1185	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1186	}
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1189	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1192	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1193	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1196	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1197	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Process locked */
bogdanm	0:9b334a45a8ff	1200	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1203	{
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* Update state */
bogdanm	0:9b334a45a8ff	1208	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1211	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1214	{
bogdanm	0:9b334a45a8ff	1215	/* Configure QSPI: PSMAR register with the status match value */
bogdanm	0:9b334a45a8ff	1216	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/* Configure QSPI: PSMKR register with the status mask value */
bogdanm	0:9b334a45a8ff	1219	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Configure QSPI: PIR register with the interval value */
bogdanm	0:9b334a45a8ff	1222	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
bogdanm	0:9b334a45a8ff	1225	(otherwise there will be an infinite loop in blocking mode) */
bogdanm	0:9b334a45a8ff	1226	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
bogdanm	0:9b334a45a8ff	1227	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1230	cmd->NbData = cfg->StatusBytesSize;
bogdanm	0:9b334a45a8ff	1231	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	/* Wait until SM flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	1234	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1235	{
bogdanm	0:9b334a45a8ff	1236	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1237	}
bogdanm	0:9b334a45a8ff	1238	else
bogdanm	0:9b334a45a8ff	1239	{
bogdanm	0:9b334a45a8ff	1240	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/* Update state */
bogdanm	0:9b334a45a8ff	1243	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1244	}
bogdanm	0:9b334a45a8ff	1245	}
bogdanm	0:9b334a45a8ff	1246	}
bogdanm	0:9b334a45a8ff	1247	else
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1252	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	/* Return function status */
bogdanm	0:9b334a45a8ff	1255	return status;
bogdanm	0:9b334a45a8ff	1256	}
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	/**
bogdanm	0:9b334a45a8ff	1259	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
bogdanm	0:9b334a45a8ff	1260	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1261	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1262	* @param cfg: structure that contains the polling configuration information.
bogdanm	0:9b334a45a8ff	1263	* @note This function is used only in Automatic Polling Mode
bogdanm	0:9b334a45a8ff	1264	* @retval HAL status
bogdanm	0:9b334a45a8ff	1265	*/
bogdanm	0:9b334a45a8ff	1266	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1267	{
bogdanm	0:9b334a45a8ff	1268	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1271	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1272	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1273	{
bogdanm	0:9b334a45a8ff	1274	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1275	}
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1278	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1279	{
bogdanm	0:9b334a45a8ff	1280	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1284	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1285	{
bogdanm	0:9b334a45a8ff	1286	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1287	}
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1290	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1293	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1294	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1297	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1298	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1299	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	/* Process locked */
bogdanm	0:9b334a45a8ff	1302	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Update state */
bogdanm	0:9b334a45a8ff	1309	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1312	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1313
mbed_official	19:112740acecfa	1314	if (status == HAL_OK)
mbed_official	19:112740acecfa	1315	{
mbed_official	19:112740acecfa	1316	/* Configure QSPI: PSMAR register with the status match value */
mbed_official	19:112740acecfa	1317	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
bogdanm	0:9b334a45a8ff	1318
mbed_official	19:112740acecfa	1319	/* Configure QSPI: PSMKR register with the status mask value */
mbed_official	19:112740acecfa	1320	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
bogdanm	0:9b334a45a8ff	1321
mbed_official	19:112740acecfa	1322	/* Configure QSPI: PIR register with the interval value */
mbed_official	19:112740acecfa	1323	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
bogdanm	0:9b334a45a8ff	1324
mbed_official	19:112740acecfa	1325	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
mbed_official	19:112740acecfa	1326	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
bogdanm	0:9b334a45a8ff	1327	(cfg->MatchMode \| cfg->AutomaticStop));
mbed_official	19:112740acecfa	1328
mbed_official	19:112740acecfa	1329	/* Clear interrupt */
mbed_official	19:112740acecfa	1330	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	1331
mbed_official	19:112740acecfa	1332	/* Enable the QSPI Transfer Error and status match Interrupt */
mbed_official	19:112740acecfa	1333	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
mbed_official	19:112740acecfa	1334
mbed_official	19:112740acecfa	1335	/* Call the configuration function */
mbed_official	19:112740acecfa	1336	cmd->NbData = cfg->StatusBytesSize;
mbed_official	19:112740acecfa	1337	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
mbed_official	19:112740acecfa	1338	}
bogdanm	0:9b334a45a8ff	1339	}
bogdanm	0:9b334a45a8ff	1340	else
bogdanm	0:9b334a45a8ff	1341	{
bogdanm	0:9b334a45a8ff	1342	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1343	}
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1346	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Return function status */
bogdanm	0:9b334a45a8ff	1349	return status;
bogdanm	0:9b334a45a8ff	1350	}
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/**
bogdanm	0:9b334a45a8ff	1353	* @brief Configure the Memory Mapped mode.
bogdanm	0:9b334a45a8ff	1354	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1355	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1356	* @param cfg: structure that contains the memory mapped configuration information.
bogdanm	0:9b334a45a8ff	1357	* @note This function is used only in Memory mapped Mode
bogdanm	0:9b334a45a8ff	1358	* @retval HAL status
bogdanm	0:9b334a45a8ff	1359	*/
bogdanm	0:9b334a45a8ff	1360	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1361	{
bogdanm	0:9b334a45a8ff	1362	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1365	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1366	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1367	{
bogdanm	0:9b334a45a8ff	1368	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1369	}
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1372	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1373	{
bogdanm	0:9b334a45a8ff	1374	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1378	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1379	{
bogdanm	0:9b334a45a8ff	1380	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1384	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1387	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1388	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/* Process locked */
bogdanm	0:9b334a45a8ff	1393	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1396	{
bogdanm	0:9b334a45a8ff	1397	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/* Update state */
bogdanm	0:9b334a45a8ff	1400	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1403	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1406	{
bogdanm	0:9b334a45a8ff	1407	/* Configure QSPI: CR register with time out counter enable */
bogdanm	0:9b334a45a8ff	1408	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
bogdanm	0:9b334a45a8ff	1411	{
bogdanm	0:9b334a45a8ff	1412	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	/* Configure QSPI: LPTR register with the low-power time out value */
bogdanm	0:9b334a45a8ff	1415	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
bogdanm	0:9b334a45a8ff	1416
bogdanm	0:9b334a45a8ff	1417	/* Enable the QSPI TimeOut Interrupt */
bogdanm	0:9b334a45a8ff	1418	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1422	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	}
bogdanm	0:9b334a45a8ff	1425	}
bogdanm	0:9b334a45a8ff	1426	else
bogdanm	0:9b334a45a8ff	1427	{
bogdanm	0:9b334a45a8ff	1428	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1433	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/* Return function status */
bogdanm	0:9b334a45a8ff	1436	return status;
bogdanm	0:9b334a45a8ff	1437	}
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/**
bogdanm	0:9b334a45a8ff	1440	* @brief Transfer Error callbacks
bogdanm	0:9b334a45a8ff	1441	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1442	* @retval None
bogdanm	0:9b334a45a8ff	1443	*/
bogdanm	0:9b334a45a8ff	1444	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1445	{
bogdanm	0:9b334a45a8ff	1446	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1447	the HAL_QSPI_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1448	*/
bogdanm	0:9b334a45a8ff	1449	}
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	/**
bogdanm	0:9b334a45a8ff	1452	* @brief Command completed callbacks.
bogdanm	0:9b334a45a8ff	1453	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1454	* @retval None
bogdanm	0:9b334a45a8ff	1455	*/
bogdanm	0:9b334a45a8ff	1456	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1457	{
bogdanm	0:9b334a45a8ff	1458	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1459	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1460	*/
bogdanm	0:9b334a45a8ff	1461	}
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	/**
bogdanm	0:9b334a45a8ff	1464	* @brief Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1465	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1466	* @retval None
bogdanm	0:9b334a45a8ff	1467	*/
bogdanm	0:9b334a45a8ff	1468	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1469	{
bogdanm	0:9b334a45a8ff	1470	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1471	the HAL_QSPI_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1472	*/
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/**
bogdanm	0:9b334a45a8ff	1476	* @brief Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1477	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1478	* @retval None
bogdanm	0:9b334a45a8ff	1479	*/
bogdanm	0:9b334a45a8ff	1480	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1481	{
bogdanm	0:9b334a45a8ff	1482	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1483	the HAL_QSPI_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1484	*/
bogdanm	0:9b334a45a8ff	1485	}
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/**
bogdanm	0:9b334a45a8ff	1488	* @brief Rx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1489	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1490	* @retval None
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1495	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1496	*/
bogdanm	0:9b334a45a8ff	1497	}
bogdanm	0:9b334a45a8ff	1498
bogdanm	0:9b334a45a8ff	1499	/**
bogdanm	0:9b334a45a8ff	1500	* @brief Tx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1501	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1502	* @retval None
bogdanm	0:9b334a45a8ff	1503	*/
bogdanm	0:9b334a45a8ff	1504	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1505	{
bogdanm	0:9b334a45a8ff	1506	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1507	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1508	*/
bogdanm	0:9b334a45a8ff	1509	}
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	/**
bogdanm	0:9b334a45a8ff	1512	* @brief FIFO Threshold callbacks
bogdanm	0:9b334a45a8ff	1513	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1514	* @retval None
bogdanm	0:9b334a45a8ff	1515	*/
bogdanm	0:9b334a45a8ff	1516	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1517	{
bogdanm	0:9b334a45a8ff	1518	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1519	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1520	*/
bogdanm	0:9b334a45a8ff	1521	}
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	/**
bogdanm	0:9b334a45a8ff	1524	* @brief Status Match callbacks
bogdanm	0:9b334a45a8ff	1525	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1526	* @retval None
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1529	{
bogdanm	0:9b334a45a8ff	1530	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1531	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1532	*/
bogdanm	0:9b334a45a8ff	1533	}
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	/**
bogdanm	0:9b334a45a8ff	1536	* @brief Timeout callbacks
bogdanm	0:9b334a45a8ff	1537	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1538	* @retval None
bogdanm	0:9b334a45a8ff	1539	*/
bogdanm	0:9b334a45a8ff	1540	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1541	{
bogdanm	0:9b334a45a8ff	1542	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1543	the HAL_QSPI_TimeOutCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1544	*/
bogdanm	0:9b334a45a8ff	1545	}
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/**
bogdanm	0:9b334a45a8ff	1548	* @}
bogdanm	0:9b334a45a8ff	1549	*/
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
bogdanm	0:9b334a45a8ff	1552	* @brief QSPI control and State functions
bogdanm	0:9b334a45a8ff	1553	*
bogdanm	0:9b334a45a8ff	1554	@verbatim
bogdanm	0:9b334a45a8ff	1555	===============================================================================
bogdanm	0:9b334a45a8ff	1556	##### Peripheral Control and State functions #####
bogdanm	0:9b334a45a8ff	1557	===============================================================================
bogdanm	0:9b334a45a8ff	1558	[..]
bogdanm	0:9b334a45a8ff	1559	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	1560	(+) Check in run-time the state of the driver.
bogdanm	0:9b334a45a8ff	1561	(+) Check the error code set during last operation.
bogdanm	0:9b334a45a8ff	1562	(+) Abort any operation.
bogdanm	0:9b334a45a8ff	1563	.....
bogdanm	0:9b334a45a8ff	1564	@endverbatim
bogdanm	0:9b334a45a8ff	1565	* @{
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	/**
bogdanm	0:9b334a45a8ff	1569	* @brief Return the QSPI state.
bogdanm	0:9b334a45a8ff	1570	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1571	* @retval HAL state
bogdanm	0:9b334a45a8ff	1572	*/
bogdanm	0:9b334a45a8ff	1573	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1574	{
bogdanm	0:9b334a45a8ff	1575	return hqspi->State;
bogdanm	0:9b334a45a8ff	1576	}
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	/**
bogdanm	0:9b334a45a8ff	1579	* @brief Return the QSPI error code
bogdanm	0:9b334a45a8ff	1580	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1581	* @retval QSPI Error Code
bogdanm	0:9b334a45a8ff	1582	*/
bogdanm	0:9b334a45a8ff	1583	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1584	{
bogdanm	0:9b334a45a8ff	1585	return hqspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1586	}
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/**
bogdanm	0:9b334a45a8ff	1589	* @brief Abort the current transmission
bogdanm	0:9b334a45a8ff	1590	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1591	* @retval HAL status
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1594	{
bogdanm	0:9b334a45a8ff	1595	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/* Configure QSPI: CR register with Abort request */
bogdanm	0:9b334a45a8ff	1598	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	1601	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1602	{
bogdanm	0:9b334a45a8ff	1603	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1604	}
bogdanm	0:9b334a45a8ff	1605	else
bogdanm	0:9b334a45a8ff	1606	{
bogdanm	0:9b334a45a8ff	1607	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	1610	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	/* Update state */
bogdanm	0:9b334a45a8ff	1613	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1614	}
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	return status;
bogdanm	0:9b334a45a8ff	1617	}
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/** @brief Set QSPI timeout
bogdanm	0:9b334a45a8ff	1620	* @param hqspi: QSPI handle.
bogdanm	0:9b334a45a8ff	1621	* @param Timeout: Timeout for the QSPI memory access.
bogdanm	0:9b334a45a8ff	1622	* @retval None
bogdanm	0:9b334a45a8ff	1623	*/
bogdanm	0:9b334a45a8ff	1624	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1625	{
bogdanm	0:9b334a45a8ff	1626	hqspi->Timeout = Timeout;
bogdanm	0:9b334a45a8ff	1627	}
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	/**
bogdanm	0:9b334a45a8ff	1630	* @}
bogdanm	0:9b334a45a8ff	1631	*/
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1634
bogdanm	0:9b334a45a8ff	1635	/**
bogdanm	0:9b334a45a8ff	1636	* @brief DMA QSPI receive process complete callback.
bogdanm	0:9b334a45a8ff	1637	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1638	* @retval None
bogdanm	0:9b334a45a8ff	1639	*/
bogdanm	0:9b334a45a8ff	1640	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1641	{
bogdanm	0:9b334a45a8ff	1642	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1643	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1646	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1647	{
bogdanm	0:9b334a45a8ff	1648	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1649	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1650	}
bogdanm	0:9b334a45a8ff	1651	else
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1654	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1657	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1660	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	1663	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	/* Update state */
bogdanm	0:9b334a45a8ff	1666	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1669	}
bogdanm	0:9b334a45a8ff	1670	}
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/**
bogdanm	0:9b334a45a8ff	1673	* @brief DMA QSPI transmit process complete callback.
bogdanm	0:9b334a45a8ff	1674	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1675	* @retval None
bogdanm	0:9b334a45a8ff	1676	*/
bogdanm	0:9b334a45a8ff	1677	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1678	{
bogdanm	0:9b334a45a8ff	1679	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1680	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1683	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1684	{
bogdanm	0:9b334a45a8ff	1685	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1686	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1687	}
bogdanm	0:9b334a45a8ff	1688	else
bogdanm	0:9b334a45a8ff	1689	{
bogdanm	0:9b334a45a8ff	1690	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1691	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1694	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1697	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	1700	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	/* Update state */
bogdanm	0:9b334a45a8ff	1703	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1706	}
bogdanm	0:9b334a45a8ff	1707	}
bogdanm	0:9b334a45a8ff	1708
bogdanm	0:9b334a45a8ff	1709	/**
bogdanm	0:9b334a45a8ff	1710	* @brief DMA QSPI receive process half complete callback
bogdanm	0:9b334a45a8ff	1711	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1712	* @retval None
bogdanm	0:9b334a45a8ff	1713	*/
bogdanm	0:9b334a45a8ff	1714	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1715	{
bogdanm	0:9b334a45a8ff	1716	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	HAL_QSPI_RxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1719	}
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	/**
bogdanm	0:9b334a45a8ff	1722	* @brief DMA QSPI transmit process half complete callback
bogdanm	0:9b334a45a8ff	1723	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1724	* @retval None
bogdanm	0:9b334a45a8ff	1725	*/
bogdanm	0:9b334a45a8ff	1726	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1727	{
bogdanm	0:9b334a45a8ff	1728	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1729
bogdanm	0:9b334a45a8ff	1730	HAL_QSPI_TxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1731	}
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/**
bogdanm	0:9b334a45a8ff	1734	* @brief DMA QSPI communication error callback.
bogdanm	0:9b334a45a8ff	1735	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1736	* @retval None
bogdanm	0:9b334a45a8ff	1737	*/
bogdanm	0:9b334a45a8ff	1738	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1739	{
bogdanm	0:9b334a45a8ff	1740	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1743	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1744	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1745	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1746
bogdanm	0:9b334a45a8ff	1747	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1748	}
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	/**
bogdanm	0:9b334a45a8ff	1751	* @brief This function wait a flag state until time out.
bogdanm	0:9b334a45a8ff	1752	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1753	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1754	* @param State: Value of the flag expected
bogdanm	0:9b334a45a8ff	1755	* @param Timeout: Duration of the time out
bogdanm	0:9b334a45a8ff	1756	* @retval HAL status
bogdanm	0:9b334a45a8ff	1757	*/
bogdanm	0:9b334a45a8ff	1758	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
bogdanm	0:9b334a45a8ff	1759	FlagStatus State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1760	{
bogdanm	0:9b334a45a8ff	1761	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1762
bogdanm	0:9b334a45a8ff	1763	/* Wait until flag is in expected state */
bogdanm	0:9b334a45a8ff	1764	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1767	if (Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1768	{
bogdanm	0:9b334a45a8ff	1769	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1772	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1775	}
bogdanm	0:9b334a45a8ff	1776	}
bogdanm	0:9b334a45a8ff	1777	}
bogdanm	0:9b334a45a8ff	1778	return HAL_OK;
bogdanm	0:9b334a45a8ff	1779	}
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/**
bogdanm	0:9b334a45a8ff	1782	* @brief This function configures the communication registers
bogdanm	0:9b334a45a8ff	1783	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1784	* @param cmd: structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	1785	* @param FunctionalMode: functional mode to configured
bogdanm	0:9b334a45a8ff	1786	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1787	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
bogdanm	0:9b334a45a8ff	1788	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
bogdanm	0:9b334a45a8ff	1789	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
bogdanm	0:9b334a45a8ff	1790	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
bogdanm	0:9b334a45a8ff	1791	* @retval None
bogdanm	0:9b334a45a8ff	1792	*/
bogdanm	0:9b334a45a8ff	1793	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
bogdanm	0:9b334a45a8ff	1794	{
bogdanm	0:9b334a45a8ff	1795	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	1798	{
bogdanm	0:9b334a45a8ff	1799	/* Configure QSPI: DLR register with the number of data to read or write */
bogdanm	0:9b334a45a8ff	1800	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
bogdanm	0:9b334a45a8ff	1801	}
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1804	{
bogdanm	0:9b334a45a8ff	1805	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1808	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1809
bogdanm	0:9b334a45a8ff	1810	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1811	{
bogdanm	0:9b334a45a8ff	1812	/---- Command with instruction, address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1813	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1814	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1815	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1816	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1817	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1818
bogdanm	0:9b334a45a8ff	1819	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1820	{
bogdanm	0:9b334a45a8ff	1821	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1822	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1823	}
bogdanm	0:9b334a45a8ff	1824	}
bogdanm	0:9b334a45a8ff	1825	else
bogdanm	0:9b334a45a8ff	1826	{
bogdanm	0:9b334a45a8ff	1827	/---- Command with instruction and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1828	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1829	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1830	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1831	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1832	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1833	}
bogdanm	0:9b334a45a8ff	1834	}
bogdanm	0:9b334a45a8ff	1835	else
bogdanm	0:9b334a45a8ff	1836	{
bogdanm	0:9b334a45a8ff	1837	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1838	{
bogdanm	0:9b334a45a8ff	1839	/---- Command with instruction and address ----/
bogdanm	0:9b334a45a8ff	1840	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1841	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1842	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1843	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1844	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1845
bogdanm	0:9b334a45a8ff	1846	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1847	{
bogdanm	0:9b334a45a8ff	1848	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1849	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1850	}
bogdanm	0:9b334a45a8ff	1851	}
bogdanm	0:9b334a45a8ff	1852	else
bogdanm	0:9b334a45a8ff	1853	{
bogdanm	0:9b334a45a8ff	1854	/---- Command with only instruction ----/
bogdanm	0:9b334a45a8ff	1855	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1856	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1857	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1858	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
bogdanm	0:9b334a45a8ff	1859	FunctionalMode));
bogdanm	0:9b334a45a8ff	1860	}
bogdanm	0:9b334a45a8ff	1861	}
bogdanm	0:9b334a45a8ff	1862	}
bogdanm	0:9b334a45a8ff	1863	else
bogdanm	0:9b334a45a8ff	1864	{
bogdanm	0:9b334a45a8ff	1865	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1866	{
bogdanm	0:9b334a45a8ff	1867	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1868	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1869
bogdanm	0:9b334a45a8ff	1870	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1871	{
bogdanm	0:9b334a45a8ff	1872	/---- Command with address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1873	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1874	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1875	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1876	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1877	cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1880	{
bogdanm	0:9b334a45a8ff	1881	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1882	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1883	}
bogdanm	0:9b334a45a8ff	1884	}
bogdanm	0:9b334a45a8ff	1885	else
bogdanm	0:9b334a45a8ff	1886	{
bogdanm	0:9b334a45a8ff	1887	/---- Command with only alternate bytes ----/
bogdanm	0:9b334a45a8ff	1888	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1889	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1890	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1891	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1892	FunctionalMode));
bogdanm	0:9b334a45a8ff	1893	}
bogdanm	0:9b334a45a8ff	1894	}
bogdanm	0:9b334a45a8ff	1895	else
bogdanm	0:9b334a45a8ff	1896	{
bogdanm	0:9b334a45a8ff	1897	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1898	{
bogdanm	0:9b334a45a8ff	1899	/---- Command with only address ----/
bogdanm	0:9b334a45a8ff	1900	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1901	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1902	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1903	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1904	FunctionalMode));
bogdanm	0:9b334a45a8ff	1905
bogdanm	0:9b334a45a8ff	1906	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1907	{
bogdanm	0:9b334a45a8ff	1908	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1909	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1910	}
bogdanm	0:9b334a45a8ff	1911	}
bogdanm	0:9b334a45a8ff	1912	else
bogdanm	0:9b334a45a8ff	1913	{
bogdanm	0:9b334a45a8ff	1914	/---- Command with only data phase ----/
bogdanm	0:9b334a45a8ff	1915	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	1916	{
bogdanm	0:9b334a45a8ff	1917	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1918	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1919	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1920	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1921	}
bogdanm	0:9b334a45a8ff	1922	}
bogdanm	0:9b334a45a8ff	1923	}
bogdanm	0:9b334a45a8ff	1924	}
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	/**
bogdanm	0:9b334a45a8ff	1928	* @}
bogdanm	0:9b334a45a8ff	1929	*/
bogdanm	0:9b334a45a8ff	1930
bogdanm	0:9b334a45a8ff	1931	/**
bogdanm	0:9b334a45a8ff	1932	* @}
bogdanm	0:9b334a45a8ff	1933	*/
mbed_official	19:112740acecfa	1934	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	#endif /* HAL_QSPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1937	/**
bogdanm	0:9b334a45a8ff	1938	* @}
bogdanm	0:9b334a45a8ff	1939	*/
bogdanm	0:9b334a45a8ff	1940
bogdanm	0:9b334a45a8ff	1941	/**
bogdanm	0:9b334a45a8ff	1942	* @}
bogdanm	0:9b334a45a8ff	1943	*/
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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