fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_nor.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of NOR HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F4xx_HAL_NOR_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F4xx_HAL_NOR_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
mbed_official 19:112740acecfa 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 48 #include "stm32f4xx_ll_fsmc.h"
mbed_official 19:112740acecfa 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 50
mbed_official 19:112740acecfa 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
mbed_official 19:112740acecfa 52 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 53 #include "stm32f4xx_ll_fmc.h"
mbed_official 19:112740acecfa 54 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 57 * @{
bogdanm 0:9b334a45a8ff 58 */
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /** @addtogroup NOR
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
bogdanm 0:9b334a45a8ff 65 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
mbed_official 19:112740acecfa 66 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /* Exported typedef ----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 69 /** @defgroup NOR_Exported_Types NOR Exported Types
bogdanm 0:9b334a45a8ff 70 * @{
bogdanm 0:9b334a45a8ff 71 */
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /**
bogdanm 0:9b334a45a8ff 74 * @brief HAL SRAM State structures definition
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76 typedef enum
bogdanm 0:9b334a45a8ff 77 {
bogdanm 0:9b334a45a8ff 78 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 79 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
bogdanm 0:9b334a45a8ff 80 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
bogdanm 0:9b334a45a8ff 81 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
bogdanm 0:9b334a45a8ff 82 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
bogdanm 0:9b334a45a8ff 83 }HAL_NOR_StateTypeDef;
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /**
bogdanm 0:9b334a45a8ff 86 * @brief FMC NOR Status typedef
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88 typedef enum
bogdanm 0:9b334a45a8ff 89 {
bogdanm 0:9b334a45a8ff 90 HAL_NOR_STATUS_SUCCESS = 0,
bogdanm 0:9b334a45a8ff 91 HAL_NOR_STATUS_ONGOING,
bogdanm 0:9b334a45a8ff 92 HAL_NOR_STATUS_ERROR,
bogdanm 0:9b334a45a8ff 93 HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 94 }HAL_NOR_StatusTypeDef;
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /**
bogdanm 0:9b334a45a8ff 97 * @brief FMC NOR ID typedef
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99 typedef struct
bogdanm 0:9b334a45a8ff 100 {
bogdanm 0:9b334a45a8ff 101 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 uint16_t Device_Code1;
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 uint16_t Device_Code2;
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
bogdanm 0:9b334a45a8ff 108 These codes can be accessed by performing read operations with specific
bogdanm 0:9b334a45a8ff 109 control signals and addresses set.They can also be accessed by issuing
bogdanm 0:9b334a45a8ff 110 an Auto Select command */
bogdanm 0:9b334a45a8ff 111 }NOR_IDTypeDef;
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /**
bogdanm 0:9b334a45a8ff 114 * @brief FMC NOR CFI typedef
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116 typedef struct
bogdanm 0:9b334a45a8ff 117 {
bogdanm 0:9b334a45a8ff 118 /*!< Defines the information stored in the memory's Common flash interface
bogdanm 0:9b334a45a8ff 119 which contains a description of various electrical and timing parameters,
bogdanm 0:9b334a45a8ff 120 density information and functions supported by the memory */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 uint16_t CFI_1;
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 uint16_t CFI_2;
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 uint16_t CFI_3;
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 uint16_t CFI_4;
bogdanm 0:9b334a45a8ff 129 }NOR_CFITypeDef;
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @brief NOR handle Structure definition
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134 typedef struct
bogdanm 0:9b334a45a8ff 135 {
bogdanm 0:9b334a45a8ff 136 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 HAL_LockTypeDef Lock; /*!< NOR locking object */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 }NOR_HandleTypeDef;
bogdanm 0:9b334a45a8ff 147 /**
bogdanm 0:9b334a45a8ff 148 * @}
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 152 /* Exported macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 153 /** @defgroup NOR_Exported_Macros NOR Exported Macros
bogdanm 0:9b334a45a8ff 154 * @{
bogdanm 0:9b334a45a8ff 155 */
bogdanm 0:9b334a45a8ff 156 /** @brief Reset NOR handle state
bogdanm 0:9b334a45a8ff 157 * @param __HANDLE__: specifies the NOR handle.
bogdanm 0:9b334a45a8ff 158 * @retval None
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 161 /**
bogdanm 0:9b334a45a8ff 162 * @}
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 166 /** @addtogroup NOR_Exported_Functions
bogdanm 0:9b334a45a8ff 167 * @{
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /** @addtogroup NOR_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173 /* Initialization/de-initialization functions ********************************/
bogdanm 0:9b334a45a8ff 174 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
bogdanm 0:9b334a45a8ff 175 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 176 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 177 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 178 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 179 /**
bogdanm 0:9b334a45a8ff 180 * @}
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /** @addtogroup NOR_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 184 * @{
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186 /* I/O operation functions ***************************************************/
bogdanm 0:9b334a45a8ff 187 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
bogdanm 0:9b334a45a8ff 188 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 189 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 0:9b334a45a8ff 190 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 0:9b334a45a8ff 193 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
bogdanm 0:9b334a45a8ff 196 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
bogdanm 0:9b334a45a8ff 197 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
bogdanm 0:9b334a45a8ff 198 /**
bogdanm 0:9b334a45a8ff 199 * @}
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /** @addtogroup NOR_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 203 * @{
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205 /* NOR Control functions *****************************************************/
bogdanm 0:9b334a45a8ff 206 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 207 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 208 /**
bogdanm 0:9b334a45a8ff 209 * @}
bogdanm 0:9b334a45a8ff 210 */
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /** @addtogroup NOR_Exported_Functions_Group4
bogdanm 0:9b334a45a8ff 213 * @{
bogdanm 0:9b334a45a8ff 214 */
bogdanm 0:9b334a45a8ff 215 /* NOR State functions ********************************************************/
bogdanm 0:9b334a45a8ff 216 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 217 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @}
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /**
bogdanm 0:9b334a45a8ff 223 * @}
bogdanm 0:9b334a45a8ff 224 */
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 227 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 228 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 229 /** @defgroup NOR_Private_Constants NOR Private Constants
bogdanm 0:9b334a45a8ff 230 * @{
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232 /* NOR device IDs addresses */
bogdanm 0:9b334a45a8ff 233 #define MC_ADDRESS ((uint16_t)0x0000)
bogdanm 0:9b334a45a8ff 234 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
bogdanm 0:9b334a45a8ff 235 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
bogdanm 0:9b334a45a8ff 236 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* NOR CFI IDs addresses */
bogdanm 0:9b334a45a8ff 239 #define CFI1_ADDRESS ((uint16_t)0x61)
bogdanm 0:9b334a45a8ff 240 #define CFI2_ADDRESS ((uint16_t)0x62)
bogdanm 0:9b334a45a8ff 241 #define CFI3_ADDRESS ((uint16_t)0x63)
bogdanm 0:9b334a45a8ff 242 #define CFI4_ADDRESS ((uint16_t)0x64)
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /* NOR operation wait timeout */
bogdanm 0:9b334a45a8ff 245 #define NOR_TMEOUT ((uint16_t)0xFFFF)
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /* NOR memory data width */
bogdanm 0:9b334a45a8ff 248 #define NOR_MEMORY_8B ((uint8_t)0x0)
bogdanm 0:9b334a45a8ff 249 #define NOR_MEMORY_16B ((uint8_t)0x1)
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* NOR memory device read/write start address */
bogdanm 0:9b334a45a8ff 252 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
bogdanm 0:9b334a45a8ff 253 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
bogdanm 0:9b334a45a8ff 254 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
bogdanm 0:9b334a45a8ff 255 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
bogdanm 0:9b334a45a8ff 256 /**
bogdanm 0:9b334a45a8ff 257 * @}
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 261 /** @defgroup NOR_Private_Macros NOR Private Macros
bogdanm 0:9b334a45a8ff 262 * @{
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 /**
bogdanm 0:9b334a45a8ff 265 * @brief NOR memory address shifting.
bogdanm 0:9b334a45a8ff 266 * @param __NOR_ADDRESS__: NOR base address
bogdanm 0:9b334a45a8ff 267 * @param NOR_MEMORY_WIDTH: NOR memory width
bogdanm 0:9b334a45a8ff 268 * @param ADDRESS: NOR memory address
bogdanm 0:9b334a45a8ff 269 * @retval NOR shifted address value
bogdanm 0:9b334a45a8ff 270 */
bogdanm 0:9b334a45a8ff 271 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
bogdanm 0:9b334a45a8ff 272 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /**
bogdanm 0:9b334a45a8ff 275 * @brief NOR memory write data to specified address.
bogdanm 0:9b334a45a8ff 276 * @param ADDRESS: NOR memory address
bogdanm 0:9b334a45a8ff 277 * @param DATA: Data to write
bogdanm 0:9b334a45a8ff 278 * @retval None
bogdanm 0:9b334a45a8ff 279 */
bogdanm 0:9b334a45a8ff 280 #define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /**
bogdanm 0:9b334a45a8ff 283 * @}
bogdanm 0:9b334a45a8ff 284 */
bogdanm 0:9b334a45a8ff 285 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
bogdanm 0:9b334a45a8ff 286 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
mbed_official 19:112740acecfa 287 STM32F446xx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 288 /**
bogdanm 0:9b334a45a8ff 289 * @}
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /**
bogdanm 0:9b334a45a8ff 293 * @}
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298 #endif
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 #endif /* __STM32F4xx_HAL_NOR_H */
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/