mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_i2s.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief I2S HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Integrated Interchip Sound (I2S) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	===============================================================================
bogdanm	0:9b334a45a8ff	15	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	16	===============================================================================
bogdanm	0:9b334a45a8ff	17	[..]
bogdanm	0:9b334a45a8ff	18	The I2S HAL driver can be used as follow:
bogdanm	0:9b334a45a8ff	19
bogdanm	0:9b334a45a8ff	20	(#) Declare a I2S_HandleTypeDef handle structure.
bogdanm	0:9b334a45a8ff	21	(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
bogdanm	0:9b334a45a8ff	22	(##) Enable the SPIx interface clock.
bogdanm	0:9b334a45a8ff	23	(##) I2S pins configuration:
bogdanm	0:9b334a45a8ff	24	(+++) Enable the clock for the I2S GPIOs.
bogdanm	0:9b334a45a8ff	25	(+++) Configure these I2S pins as alternate function pull-up.
bogdanm	0:9b334a45a8ff	26	(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	27	and HAL_I2S_Receive_IT() APIs).
bogdanm	0:9b334a45a8ff	28	(+++) Configure the I2Sx interrupt priority.
bogdanm	0:9b334a45a8ff	29	(+++) Enable the NVIC I2S IRQ handle.
bogdanm	0:9b334a45a8ff	30	(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	31	and HAL_I2S_Receive_DMA() APIs:
bogdanm	0:9b334a45a8ff	32	(+++) Declare a DMA handle structure for the Tx/Rx stream.
bogdanm	0:9b334a45a8ff	33	(+++) Enable the DMAx interface clock.
bogdanm	0:9b334a45a8ff	34	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA Tx/Rx Stream.
bogdanm	0:9b334a45a8ff	36	(+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
bogdanm	0:9b334a45a8ff	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
bogdanm	0:9b334a45a8ff	38	DMA Tx/Rx Stream.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
bogdanm	0:9b334a45a8ff	41	using HAL_I2S_Init() function.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	-@- The specific I2S interrupts (Transmission complete interrupt,
bogdanm	0:9b334a45a8ff	44	RXNE interrupt and Error Interrupts) will be managed using the macros
bogdanm	0:9b334a45a8ff	45	__I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
bogdanm	0:9b334a45a8ff	46	-@- Make sure that either:
bogdanm	0:9b334a45a8ff	47	(+@) I2S PLL is configured or
bogdanm	0:9b334a45a8ff	48	(+@) External clock source is configured after setting correctly
bogdanm	0:9b334a45a8ff	49	the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	(#) Three operation modes are available within this driver :
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	54	=================================
bogdanm	0:9b334a45a8ff	55	[..]
bogdanm	0:9b334a45a8ff	56	(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	57	(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	60	===================================
bogdanm	0:9b334a45a8ff	61	[..]
bogdanm	0:9b334a45a8ff	62	(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	63	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	64	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	65	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	66	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	67	(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	68	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	69	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	70	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	71	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	72	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	73	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	76	==============================
bogdanm	0:9b334a45a8ff	77	[..]
bogdanm	0:9b334a45a8ff	78	(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	79	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	80	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	81	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	82	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	83	(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	84	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	85	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	86	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	87	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	88	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	89	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	90	(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm	0:9b334a45a8ff	91	(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm	0:9b334a45a8ff	92	(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	* I2S HAL driver macros list *
bogdanm	0:9b334a45a8ff	95	=============================================
bogdanm	0:9b334a45a8ff	96	[..]
bogdanm	0:9b334a45a8ff	97	Below the list of most used macros in USART HAL driver.
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	100	(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	101	(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	102	(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	103	(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	[..]
bogdanm	0:9b334a45a8ff	106	(@) You can refer to the I2S HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	@endverbatim
bogdanm	0:9b334a45a8ff	109	******************************************************************************
bogdanm	0:9b334a45a8ff	110	* @attention
bogdanm	0:9b334a45a8ff	111	*
bogdanm	0:9b334a45a8ff	112	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	115	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	116	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	117	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	118	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	119	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	120	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	121	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	122	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	123	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	126	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	127	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	128	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	129	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	130	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	131	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	132	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	133	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	134	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	135	*
bogdanm	0:9b334a45a8ff	136	******************************************************************************
bogdanm	0:9b334a45a8ff	137	*/
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	140	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	143	* @{
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/** @defgroup I2S I2S
bogdanm	0:9b334a45a8ff	147	* @brief I2S HAL module driver
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	#ifdef HAL_I2S_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	154	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	155	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	158	/** @addtogroup I2S_Private_Functions
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/**
bogdanm	0:9b334a45a8ff	163	* @}
bogdanm	0:9b334a45a8ff	164	*/
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	167	/** @defgroup I2S_Exported_Functions I2S Exported Functions
bogdanm	0:9b334a45a8ff	168	* @{
bogdanm	0:9b334a45a8ff	169	*/
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	172	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	173	*
bogdanm	0:9b334a45a8ff	174	@verbatim
bogdanm	0:9b334a45a8ff	175	===============================================================================
bogdanm	0:9b334a45a8ff	176	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	177	===============================================================================
bogdanm	0:9b334a45a8ff	178	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	179	de-initialize the I2Sx peripheral in simplex mode:
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	(+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	182	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	(+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	185	the selected configuration:
bogdanm	0:9b334a45a8ff	186	(++) Mode
bogdanm	0:9b334a45a8ff	187	(++) Standard
bogdanm	0:9b334a45a8ff	188	(++) Data Format
bogdanm	0:9b334a45a8ff	189	(++) MCLK Output
bogdanm	0:9b334a45a8ff	190	(++) Audio frequency
bogdanm	0:9b334a45a8ff	191	(++) Polarity
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	(+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	194	of the selected I2Sx peripheral.
bogdanm	0:9b334a45a8ff	195	@endverbatim
bogdanm	0:9b334a45a8ff	196	* @{
bogdanm	0:9b334a45a8ff	197	*/
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	/**
bogdanm	0:9b334a45a8ff	200	* @brief Initializes the I2S according to the specified parameters
bogdanm	0:9b334a45a8ff	201	* in the I2S_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	202	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	203	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	204	* @retval HAL status
bogdanm	0:9b334a45a8ff	205	*/
bogdanm	0:9b334a45a8ff	206	__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	207	{
bogdanm	0:9b334a45a8ff	208	uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm	0:9b334a45a8ff	209	uint32_t tmp = 0, i2sclk = 0;
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	212	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	213	{
bogdanm	0:9b334a45a8ff	214	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	215	}
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	/* Check the I2S parameters */
bogdanm	0:9b334a45a8ff	218	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm	0:9b334a45a8ff	219	assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm	0:9b334a45a8ff	220	assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm	0:9b334a45a8ff	221	assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm	0:9b334a45a8ff	222	assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	223	assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm	0:9b334a45a8ff	224	assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm	0:9b334a45a8ff	225	assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm	0:9b334a45a8ff	228	{
bogdanm	0:9b334a45a8ff	229	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	230	hi2s->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	231	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm	0:9b334a45a8ff	232	HAL_I2S_MspInit(hi2s);
bogdanm	0:9b334a45a8ff	233	}
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	/----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------/
bogdanm	0:9b334a45a8ff	238	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm	0:9b334a45a8ff	239	hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CKPOL \| \
bogdanm	0:9b334a45a8ff	240	SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \| \
bogdanm	0:9b334a45a8ff	241	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD);
bogdanm	0:9b334a45a8ff	242	hi2s->Instance->I2SPR = 0x0002;
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* Get the I2SCFGR register value */
bogdanm	0:9b334a45a8ff	245	tmpreg = hi2s->Instance->I2SCFGR;
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
bogdanm	0:9b334a45a8ff	248	/* If the requested audio frequency is not the default, compute the prescaler */
bogdanm	0:9b334a45a8ff	249	if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	/* Check the frame length (For the Prescaler computing) *******************/
bogdanm	0:9b334a45a8ff	252	if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
bogdanm	0:9b334a45a8ff	253	{
bogdanm	0:9b334a45a8ff	254	/* Packet length is 32 bits */
bogdanm	0:9b334a45a8ff	255	packetlength = 2;
bogdanm	0:9b334a45a8ff	256	}
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/* Get I2S source Clock frequency ****************************************/
bogdanm	0:9b334a45a8ff	259	/* If an external I2S clock has to be used, the specific define should be set
bogdanm	0:9b334a45a8ff	260	in the project configuration or in the stm32f4xx_conf.h file */
bogdanm	0:9b334a45a8ff	261	i2sclk = I2S_GetInputClock(hi2s);
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm	0:9b334a45a8ff	264	if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm	0:9b334a45a8ff	265	{
bogdanm	0:9b334a45a8ff	266	/* MCLK output is enabled */
bogdanm	0:9b334a45a8ff	267	tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	268	}
bogdanm	0:9b334a45a8ff	269	else
bogdanm	0:9b334a45a8ff	270	{
bogdanm	0:9b334a45a8ff	271	/* MCLK output is disabled */
bogdanm	0:9b334a45a8ff	272	tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	273	}
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	/* Remove the flatting point */
bogdanm	0:9b334a45a8ff	276	tmp = tmp / 10;
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Check the parity of the divider */
bogdanm	0:9b334a45a8ff	279	i2sodd = (uint32_t)(tmp & (uint32_t)1);
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/* Compute the i2sdiv prescaler */
bogdanm	0:9b334a45a8ff	282	i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm	0:9b334a45a8ff	285	i2sodd = (uint32_t) (i2sodd << 8);
bogdanm	0:9b334a45a8ff	286	}
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm	0:9b334a45a8ff	289	if((i2sdiv < 2) \|\| (i2sdiv > 0xFF))
bogdanm	0:9b334a45a8ff	290	{
bogdanm	0:9b334a45a8ff	291	/* Set the default values */
bogdanm	0:9b334a45a8ff	292	i2sdiv = 2;
bogdanm	0:9b334a45a8ff	293	i2sodd = 0;
bogdanm	0:9b334a45a8ff	294	}
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	/* Write to SPIx I2SPR register the computed value */
bogdanm	0:9b334a45a8ff	297	hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv \| (uint32_t)(i2sodd \| (uint32_t)hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	/* Configure the I2S with the I2S_InitStruct values */
bogdanm	0:9b334a45a8ff	300	tmpreg \|= (uint32_t)(SPI_I2SCFGR_I2SMOD \| hi2s->Init.Mode \| hi2s->Init.Standard \| hi2s->Init.DataFormat \| hi2s->Init.CPOL);
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	#if defined(SPI_I2SCFGR_ASTRTEN)
bogdanm	0:9b334a45a8ff	303	if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	306	hi2s->Instance->I2SCFGR = tmpreg \| SPI_I2SCFGR_ASTRTEN;
bogdanm	0:9b334a45a8ff	307	}
bogdanm	0:9b334a45a8ff	308	else
bogdanm	0:9b334a45a8ff	309	{
bogdanm	0:9b334a45a8ff	310	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	311	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	312	}
bogdanm	0:9b334a45a8ff	313	#else
bogdanm	0:9b334a45a8ff	314	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	315	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	316	#endif
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	319	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	return HAL_OK;
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/**
bogdanm	0:9b334a45a8ff	325	* @brief DeInitializes the I2S peripheral
bogdanm	0:9b334a45a8ff	326	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	327	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	328	* @retval HAL status
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	331	{
bogdanm	0:9b334a45a8ff	332	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	333	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	334	{
bogdanm	0:9b334a45a8ff	335	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	336	}
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	341	HAL_I2S_MspDeInit(hi2s);
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	344	hi2s->State = HAL_I2S_STATE_RESET;
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	/* Release Lock */
bogdanm	0:9b334a45a8ff	347	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	return HAL_OK;
bogdanm	0:9b334a45a8ff	350	}
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @brief I2S MSP Init
bogdanm	0:9b334a45a8ff	354	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	355	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	356	* @retval None
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	359	{
bogdanm	0:9b334a45a8ff	360	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	361	the HAL_I2S_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363	}
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/**
bogdanm	0:9b334a45a8ff	366	* @brief I2S MSP DeInit
bogdanm	0:9b334a45a8ff	367	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	368	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	369	* @retval None
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	374	the HAL_I2S_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	375	*/
bogdanm	0:9b334a45a8ff	376	}
bogdanm	0:9b334a45a8ff	377	/**
bogdanm	0:9b334a45a8ff	378	* @}
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	382	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	383	*
bogdanm	0:9b334a45a8ff	384	@verbatim
bogdanm	0:9b334a45a8ff	385	===============================================================================
bogdanm	0:9b334a45a8ff	386	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	387	===============================================================================
bogdanm	0:9b334a45a8ff	388	[..]
bogdanm	0:9b334a45a8ff	389	This subsection provides a set of functions allowing to manage the I2S data
bogdanm	0:9b334a45a8ff	390	transfers.
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	393	(++) Blocking mode : The communication is performed in the polling mode.
bogdanm	0:9b334a45a8ff	394	The status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	395	after finishing transfer.
bogdanm	0:9b334a45a8ff	396	(++) No-Blocking mode : The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	397	or DMA. These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	398	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	399	dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	400	using DMA mode.
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	(#) Blocking mode functions are :
bogdanm	0:9b334a45a8ff	403	(++) HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	404	(++) HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	(#) No-Blocking mode functions with Interrupt are :
bogdanm	0:9b334a45a8ff	407	(++) HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	408	(++) HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	(#) No-Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	411	(++) HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	412	(++) HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	415	(++) HAL_I2S_TxCpltCallback()
bogdanm	0:9b334a45a8ff	416	(++) HAL_I2S_RxCpltCallback()
bogdanm	0:9b334a45a8ff	417	(++) HAL_I2S_ErrorCallback()
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	@endverbatim
bogdanm	0:9b334a45a8ff	420	* @{
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/**
bogdanm	0:9b334a45a8ff	424	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	425	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	426	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	427	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	428	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	429	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	430	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	431	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	432	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	433	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	434	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	435	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	436	* @retval HAL status
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438	HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	439	{
bogdanm	0:9b334a45a8ff	440	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	441	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	442	{
bogdanm	0:9b334a45a8ff	443	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	444	}
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	449	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	450	if((tmp1 == I2S_DATAFORMAT_24B)\|\| \
bogdanm	0:9b334a45a8ff	451	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	452	{
bogdanm	0:9b334a45a8ff	453	hi2s->TxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	454	hi2s->TxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	455	}
bogdanm	0:9b334a45a8ff	456	else
bogdanm	0:9b334a45a8ff	457	{
bogdanm	0:9b334a45a8ff	458	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	459	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	460	}
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	/* Process Locked */
bogdanm	0:9b334a45a8ff	463	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	468	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	469	{
bogdanm	0:9b334a45a8ff	470	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	471	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	472	}
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	while(hi2s->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	hi2s->Instance->DR = (*pData++);
bogdanm	0:9b334a45a8ff	477	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	478	/* Wait until TXE flag is set */
bogdanm	0:9b334a45a8ff	479	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	482	}
mbed_official	19:112740acecfa	483	}
bogdanm	0:9b334a45a8ff	484	/* Check if Slave mode is selected */
bogdanm	0:9b334a45a8ff	485	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
bogdanm	0:9b334a45a8ff	486	{
bogdanm	0:9b334a45a8ff	487	/* Wait until Busy flag is reset */
bogdanm	0:9b334a45a8ff	488	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	489	{
bogdanm	0:9b334a45a8ff	490	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492	}
bogdanm	0:9b334a45a8ff	493	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	496	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	return HAL_OK;
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500	else
bogdanm	0:9b334a45a8ff	501	{
bogdanm	0:9b334a45a8ff	502	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504	}
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	/**
bogdanm	0:9b334a45a8ff	507	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	508	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	509	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	510	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	511	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	512	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	513	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	514	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	515	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	516	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	517	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	518	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	519	* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
bogdanm	0:9b334a45a8ff	520	* in continuous way and as the I2S is not disabled at the end of the I2S transaction.
bogdanm	0:9b334a45a8ff	521	* @retval HAL status
bogdanm	0:9b334a45a8ff	522	*/
bogdanm	0:9b334a45a8ff	523	HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	524	{
bogdanm	0:9b334a45a8ff	525	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	526	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	527	{
bogdanm	0:9b334a45a8ff	528	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	534	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	535	if((tmp1 == I2S_DATAFORMAT_24B)\|\| \
bogdanm	0:9b334a45a8ff	536	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	537	{
bogdanm	0:9b334a45a8ff	538	hi2s->RxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	539	hi2s->RxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541	else
bogdanm	0:9b334a45a8ff	542	{
bogdanm	0:9b334a45a8ff	543	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	544	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	545	}
bogdanm	0:9b334a45a8ff	546	/* Process Locked */
bogdanm	0:9b334a45a8ff	547	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	552	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	555	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	559	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	562	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	563	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/* Receive data */
bogdanm	0:9b334a45a8ff	567	while(hi2s->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	568	{
bogdanm	0:9b334a45a8ff	569	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	570	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	571	{
bogdanm	0:9b334a45a8ff	572	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	573	}
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	(*pData++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	576	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	582	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	return HAL_OK;
bogdanm	0:9b334a45a8ff	585	}
bogdanm	0:9b334a45a8ff	586	else
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590	}
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/**
bogdanm	0:9b334a45a8ff	593	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	594	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	595	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	596	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	597	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	598	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	599	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	600	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	601	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	602	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	603	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	604	* @retval HAL status
bogdanm	0:9b334a45a8ff	605	*/
bogdanm	0:9b334a45a8ff	606	HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	607	{
bogdanm	0:9b334a45a8ff	608	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	609	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	612	{
bogdanm	0:9b334a45a8ff	613	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	614	}
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	617	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	618	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	619	if((tmp1 == I2S_DATAFORMAT_24B)\|\| \
bogdanm	0:9b334a45a8ff	620	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	621	{
bogdanm	0:9b334a45a8ff	622	hi2s->TxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	623	hi2s->TxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	624	}
bogdanm	0:9b334a45a8ff	625	else
bogdanm	0:9b334a45a8ff	626	{
bogdanm	0:9b334a45a8ff	627	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	628	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/* Process Locked */
bogdanm	0:9b334a45a8ff	632	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	635	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	638	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	641	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	642	{
bogdanm	0:9b334a45a8ff	643	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	644	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	645	}
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	648	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	return HAL_OK;
bogdanm	0:9b334a45a8ff	651	}
bogdanm	0:9b334a45a8ff	652	else
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	655	}
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/**
bogdanm	0:9b334a45a8ff	659	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	660	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	661	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	662	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	663	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	664	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	665	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	666	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	667	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	668	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	669	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	670	* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
bogdanm	0:9b334a45a8ff	671	* between Master and Slave otherwise the I2S interrupt should be optimized.
bogdanm	0:9b334a45a8ff	672	* @retval HAL status
bogdanm	0:9b334a45a8ff	673	*/
bogdanm	0:9b334a45a8ff	674	HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	677	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	685	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	686	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	687	if((tmp1 == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	688	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	689	{
bogdanm	0:9b334a45a8ff	690	hi2s->RxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	691	hi2s->RxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693	else
bogdanm	0:9b334a45a8ff	694	{
bogdanm	0:9b334a45a8ff	695	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	696	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	697	}
bogdanm	0:9b334a45a8ff	698	/* Process Locked */
bogdanm	0:9b334a45a8ff	699	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	702	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	705	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	708	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	711	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	712	}
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	715	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	return HAL_OK;
bogdanm	0:9b334a45a8ff	718	}
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	else
bogdanm	0:9b334a45a8ff	721	{
bogdanm	0:9b334a45a8ff	722	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724	}
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	/**
bogdanm	0:9b334a45a8ff	727	* @brief Transmit an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	728	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	729	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	730	* @param pData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	731	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	732	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	733	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	734	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	735	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	736	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	737	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	738	* @retval HAL status
bogdanm	0:9b334a45a8ff	739	*/
bogdanm	0:9b334a45a8ff	740	HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	743	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	746	{
bogdanm	0:9b334a45a8ff	747	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	748	}
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	753	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	754	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	755	if((tmp1 == I2S_DATAFORMAT_24B)\|\| \
bogdanm	0:9b334a45a8ff	756	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	hi2s->TxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	759	hi2s->TxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	760	}
bogdanm	0:9b334a45a8ff	761	else
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	764	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	765	}
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* Process Locked */
bogdanm	0:9b334a45a8ff	768	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	771	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/* Set the I2S Tx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	774	hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Set the I2S Tx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	777	hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	780	hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/* Enable the Tx DMA Stream */
bogdanm	0:9b334a45a8ff	783	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	784	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	787	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	790	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	791	}
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/* Check if the I2S Tx request is already enabled */
bogdanm	0:9b334a45a8ff	794	if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
bogdanm	0:9b334a45a8ff	795	{
bogdanm	0:9b334a45a8ff	796	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	797	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	801	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	return HAL_OK;
bogdanm	0:9b334a45a8ff	804	}
bogdanm	0:9b334a45a8ff	805	else
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	808	}
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/**
bogdanm	0:9b334a45a8ff	812	* @brief Receive an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	813	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	814	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	815	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	816	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	817	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	818	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	819	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	820	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	821	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	822	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	823	* @retval HAL status
bogdanm	0:9b334a45a8ff	824	*/
bogdanm	0:9b334a45a8ff	825	HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	826	{
bogdanm	0:9b334a45a8ff	827	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	828	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	836	{
bogdanm	0:9b334a45a8ff	837	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	838	tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	839	tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN);
bogdanm	0:9b334a45a8ff	840	if((tmp1 == I2S_DATAFORMAT_24B)\|\| \
bogdanm	0:9b334a45a8ff	841	(tmp2 == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	842	{
bogdanm	0:9b334a45a8ff	843	hi2s->RxXferSize = Size*2;
bogdanm	0:9b334a45a8ff	844	hi2s->RxXferCount = Size*2;
bogdanm	0:9b334a45a8ff	845	}
bogdanm	0:9b334a45a8ff	846	else
bogdanm	0:9b334a45a8ff	847	{
bogdanm	0:9b334a45a8ff	848	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	849	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851	/* Process Locked */
bogdanm	0:9b334a45a8ff	852	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	855	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Set the I2S Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	858	hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Set the I2S Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	861	hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	864	hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	867	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	868	{
bogdanm	0:9b334a45a8ff	869	/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	870	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	871	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	872	}
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/* Enable the Rx DMA Stream */
bogdanm	0:9b334a45a8ff	875	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	876	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)tmp, hi2s->RxXferSize);
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	879	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	882	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/* Check if the I2S Rx request is already enabled */
bogdanm	0:9b334a45a8ff	886	if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	889	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	890	}
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	893	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	return HAL_OK;
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	else
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	900	}
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/**
bogdanm	0:9b334a45a8ff	904	* @brief Pauses the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	905	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	906	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	907	* @retval HAL status
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909	__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	910	{
bogdanm	0:9b334a45a8ff	911	/* Process Locked */
bogdanm	0:9b334a45a8ff	912	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	915	{
bogdanm	0:9b334a45a8ff	916	/* Disable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	917	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	918	}
bogdanm	0:9b334a45a8ff	919	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	920	{
bogdanm	0:9b334a45a8ff	921	/* Disable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	922	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	925	{
bogdanm	0:9b334a45a8ff	926	if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)\|\|(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
bogdanm	0:9b334a45a8ff	927	{
bogdanm	0:9b334a45a8ff	928	/* Disable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	929	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	930	}
bogdanm	0:9b334a45a8ff	931	else
bogdanm	0:9b334a45a8ff	932	{
bogdanm	0:9b334a45a8ff	933	/* Disable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	934	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	935	}
bogdanm	0:9b334a45a8ff	936	}
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	939	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	return HAL_OK;
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/**
bogdanm	0:9b334a45a8ff	945	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	946	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	947	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	948	* @retval HAL status
bogdanm	0:9b334a45a8ff	949	*/
bogdanm	0:9b334a45a8ff	950	__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	951	{
bogdanm	0:9b334a45a8ff	952	/* Process Locked */
bogdanm	0:9b334a45a8ff	953	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	956	{
bogdanm	0:9b334a45a8ff	957	/* Enable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	958	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	959	}
bogdanm	0:9b334a45a8ff	960	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	961	{
bogdanm	0:9b334a45a8ff	962	/* Enable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	963	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	964	}
bogdanm	0:9b334a45a8ff	965	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	966	{
bogdanm	0:9b334a45a8ff	967	if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)\|\|(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
bogdanm	0:9b334a45a8ff	968	{
bogdanm	0:9b334a45a8ff	969	/* Enable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	970	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	971	}
bogdanm	0:9b334a45a8ff	972	else
bogdanm	0:9b334a45a8ff	973	{
bogdanm	0:9b334a45a8ff	974	/* Enable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	975	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	976	}
bogdanm	0:9b334a45a8ff	977	}
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/* If the I2S peripheral is still not enabled, enable it */
bogdanm	0:9b334a45a8ff	980	if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
bogdanm	0:9b334a45a8ff	981	{
bogdanm	0:9b334a45a8ff	982	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	983	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	984	}
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	987	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	return HAL_OK;
bogdanm	0:9b334a45a8ff	990	}
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	994	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	995	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	996	* @retval HAL status
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998	__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	999	{
bogdanm	0:9b334a45a8ff	1000	/* Process Locked */
bogdanm	0:9b334a45a8ff	1001	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Disable the I2S Tx/Rx DMA requests */
bogdanm	0:9b334a45a8ff	1004	hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1005	hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	/* Abort the I2S DMA Stream tx */
bogdanm	0:9b334a45a8ff	1008	if(hi2s->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1009	{
bogdanm	0:9b334a45a8ff	1010	HAL_DMA_Abort(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	1011	}
bogdanm	0:9b334a45a8ff	1012	/* Abort the I2S DMA Stream rx */
bogdanm	0:9b334a45a8ff	1013	if(hi2s->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1014	{
bogdanm	0:9b334a45a8ff	1015	HAL_DMA_Abort(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Disable I2S peripheral */
bogdanm	0:9b334a45a8ff	1019	__HAL_I2S_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1024	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	return HAL_OK;
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	/**
bogdanm	0:9b334a45a8ff	1030	* @brief This function handles I2S interrupt request.
bogdanm	0:9b334a45a8ff	1031	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1032	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1033	* @retval None
bogdanm	0:9b334a45a8ff	1034	*/
bogdanm	0:9b334a45a8ff	1035	__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1036	{
bogdanm	0:9b334a45a8ff	1037	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1040	{
bogdanm	0:9b334a45a8ff	1041	tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
bogdanm	0:9b334a45a8ff	1042	tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
bogdanm	0:9b334a45a8ff	1043	/* I2S in mode Receiver ------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1044	if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm	0:9b334a45a8ff	1045	{
bogdanm	0:9b334a45a8ff	1046	I2S_Receive_IT(hi2s);
bogdanm	0:9b334a45a8ff	1047	}
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1050	tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
bogdanm	0:9b334a45a8ff	1051	/* I2S Overrun error interrupt occurred ---------------------------------*/
bogdanm	0:9b334a45a8ff	1052	if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm	0:9b334a45a8ff	1053	{
bogdanm	0:9b334a45a8ff	1054	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	1055	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1056	}
bogdanm	0:9b334a45a8ff	1057	}
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
bogdanm	0:9b334a45a8ff	1062	tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
bogdanm	0:9b334a45a8ff	1063	/* I2S in mode Transmitter -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1064	if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm	0:9b334a45a8ff	1065	{
bogdanm	0:9b334a45a8ff	1066	I2S_Transmit_IT(hi2s);
bogdanm	0:9b334a45a8ff	1067	}
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
bogdanm	0:9b334a45a8ff	1070	tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
bogdanm	0:9b334a45a8ff	1071	/* I2S Underrun error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1072	if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm	0:9b334a45a8ff	1073	{
bogdanm	0:9b334a45a8ff	1074	__HAL_I2S_CLEAR_UDRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	1075	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077	}
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1080	if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1081	{
bogdanm	0:9b334a45a8ff	1082	/* Set the I2S state ready to be able to start again the process */
bogdanm	0:9b334a45a8ff	1083	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1084	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1085	}
bogdanm	0:9b334a45a8ff	1086	}
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/**
bogdanm	0:9b334a45a8ff	1089	* @brief Tx Transfer Half completed callbacks
bogdanm	0:9b334a45a8ff	1090	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1091	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1092	* @retval None
bogdanm	0:9b334a45a8ff	1093	*/
bogdanm	0:9b334a45a8ff	1094	__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1097	the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1098	*/
bogdanm	0:9b334a45a8ff	1099	}
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/**
bogdanm	0:9b334a45a8ff	1102	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1103	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1104	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1105	* @retval None
bogdanm	0:9b334a45a8ff	1106	*/
bogdanm	0:9b334a45a8ff	1107	__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1108	{
bogdanm	0:9b334a45a8ff	1109	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1110	the HAL_I2S_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1111	*/
bogdanm	0:9b334a45a8ff	1112	}
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/**
bogdanm	0:9b334a45a8ff	1115	* @brief Rx Transfer half completed callbacks
bogdanm	0:9b334a45a8ff	1116	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1117	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1118	* @retval None
bogdanm	0:9b334a45a8ff	1119	*/
bogdanm	0:9b334a45a8ff	1120	__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1121	{
bogdanm	0:9b334a45a8ff	1122	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1123	the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1124	*/
bogdanm	0:9b334a45a8ff	1125	}
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/**
bogdanm	0:9b334a45a8ff	1128	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1129	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1130	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1131	* @retval None
bogdanm	0:9b334a45a8ff	1132	*/
bogdanm	0:9b334a45a8ff	1133	__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1134	{
bogdanm	0:9b334a45a8ff	1135	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1136	the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1137	*/
bogdanm	0:9b334a45a8ff	1138	}
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/**
bogdanm	0:9b334a45a8ff	1141	* @brief I2S error callbacks
bogdanm	0:9b334a45a8ff	1142	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1143	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1144	* @retval None
bogdanm	0:9b334a45a8ff	1145	*/
bogdanm	0:9b334a45a8ff	1146	__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1147	{
bogdanm	0:9b334a45a8ff	1148	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1149	the HAL_I2S_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1150	*/
bogdanm	0:9b334a45a8ff	1151	}
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/**
bogdanm	0:9b334a45a8ff	1154	* @}
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1158	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1159	@verbatim
bogdanm	0:9b334a45a8ff	1160	===============================================================================
bogdanm	0:9b334a45a8ff	1161	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1162	===============================================================================
bogdanm	0:9b334a45a8ff	1163	[..]
bogdanm	0:9b334a45a8ff	1164	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1165	and the data flow.
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	@endverbatim
bogdanm	0:9b334a45a8ff	1168	* @{
bogdanm	0:9b334a45a8ff	1169	*/
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/**
bogdanm	0:9b334a45a8ff	1172	* @brief Return the I2S state
bogdanm	0:9b334a45a8ff	1173	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1174	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1175	* @retval HAL state
bogdanm	0:9b334a45a8ff	1176	*/
bogdanm	0:9b334a45a8ff	1177	HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1178	{
bogdanm	0:9b334a45a8ff	1179	return hi2s->State;
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/**
bogdanm	0:9b334a45a8ff	1183	* @brief Return the I2S error code
bogdanm	0:9b334a45a8ff	1184	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1185	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1186	* @retval I2S Error Code
bogdanm	0:9b334a45a8ff	1187	*/
bogdanm	0:9b334a45a8ff	1188	uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1189	{
bogdanm	0:9b334a45a8ff	1190	return hi2s->ErrorCode;
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192	/**
bogdanm	0:9b334a45a8ff	1193	* @}
bogdanm	0:9b334a45a8ff	1194	*/
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/**
bogdanm	0:9b334a45a8ff	1197	* @brief DMA I2S transmit process half complete callback
bogdanm	0:9b334a45a8ff	1198	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1199	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1200	* @retval None
bogdanm	0:9b334a45a8ff	1201	*/
bogdanm	0:9b334a45a8ff	1202	void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1203	{
bogdanm	0:9b334a45a8ff	1204	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	HAL_I2S_TxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/**
bogdanm	0:9b334a45a8ff	1210	* @brief DMA I2S receive process half complete callback
bogdanm	0:9b334a45a8ff	1211	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1212	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1213	* @retval None
bogdanm	0:9b334a45a8ff	1214	*/
bogdanm	0:9b334a45a8ff	1215	void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	HAL_I2S_RxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/**
bogdanm	0:9b334a45a8ff	1223	* @brief DMA I2S communication error callback
bogdanm	0:9b334a45a8ff	1224	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1225	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1226	* @retval None
bogdanm	0:9b334a45a8ff	1227	*/
bogdanm	0:9b334a45a8ff	1228	void I2S_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1229	{
bogdanm	0:9b334a45a8ff	1230	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1231
bogdanm	0:9b334a45a8ff	1232	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1233	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	hi2s->ErrorCode \|= HAL_I2S_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1238	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1239	}
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/**
bogdanm	0:9b334a45a8ff	1242	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1243	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1244	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1245	* @retval HAL status
bogdanm	0:9b334a45a8ff	1246	*/
bogdanm	0:9b334a45a8ff	1247	HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1250	{
bogdanm	0:9b334a45a8ff	1251	/* Process Locked */
bogdanm	0:9b334a45a8ff	1252	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	/* Transmit data */
bogdanm	0:9b334a45a8ff	1255	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1260	{
bogdanm	0:9b334a45a8ff	1261	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1262	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1267	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1268	HAL_I2S_TxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1269	}
bogdanm	0:9b334a45a8ff	1270	else
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1273	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1274	}
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	return HAL_OK;
bogdanm	0:9b334a45a8ff	1277	}
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	else
bogdanm	0:9b334a45a8ff	1280	{
bogdanm	0:9b334a45a8ff	1281	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1282	}
bogdanm	0:9b334a45a8ff	1283	}
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	/**
bogdanm	0:9b334a45a8ff	1286	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1287	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1288	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1289	* @retval HAL status
bogdanm	0:9b334a45a8ff	1290	*/
bogdanm	0:9b334a45a8ff	1291	HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1294	{
bogdanm	0:9b334a45a8ff	1295	/* Process Locked */
bogdanm	0:9b334a45a8ff	1296	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/* Receive data */
bogdanm	0:9b334a45a8ff	1299	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	1304	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	1307	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	1308	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	1309	}
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1312	{
bogdanm	0:9b334a45a8ff	1313	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1314	__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE \| I2S_IT_ERR);
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1319	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	HAL_I2S_RxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323	else
bogdanm	0:9b334a45a8ff	1324	{
bogdanm	0:9b334a45a8ff	1325	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1326	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	return HAL_OK;
bogdanm	0:9b334a45a8ff	1330	}
bogdanm	0:9b334a45a8ff	1331	else
bogdanm	0:9b334a45a8ff	1332	{
bogdanm	0:9b334a45a8ff	1333	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335	}
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/**
bogdanm	0:9b334a45a8ff	1338	* @brief This function handles I2S Communication Timeout.
bogdanm	0:9b334a45a8ff	1339	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1340	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1341	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1342	* @param Status: Value of the flag expected
bogdanm	0:9b334a45a8ff	1343	* @param Timeout: Duration of the timeout
bogdanm	0:9b334a45a8ff	1344	* @retval HAL status
bogdanm	0:9b334a45a8ff	1345	*/
bogdanm	0:9b334a45a8ff	1346	HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1347	{
bogdanm	0:9b334a45a8ff	1348	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Get tick */
bogdanm	0:9b334a45a8ff	1351	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	1354	if(Status == RESET)
bogdanm	0:9b334a45a8ff	1355	{
bogdanm	0:9b334a45a8ff	1356	while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
bogdanm	0:9b334a45a8ff	1357	{
bogdanm	0:9b334a45a8ff	1358	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1359	{
bogdanm	0:9b334a45a8ff	1360	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1361	{
bogdanm	0:9b334a45a8ff	1362	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1363	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1366	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1369	}
bogdanm	0:9b334a45a8ff	1370	}
bogdanm	0:9b334a45a8ff	1371	}
bogdanm	0:9b334a45a8ff	1372	}
bogdanm	0:9b334a45a8ff	1373	else
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
bogdanm	0:9b334a45a8ff	1376	{
bogdanm	0:9b334a45a8ff	1377	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1382	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1385	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1388	}
bogdanm	0:9b334a45a8ff	1389	}
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391	}
bogdanm	0:9b334a45a8ff	1392	return HAL_OK;
bogdanm	0:9b334a45a8ff	1393	}
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/**
bogdanm	0:9b334a45a8ff	1396	* @}
bogdanm	0:9b334a45a8ff	1397	*/
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	#endif /* HAL_I2S_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1400	/**
bogdanm	0:9b334a45a8ff	1401	* @}
bogdanm	0:9b334a45a8ff	1402	*/
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/**
bogdanm	0:9b334a45a8ff	1405	* @}
bogdanm	0:9b334a45a8ff	1406	*/
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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