en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_dma_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief DMA Extension HAL module driver
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the DMA Extension peripheral:
bogdanm 0:9b334a45a8ff 10 * + Extended features functions
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 @verbatim
bogdanm 0:9b334a45a8ff 13 ==============================================================================
bogdanm 0:9b334a45a8ff 14 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 [..]
bogdanm 0:9b334a45a8ff 17 The DMA Extension HAL driver can be used as follows:
bogdanm 0:9b334a45a8ff 18 (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
bogdanm 0:9b334a45a8ff 19 for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
bogdanm 0:9b334a45a8ff 22 -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
bogdanm 0:9b334a45a8ff 23 -@- In Multi (Double) buffer mode, it is possible to update the base address for
bogdanm 0:9b334a45a8ff 24 the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 @endverbatim
bogdanm 0:9b334a45a8ff 27 ******************************************************************************
bogdanm 0:9b334a45a8ff 28 * @attention
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 31 *
bogdanm 0:9b334a45a8ff 32 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 33 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 34 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 35 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 36 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 37 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 38 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 39 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 40 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 41 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 44 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 46 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 50 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 53 *
bogdanm 0:9b334a45a8ff 54 ******************************************************************************
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /** @defgroup DMAEx DMAEx
bogdanm 0:9b334a45a8ff 65 * @brief DMA Extended HAL module driver
bogdanm 0:9b334a45a8ff 66 * @{
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 72 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 73 /* Private Constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 74 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 75 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 76 /** @addtogroup DMAEx_Private_Functions
bogdanm 0:9b334a45a8ff 77 * @{
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 80 /**
bogdanm 0:9b334a45a8ff 81 * @}
bogdanm 0:9b334a45a8ff 82 */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /** @addtogroup DMAEx_Exported_Functions
bogdanm 0:9b334a45a8ff 87 * @{
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /** @addtogroup DMAEx_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 92 *
bogdanm 0:9b334a45a8ff 93 @verbatim
bogdanm 0:9b334a45a8ff 94 ===============================================================================
bogdanm 0:9b334a45a8ff 95 ##### Extended features functions #####
bogdanm 0:9b334a45a8ff 96 ===============================================================================
bogdanm 0:9b334a45a8ff 97 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 98 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 99 Start MultiBuffer DMA transfer
bogdanm 0:9b334a45a8ff 100 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 101 Start MultiBuffer DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 102 (+) Change on the fly the memory0 or memory1 address.
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 @endverbatim
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /**
bogdanm 0:9b334a45a8ff 110 * @brief Starts the multi_buffer DMA Transfer.
bogdanm 0:9b334a45a8ff 111 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 112 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 113 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 114 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 115 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
bogdanm 0:9b334a45a8ff 116 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 117 * @retval HAL status
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 /* Process Locked */
bogdanm 0:9b334a45a8ff 122 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 125 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 126 {
bogdanm 0:9b334a45a8ff 127 hdma->State = HAL_DMA_STATE_BUSY_MEM0;
bogdanm 0:9b334a45a8ff 128 }
bogdanm 0:9b334a45a8ff 129 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 130 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 131 {
bogdanm 0:9b334a45a8ff 132 hdma->State = HAL_DMA_STATE_BUSY_MEM1;
bogdanm 0:9b334a45a8ff 133 }
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /* Check the parameters */
bogdanm 0:9b334a45a8ff 136 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 139 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Enable the double buffer mode */
bogdanm 0:9b334a45a8ff 142 hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 145 hdma->Instance->M1AR = SecondMemAddress;
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 148 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* Enable the peripheral */
bogdanm 0:9b334a45a8ff 151 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 return HAL_OK;
bogdanm 0:9b334a45a8ff 154 }
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /**
bogdanm 0:9b334a45a8ff 157 * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 158 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 159 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 160 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 161 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 162 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
bogdanm 0:9b334a45a8ff 163 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 164 * @retval HAL status
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 /* Process Locked */
bogdanm 0:9b334a45a8ff 169 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 172 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 173 {
bogdanm 0:9b334a45a8ff 174 hdma->State = HAL_DMA_STATE_BUSY_MEM0;
bogdanm 0:9b334a45a8ff 175 }
bogdanm 0:9b334a45a8ff 176 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 177 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 hdma->State = HAL_DMA_STATE_BUSY_MEM1;
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /* Check the parameters */
bogdanm 0:9b334a45a8ff 183 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 186 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Enable the Double buffer mode */
bogdanm 0:9b334a45a8ff 189 hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 192 hdma->Instance->M1AR = SecondMemAddress;
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 195 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 198 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Enable the Half transfer interrupt */
bogdanm 0:9b334a45a8ff 201 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 204 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Enable the fifo Error interrupt */
bogdanm 0:9b334a45a8ff 207 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Enable the direct mode Error interrupt */
bogdanm 0:9b334a45a8ff 210 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Enable the peripheral */
bogdanm 0:9b334a45a8ff 213 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 return HAL_OK;
bogdanm 0:9b334a45a8ff 216 }
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief Change the memory0 or memory1 address on the fly.
bogdanm 0:9b334a45a8ff 220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 221 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 222 * @param Address: The new address
bogdanm 0:9b334a45a8ff 223 * @param memory: the memory to be changed, This parameter can be one of
bogdanm 0:9b334a45a8ff 224 * the following values:
bogdanm 0:9b334a45a8ff 225 * MEMORY0 /
bogdanm 0:9b334a45a8ff 226 * MEMORY1
bogdanm 0:9b334a45a8ff 227 * @note The MEMORY0 address can be changed only when the current transfer use
bogdanm 0:9b334a45a8ff 228 * MEMORY1 and the MEMORY1 address can be changed only when the current
bogdanm 0:9b334a45a8ff 229 * transfer use MEMORY0.
bogdanm 0:9b334a45a8ff 230 * @retval HAL status
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
bogdanm 0:9b334a45a8ff 233 {
bogdanm 0:9b334a45a8ff 234 if(memory == MEMORY0)
bogdanm 0:9b334a45a8ff 235 {
bogdanm 0:9b334a45a8ff 236 /* change the memory0 address */
bogdanm 0:9b334a45a8ff 237 hdma->Instance->M0AR = Address;
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239 else
bogdanm 0:9b334a45a8ff 240 {
bogdanm 0:9b334a45a8ff 241 /* change the memory1 address */
bogdanm 0:9b334a45a8ff 242 hdma->Instance->M1AR = Address;
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 return HAL_OK;
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /**
bogdanm 0:9b334a45a8ff 249 * @}
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /**
bogdanm 0:9b334a45a8ff 253 * @}
bogdanm 0:9b334a45a8ff 254 */
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /** @addtogroup DMAEx_Private_Functions
bogdanm 0:9b334a45a8ff 257 * @{
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /**
bogdanm 0:9b334a45a8ff 261 * @brief Set the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 262 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 263 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 264 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 265 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 266 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 267 * @retval HAL status
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 /* Configure DMA Stream data length */
bogdanm 0:9b334a45a8ff 272 hdma->Instance->NDTR = DataLength;
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 275 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 278 hdma->Instance->PAR = DstAddress;
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 281 hdma->Instance->M0AR = SrcAddress;
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 284 else
bogdanm 0:9b334a45a8ff 285 {
bogdanm 0:9b334a45a8ff 286 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 287 hdma->Instance->PAR = SrcAddress;
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 290 hdma->Instance->M0AR = DstAddress;
bogdanm 0:9b334a45a8ff 291 }
bogdanm 0:9b334a45a8ff 292 }
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /**
bogdanm 0:9b334a45a8ff 295 * @}
bogdanm 0:9b334a45a8ff 296 */
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 299 /**
bogdanm 0:9b334a45a8ff 300 * @}
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @}
bogdanm 0:9b334a45a8ff 305 */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/