en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_dma2d.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief DMA2D HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the DMA2D peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 [..]
bogdanm 0:9b334a45a8ff 20 (#) Program the required configuration through following parameters:
bogdanm 0:9b334a45a8ff 21 the Transfer Mode, the output color mode and the output offset using
bogdanm 0:9b334a45a8ff 22 HAL_DMA2D_Init() function.
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) Program the required configuration through following parameters:
bogdanm 0:9b334a45a8ff 25 the input color mode, the input color, input alpha value, alpha mode
bogdanm 0:9b334a45a8ff 26 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
bogdanm 0:9b334a45a8ff 27 or/and background layer.
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 30 =================================
bogdanm 0:9b334a45a8ff 31 [..]
bogdanm 0:9b334a45a8ff 32 (+) Configure the pdata, Destination and data length and Enable
bogdanm 0:9b334a45a8ff 33 the transfer using HAL_DMA2D_Start()
bogdanm 0:9b334a45a8ff 34 (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
bogdanm 0:9b334a45a8ff 35 user can specify the value of timeout according to his end application.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 38 ===================================
bogdanm 0:9b334a45a8ff 39 [..]
bogdanm 0:9b334a45a8ff 40 (#) Configure the pdata, Destination and data length and Enable
bogdanm 0:9b334a45a8ff 41 the transfer using HAL_DMA2D_Start_IT()
bogdanm 0:9b334a45a8ff 42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 44 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 45 XferErrorCallback (i.e a member of DMA2D handle structure).
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 -@- In Register-to-Memory transfer mode, the pdata parameter is the register
bogdanm 0:9b334a45a8ff 48 color, in Memory-to-memory or memory-to-memory with pixel format
bogdanm 0:9b334a45a8ff 49 conversion the pdata is the source address.
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 -@- Configure the foreground source address, the background source address,
bogdanm 0:9b334a45a8ff 52 the Destination and data length and Enable the transfer using
bogdanm 0:9b334a45a8ff 53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
bogdanm 0:9b334a45a8ff 54 in interrupt mode.
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
bogdanm 0:9b334a45a8ff 57 are used if the memory to memory with blending transfer mode is selected.
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
bogdanm 0:9b334a45a8ff 60 HAL_DMA2D_EnableCLUT() functions.
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 (#) Optionally, configure and enable LineInterrupt using the following function:
bogdanm 0:9b334a45a8ff 63 HAL_DMA2D_ProgramLineEvent().
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 (#) The transfer can be suspended, continued and aborted using the following
bogdanm 0:9b334a45a8ff 66 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 *** DMA2D HAL driver macros list ***
bogdanm 0:9b334a45a8ff 71 =============================================
bogdanm 0:9b334a45a8ff 72 [..]
bogdanm 0:9b334a45a8ff 73 Below the list of most used macros in DMA2D HAL driver :
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
bogdanm 0:9b334a45a8ff 76 (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
bogdanm 0:9b334a45a8ff 77 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
bogdanm 0:9b334a45a8ff 78 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
bogdanm 0:9b334a45a8ff 79 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
bogdanm 0:9b334a45a8ff 80 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
bogdanm 0:9b334a45a8ff 81 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 [..]
bogdanm 0:9b334a45a8ff 84 (@) You can refer to the DMA2D HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 @endverbatim
bogdanm 0:9b334a45a8ff 87 ******************************************************************************
bogdanm 0:9b334a45a8ff 88 * @attention
bogdanm 0:9b334a45a8ff 89 *
bogdanm 0:9b334a45a8ff 90 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 91 *
bogdanm 0:9b334a45a8ff 92 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 93 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 94 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 95 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 96 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 97 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 98 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 99 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 100 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 101 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 102 *
bogdanm 0:9b334a45a8ff 103 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 104 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 105 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 106 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 107 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 108 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 109 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 110 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 111 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 112 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 113 *
bogdanm 0:9b334a45a8ff 114 ******************************************************************************
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 121 * @{
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123 /** @addtogroup DMA2D
bogdanm 0:9b334a45a8ff 124 * @brief DMA2D HAL module driver
bogdanm 0:9b334a45a8ff 125 * @{
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 #ifdef HAL_DMA2D_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 129
mbed_official 19:112740acecfa 130 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 133 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 134 /** @addtogroup DMA2D_Private_Defines
bogdanm 0:9b334a45a8ff 135 * @{
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137 #define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 138 #define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 139 /**
bogdanm 0:9b334a45a8ff 140 * @}
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 144 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 145 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 146 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /** @addtogroup DMA2D_Private_Functions_Prototypes
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 0:9b334a45a8ff 151 /**
bogdanm 0:9b334a45a8ff 152 * @}
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 156 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 157 /** @addtogroup DMA2D_Exported_Functions
bogdanm 0:9b334a45a8ff 158 * @{
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /** @defgroup DMA2D_Group1 Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 162 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 163 *
bogdanm 0:9b334a45a8ff 164 @verbatim
bogdanm 0:9b334a45a8ff 165 ===============================================================================
bogdanm 0:9b334a45a8ff 166 ##### Initialization and Configuration functions #####
bogdanm 0:9b334a45a8ff 167 ===============================================================================
bogdanm 0:9b334a45a8ff 168 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 169 (+) Initialize and configure the DMA2D
bogdanm 0:9b334a45a8ff 170 (+) De-initialize the DMA2D
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 @endverbatim
bogdanm 0:9b334a45a8ff 173 * @{
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /**
bogdanm 0:9b334a45a8ff 177 * @brief Initializes the DMA2D according to the specified
bogdanm 0:9b334a45a8ff 178 * parameters in the DMA2D_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 179 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 180 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 181 * @retval HAL status
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 184 {
bogdanm 0:9b334a45a8ff 185 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /* Check the DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 188 if(hdma2d == NULL)
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 191 }
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /* Check the parameters */
bogdanm 0:9b334a45a8ff 194 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
bogdanm 0:9b334a45a8ff 195 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
bogdanm 0:9b334a45a8ff 196 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
bogdanm 0:9b334a45a8ff 197 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
bogdanm 0:9b334a45a8ff 200 {
bogdanm 0:9b334a45a8ff 201 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 202 hdma2d->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 203 /* Init the low level hardware */
bogdanm 0:9b334a45a8ff 204 HAL_DMA2D_MspInit(hdma2d);
bogdanm 0:9b334a45a8ff 205 }
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 208 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* DMA2D CR register configuration -------------------------------------------*/
bogdanm 0:9b334a45a8ff 211 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 212 tmp = hdma2d->Instance->CR;
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /* Clear Mode bits */
bogdanm 0:9b334a45a8ff 215 tmp &= (uint32_t)~DMA2D_CR_MODE;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /* Prepare the value to be wrote to the CR register */
bogdanm 0:9b334a45a8ff 218 tmp |= hdma2d->Init.Mode;
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 /* Write to DMA2D CR register */
bogdanm 0:9b334a45a8ff 221 hdma2d->Instance->CR = tmp;
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* DMA2D OPFCCR register configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 224 /* Get the OPFCCR register value */
bogdanm 0:9b334a45a8ff 225 tmp = hdma2d->Instance->OPFCCR;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Clear Color Mode bits */
bogdanm 0:9b334a45a8ff 228 tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Prepare the value to be wrote to the OPFCCR register */
bogdanm 0:9b334a45a8ff 231 tmp |= hdma2d->Init.ColorMode;
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Write to DMA2D OPFCCR register */
bogdanm 0:9b334a45a8ff 234 hdma2d->Instance->OPFCCR = tmp;
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* DMA2D OOR register configuration ------------------------------------------*/
bogdanm 0:9b334a45a8ff 237 /* Get the OOR register value */
bogdanm 0:9b334a45a8ff 238 tmp = hdma2d->Instance->OOR;
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 /* Clear Offset bits */
bogdanm 0:9b334a45a8ff 241 tmp &= (uint32_t)~DMA2D_OOR_LO;
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /* Prepare the value to be wrote to the OOR register */
bogdanm 0:9b334a45a8ff 244 tmp |= hdma2d->Init.OutputOffset;
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /* Write to DMA2D OOR register */
bogdanm 0:9b334a45a8ff 247 hdma2d->Instance->OOR = tmp;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* Update error code */
bogdanm 0:9b334a45a8ff 250 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /* Initialize the DMA2D state*/
bogdanm 0:9b334a45a8ff 253 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 return HAL_OK;
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /**
bogdanm 0:9b334a45a8ff 259 * @brief Deinitializes the DMA2D peripheral registers to their default reset
bogdanm 0:9b334a45a8ff 260 * values.
bogdanm 0:9b334a45a8ff 261 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 262 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 263 * @retval None
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 /* Check the DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 269 if(hdma2d == NULL)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 272 }
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* DeInit the low level hardware */
bogdanm 0:9b334a45a8ff 275 HAL_DMA2D_MspDeInit(hdma2d);
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* Update error code */
bogdanm 0:9b334a45a8ff 278 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* Initialize the DMA2D state*/
bogdanm 0:9b334a45a8ff 281 hdma2d->State = HAL_DMA2D_STATE_RESET;
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /* Release Lock */
bogdanm 0:9b334a45a8ff 284 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 return HAL_OK;
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /**
bogdanm 0:9b334a45a8ff 290 * @brief Initializes the DMA2D MSP.
bogdanm 0:9b334a45a8ff 291 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 292 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 293 * @retval None
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 298 the HAL_DMA2D_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /**
bogdanm 0:9b334a45a8ff 303 * @brief DeInitializes the DMA2D MSP.
bogdanm 0:9b334a45a8ff 304 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 305 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 306 * @retval None
bogdanm 0:9b334a45a8ff 307 */
bogdanm 0:9b334a45a8ff 308 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
bogdanm 0:9b334a45a8ff 309 {
bogdanm 0:9b334a45a8ff 310 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 311 the HAL_DMA2D_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 312 */
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /**
bogdanm 0:9b334a45a8ff 316 * @}
bogdanm 0:9b334a45a8ff 317 */
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /** @defgroup DMA2D_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 320 * @brief IO operation functions
bogdanm 0:9b334a45a8ff 321 *
bogdanm 0:9b334a45a8ff 322 @verbatim
bogdanm 0:9b334a45a8ff 323 ===============================================================================
bogdanm 0:9b334a45a8ff 324 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 325 ===============================================================================
bogdanm 0:9b334a45a8ff 326 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 327 (+) Configure the pdata, destination address and data size and
bogdanm 0:9b334a45a8ff 328 Start DMA2D transfer.
bogdanm 0:9b334a45a8ff 329 (+) Configure the source for foreground and background, destination address
bogdanm 0:9b334a45a8ff 330 and data size and Start MultiBuffer DMA2D transfer.
bogdanm 0:9b334a45a8ff 331 (+) Configure the pdata, destination address and data size and
bogdanm 0:9b334a45a8ff 332 Start DMA2D transfer with interrupt.
bogdanm 0:9b334a45a8ff 333 (+) Configure the source for foreground and background, destination address
bogdanm 0:9b334a45a8ff 334 and data size and Start MultiBuffer DMA2D transfer with interrupt.
bogdanm 0:9b334a45a8ff 335 (+) Abort DMA2D transfer.
bogdanm 0:9b334a45a8ff 336 (+) Suspend DMA2D transfer.
bogdanm 0:9b334a45a8ff 337 (+) Continue DMA2D transfer.
bogdanm 0:9b334a45a8ff 338 (+) Poll for transfer complete.
bogdanm 0:9b334a45a8ff 339 (+) handle DMA2D interrupt request.
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 @endverbatim
bogdanm 0:9b334a45a8ff 342 * @{
bogdanm 0:9b334a45a8ff 343 */
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Start the DMA2D Transfer.
bogdanm 0:9b334a45a8ff 347 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 348 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 349 * @param pdata: Configure the source memory Buffer address if
bogdanm 0:9b334a45a8ff 350 * the memory to memory or memory to memory with pixel format
bogdanm 0:9b334a45a8ff 351 * conversion DMA2D mode is selected, and configure
bogdanm 0:9b334a45a8ff 352 * the color value if register to memory DMA2D mode is selected.
bogdanm 0:9b334a45a8ff 353 * @param DstAddress: The destination memory Buffer address.
bogdanm 0:9b334a45a8ff 354 * @param Width: The width of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 355 * @param Height: The height of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 356 * @retval HAL status
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 /* Process locked */
bogdanm 0:9b334a45a8ff 361 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 364 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Check the parameters */
bogdanm 0:9b334a45a8ff 367 assert_param(IS_DMA2D_LINE(Height));
bogdanm 0:9b334a45a8ff 368 assert_param(IS_DMA2D_PIXEL(Width));
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 371 __HAL_DMA2D_DISABLE(hdma2d);
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Configure the source, destination address and the data size */
bogdanm 0:9b334a45a8ff 374 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 377 __HAL_DMA2D_ENABLE(hdma2d);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 return HAL_OK;
bogdanm 0:9b334a45a8ff 380 }
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @brief Start the DMA2D Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 384 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 385 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 386 * @param pdata: Configure the source memory Buffer address if
bogdanm 0:9b334a45a8ff 387 * the memory to memory or memory to memory with pixel format
bogdanm 0:9b334a45a8ff 388 * conversion DMA2D mode is selected, and configure
bogdanm 0:9b334a45a8ff 389 * the color value if register to memory DMA2D mode is selected.
bogdanm 0:9b334a45a8ff 390 * @param DstAddress: The destination memory Buffer address.
bogdanm 0:9b334a45a8ff 391 * @param Width: The width of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 392 * @param Height: The height of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 393 * @retval HAL status
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
bogdanm 0:9b334a45a8ff 396 {
bogdanm 0:9b334a45a8ff 397 /* Process locked */
bogdanm 0:9b334a45a8ff 398 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 401 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* Check the parameters */
bogdanm 0:9b334a45a8ff 404 assert_param(IS_DMA2D_LINE(Height));
bogdanm 0:9b334a45a8ff 405 assert_param(IS_DMA2D_PIXEL(Width));
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 408 __HAL_DMA2D_DISABLE(hdma2d);
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Configure the source, destination address and the data size */
bogdanm 0:9b334a45a8ff 411 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 414 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 417 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 420 __HAL_DMA2D_ENABLE(hdma2d);
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* Enable the configuration error interrupt */
bogdanm 0:9b334a45a8ff 423 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 return HAL_OK;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @brief Start the multi-source DMA2D Transfer.
bogdanm 0:9b334a45a8ff 430 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 431 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 432 * @param SrcAddress1: The source memory Buffer address of the foreground layer.
bogdanm 0:9b334a45a8ff 433 * @param SrcAddress2: The source memory Buffer address of the background layer.
bogdanm 0:9b334a45a8ff 434 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 435 * @param Width: The width of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 436 * @param Height: The height of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 437 * @retval HAL status
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Process locked */
bogdanm 0:9b334a45a8ff 442 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 445 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Check the parameters */
bogdanm 0:9b334a45a8ff 448 assert_param(IS_DMA2D_LINE(Height));
bogdanm 0:9b334a45a8ff 449 assert_param(IS_DMA2D_PIXEL(Width));
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 452 __HAL_DMA2D_DISABLE(hdma2d);
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /* Configure DMA2D Stream source2 address */
bogdanm 0:9b334a45a8ff 455 hdma2d->Instance->BGMAR = SrcAddress2;
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 /* Configure the source, destination address and the data size */
bogdanm 0:9b334a45a8ff 458 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 461 __HAL_DMA2D_ENABLE(hdma2d);
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 return HAL_OK;
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 468 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 469 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 470 * @param SrcAddress1: The source memory Buffer address of the foreground layer.
bogdanm 0:9b334a45a8ff 471 * @param SrcAddress2: The source memory Buffer address of the background layer.
bogdanm 0:9b334a45a8ff 472 * @param DstAddress: The destination memory Buffer address.
bogdanm 0:9b334a45a8ff 473 * @param Width: The width of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 474 * @param Height: The height of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 475 * @retval HAL status
bogdanm 0:9b334a45a8ff 476 */
bogdanm 0:9b334a45a8ff 477 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 /* Process locked */
bogdanm 0:9b334a45a8ff 480 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 483 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* Check the parameters */
bogdanm 0:9b334a45a8ff 486 assert_param(IS_DMA2D_LINE(Height));
bogdanm 0:9b334a45a8ff 487 assert_param(IS_DMA2D_PIXEL(Width));
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 490 __HAL_DMA2D_DISABLE(hdma2d);
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /* Configure DMA2D Stream source2 address */
bogdanm 0:9b334a45a8ff 493 hdma2d->Instance->BGMAR = SrcAddress2;
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Configure the source, destination address and the data size */
bogdanm 0:9b334a45a8ff 496 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Enable the configuration error interrupt */
bogdanm 0:9b334a45a8ff 499 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /* Enable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 502 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* Enable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 505 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 508 __HAL_DMA2D_ENABLE(hdma2d);
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 return HAL_OK;
bogdanm 0:9b334a45a8ff 511 }
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /**
bogdanm 0:9b334a45a8ff 514 * @brief Abort the DMA2D Transfer.
bogdanm 0:9b334a45a8ff 515 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 516 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 517 * @retval HAL status
bogdanm 0:9b334a45a8ff 518 */
bogdanm 0:9b334a45a8ff 519 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 520 {
bogdanm 0:9b334a45a8ff 521 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Disable the DMA2D */
bogdanm 0:9b334a45a8ff 524 __HAL_DMA2D_DISABLE(hdma2d);
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* Get tick */
bogdanm 0:9b334a45a8ff 527 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /* Check if the DMA2D is effectively disabled */
bogdanm 0:9b334a45a8ff 530 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
bogdanm 0:9b334a45a8ff 531 {
bogdanm 0:9b334a45a8ff 532 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)
bogdanm 0:9b334a45a8ff 533 {
bogdanm 0:9b334a45a8ff 534 /* Update error code */
bogdanm 0:9b334a45a8ff 535 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /* Change the DMA2D state */
bogdanm 0:9b334a45a8ff 538 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 541 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 544 }
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 547 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /* Change the DMA2D state*/
bogdanm 0:9b334a45a8ff 550 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 return HAL_OK;
bogdanm 0:9b334a45a8ff 553 }
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 /**
bogdanm 0:9b334a45a8ff 556 * @brief Suspend the DMA2D Transfer.
bogdanm 0:9b334a45a8ff 557 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 558 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 559 * @retval HAL status
bogdanm 0:9b334a45a8ff 560 */
bogdanm 0:9b334a45a8ff 561 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 562 {
bogdanm 0:9b334a45a8ff 563 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* Suspend the DMA2D transfer */
bogdanm 0:9b334a45a8ff 566 hdma2d->Instance->CR |= DMA2D_CR_SUSP;
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /* Get tick */
bogdanm 0:9b334a45a8ff 569 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /* Check if the DMA2D is effectively suspended */
bogdanm 0:9b334a45a8ff 572 while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP)
bogdanm 0:9b334a45a8ff 573 {
bogdanm 0:9b334a45a8ff 574 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 /* Update error code */
bogdanm 0:9b334a45a8ff 577 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Change the DMA2D state */
bogdanm 0:9b334a45a8ff 580 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584 }
bogdanm 0:9b334a45a8ff 585 /* Change the DMA2D state*/
bogdanm 0:9b334a45a8ff 586 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 return HAL_OK;
bogdanm 0:9b334a45a8ff 589 }
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /**
bogdanm 0:9b334a45a8ff 592 * @brief Resume the DMA2D Transfer.
bogdanm 0:9b334a45a8ff 593 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 594 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 595 * @retval HAL status
bogdanm 0:9b334a45a8ff 596 */
bogdanm 0:9b334a45a8ff 597 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 /* Resume the DMA2D transfer */
bogdanm 0:9b334a45a8ff 600 hdma2d->Instance->CR &= ~DMA2D_CR_SUSP;
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* Change the DMA2D state*/
bogdanm 0:9b334a45a8ff 603 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 return HAL_OK;
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @brief Polling for transfer complete or CLUT loading.
bogdanm 0:9b334a45a8ff 610 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 611 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 612 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 613 * @retval HAL status
bogdanm 0:9b334a45a8ff 614 */
bogdanm 0:9b334a45a8ff 615 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 616 {
bogdanm 0:9b334a45a8ff 617 uint32_t tmp, tmp1;
bogdanm 0:9b334a45a8ff 618 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /* Polling for DMA2D transfer */
bogdanm 0:9b334a45a8ff 621 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
bogdanm 0:9b334a45a8ff 622 {
bogdanm 0:9b334a45a8ff 623 /* Get tick */
bogdanm 0:9b334a45a8ff 624 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
bogdanm 0:9b334a45a8ff 627 {
bogdanm 0:9b334a45a8ff 628 tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE);
bogdanm 0:9b334a45a8ff 629 tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE);
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 if((tmp != RESET) || (tmp1 != RESET))
bogdanm 0:9b334a45a8ff 632 {
bogdanm 0:9b334a45a8ff 633 /* Clear the transfer and configuration error flags */
bogdanm 0:9b334a45a8ff 634 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
bogdanm 0:9b334a45a8ff 635 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 638 hdma2d->State= HAL_DMA2D_STATE_ERROR;
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /* Process unlocked */
bogdanm 0:9b334a45a8ff 641 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 644 }
bogdanm 0:9b334a45a8ff 645 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 646 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 /* Process unlocked */
bogdanm 0:9b334a45a8ff 651 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /* Update error code */
bogdanm 0:9b334a45a8ff 654 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /* Change the DMA2D state */
bogdanm 0:9b334a45a8ff 657 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 660 }
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662 }
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664 /* Polling for CLUT loading */
bogdanm 0:9b334a45a8ff 665 if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0)
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 /* Get tick */
bogdanm 0:9b334a45a8ff 668 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 /* Clear the transfer and configuration error flags */
bogdanm 0:9b334a45a8ff 675 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 678 hdma2d->State= HAL_DMA2D_STATE_ERROR;
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 683 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 /* Update error code */
bogdanm 0:9b334a45a8ff 688 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* Change the DMA2D state */
bogdanm 0:9b334a45a8ff 691 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697 }
bogdanm 0:9b334a45a8ff 698 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 699 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Clear the CLUT loading flag */
bogdanm 0:9b334a45a8ff 702 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 705 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 /* Process unlocked */
bogdanm 0:9b334a45a8ff 708 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 return HAL_OK;
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712 /**
bogdanm 0:9b334a45a8ff 713 * @brief Handles DMA2D interrupt request.
bogdanm 0:9b334a45a8ff 714 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 715 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 716 * @retval HAL status
bogdanm 0:9b334a45a8ff 717 */
bogdanm 0:9b334a45a8ff 718 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 719 {
bogdanm 0:9b334a45a8ff 720 /* Transfer Error Interrupt management ***************************************/
bogdanm 0:9b334a45a8ff 721 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
bogdanm 0:9b334a45a8ff 722 {
bogdanm 0:9b334a45a8ff 723 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 724 {
bogdanm 0:9b334a45a8ff 725 /* Disable the transfer Error interrupt */
bogdanm 0:9b334a45a8ff 726 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /* Update error code */
bogdanm 0:9b334a45a8ff 729 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /* Clear the transfer error flag */
bogdanm 0:9b334a45a8ff 732 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 735 hdma2d->State = HAL_DMA2D_STATE_ERROR;
bogdanm 0:9b334a45a8ff 736
bogdanm 0:9b334a45a8ff 737 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 738 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 if(hdma2d->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 /* Transfer error Callback */
bogdanm 0:9b334a45a8ff 743 hdma2d->XferErrorCallback(hdma2d);
bogdanm 0:9b334a45a8ff 744 }
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746 }
bogdanm 0:9b334a45a8ff 747 /* Configuration Error Interrupt management **********************************/
bogdanm 0:9b334a45a8ff 748 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
bogdanm 0:9b334a45a8ff 749 {
bogdanm 0:9b334a45a8ff 750 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
bogdanm 0:9b334a45a8ff 751 {
bogdanm 0:9b334a45a8ff 752 /* Disable the Configuration Error interrupt */
bogdanm 0:9b334a45a8ff 753 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /* Clear the Configuration error flag */
bogdanm 0:9b334a45a8ff 756 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 /* Update error code */
bogdanm 0:9b334a45a8ff 759 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 762 hdma2d->State = HAL_DMA2D_STATE_ERROR;
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 765 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 if(hdma2d->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 /* Transfer error Callback */
bogdanm 0:9b334a45a8ff 770 hdma2d->XferErrorCallback(hdma2d);
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772 }
bogdanm 0:9b334a45a8ff 773 }
bogdanm 0:9b334a45a8ff 774 /* Transfer Complete Interrupt management ************************************/
bogdanm 0:9b334a45a8ff 775 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 778 {
bogdanm 0:9b334a45a8ff 779 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 780 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /* Clear the transfer complete flag */
bogdanm 0:9b334a45a8ff 783 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 /* Update error code */
bogdanm 0:9b334a45a8ff 786 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /* Change DMA2D state */
bogdanm 0:9b334a45a8ff 789 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 792 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794 if(hdma2d->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 /* Transfer complete Callback */
bogdanm 0:9b334a45a8ff 797 hdma2d->XferCpltCallback(hdma2d);
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799 }
bogdanm 0:9b334a45a8ff 800 }
bogdanm 0:9b334a45a8ff 801 }
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803 /**
bogdanm 0:9b334a45a8ff 804 * @}
bogdanm 0:9b334a45a8ff 805 */
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /** @defgroup DMA2D_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 808 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 809 *
bogdanm 0:9b334a45a8ff 810 @verbatim
bogdanm 0:9b334a45a8ff 811 ===============================================================================
bogdanm 0:9b334a45a8ff 812 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 813 ===============================================================================
bogdanm 0:9b334a45a8ff 814 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 815 (+) Configure the DMA2D foreground or/and background parameters.
bogdanm 0:9b334a45a8ff 816 (+) Configure the DMA2D CLUT transfer.
bogdanm 0:9b334a45a8ff 817 (+) Enable DMA2D CLUT.
bogdanm 0:9b334a45a8ff 818 (+) Disable DMA2D CLUT.
bogdanm 0:9b334a45a8ff 819 (+) Configure the line watermark
bogdanm 0:9b334a45a8ff 820
bogdanm 0:9b334a45a8ff 821 @endverbatim
bogdanm 0:9b334a45a8ff 822 * @{
bogdanm 0:9b334a45a8ff 823 */
bogdanm 0:9b334a45a8ff 824 /**
bogdanm 0:9b334a45a8ff 825 * @brief Configure the DMA2D Layer according to the specified
bogdanm 0:9b334a45a8ff 826 * parameters in the DMA2D_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 827 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 828 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 829 * @param LayerIdx: DMA2D Layer index.
bogdanm 0:9b334a45a8ff 830 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 831 * 0(background) / 1(foreground)
bogdanm 0:9b334a45a8ff 832 * @retval HAL status
bogdanm 0:9b334a45a8ff 833 */
bogdanm 0:9b334a45a8ff 834 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 /* Process locked */
bogdanm 0:9b334a45a8ff 841 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 844 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846 /* Check the parameters */
bogdanm 0:9b334a45a8ff 847 assert_param(IS_DMA2D_LAYER(LayerIdx));
bogdanm 0:9b334a45a8ff 848 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
bogdanm 0:9b334a45a8ff 849 if(hdma2d->Init.Mode != DMA2D_R2M)
bogdanm 0:9b334a45a8ff 850 {
bogdanm 0:9b334a45a8ff 851 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
bogdanm 0:9b334a45a8ff 852 if(hdma2d->Init.Mode != DMA2D_M2M)
bogdanm 0:9b334a45a8ff 853 {
bogdanm 0:9b334a45a8ff 854 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
bogdanm 0:9b334a45a8ff 855 }
bogdanm 0:9b334a45a8ff 856 }
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /* Configure the background DMA2D layer */
bogdanm 0:9b334a45a8ff 859 if(LayerIdx == 0)
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 /* DMA2D BGPFCR register configuration -----------------------------------*/
bogdanm 0:9b334a45a8ff 862 /* Get the BGPFCCR register value */
bogdanm 0:9b334a45a8ff 863 tmp = hdma2d->Instance->BGPFCCR;
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /* Clear Input color mode, alpha value and alpha mode bits */
bogdanm 0:9b334a45a8ff 866 tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA);
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
bogdanm 0:9b334a45a8ff 869 {
bogdanm 0:9b334a45a8ff 870 /* Prepare the value to be wrote to the BGPFCCR register */
bogdanm 0:9b334a45a8ff 871 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
bogdanm 0:9b334a45a8ff 872 }
bogdanm 0:9b334a45a8ff 873 else
bogdanm 0:9b334a45a8ff 874 {
bogdanm 0:9b334a45a8ff 875 /* Prepare the value to be wrote to the BGPFCCR register */
bogdanm 0:9b334a45a8ff 876 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
bogdanm 0:9b334a45a8ff 877 }
bogdanm 0:9b334a45a8ff 878
bogdanm 0:9b334a45a8ff 879 /* Write to DMA2D BGPFCCR register */
bogdanm 0:9b334a45a8ff 880 hdma2d->Instance->BGPFCCR = tmp;
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 /* DMA2D BGOR register configuration -------------------------------------*/
bogdanm 0:9b334a45a8ff 883 /* Get the BGOR register value */
bogdanm 0:9b334a45a8ff 884 tmp = hdma2d->Instance->BGOR;
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 /* Clear colors bits */
bogdanm 0:9b334a45a8ff 887 tmp &= (uint32_t)~DMA2D_BGOR_LO;
bogdanm 0:9b334a45a8ff 888
bogdanm 0:9b334a45a8ff 889 /* Prepare the value to be wrote to the BGOR register */
bogdanm 0:9b334a45a8ff 890 tmp |= pLayerCfg->InputOffset;
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Write to DMA2D BGOR register */
bogdanm 0:9b334a45a8ff 893 hdma2d->Instance->BGOR = tmp;
bogdanm 0:9b334a45a8ff 894
bogdanm 0:9b334a45a8ff 895 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
bogdanm 0:9b334a45a8ff 896 {
bogdanm 0:9b334a45a8ff 897 /* Prepare the value to be wrote to the BGCOLR register */
bogdanm 0:9b334a45a8ff 898 tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 /* Write to DMA2D BGCOLR register */
bogdanm 0:9b334a45a8ff 901 hdma2d->Instance->BGCOLR = tmp;
bogdanm 0:9b334a45a8ff 902 }
bogdanm 0:9b334a45a8ff 903 }
bogdanm 0:9b334a45a8ff 904 /* Configure the foreground DMA2D layer */
bogdanm 0:9b334a45a8ff 905 else
bogdanm 0:9b334a45a8ff 906 {
bogdanm 0:9b334a45a8ff 907 /* DMA2D FGPFCR register configuration -----------------------------------*/
bogdanm 0:9b334a45a8ff 908 /* Get the FGPFCCR register value */
bogdanm 0:9b334a45a8ff 909 tmp = hdma2d->Instance->FGPFCCR;
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 /* Clear Input color mode, alpha value and alpha mode bits */
bogdanm 0:9b334a45a8ff 912 tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA);
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
bogdanm 0:9b334a45a8ff 915 {
bogdanm 0:9b334a45a8ff 916 /* Prepare the value to be wrote to the FGPFCCR register */
bogdanm 0:9b334a45a8ff 917 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
bogdanm 0:9b334a45a8ff 918 }
bogdanm 0:9b334a45a8ff 919 else
bogdanm 0:9b334a45a8ff 920 {
bogdanm 0:9b334a45a8ff 921 /* Prepare the value to be wrote to the FGPFCCR register */
bogdanm 0:9b334a45a8ff 922 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
bogdanm 0:9b334a45a8ff 923 }
bogdanm 0:9b334a45a8ff 924
bogdanm 0:9b334a45a8ff 925 /* Write to DMA2D FGPFCCR register */
bogdanm 0:9b334a45a8ff 926 hdma2d->Instance->FGPFCCR = tmp;
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* DMA2D FGOR register configuration -------------------------------------*/
bogdanm 0:9b334a45a8ff 929 /* Get the FGOR register value */
bogdanm 0:9b334a45a8ff 930 tmp = hdma2d->Instance->FGOR;
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /* Clear colors bits */
bogdanm 0:9b334a45a8ff 933 tmp &= (uint32_t)~DMA2D_FGOR_LO;
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /* Prepare the value to be wrote to the FGOR register */
bogdanm 0:9b334a45a8ff 936 tmp |= pLayerCfg->InputOffset;
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /* Write to DMA2D FGOR register */
bogdanm 0:9b334a45a8ff 939 hdma2d->Instance->FGOR = tmp;
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
bogdanm 0:9b334a45a8ff 942 {
bogdanm 0:9b334a45a8ff 943 /* Prepare the value to be wrote to the FGCOLR register */
bogdanm 0:9b334a45a8ff 944 tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
bogdanm 0:9b334a45a8ff 945
bogdanm 0:9b334a45a8ff 946 /* Write to DMA2D FGCOLR register */
bogdanm 0:9b334a45a8ff 947 hdma2d->Instance->FGCOLR = tmp;
bogdanm 0:9b334a45a8ff 948 }
bogdanm 0:9b334a45a8ff 949 }
bogdanm 0:9b334a45a8ff 950 /* Initialize the DMA2D state*/
bogdanm 0:9b334a45a8ff 951 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 952
bogdanm 0:9b334a45a8ff 953 /* Process unlocked */
bogdanm 0:9b334a45a8ff 954 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 return HAL_OK;
bogdanm 0:9b334a45a8ff 957 }
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 /**
bogdanm 0:9b334a45a8ff 960 * @brief Configure the DMA2D CLUT Transfer.
bogdanm 0:9b334a45a8ff 961 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 962 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 963 * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains
bogdanm 0:9b334a45a8ff 964 * the configuration information for the color look up table.
bogdanm 0:9b334a45a8ff 965 * @param LayerIdx: DMA2D Layer index.
bogdanm 0:9b334a45a8ff 966 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 967 * 0(background) / 1(foreground)
bogdanm 0:9b334a45a8ff 968 * @retval HAL status
bogdanm 0:9b334a45a8ff 969 */
bogdanm 0:9b334a45a8ff 970 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 uint32_t tmp = 0, tmp1 = 0;
bogdanm 0:9b334a45a8ff 973
bogdanm 0:9b334a45a8ff 974 /* Check the parameters */
bogdanm 0:9b334a45a8ff 975 assert_param(IS_DMA2D_LAYER(LayerIdx));
bogdanm 0:9b334a45a8ff 976 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
bogdanm 0:9b334a45a8ff 977 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
bogdanm 0:9b334a45a8ff 978
bogdanm 0:9b334a45a8ff 979 /* Configure the CLUT of the background DMA2D layer */
bogdanm 0:9b334a45a8ff 980 if(LayerIdx == 0)
bogdanm 0:9b334a45a8ff 981 {
bogdanm 0:9b334a45a8ff 982 /* Get the BGCMAR register value */
bogdanm 0:9b334a45a8ff 983 tmp = hdma2d->Instance->BGCMAR;
bogdanm 0:9b334a45a8ff 984
bogdanm 0:9b334a45a8ff 985 /* Clear CLUT address bits */
bogdanm 0:9b334a45a8ff 986 tmp &= (uint32_t)~DMA2D_BGCMAR_MA;
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /* Prepare the value to be wrote to the BGCMAR register */
bogdanm 0:9b334a45a8ff 989 tmp |= (uint32_t)CLUTCfg.pCLUT;
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /* Write to DMA2D BGCMAR register */
bogdanm 0:9b334a45a8ff 992 hdma2d->Instance->BGCMAR = tmp;
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /* Get the BGPFCCR register value */
bogdanm 0:9b334a45a8ff 995 tmp = hdma2d->Instance->BGPFCCR;
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997 /* Clear CLUT size and CLUT address bits */
bogdanm 0:9b334a45a8ff 998 tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM);
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /* Get the CLUT size */
bogdanm 0:9b334a45a8ff 1001 tmp1 = CLUTCfg.Size << 16;
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Prepare the value to be wrote to the BGPFCCR register */
bogdanm 0:9b334a45a8ff 1004 tmp |= (CLUTCfg.CLUTColorMode | tmp1);
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /* Write to DMA2D BGPFCCR register */
bogdanm 0:9b334a45a8ff 1007 hdma2d->Instance->BGPFCCR = tmp;
bogdanm 0:9b334a45a8ff 1008 }
bogdanm 0:9b334a45a8ff 1009 /* Configure the CLUT of the foreground DMA2D layer */
bogdanm 0:9b334a45a8ff 1010 else
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 /* Get the FGCMAR register value */
bogdanm 0:9b334a45a8ff 1013 tmp = hdma2d->Instance->FGCMAR;
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /* Clear CLUT address bits */
bogdanm 0:9b334a45a8ff 1016 tmp &= (uint32_t)~DMA2D_FGCMAR_MA;
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /* Prepare the value to be wrote to the FGCMAR register */
bogdanm 0:9b334a45a8ff 1019 tmp |= (uint32_t)CLUTCfg.pCLUT;
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /* Write to DMA2D FGCMAR register */
bogdanm 0:9b334a45a8ff 1022 hdma2d->Instance->FGCMAR = tmp;
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* Get the FGPFCCR register value */
bogdanm 0:9b334a45a8ff 1025 tmp = hdma2d->Instance->FGPFCCR;
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 /* Clear CLUT size and CLUT address bits */
bogdanm 0:9b334a45a8ff 1028 tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM);
bogdanm 0:9b334a45a8ff 1029
bogdanm 0:9b334a45a8ff 1030 /* Get the CLUT size */
bogdanm 0:9b334a45a8ff 1031 tmp1 = CLUTCfg.Size << 8;
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 /* Prepare the value to be wrote to the FGPFCCR register */
bogdanm 0:9b334a45a8ff 1034 tmp |= (CLUTCfg.CLUTColorMode | tmp1);
bogdanm 0:9b334a45a8ff 1035
bogdanm 0:9b334a45a8ff 1036 /* Write to DMA2D FGPFCCR register */
bogdanm 0:9b334a45a8ff 1037 hdma2d->Instance->FGPFCCR = tmp;
bogdanm 0:9b334a45a8ff 1038 }
bogdanm 0:9b334a45a8ff 1039
bogdanm 0:9b334a45a8ff 1040 return HAL_OK;
bogdanm 0:9b334a45a8ff 1041 }
bogdanm 0:9b334a45a8ff 1042
bogdanm 0:9b334a45a8ff 1043 /**
bogdanm 0:9b334a45a8ff 1044 * @brief Enable the DMA2D CLUT Transfer.
bogdanm 0:9b334a45a8ff 1045 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1046 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 1047 * @param LayerIdx: DMA2D Layer index.
bogdanm 0:9b334a45a8ff 1048 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1049 * 0(background) / 1(foreground)
bogdanm 0:9b334a45a8ff 1050 * @retval HAL status
bogdanm 0:9b334a45a8ff 1051 */
bogdanm 0:9b334a45a8ff 1052 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
bogdanm 0:9b334a45a8ff 1053 {
bogdanm 0:9b334a45a8ff 1054 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1055 assert_param(IS_DMA2D_LAYER(LayerIdx));
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 if(LayerIdx == 0)
bogdanm 0:9b334a45a8ff 1058 {
bogdanm 0:9b334a45a8ff 1059 /* Enable the CLUT loading for the background */
bogdanm 0:9b334a45a8ff 1060 hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
bogdanm 0:9b334a45a8ff 1061 }
bogdanm 0:9b334a45a8ff 1062 else
bogdanm 0:9b334a45a8ff 1063 {
bogdanm 0:9b334a45a8ff 1064 /* Enable the CLUT loading for the foreground */
bogdanm 0:9b334a45a8ff 1065 hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
bogdanm 0:9b334a45a8ff 1066 }
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 return HAL_OK;
bogdanm 0:9b334a45a8ff 1069 }
bogdanm 0:9b334a45a8ff 1070
bogdanm 0:9b334a45a8ff 1071 /**
bogdanm 0:9b334a45a8ff 1072 * @brief Disable the DMA2D CLUT Transfer.
bogdanm 0:9b334a45a8ff 1073 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1074 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 1075 * @param LayerIdx: DMA2D Layer index.
bogdanm 0:9b334a45a8ff 1076 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1077 * 0(background) / 1(foreground)
bogdanm 0:9b334a45a8ff 1078 * @retval HAL status
bogdanm 0:9b334a45a8ff 1079 */
bogdanm 0:9b334a45a8ff 1080 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
bogdanm 0:9b334a45a8ff 1081 {
bogdanm 0:9b334a45a8ff 1082 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1083 assert_param(IS_DMA2D_LAYER(LayerIdx));
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 if(LayerIdx == 0)
bogdanm 0:9b334a45a8ff 1086 {
bogdanm 0:9b334a45a8ff 1087 /* Disable the CLUT loading for the background */
bogdanm 0:9b334a45a8ff 1088 hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
bogdanm 0:9b334a45a8ff 1089 }
bogdanm 0:9b334a45a8ff 1090 else
bogdanm 0:9b334a45a8ff 1091 {
bogdanm 0:9b334a45a8ff 1092 /* Disable the CLUT loading for the foreground */
bogdanm 0:9b334a45a8ff 1093 hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
bogdanm 0:9b334a45a8ff 1094 }
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096 return HAL_OK;
bogdanm 0:9b334a45a8ff 1097 }
bogdanm 0:9b334a45a8ff 1098
bogdanm 0:9b334a45a8ff 1099 /**
bogdanm 0:9b334a45a8ff 1100 * @brief Define the configuration of the line watermark .
bogdanm 0:9b334a45a8ff 1101 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1102 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 1103 * @param Line: Line Watermark configuration.
bogdanm 0:9b334a45a8ff 1104 * @retval HAL status
bogdanm 0:9b334a45a8ff 1105 */
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
bogdanm 0:9b334a45a8ff 1108 {
bogdanm 0:9b334a45a8ff 1109 /* Process locked */
bogdanm 0:9b334a45a8ff 1110 __HAL_LOCK(hdma2d);
bogdanm 0:9b334a45a8ff 1111
bogdanm 0:9b334a45a8ff 1112 /* Change DMA2D peripheral state */
bogdanm 0:9b334a45a8ff 1113 hdma2d->State = HAL_DMA2D_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1114
bogdanm 0:9b334a45a8ff 1115 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1116 assert_param(IS_DMA2D_LineWatermark(Line));
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 /* Sets the Line watermark configuration */
bogdanm 0:9b334a45a8ff 1119 DMA2D->LWR = (uint32_t)Line;
bogdanm 0:9b334a45a8ff 1120
bogdanm 0:9b334a45a8ff 1121 /* Initialize the DMA2D state*/
bogdanm 0:9b334a45a8ff 1122 hdma2d->State = HAL_DMA2D_STATE_READY;
bogdanm 0:9b334a45a8ff 1123
bogdanm 0:9b334a45a8ff 1124 /* Process unlocked */
bogdanm 0:9b334a45a8ff 1125 __HAL_UNLOCK(hdma2d);
bogdanm 0:9b334a45a8ff 1126
bogdanm 0:9b334a45a8ff 1127 return HAL_OK;
bogdanm 0:9b334a45a8ff 1128 }
bogdanm 0:9b334a45a8ff 1129
bogdanm 0:9b334a45a8ff 1130 /**
bogdanm 0:9b334a45a8ff 1131 * @}
bogdanm 0:9b334a45a8ff 1132 */
bogdanm 0:9b334a45a8ff 1133
bogdanm 0:9b334a45a8ff 1134 /** @defgroup DMA2D_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1135 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1136 *
bogdanm 0:9b334a45a8ff 1137 @verbatim
bogdanm 0:9b334a45a8ff 1138 ===============================================================================
bogdanm 0:9b334a45a8ff 1139 ##### Peripheral State and Errors functions #####
bogdanm 0:9b334a45a8ff 1140 ===============================================================================
bogdanm 0:9b334a45a8ff 1141 [..]
bogdanm 0:9b334a45a8ff 1142 This subsection provides functions allowing to :
bogdanm 0:9b334a45a8ff 1143 (+) Check the DMA2D state
bogdanm 0:9b334a45a8ff 1144 (+) Get error code
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 @endverbatim
bogdanm 0:9b334a45a8ff 1147 * @{
bogdanm 0:9b334a45a8ff 1148 */
bogdanm 0:9b334a45a8ff 1149
bogdanm 0:9b334a45a8ff 1150 /**
bogdanm 0:9b334a45a8ff 1151 * @brief Return the DMA2D state
bogdanm 0:9b334a45a8ff 1152 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1153 * the configuration information for the DMA2D.
bogdanm 0:9b334a45a8ff 1154 * @retval HAL state
bogdanm 0:9b334a45a8ff 1155 */
bogdanm 0:9b334a45a8ff 1156 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 1157 {
bogdanm 0:9b334a45a8ff 1158 return hdma2d->State;
bogdanm 0:9b334a45a8ff 1159 }
bogdanm 0:9b334a45a8ff 1160
bogdanm 0:9b334a45a8ff 1161 /**
bogdanm 0:9b334a45a8ff 1162 * @brief Return the DMA2D error code
bogdanm 0:9b334a45a8ff 1163 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1164 * the configuration information for DMA2D.
bogdanm 0:9b334a45a8ff 1165 * @retval DMA2D Error Code
bogdanm 0:9b334a45a8ff 1166 */
bogdanm 0:9b334a45a8ff 1167 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
bogdanm 0:9b334a45a8ff 1168 {
bogdanm 0:9b334a45a8ff 1169 return hdma2d->ErrorCode;
bogdanm 0:9b334a45a8ff 1170 }
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 /**
bogdanm 0:9b334a45a8ff 1173 * @}
bogdanm 0:9b334a45a8ff 1174 */
bogdanm 0:9b334a45a8ff 1175
bogdanm 0:9b334a45a8ff 1176
bogdanm 0:9b334a45a8ff 1177 /**
bogdanm 0:9b334a45a8ff 1178 * @brief Set the DMA2D Transfer parameter.
bogdanm 0:9b334a45a8ff 1179 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1180 * the configuration information for the specified DMA2D.
bogdanm 0:9b334a45a8ff 1181 * @param pdata: The source memory Buffer address
bogdanm 0:9b334a45a8ff 1182 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 1183 * @param Width: The width of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 1184 * @param Height: The height of data to be transferred from source to destination.
bogdanm 0:9b334a45a8ff 1185 * @retval HAL status
bogdanm 0:9b334a45a8ff 1186 */
bogdanm 0:9b334a45a8ff 1187 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
bogdanm 0:9b334a45a8ff 1188 {
bogdanm 0:9b334a45a8ff 1189 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 1190 uint32_t tmp1 = 0;
bogdanm 0:9b334a45a8ff 1191 uint32_t tmp2 = 0;
bogdanm 0:9b334a45a8ff 1192 uint32_t tmp3 = 0;
bogdanm 0:9b334a45a8ff 1193 uint32_t tmp4 = 0;
bogdanm 0:9b334a45a8ff 1194
bogdanm 0:9b334a45a8ff 1195 tmp = Width << 16;
bogdanm 0:9b334a45a8ff 1196
bogdanm 0:9b334a45a8ff 1197 /* Configure DMA2D data size */
bogdanm 0:9b334a45a8ff 1198 hdma2d->Instance->NLR = (Height | tmp);
bogdanm 0:9b334a45a8ff 1199
bogdanm 0:9b334a45a8ff 1200 /* Configure DMA2D destination address */
bogdanm 0:9b334a45a8ff 1201 hdma2d->Instance->OMAR = DstAddress;
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 /* Register to memory DMA2D mode selected */
bogdanm 0:9b334a45a8ff 1204 if (hdma2d->Init.Mode == DMA2D_R2M)
bogdanm 0:9b334a45a8ff 1205 {
bogdanm 0:9b334a45a8ff 1206 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
bogdanm 0:9b334a45a8ff 1207 tmp2 = pdata & DMA2D_OCOLR_RED_1;
bogdanm 0:9b334a45a8ff 1208 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
bogdanm 0:9b334a45a8ff 1209 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
bogdanm 0:9b334a45a8ff 1210
bogdanm 0:9b334a45a8ff 1211 /* Prepare the value to be wrote to the OCOLR register according to the color mode */
bogdanm 0:9b334a45a8ff 1212 if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
bogdanm 0:9b334a45a8ff 1213 {
bogdanm 0:9b334a45a8ff 1214 tmp = (tmp3 | tmp2 | tmp1| tmp4);
bogdanm 0:9b334a45a8ff 1215 }
bogdanm 0:9b334a45a8ff 1216 else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
bogdanm 0:9b334a45a8ff 1217 {
bogdanm 0:9b334a45a8ff 1218 tmp = (tmp3 | tmp2 | tmp4);
bogdanm 0:9b334a45a8ff 1219 }
bogdanm 0:9b334a45a8ff 1220 else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
bogdanm 0:9b334a45a8ff 1221 {
bogdanm 0:9b334a45a8ff 1222 tmp2 = (tmp2 >> 19);
bogdanm 0:9b334a45a8ff 1223 tmp3 = (tmp3 >> 10);
bogdanm 0:9b334a45a8ff 1224 tmp4 = (tmp4 >> 3 );
bogdanm 0:9b334a45a8ff 1225 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
bogdanm 0:9b334a45a8ff 1226 }
bogdanm 0:9b334a45a8ff 1227 else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
bogdanm 0:9b334a45a8ff 1228 {
bogdanm 0:9b334a45a8ff 1229 tmp1 = (tmp1 >> 31);
bogdanm 0:9b334a45a8ff 1230 tmp2 = (tmp2 >> 19);
bogdanm 0:9b334a45a8ff 1231 tmp3 = (tmp3 >> 11);
bogdanm 0:9b334a45a8ff 1232 tmp4 = (tmp4 >> 3 );
bogdanm 0:9b334a45a8ff 1233 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
bogdanm 0:9b334a45a8ff 1234 }
bogdanm 0:9b334a45a8ff 1235 else /* DMA2D_CMode = DMA2D_ARGB4444 */
bogdanm 0:9b334a45a8ff 1236 {
bogdanm 0:9b334a45a8ff 1237 tmp1 = (tmp1 >> 28);
bogdanm 0:9b334a45a8ff 1238 tmp2 = (tmp2 >> 20);
bogdanm 0:9b334a45a8ff 1239 tmp3 = (tmp3 >> 12);
bogdanm 0:9b334a45a8ff 1240 tmp4 = (tmp4 >> 4 );
bogdanm 0:9b334a45a8ff 1241 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
bogdanm 0:9b334a45a8ff 1242 }
bogdanm 0:9b334a45a8ff 1243 /* Write to DMA2D OCOLR register */
bogdanm 0:9b334a45a8ff 1244 hdma2d->Instance->OCOLR = tmp;
bogdanm 0:9b334a45a8ff 1245 }
bogdanm 0:9b334a45a8ff 1246 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
bogdanm 0:9b334a45a8ff 1247 {
bogdanm 0:9b334a45a8ff 1248 /* Configure DMA2D source address */
bogdanm 0:9b334a45a8ff 1249 hdma2d->Instance->FGMAR = pdata;
bogdanm 0:9b334a45a8ff 1250 }
bogdanm 0:9b334a45a8ff 1251 }
bogdanm 0:9b334a45a8ff 1252
bogdanm 0:9b334a45a8ff 1253 /**
bogdanm 0:9b334a45a8ff 1254 * @}
bogdanm 0:9b334a45a8ff 1255 */
mbed_official 19:112740acecfa 1256 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 1257 #endif /* HAL_DMA2D_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1258 /**
bogdanm 0:9b334a45a8ff 1259 * @}
bogdanm 0:9b334a45a8ff 1260 */
bogdanm 0:9b334a45a8ff 1261
bogdanm 0:9b334a45a8ff 1262 /**
bogdanm 0:9b334a45a8ff 1263 * @}
bogdanm 0:9b334a45a8ff 1264 */
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/