en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_dma.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief DMA HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Direct Memory Access (DMA) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + IO operation functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and errors functions
bogdanm 0:9b334a45a8ff 14 @verbatim
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
bogdanm 0:9b334a45a8ff 20 (except for internal SRAM/FLASH memories: no initialization is
bogdanm 0:9b334a45a8ff 21 necessary) please refer to Reference manual for connection between peripherals
bogdanm 0:9b334a45a8ff 22 and DMA requests .
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) For a given Stream, program the required configuration through the following parameters:
bogdanm 0:9b334a45a8ff 25 Transfer Direction, Source and Destination data formats,
bogdanm 0:9b334a45a8ff 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
bogdanm 0:9b334a45a8ff 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
bogdanm 0:9b334a45a8ff 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 31 =================================
bogdanm 0:9b334a45a8ff 32 [..]
bogdanm 0:9b334a45a8ff 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
bogdanm 0:9b334a45a8ff 34 address and destination address and the Length of data to be transferred
bogdanm 0:9b334a45a8ff 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
bogdanm 0:9b334a45a8ff 36 case a fixed Timeout can be configured by User depending from his application.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 39 ===================================
bogdanm 0:9b334a45a8ff 40 [..]
bogdanm 0:9b334a45a8ff 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
bogdanm 0:9b334a45a8ff 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm 0:9b334a45a8ff 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
bogdanm 0:9b334a45a8ff 44 Source address and destination address and the Length of data to be transferred. In this
bogdanm 0:9b334a45a8ff 45 case the DMA interrupt is configured
bogdanm 0:9b334a45a8ff 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 48 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 49 XferErrorCallback (i.e a member of DMA handle structure).
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
bogdanm 0:9b334a45a8ff 52 detection.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
bogdanm 0:9b334a45a8ff 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
bogdanm 0:9b334a45a8ff 60 Half-Word data size for the peripheral to access its data register and set Word data size
bogdanm 0:9b334a45a8ff 61 for the Memory to gain in access time. Each two half words will be packed and written in
bogdanm 0:9b334a45a8ff 62 a single access to a Word in the Memory).
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
bogdanm 0:9b334a45a8ff 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
bogdanm 0:9b334a45a8ff 66 and Destination.
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 *** DMA HAL driver macros list ***
bogdanm 0:9b334a45a8ff 69 =============================================
bogdanm 0:9b334a45a8ff 70 [..]
bogdanm 0:9b334a45a8ff 71 Below the list of most used macros in DMA HAL driver.
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
bogdanm 0:9b334a45a8ff 76 (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
bogdanm 0:9b334a45a8ff 77 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
bogdanm 0:9b334a45a8ff 78 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 79 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 80 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 [..]
bogdanm 0:9b334a45a8ff 83 (@) You can refer to the DMA HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 @endverbatim
bogdanm 0:9b334a45a8ff 86 ******************************************************************************
bogdanm 0:9b334a45a8ff 87 * @attention
bogdanm 0:9b334a45a8ff 88 *
bogdanm 0:9b334a45a8ff 89 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 90 *
bogdanm 0:9b334a45a8ff 91 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 92 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 93 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 94 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 95 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 96 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 97 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 98 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 99 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 100 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 101 *
bogdanm 0:9b334a45a8ff 102 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 103 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 104 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 105 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 106 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 107 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 108 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 109 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 110 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 111 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 112 *
bogdanm 0:9b334a45a8ff 113 ******************************************************************************
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 117 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 120 * @{
bogdanm 0:9b334a45a8ff 121 */
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /** @defgroup DMA DMA
bogdanm 0:9b334a45a8ff 124 * @brief DMA HAL module driver
bogdanm 0:9b334a45a8ff 125 * @{
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Private types -------------------------------------------------------------*/
mbed_official 19:112740acecfa 131
mbed_official 19:112740acecfa 132 typedef struct
mbed_official 19:112740acecfa 133 {
mbed_official 19:112740acecfa 134 __IO uint32_t ISR; /*!< DMA interrupt status register */
mbed_official 19:112740acecfa 135 __IO uint32_t Reserved0;
mbed_official 19:112740acecfa 136 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
mbed_official 19:112740acecfa 137 } DMA_Base_Registers;
mbed_official 19:112740acecfa 138
bogdanm 0:9b334a45a8ff 139 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 140 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 141 /** @addtogroup DMA_Private_Constants
bogdanm 0:9b334a45a8ff 142 * @{
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 145 /**
bogdanm 0:9b334a45a8ff 146 * @}
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 149 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 150 /** @addtogroup DMA_Private_Functions
bogdanm 0:9b334a45a8ff 151 * @{
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 19:112740acecfa 154 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
mbed_official 19:112740acecfa 155
bogdanm 0:9b334a45a8ff 156 /**
bogdanm 0:9b334a45a8ff 157 * @}
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 161 /** @addtogroup DMA_Exported_Functions
bogdanm 0:9b334a45a8ff 162 * @{
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /** @addtogroup DMA_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 166 *
bogdanm 0:9b334a45a8ff 167 @verbatim
bogdanm 0:9b334a45a8ff 168 ===============================================================================
bogdanm 0:9b334a45a8ff 169 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 170 ===============================================================================
bogdanm 0:9b334a45a8ff 171 [..]
bogdanm 0:9b334a45a8ff 172 This section provides functions allowing to initialize the DMA Stream source
bogdanm 0:9b334a45a8ff 173 and destination addresses, incrementation and data sizes, transfer direction,
bogdanm 0:9b334a45a8ff 174 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
bogdanm 0:9b334a45a8ff 175 [..]
bogdanm 0:9b334a45a8ff 176 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
bogdanm 0:9b334a45a8ff 177 reference manual.
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 @endverbatim
bogdanm 0:9b334a45a8ff 180 * @{
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @brief Initializes the DMA according to the specified
bogdanm 0:9b334a45a8ff 185 * parameters in the DMA_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 186 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 187 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 188 * @retval HAL status
bogdanm 0:9b334a45a8ff 189 */
bogdanm 0:9b334a45a8ff 190 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
mbed_official 19:112740acecfa 191 {
bogdanm 0:9b334a45a8ff 192 uint32_t tmp = 0;
mbed_official 19:112740acecfa 193
bogdanm 0:9b334a45a8ff 194 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 195 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 196 {
bogdanm 0:9b334a45a8ff 197 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 198 }
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Check the parameters */
bogdanm 0:9b334a45a8ff 201 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 202 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
bogdanm 0:9b334a45a8ff 203 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
bogdanm 0:9b334a45a8ff 204 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
bogdanm 0:9b334a45a8ff 205 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
bogdanm 0:9b334a45a8ff 206 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
bogdanm 0:9b334a45a8ff 207 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
bogdanm 0:9b334a45a8ff 208 assert_param(IS_DMA_MODE(hdma->Init.Mode));
bogdanm 0:9b334a45a8ff 209 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
bogdanm 0:9b334a45a8ff 210 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
bogdanm 0:9b334a45a8ff 211 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
bogdanm 0:9b334a45a8ff 212 when FIFO mode is enabled */
bogdanm 0:9b334a45a8ff 213 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
bogdanm 0:9b334a45a8ff 216 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
bogdanm 0:9b334a45a8ff 217 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 221 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 224 tmp = hdma->Instance->CR;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
bogdanm 0:9b334a45a8ff 227 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
bogdanm 0:9b334a45a8ff 228 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
bogdanm 0:9b334a45a8ff 229 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
bogdanm 0:9b334a45a8ff 230 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Prepare the DMA Stream configuration */
bogdanm 0:9b334a45a8ff 233 tmp |= hdma->Init.Channel | hdma->Init.Direction |
bogdanm 0:9b334a45a8ff 234 hdma->Init.PeriphInc | hdma->Init.MemInc |
bogdanm 0:9b334a45a8ff 235 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
bogdanm 0:9b334a45a8ff 236 hdma->Init.Mode | hdma->Init.Priority;
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
bogdanm 0:9b334a45a8ff 239 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
bogdanm 0:9b334a45a8ff 240 {
bogdanm 0:9b334a45a8ff 241 /* Get memory burst and peripheral burst */
bogdanm 0:9b334a45a8ff 242 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Write to DMA Stream CR register */
bogdanm 0:9b334a45a8ff 246 hdma->Instance->CR = tmp;
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Get the FCR register value */
bogdanm 0:9b334a45a8ff 249 tmp = hdma->Instance->FCR;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Clear Direct mode and FIFO threshold bits */
bogdanm 0:9b334a45a8ff 252 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /* Prepare the DMA Stream FIFO configuration */
bogdanm 0:9b334a45a8ff 255 tmp |= hdma->Init.FIFOMode;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* the FIFO threshold is not used when the FIFO mode is disabled */
bogdanm 0:9b334a45a8ff 258 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
bogdanm 0:9b334a45a8ff 259 {
bogdanm 0:9b334a45a8ff 260 /* Get the FIFO threshold */
bogdanm 0:9b334a45a8ff 261 tmp |= hdma->Init.FIFOThreshold;
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /* Write to DMA Stream FCR */
bogdanm 0:9b334a45a8ff 265 hdma->Instance->FCR = tmp;
bogdanm 0:9b334a45a8ff 266
mbed_official 19:112740acecfa 267 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
mbed_official 19:112740acecfa 268 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
mbed_official 19:112740acecfa 269 DMA_CalcBaseAndBitshift(hdma);
mbed_official 19:112740acecfa 270
bogdanm 0:9b334a45a8ff 271 /* Initialize the error code */
bogdanm 0:9b334a45a8ff 272 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 275 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 return HAL_OK;
bogdanm 0:9b334a45a8ff 278 }
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @brief DeInitializes the DMA peripheral
bogdanm 0:9b334a45a8ff 282 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 283 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 284 * @retval HAL status
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 287 {
mbed_official 19:112740acecfa 288 DMA_Base_Registers *regs;
mbed_official 19:112740acecfa 289
bogdanm 0:9b334a45a8ff 290 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 291 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 297 if(hdma->State == HAL_DMA_STATE_BUSY)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Disable the selected DMA Streamx */
bogdanm 0:9b334a45a8ff 303 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /* Reset DMA Streamx control register */
bogdanm 0:9b334a45a8ff 306 hdma->Instance->CR = 0;
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Reset DMA Streamx number of data to transfer register */
bogdanm 0:9b334a45a8ff 309 hdma->Instance->NDTR = 0;
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Reset DMA Streamx peripheral address register */
bogdanm 0:9b334a45a8ff 312 hdma->Instance->PAR = 0;
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /* Reset DMA Streamx memory 0 address register */
bogdanm 0:9b334a45a8ff 315 hdma->Instance->M0AR = 0;
mbed_official 19:112740acecfa 316
bogdanm 0:9b334a45a8ff 317 /* Reset DMA Streamx memory 1 address register */
bogdanm 0:9b334a45a8ff 318 hdma->Instance->M1AR = 0;
mbed_official 19:112740acecfa 319
bogdanm 0:9b334a45a8ff 320 /* Reset DMA Streamx FIFO control register */
bogdanm 0:9b334a45a8ff 321 hdma->Instance->FCR = (uint32_t)0x00000021;
mbed_official 19:112740acecfa 322
mbed_official 19:112740acecfa 323 /* Get DMA steam Base Address */
mbed_official 19:112740acecfa 324 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
mbed_official 19:112740acecfa 325
mbed_official 19:112740acecfa 326 /* Clear all interrupt flags at correct offset within the register */
mbed_official 19:112740acecfa 327 regs->IFCR = 0x3F << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Initialize the error code */
bogdanm 0:9b334a45a8ff 330 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 333 hdma->State = HAL_DMA_STATE_RESET;
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Release Lock */
bogdanm 0:9b334a45a8ff 336 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 return HAL_OK;
bogdanm 0:9b334a45a8ff 339 }
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /**
bogdanm 0:9b334a45a8ff 342 * @}
bogdanm 0:9b334a45a8ff 343 */
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /** @addtogroup DMA_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 346 *
bogdanm 0:9b334a45a8ff 347 @verbatim
bogdanm 0:9b334a45a8ff 348 ===============================================================================
bogdanm 0:9b334a45a8ff 349 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 350 ===============================================================================
bogdanm 0:9b334a45a8ff 351 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 352 (+) Configure the source, destination address and data length and Start DMA transfer
bogdanm 0:9b334a45a8ff 353 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 354 Start DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 355 (+) Abort DMA transfer
bogdanm 0:9b334a45a8ff 356 (+) Poll for transfer complete
bogdanm 0:9b334a45a8ff 357 (+) Handle DMA interrupt request
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 @endverbatim
bogdanm 0:9b334a45a8ff 360 * @{
bogdanm 0:9b334a45a8ff 361 */
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /**
bogdanm 0:9b334a45a8ff 364 * @brief Starts the DMA Transfer.
bogdanm 0:9b334a45a8ff 365 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 366 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 367 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 368 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 369 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 370 * @retval HAL status
bogdanm 0:9b334a45a8ff 371 */
bogdanm 0:9b334a45a8ff 372 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 /* Process locked */
bogdanm 0:9b334a45a8ff 375 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 378 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 /* Check the parameters */
bogdanm 0:9b334a45a8ff 381 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 384 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 387 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 390 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 return HAL_OK;
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /**
bogdanm 0:9b334a45a8ff 396 * @brief Start the DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 397 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 398 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 399 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 400 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 401 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 402 * @retval HAL status
bogdanm 0:9b334a45a8ff 403 */
bogdanm 0:9b334a45a8ff 404 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 405 {
bogdanm 0:9b334a45a8ff 406 /* Process locked */
bogdanm 0:9b334a45a8ff 407 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 410 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 /* Check the parameters */
bogdanm 0:9b334a45a8ff 413 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 416 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 419 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 420
mbed_official 19:112740acecfa 421 /* Enable all interrupts */
mbed_official 19:112740acecfa 422 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
mbed_official 19:112740acecfa 423 hdma->Instance->FCR |= DMA_IT_FE;
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 426 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 return HAL_OK;
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /**
bogdanm 0:9b334a45a8ff 432 * @brief Aborts the DMA Transfer.
bogdanm 0:9b334a45a8ff 433 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 434 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 435 *
bogdanm 0:9b334a45a8ff 436 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
bogdanm 0:9b334a45a8ff 437 * effectively disabled is added. If a Stream is disabled
bogdanm 0:9b334a45a8ff 438 * while a data transfer is ongoing, the current data will be transferred
bogdanm 0:9b334a45a8ff 439 * and the Stream will be effectively disabled only after the transfer of
bogdanm 0:9b334a45a8ff 440 * this single data is finished.
bogdanm 0:9b334a45a8ff 441 * @retval HAL status
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 444 {
bogdanm 0:9b334a45a8ff 445 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Disable the stream */
bogdanm 0:9b334a45a8ff 448 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Get tick */
bogdanm 0:9b334a45a8ff 451 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Check if the DMA Stream is effectively disabled */
bogdanm 0:9b334a45a8ff 454 while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
bogdanm 0:9b334a45a8ff 455 {
bogdanm 0:9b334a45a8ff 456 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 457 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 /* Update error code */
bogdanm 0:9b334a45a8ff 460 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 463 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 466 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 469 }
bogdanm 0:9b334a45a8ff 470 }
bogdanm 0:9b334a45a8ff 471 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 472 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Change the DMA state*/
bogdanm 0:9b334a45a8ff 475 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 return HAL_OK;
bogdanm 0:9b334a45a8ff 478 }
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /**
bogdanm 0:9b334a45a8ff 481 * @brief Polling for transfer complete.
bogdanm 0:9b334a45a8ff 482 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 483 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 484 * @param CompleteLevel: Specifies the DMA level complete.
bogdanm 0:9b334a45a8ff 485 * @param Timeout: Timeout duration.
bogdanm 0:9b334a45a8ff 486 * @retval HAL status
bogdanm 0:9b334a45a8ff 487 */
bogdanm 0:9b334a45a8ff 488 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 uint32_t temp, tmp, tmp1, tmp2;
mbed_official 19:112740acecfa 491 uint32_t tickstart = 0;
mbed_official 19:112740acecfa 492
mbed_official 19:112740acecfa 493 /* calculate DMA base and stream number */
mbed_official 19:112740acecfa 494 DMA_Base_Registers *regs;
mbed_official 19:112740acecfa 495
mbed_official 19:112740acecfa 496 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Get the level transfer complete flag */
bogdanm 0:9b334a45a8ff 499 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 /* Transfer Complete flag */
mbed_official 19:112740acecfa 502 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 else
bogdanm 0:9b334a45a8ff 505 {
bogdanm 0:9b334a45a8ff 506 /* Half Transfer Complete flag */
mbed_official 19:112740acecfa 507 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Get tick */
bogdanm 0:9b334a45a8ff 511 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 512
mbed_official 19:112740acecfa 513 while((regs->ISR & temp) == RESET)
bogdanm 0:9b334a45a8ff 514 {
mbed_official 19:112740acecfa 515 tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
mbed_official 19:112740acecfa 516 tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
mbed_official 19:112740acecfa 517 tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
bogdanm 0:9b334a45a8ff 518 if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 if(tmp != RESET)
bogdanm 0:9b334a45a8ff 521 {
bogdanm 0:9b334a45a8ff 522 /* Update error code */
bogdanm 0:9b334a45a8ff 523 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Clear the transfer error flag */
mbed_official 19:112740acecfa 526 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 527 }
bogdanm 0:9b334a45a8ff 528 if(tmp1 != RESET)
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 /* Update error code */
bogdanm 0:9b334a45a8ff 531 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
mbed_official 19:112740acecfa 532
bogdanm 0:9b334a45a8ff 533 /* Clear the FIFO error flag */
mbed_official 19:112740acecfa 534 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 535 }
bogdanm 0:9b334a45a8ff 536 if(tmp2 != RESET)
bogdanm 0:9b334a45a8ff 537 {
bogdanm 0:9b334a45a8ff 538 /* Update error code */
bogdanm 0:9b334a45a8ff 539 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /* Clear the Direct Mode error flag */
mbed_official 19:112740acecfa 542 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 543 }
bogdanm 0:9b334a45a8ff 544 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 545 hdma->State= HAL_DMA_STATE_ERROR;
mbed_official 19:112740acecfa 546
bogdanm 0:9b334a45a8ff 547 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 548 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 return HAL_ERROR;
mbed_official 19:112740acecfa 551 }
bogdanm 0:9b334a45a8ff 552 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 553 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 /* Update error code */
bogdanm 0:9b334a45a8ff 558 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 561 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 564 __HAL_UNLOCK(hdma);
mbed_official 19:112740acecfa 565
bogdanm 0:9b334a45a8ff 566 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 572 {
mbed_official 19:112740acecfa 573 /* Clear the half transfer and transfer complete flags */
mbed_official 19:112740acecfa 574 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
mbed_official 19:112740acecfa 575
bogdanm 0:9b334a45a8ff 576 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 577 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 578 {
bogdanm 0:9b334a45a8ff 579 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 580 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 583 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 584 }
bogdanm 0:9b334a45a8ff 585 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 586 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 587 {
bogdanm 0:9b334a45a8ff 588 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 589 hdma->State = HAL_DMA_STATE_READY_MEM1;
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591 }
bogdanm 0:9b334a45a8ff 592 else
bogdanm 0:9b334a45a8ff 593 {
bogdanm 0:9b334a45a8ff 594 /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
bogdanm 0:9b334a45a8ff 595 are complete) */
bogdanm 0:9b334a45a8ff 596 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 597 }
bogdanm 0:9b334a45a8ff 598 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 599 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601 else
mbed_official 19:112740acecfa 602 {
mbed_official 19:112740acecfa 603 /* Clear the half transfer complete flag */
mbed_official 19:112740acecfa 604 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
mbed_official 19:112740acecfa 605
bogdanm 0:9b334a45a8ff 606 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 607 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 608 {
bogdanm 0:9b334a45a8ff 609 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 610 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 611 {
bogdanm 0:9b334a45a8ff 612 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 613 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 616 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 617 {
bogdanm 0:9b334a45a8ff 618 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 619 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
bogdanm 0:9b334a45a8ff 620 }
bogdanm 0:9b334a45a8ff 621 }
bogdanm 0:9b334a45a8ff 622 else
bogdanm 0:9b334a45a8ff 623 {
bogdanm 0:9b334a45a8ff 624 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 625 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 626 }
bogdanm 0:9b334a45a8ff 627 }
bogdanm 0:9b334a45a8ff 628 return HAL_OK;
bogdanm 0:9b334a45a8ff 629 }
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /**
bogdanm 0:9b334a45a8ff 632 * @brief Handles DMA interrupt request.
bogdanm 0:9b334a45a8ff 633 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 634 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 635 * @retval None
bogdanm 0:9b334a45a8ff 636 */
bogdanm 0:9b334a45a8ff 637 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 638 {
mbed_official 19:112740acecfa 639 /* calculate DMA base and stream number */
mbed_official 19:112740acecfa 640 DMA_Base_Registers *regs;
mbed_official 19:112740acecfa 641
mbed_official 19:112740acecfa 642 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
mbed_official 19:112740acecfa 643
bogdanm 0:9b334a45a8ff 644 /* Transfer Error Interrupt management ***************************************/
mbed_official 19:112740acecfa 645 if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 646 {
bogdanm 0:9b334a45a8ff 647 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 648 {
bogdanm 0:9b334a45a8ff 649 /* Disable the transfer error interrupt */
bogdanm 0:9b334a45a8ff 650 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 /* Clear the transfer error flag */
mbed_official 19:112740acecfa 653 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 /* Update error code */
bogdanm 0:9b334a45a8ff 656 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 659 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /* Process Unlocked */
mbed_official 19:112740acecfa 662 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 665 {
bogdanm 0:9b334a45a8ff 666 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 667 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671 /* FIFO Error Interrupt management ******************************************/
mbed_official 19:112740acecfa 672 if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 /* Disable the FIFO Error interrupt */
bogdanm 0:9b334a45a8ff 677 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 /* Clear the FIFO error flag */
mbed_official 19:112740acecfa 680 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /* Update error code */
bogdanm 0:9b334a45a8ff 683 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 686 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 689 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 692 {
bogdanm 0:9b334a45a8ff 693 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 694 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697 }
bogdanm 0:9b334a45a8ff 698 /* Direct Mode Error Interrupt management ***********************************/
mbed_official 19:112740acecfa 699 if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 700 {
bogdanm 0:9b334a45a8ff 701 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
bogdanm 0:9b334a45a8ff 702 {
bogdanm 0:9b334a45a8ff 703 /* Disable the direct mode Error interrupt */
bogdanm 0:9b334a45a8ff 704 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* Clear the direct mode error flag */
mbed_official 19:112740acecfa 707 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /* Update error code */
bogdanm 0:9b334a45a8ff 710 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 713 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 716 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 719 {
bogdanm 0:9b334a45a8ff 720 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 721 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723 }
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725 /* Half Transfer Complete Interrupt management ******************************/
mbed_official 19:112740acecfa 726 if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 727 {
bogdanm 0:9b334a45a8ff 728 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
mbed_official 19:112740acecfa 729 {
bogdanm 0:9b334a45a8ff 730 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 731 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 /* Clear the half transfer complete flag */
mbed_official 19:112740acecfa 734 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 737 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 738 {
bogdanm 0:9b334a45a8ff 739 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 740 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 741 }
bogdanm 0:9b334a45a8ff 742 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 743 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 744 {
bogdanm 0:9b334a45a8ff 745 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 746 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
bogdanm 0:9b334a45a8ff 747 }
bogdanm 0:9b334a45a8ff 748 }
bogdanm 0:9b334a45a8ff 749 else
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 752 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 753 {
bogdanm 0:9b334a45a8ff 754 /* Disable the half transfer interrupt */
bogdanm 0:9b334a45a8ff 755 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 756 }
bogdanm 0:9b334a45a8ff 757 /* Clear the half transfer complete flag */
mbed_official 19:112740acecfa 758 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 759
bogdanm 0:9b334a45a8ff 760 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 761 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 762 }
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 if(hdma->XferHalfCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 765 {
bogdanm 0:9b334a45a8ff 766 /* Half transfer callback */
bogdanm 0:9b334a45a8ff 767 hdma->XferHalfCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 768 }
bogdanm 0:9b334a45a8ff 769 }
bogdanm 0:9b334a45a8ff 770 }
bogdanm 0:9b334a45a8ff 771 /* Transfer Complete Interrupt management ***********************************/
mbed_official 19:112740acecfa 772 if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 773 {
bogdanm 0:9b334a45a8ff 774 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 777 {
bogdanm 0:9b334a45a8ff 778 /* Clear the transfer complete flag */
mbed_official 19:112740acecfa 779 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 782 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 783 {
bogdanm 0:9b334a45a8ff 784 if(hdma->XferM1CpltCallback != NULL)
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 /* Transfer complete Callback for memory1 */
bogdanm 0:9b334a45a8ff 787 hdma->XferM1CpltCallback(hdma);
bogdanm 0:9b334a45a8ff 788 }
bogdanm 0:9b334a45a8ff 789 }
bogdanm 0:9b334a45a8ff 790 /* Current memory buffer used is Memory 0 */
mbed_official 19:112740acecfa 791 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 794 {
bogdanm 0:9b334a45a8ff 795 /* Transfer complete Callback for memory0 */
bogdanm 0:9b334a45a8ff 796 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 797 }
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799 }
bogdanm 0:9b334a45a8ff 800 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 801 else
bogdanm 0:9b334a45a8ff 802 {
bogdanm 0:9b334a45a8ff 803 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 804 {
bogdanm 0:9b334a45a8ff 805 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 806 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808 /* Clear the transfer complete flag */
mbed_official 19:112740acecfa 809 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 /* Update error code */
bogdanm 0:9b334a45a8ff 812 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 815 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 /* Process Unlocked */
mbed_official 19:112740acecfa 818 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 821 {
bogdanm 0:9b334a45a8ff 822 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 823 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 824 }
bogdanm 0:9b334a45a8ff 825 }
bogdanm 0:9b334a45a8ff 826 }
bogdanm 0:9b334a45a8ff 827 }
bogdanm 0:9b334a45a8ff 828 }
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 /**
bogdanm 0:9b334a45a8ff 831 * @}
bogdanm 0:9b334a45a8ff 832 */
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /** @addtogroup DMA_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 835 *
bogdanm 0:9b334a45a8ff 836 @verbatim
bogdanm 0:9b334a45a8ff 837 ===============================================================================
bogdanm 0:9b334a45a8ff 838 ##### State and Errors functions #####
bogdanm 0:9b334a45a8ff 839 ===============================================================================
bogdanm 0:9b334a45a8ff 840 [..]
bogdanm 0:9b334a45a8ff 841 This subsection provides functions allowing to
bogdanm 0:9b334a45a8ff 842 (+) Check the DMA state
bogdanm 0:9b334a45a8ff 843 (+) Get error code
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 @endverbatim
bogdanm 0:9b334a45a8ff 846 * @{
bogdanm 0:9b334a45a8ff 847 */
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /**
bogdanm 0:9b334a45a8ff 850 * @brief Returns the DMA state.
bogdanm 0:9b334a45a8ff 851 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 852 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 853 * @retval HAL state
bogdanm 0:9b334a45a8ff 854 */
bogdanm 0:9b334a45a8ff 855 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 856 {
bogdanm 0:9b334a45a8ff 857 return hdma->State;
bogdanm 0:9b334a45a8ff 858 }
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /**
bogdanm 0:9b334a45a8ff 861 * @brief Return the DMA error code
bogdanm 0:9b334a45a8ff 862 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 863 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 864 * @retval DMA Error Code
bogdanm 0:9b334a45a8ff 865 */
bogdanm 0:9b334a45a8ff 866 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 867 {
bogdanm 0:9b334a45a8ff 868 return hdma->ErrorCode;
bogdanm 0:9b334a45a8ff 869 }
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /**
bogdanm 0:9b334a45a8ff 872 * @}
bogdanm 0:9b334a45a8ff 873 */
bogdanm 0:9b334a45a8ff 874
bogdanm 0:9b334a45a8ff 875 /**
bogdanm 0:9b334a45a8ff 876 * @}
bogdanm 0:9b334a45a8ff 877 */
bogdanm 0:9b334a45a8ff 878
bogdanm 0:9b334a45a8ff 879 /** @addtogroup DMA_Private_Functions
bogdanm 0:9b334a45a8ff 880 * @{
bogdanm 0:9b334a45a8ff 881 */
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 /**
bogdanm 0:9b334a45a8ff 884 * @brief Sets the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 885 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 886 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 887 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 888 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 889 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 890 * @retval HAL status
bogdanm 0:9b334a45a8ff 891 */
bogdanm 0:9b334a45a8ff 892 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 893 {
bogdanm 0:9b334a45a8ff 894 /* Clear DBM bit */
bogdanm 0:9b334a45a8ff 895 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /* Configure DMA Stream data length */
bogdanm 0:9b334a45a8ff 898 hdma->Instance->NDTR = DataLength;
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 901 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
bogdanm 0:9b334a45a8ff 902 {
bogdanm 0:9b334a45a8ff 903 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 904 hdma->Instance->PAR = DstAddress;
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 907 hdma->Instance->M0AR = SrcAddress;
bogdanm 0:9b334a45a8ff 908 }
bogdanm 0:9b334a45a8ff 909 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 910 else
bogdanm 0:9b334a45a8ff 911 {
bogdanm 0:9b334a45a8ff 912 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 913 hdma->Instance->PAR = SrcAddress;
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 916 hdma->Instance->M0AR = DstAddress;
bogdanm 0:9b334a45a8ff 917 }
bogdanm 0:9b334a45a8ff 918 }
mbed_official 19:112740acecfa 919
mbed_official 19:112740acecfa 920 /**
mbed_official 19:112740acecfa 921 * @brief Returns the DMA Stream base address depending on stream number
mbed_official 19:112740acecfa 922 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 19:112740acecfa 923 * the configuration information for the specified DMA Stream.
mbed_official 19:112740acecfa 924 * @retval Stream base address
mbed_official 19:112740acecfa 925 */
mbed_official 19:112740acecfa 926 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
mbed_official 19:112740acecfa 927 {
mbed_official 19:112740acecfa 928 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
mbed_official 19:112740acecfa 929
mbed_official 19:112740acecfa 930 /* lookup table for necessary bitshift of flags within status registers */
mbed_official 19:112740acecfa 931 static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
mbed_official 19:112740acecfa 932 hdma->StreamIndex = flagBitshiftOffset[stream_number];
mbed_official 19:112740acecfa 933
mbed_official 19:112740acecfa 934 if (stream_number > 3)
mbed_official 19:112740acecfa 935 {
mbed_official 19:112740acecfa 936 /* return pointer to HISR and HIFCR */
mbed_official 19:112740acecfa 937 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
mbed_official 19:112740acecfa 938 }
mbed_official 19:112740acecfa 939 else
mbed_official 19:112740acecfa 940 {
mbed_official 19:112740acecfa 941 /* return pointer to LISR and LIFCR */
mbed_official 19:112740acecfa 942 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
mbed_official 19:112740acecfa 943 }
mbed_official 19:112740acecfa 944
mbed_official 19:112740acecfa 945 return hdma->StreamBaseAddress;
mbed_official 19:112740acecfa 946 }
bogdanm 0:9b334a45a8ff 947 /**
bogdanm 0:9b334a45a8ff 948 * @}
bogdanm 0:9b334a45a8ff 949 */
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 952 /**
bogdanm 0:9b334a45a8ff 953 * @}
bogdanm 0:9b334a45a8ff 954 */
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /**
bogdanm 0:9b334a45a8ff 957 * @}
bogdanm 0:9b334a45a8ff 958 */
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/