en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_cortex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief CORTEX HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the CORTEX:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 *** How to configure Interrupts using CORTEX HAL driver ***
bogdanm 0:9b334a45a8ff 20 ===========================================================
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
bogdanm 0:9b334a45a8ff 23 The Cortex-M4 exceptions are managed by CMSIS functions.
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
bogdanm 0:9b334a45a8ff 26 function according to the following table.
bogdanm 0:9b334a45a8ff 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
bogdanm 0:9b334a45a8ff 28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
bogdanm 0:9b334a45a8ff 29 (#) please refer to programing manual for details in how to configure priority.
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
bogdanm 0:9b334a45a8ff 32 The pending IRQ priority will be managed only by the sub priority.
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 -@- IRQ priority order (sorted by highest to lowest priority):
bogdanm 0:9b334a45a8ff 35 (+@) Lowest preemption priority
bogdanm 0:9b334a45a8ff 36 (+@) Lowest sub priority
bogdanm 0:9b334a45a8ff 37 (+@) Lowest hardware priority (IRQ number)
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 [..]
bogdanm 0:9b334a45a8ff 40 *** How to configure Systick using CORTEX HAL driver ***
bogdanm 0:9b334a45a8ff 41 ========================================================
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 Setup SysTick Timer for time base.
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
bogdanm 0:9b334a45a8ff 46 is a CMSIS function that:
bogdanm 0:9b334a45a8ff 47 (++) Configures the SysTick Reload register with value passed as function parameter.
bogdanm 0:9b334a45a8ff 48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
bogdanm 0:9b334a45a8ff 49 (++) Resets the SysTick Counter register.
bogdanm 0:9b334a45a8ff 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
bogdanm 0:9b334a45a8ff 51 (++) Enables the SysTick Interrupt.
bogdanm 0:9b334a45a8ff 52 (++) Starts the SysTick Counter.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
bogdanm 0:9b334a45a8ff 55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
bogdanm 0:9b334a45a8ff 56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
bogdanm 0:9b334a45a8ff 57 inside the stm32f4xx_hal_cortex.h file.
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 (+) You can change the SysTick IRQ priority by calling the
bogdanm 0:9b334a45a8ff 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
bogdanm 0:9b334a45a8ff 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 (+) To adjust the SysTick time base, use the following formula:
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
bogdanm 0:9b334a45a8ff 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
bogdanm 0:9b334a45a8ff 67 (++) Reload Value should not exceed 0xFFFFFF
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 @endverbatim
bogdanm 0:9b334a45a8ff 70 ******************************************************************************
bogdanm 0:9b334a45a8ff 71 * @attention
bogdanm 0:9b334a45a8ff 72 *
bogdanm 0:9b334a45a8ff 73 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 74 *
bogdanm 0:9b334a45a8ff 75 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 76 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 77 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 78 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 80 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 81 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 83 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 84 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 85 *
bogdanm 0:9b334a45a8ff 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 96 *
bogdanm 0:9b334a45a8ff 97 ******************************************************************************
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /** @defgroup CORTEX CORTEX
bogdanm 0:9b334a45a8ff 108 * @brief CORTEX HAL module driver
bogdanm 0:9b334a45a8ff 109 * @{
bogdanm 0:9b334a45a8ff 110 */
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 #ifdef HAL_CORTEX_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 115 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 116 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 117 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
bogdanm 0:9b334a45a8ff 122 * @{
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 127 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 128 *
bogdanm 0:9b334a45a8ff 129 @verbatim
bogdanm 0:9b334a45a8ff 130 ==============================================================================
bogdanm 0:9b334a45a8ff 131 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 132 ==============================================================================
bogdanm 0:9b334a45a8ff 133 [..]
bogdanm 0:9b334a45a8ff 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
bogdanm 0:9b334a45a8ff 135 Systick functionalities
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 @endverbatim
bogdanm 0:9b334a45a8ff 138 * @{
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @brief Sets the priority grouping field (preemption priority and subpriority)
bogdanm 0:9b334a45a8ff 144 * using the required unlock sequence.
bogdanm 0:9b334a45a8ff 145 * @param PriorityGroup: The priority grouping bits length.
bogdanm 0:9b334a45a8ff 146 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
bogdanm 0:9b334a45a8ff 148 * 4 bits for subpriority
bogdanm 0:9b334a45a8ff 149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
bogdanm 0:9b334a45a8ff 150 * 3 bits for subpriority
bogdanm 0:9b334a45a8ff 151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
bogdanm 0:9b334a45a8ff 152 * 2 bits for subpriority
bogdanm 0:9b334a45a8ff 153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
bogdanm 0:9b334a45a8ff 154 * 1 bits for subpriority
bogdanm 0:9b334a45a8ff 155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
bogdanm 0:9b334a45a8ff 156 * 0 bits for subpriority
bogdanm 0:9b334a45a8ff 157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
bogdanm 0:9b334a45a8ff 158 * The pending IRQ priority will be managed only by the subpriority.
bogdanm 0:9b334a45a8ff 159 * @retval None
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 0:9b334a45a8ff 162 {
bogdanm 0:9b334a45a8ff 163 /* Check the parameters */
bogdanm 0:9b334a45a8ff 164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
bogdanm 0:9b334a45a8ff 167 NVIC_SetPriorityGrouping(PriorityGroup);
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @brief Sets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 172 * @param IRQn: External interrupt number.
bogdanm 0:9b334a45a8ff 173 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 174 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 175 * @param PreemptPriority: The preemption priority for the IRQn channel.
bogdanm 0:9b334a45a8ff 176 * This parameter can be a value between 0 and 15
bogdanm 0:9b334a45a8ff 177 * A lower priority value indicates a higher priority
bogdanm 0:9b334a45a8ff 178 * @param SubPriority: the subpriority level for the IRQ channel.
bogdanm 0:9b334a45a8ff 179 * This parameter can be a value between 0 and 15
bogdanm 0:9b334a45a8ff 180 * A lower priority value indicates a higher priority.
bogdanm 0:9b334a45a8ff 181 * @retval None
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 0:9b334a45a8ff 184 {
bogdanm 0:9b334a45a8ff 185 uint32_t prioritygroup = 0x00;
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /* Check the parameters */
bogdanm 0:9b334a45a8ff 188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
bogdanm 0:9b334a45a8ff 189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 prioritygroup = NVIC_GetPriorityGrouping();
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /**
bogdanm 0:9b334a45a8ff 197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
bogdanm 0:9b334a45a8ff 199 * function should be called before.
bogdanm 0:9b334a45a8ff 200 * @param IRQn External interrupt number.
bogdanm 0:9b334a45a8ff 201 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 203 * @retval None
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 206 {
bogdanm 0:9b334a45a8ff 207 /* Check the parameters */
bogdanm 0:9b334a45a8ff 208 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Enable interrupt */
bogdanm 0:9b334a45a8ff 211 NVIC_EnableIRQ(IRQn);
bogdanm 0:9b334a45a8ff 212 }
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /**
bogdanm 0:9b334a45a8ff 215 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 216 * @param IRQn External interrupt number.
bogdanm 0:9b334a45a8ff 217 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 219 * @retval None
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 /* Check the parameters */
bogdanm 0:9b334a45a8ff 224 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Disable interrupt */
bogdanm 0:9b334a45a8ff 227 NVIC_DisableIRQ(IRQn);
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /**
bogdanm 0:9b334a45a8ff 231 * @brief Initiates a system reset request to reset the MCU.
bogdanm 0:9b334a45a8ff 232 * @retval None
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234 void HAL_NVIC_SystemReset(void)
bogdanm 0:9b334a45a8ff 235 {
bogdanm 0:9b334a45a8ff 236 /* System Reset */
bogdanm 0:9b334a45a8ff 237 NVIC_SystemReset();
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 /**
bogdanm 0:9b334a45a8ff 241 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 0:9b334a45a8ff 242 * Counter is in free running mode to generate periodic interrupts.
bogdanm 0:9b334a45a8ff 243 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
bogdanm 0:9b334a45a8ff 244 * @retval status: - 0 Function succeeded.
bogdanm 0:9b334a45a8ff 245 * - 1 Function failed.
bogdanm 0:9b334a45a8ff 246 */
bogdanm 0:9b334a45a8ff 247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
bogdanm 0:9b334a45a8ff 248 {
bogdanm 0:9b334a45a8ff 249 return SysTick_Config(TicksNumb);
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251 /**
bogdanm 0:9b334a45a8ff 252 * @}
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 256 * @brief Cortex control functions
bogdanm 0:9b334a45a8ff 257 *
bogdanm 0:9b334a45a8ff 258 @verbatim
bogdanm 0:9b334a45a8ff 259 ==============================================================================
bogdanm 0:9b334a45a8ff 260 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 261 ==============================================================================
bogdanm 0:9b334a45a8ff 262 [..]
bogdanm 0:9b334a45a8ff 263 This subsection provides a set of functions allowing to control the CORTEX
mbed_official 19:112740acecfa 264 (NVIC, SYSTICK, MPU) functionalities.
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 @endverbatim
bogdanm 0:9b334a45a8ff 268 * @{
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
mbed_official 19:112740acecfa 271 #if (__MPU_PRESENT == 1)
mbed_official 19:112740acecfa 272 /**
mbed_official 19:112740acecfa 273 * @brief Initializes and configures the Region and the memory to be protected.
mbed_official 19:112740acecfa 274 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
mbed_official 19:112740acecfa 275 * the initialization and configuration information.
mbed_official 19:112740acecfa 276 * @retval None
mbed_official 19:112740acecfa 277 */
mbed_official 19:112740acecfa 278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
mbed_official 19:112740acecfa 279 {
mbed_official 19:112740acecfa 280 /* Check the parameters */
mbed_official 19:112740acecfa 281 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
mbed_official 19:112740acecfa 282 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
mbed_official 19:112740acecfa 283
mbed_official 19:112740acecfa 284 /* Set the Region number */
mbed_official 19:112740acecfa 285 MPU->RNR = MPU_Init->Number;
mbed_official 19:112740acecfa 286
mbed_official 19:112740acecfa 287 if ((MPU_Init->Enable) != RESET)
mbed_official 19:112740acecfa 288 {
mbed_official 19:112740acecfa 289 /* Check the parameters */
mbed_official 19:112740acecfa 290 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
mbed_official 19:112740acecfa 291 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
mbed_official 19:112740acecfa 292 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
mbed_official 19:112740acecfa 293 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
mbed_official 19:112740acecfa 294 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
mbed_official 19:112740acecfa 295 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
mbed_official 19:112740acecfa 296 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
mbed_official 19:112740acecfa 297 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
mbed_official 19:112740acecfa 298
mbed_official 19:112740acecfa 299 MPU->RBAR = MPU_Init->BaseAddress;
mbed_official 19:112740acecfa 300 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
mbed_official 19:112740acecfa 301 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
mbed_official 19:112740acecfa 302 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
mbed_official 19:112740acecfa 303 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
mbed_official 19:112740acecfa 304 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
mbed_official 19:112740acecfa 305 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
mbed_official 19:112740acecfa 306 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
mbed_official 19:112740acecfa 307 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
mbed_official 19:112740acecfa 308 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
mbed_official 19:112740acecfa 309 }
mbed_official 19:112740acecfa 310 else
mbed_official 19:112740acecfa 311 {
mbed_official 19:112740acecfa 312 MPU->RBAR = 0x00;
mbed_official 19:112740acecfa 313 MPU->RASR = 0x00;
mbed_official 19:112740acecfa 314 }
mbed_official 19:112740acecfa 315 }
mbed_official 19:112740acecfa 316 #endif /* __MPU_PRESENT */
mbed_official 19:112740acecfa 317
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
bogdanm 0:9b334a45a8ff 320 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 /* Get the PRIGROUP[10:8] field value */
bogdanm 0:9b334a45a8ff 325 return NVIC_GetPriorityGrouping();
bogdanm 0:9b334a45a8ff 326 }
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 /**
bogdanm 0:9b334a45a8ff 329 * @brief Gets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 330 * @param IRQn: External interrupt number.
bogdanm 0:9b334a45a8ff 331 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 332 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 333 * @param PriorityGroup: the priority grouping bits length.
bogdanm 0:9b334a45a8ff 334 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 335 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
bogdanm 0:9b334a45a8ff 336 * 4 bits for subpriority
bogdanm 0:9b334a45a8ff 337 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
bogdanm 0:9b334a45a8ff 338 * 3 bits for subpriority
bogdanm 0:9b334a45a8ff 339 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
bogdanm 0:9b334a45a8ff 340 * 2 bits for subpriority
bogdanm 0:9b334a45a8ff 341 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
bogdanm 0:9b334a45a8ff 342 * 1 bits for subpriority
bogdanm 0:9b334a45a8ff 343 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
bogdanm 0:9b334a45a8ff 344 * 0 bits for subpriority
bogdanm 0:9b334a45a8ff 345 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
bogdanm 0:9b334a45a8ff 346 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
bogdanm 0:9b334a45a8ff 347 * @retval None
bogdanm 0:9b334a45a8ff 348 */
bogdanm 0:9b334a45a8ff 349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
bogdanm 0:9b334a45a8ff 350 {
bogdanm 0:9b334a45a8ff 351 /* Check the parameters */
bogdanm 0:9b334a45a8ff 352 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
bogdanm 0:9b334a45a8ff 353 /* Get priority for Cortex-M system or device specific interrupts */
bogdanm 0:9b334a45a8ff 354 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /**
bogdanm 0:9b334a45a8ff 358 * @brief Sets Pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 359 * @param IRQn External interrupt number
bogdanm 0:9b334a45a8ff 360 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 361 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 362 * @retval None
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 /* Check the parameters */
bogdanm 0:9b334a45a8ff 367 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /* Set interrupt pending */
bogdanm 0:9b334a45a8ff 370 NVIC_SetPendingIRQ(IRQn);
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
bogdanm 0:9b334a45a8ff 375 * and returns the pending bit for the specified interrupt).
bogdanm 0:9b334a45a8ff 376 * @param IRQn External interrupt number.
bogdanm 0:9b334a45a8ff 377 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 379 * @retval status: - 0 Interrupt status is not pending.
bogdanm 0:9b334a45a8ff 380 * - 1 Interrupt status is pending.
bogdanm 0:9b334a45a8ff 381 */
bogdanm 0:9b334a45a8ff 382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 /* Check the parameters */
bogdanm 0:9b334a45a8ff 385 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /* Return 1 if pending else 0 */
bogdanm 0:9b334a45a8ff 388 return NVIC_GetPendingIRQ(IRQn);
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /**
bogdanm 0:9b334a45a8ff 392 * @brief Clears the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 393 * @param IRQn External interrupt number.
bogdanm 0:9b334a45a8ff 394 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 395 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 396 * @retval None
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 /* Check the parameters */
bogdanm 0:9b334a45a8ff 401 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* Clear pending interrupt */
bogdanm 0:9b334a45a8ff 404 NVIC_ClearPendingIRQ(IRQn);
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /**
bogdanm 0:9b334a45a8ff 408 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
bogdanm 0:9b334a45a8ff 409 * @param IRQn External interrupt number
bogdanm 0:9b334a45a8ff 410 * This parameter can be an enumerator of IRQn_Type enumeration
bogdanm 0:9b334a45a8ff 411 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
bogdanm 0:9b334a45a8ff 412 * @retval status: - 0 Interrupt status is not pending.
bogdanm 0:9b334a45a8ff 413 * - 1 Interrupt status is pending.
bogdanm 0:9b334a45a8ff 414 */
bogdanm 0:9b334a45a8ff 415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 416 {
bogdanm 0:9b334a45a8ff 417 /* Check the parameters */
bogdanm 0:9b334a45a8ff 418 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Return 1 if active else 0 */
bogdanm 0:9b334a45a8ff 421 return NVIC_GetActive(IRQn);
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @brief Configures the SysTick clock source.
bogdanm 0:9b334a45a8ff 426 * @param CLKSource: specifies the SysTick clock source.
bogdanm 0:9b334a45a8ff 427 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 428 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
bogdanm 0:9b334a45a8ff 429 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
bogdanm 0:9b334a45a8ff 430 * @retval None
bogdanm 0:9b334a45a8ff 431 */
bogdanm 0:9b334a45a8ff 432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
bogdanm 0:9b334a45a8ff 433 {
bogdanm 0:9b334a45a8ff 434 /* Check the parameters */
bogdanm 0:9b334a45a8ff 435 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
bogdanm 0:9b334a45a8ff 436 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
bogdanm 0:9b334a45a8ff 437 {
bogdanm 0:9b334a45a8ff 438 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440 else
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 }
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /**
bogdanm 0:9b334a45a8ff 447 * @brief This function handles SYSTICK interrupt request.
bogdanm 0:9b334a45a8ff 448 * @retval None
bogdanm 0:9b334a45a8ff 449 */
bogdanm 0:9b334a45a8ff 450 void HAL_SYSTICK_IRQHandler(void)
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 HAL_SYSTICK_Callback();
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /**
bogdanm 0:9b334a45a8ff 456 * @brief SYSTICK callback.
bogdanm 0:9b334a45a8ff 457 * @retval None
bogdanm 0:9b334a45a8ff 458 */
bogdanm 0:9b334a45a8ff 459 __weak void HAL_SYSTICK_Callback(void)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 462 the HAL_SYSTICK_Callback could be implemented in the user file
bogdanm 0:9b334a45a8ff 463 */
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @}
bogdanm 0:9b334a45a8ff 468 */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /**
bogdanm 0:9b334a45a8ff 471 * @}
bogdanm 0:9b334a45a8ff 472 */
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 #endif /* HAL_CORTEX_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 475 /**
bogdanm 0:9b334a45a8ff 476 * @}
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /**
bogdanm 0:9b334a45a8ff 480 * @}
bogdanm 0:9b334a45a8ff 481 */
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/