en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f4xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.3.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32f4xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 24 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 26 * | (external 8 MHz clock) | (internal 16 MHz)
bogdanm 0:9b334a45a8ff 27 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 28 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 29 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 30 * SYSCLK(MHz) | 180 | 180
bogdanm 0:9b334a45a8ff 31 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 32 * AHBCLK (MHz) | 180 | 180
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * APB1CLK (MHz) | 45 | 45
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * APB2CLK (MHz) | 90 | 90
bogdanm 0:9b334a45a8ff 37 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 * USB capable (48 MHz precise clock) | YES | NO
bogdanm 0:9b334a45a8ff 39 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 * @attention
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 44 *
bogdanm 0:9b334a45a8ff 45 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 46 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 47 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 48 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 50 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 51 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 53 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 54 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 55 *
bogdanm 0:9b334a45a8ff 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 66 *
bogdanm 0:9b334a45a8ff 67 ******************************************************************************
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 71 * @{
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @addtogroup stm32f4xx_system
bogdanm 0:9b334a45a8ff 75 * @{
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /** @addtogroup STM32F4xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 79 * @{
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 #include "stm32f4xx.h"
bogdanm 0:9b334a45a8ff 84 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 88 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 92 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /**
bogdanm 0:9b334a45a8ff 95 * @}
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /**
bogdanm 0:9b334a45a8ff 103 * @}
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /** @addtogroup STM32F4xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
bogdanm 0:9b334a45a8ff 112 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
bogdanm 0:9b334a45a8ff 113 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 114 /* #define DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 115 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
bogdanm 0:9b334a45a8ff 118 defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 119 /* #define DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 120 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 123 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
bogdanm 0:9b334a45a8ff 124 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 127 Internal SRAM. */
bogdanm 0:9b334a45a8ff 128 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 129 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 130 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 131 /******************************************************************************/
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /**
bogdanm 0:9b334a45a8ff 134 * @}
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /** @addtogroup STM32F4xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 138 * @{
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 142 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
bogdanm 0:9b334a45a8ff 143 #define USE_PLL_HSE_XTAL (0) /* Use external xtal */
bogdanm 0:9b334a45a8ff 144 #define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /**
bogdanm 0:9b334a45a8ff 147 * @}
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /** @addtogroup STM32F4xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 151 * @{
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 154 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 155 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 156 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 157 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 158 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 159 variable is updated automatically.
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161 uint32_t SystemCoreClock = 16000000;
bogdanm 0:9b334a45a8ff 162 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /**
bogdanm 0:9b334a45a8ff 165 * @}
bogdanm 0:9b334a45a8ff 166 */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 169 * @{
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 173 static void SystemInit_ExtMemCtl(void);
bogdanm 0:9b334a45a8ff 174 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 177 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 178 #endif
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /**
bogdanm 0:9b334a45a8ff 183 * @}
bogdanm 0:9b334a45a8ff 184 */
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /** @addtogroup STM32F4xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 187 * @{
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 192 * Initialize the FPU setting, vector table location and External memory
bogdanm 0:9b334a45a8ff 193 * configuration.
bogdanm 0:9b334a45a8ff 194 * @param None
bogdanm 0:9b334a45a8ff 195 * @retval None
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197 void SystemInit(void)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 200 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 201 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 202 #endif
bogdanm 0:9b334a45a8ff 203 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 204 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 205 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 208 RCC->CFGR = 0x00000000;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 211 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 214 RCC->PLLCFGR = 0x24003010;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 217 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 220 RCC->CIR = 0x00000000;
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 223 SystemInit_ExtMemCtl();
bogdanm 0:9b334a45a8ff 224 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 227 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 228 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 229 #else
bogdanm 0:9b334a45a8ff 230 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 231 #endif
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 234 SystemCoreClock = 18000000; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 235 HAL_Init();
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 238 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 239 SetSysClock();
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 242 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 243 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /**
bogdanm 0:9b334a45a8ff 247 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 248 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 249 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 250 * other parameters.
bogdanm 0:9b334a45a8ff 251 *
bogdanm 0:9b334a45a8ff 252 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 253 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 254 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 255 *
bogdanm 0:9b334a45a8ff 256 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 257 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 258 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 259 *
bogdanm 0:9b334a45a8ff 260 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 261 *
bogdanm 0:9b334a45a8ff 262 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 263 *
bogdanm 0:9b334a45a8ff 264 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 265 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 266 *
bogdanm 0:9b334a45a8ff 267 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 268 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 269 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 270 *
bogdanm 0:9b334a45a8ff 271 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
bogdanm 0:9b334a45a8ff 272 * depends on the application requirements), user has to ensure that HSE_VALUE
bogdanm 0:9b334a45a8ff 273 * is same as the real frequency of the crystal used. Otherwise, this function
bogdanm 0:9b334a45a8ff 274 * may have wrong result.
bogdanm 0:9b334a45a8ff 275 *
bogdanm 0:9b334a45a8ff 276 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 277 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 278 *
bogdanm 0:9b334a45a8ff 279 * @param None
bogdanm 0:9b334a45a8ff 280 * @retval None
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 287 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 switch (tmp)
bogdanm 0:9b334a45a8ff 290 {
bogdanm 0:9b334a45a8ff 291 case 0x00: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 292 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 293 break;
bogdanm 0:9b334a45a8ff 294 case 0x04: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 295 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 296 break;
bogdanm 0:9b334a45a8ff 297 case 0x08: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
bogdanm 0:9b334a45a8ff 300 SYSCLK = PLL_VCO / PLL_P
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
bogdanm 0:9b334a45a8ff 303 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 if (pllsource != 0)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 308 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310 else
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 313 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
bogdanm 0:9b334a45a8ff 317 SystemCoreClock = pllvco/pllp;
bogdanm 0:9b334a45a8ff 318 break;
bogdanm 0:9b334a45a8ff 319 default:
bogdanm 0:9b334a45a8ff 320 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 321 break;
bogdanm 0:9b334a45a8ff 322 }
bogdanm 0:9b334a45a8ff 323 /* Compute HCLK frequency --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 324 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 325 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 326 /* HCLK frequency */
bogdanm 0:9b334a45a8ff 327 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * @brief Setup the external memory controller.
bogdanm 0:9b334a45a8ff 333 * Called in startup_stm32f4xx.s before jump to main.
bogdanm 0:9b334a45a8ff 334 * This function configures the external memories (SRAM/SDRAM)
bogdanm 0:9b334a45a8ff 335 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
bogdanm 0:9b334a45a8ff 336 * @param None
bogdanm 0:9b334a45a8ff 337 * @retval None
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 void SystemInit_ExtMemCtl(void)
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 __IO uint32_t tmp = 0x00;
bogdanm 0:9b334a45a8ff 342 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 343 #if defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 344 register uint32_t tmpreg = 0, timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 345 register uint32_t index;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 348 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
bogdanm 0:9b334a45a8ff 349 clock */
bogdanm 0:9b334a45a8ff 350 RCC->AHB1ENR |= 0x0000007D;
bogdanm 0:9b334a45a8ff 351 #else
bogdanm 0:9b334a45a8ff 352 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
bogdanm 0:9b334a45a8ff 353 clock */
bogdanm 0:9b334a45a8ff 354 RCC->AHB1ENR |= 0x000001F8;
bogdanm 0:9b334a45a8ff 355 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 356 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 357 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 360 /* Connect PAx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 361 GPIOA->AFR[0] |= 0xC0000000;
bogdanm 0:9b334a45a8ff 362 GPIOA->AFR[1] |= 0x00000000;
bogdanm 0:9b334a45a8ff 363 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 364 GPIOA->MODER |= 0x00008000;
bogdanm 0:9b334a45a8ff 365 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 366 GPIOA->OSPEEDR |= 0x00008000;
bogdanm 0:9b334a45a8ff 367 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 368 GPIOA->OTYPER |= 0x00000000;
bogdanm 0:9b334a45a8ff 369 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 370 GPIOA->PUPDR |= 0x00000000;
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /* Connect PCx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 373 GPIOC->AFR[0] |= 0x00CC0000;
bogdanm 0:9b334a45a8ff 374 GPIOC->AFR[1] |= 0x00000000;
bogdanm 0:9b334a45a8ff 375 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 376 GPIOC->MODER |= 0x00000A00;
bogdanm 0:9b334a45a8ff 377 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 378 GPIOC->OSPEEDR |= 0x00000A00;
bogdanm 0:9b334a45a8ff 379 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 380 GPIOC->OTYPER |= 0x00000000;
bogdanm 0:9b334a45a8ff 381 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 382 GPIOC->PUPDR |= 0x00000000;
bogdanm 0:9b334a45a8ff 383 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 386 GPIOD->AFR[0] = 0x000000CC;
bogdanm 0:9b334a45a8ff 387 GPIOD->AFR[1] = 0xCC000CCC;
bogdanm 0:9b334a45a8ff 388 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 389 GPIOD->MODER = 0xA02A000A;
bogdanm 0:9b334a45a8ff 390 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 391 GPIOD->OSPEEDR = 0xA02A000A;
bogdanm 0:9b334a45a8ff 392 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 393 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 394 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 395 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 398 GPIOE->AFR[0] = 0xC00000CC;
bogdanm 0:9b334a45a8ff 399 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 400 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 401 GPIOE->MODER = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 402 /* Configure PEx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 403 GPIOE->OSPEEDR = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 404 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 405 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 406 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 407 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 410 GPIOF->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 411 GPIOF->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 412 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 413 GPIOF->MODER = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 414 /* Configure PFx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 415 GPIOF->OSPEEDR = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 416 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 417 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 418 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 419 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 422 GPIOG->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 423 GPIOG->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 424 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 425 GPIOG->MODER = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 426 /* Configure PGx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 427 GPIOG->OSPEEDR = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 428 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 429 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 430 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 431 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 434 /* Connect PHx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 435 GPIOH->AFR[0] = 0x00C0CC00;
bogdanm 0:9b334a45a8ff 436 GPIOH->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 437 /* Configure PHx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 438 GPIOH->MODER = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 439 /* Configure PHx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 440 GPIOH->OSPEEDR = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 441 /* Configure PHx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 442 GPIOH->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 443 /* No pull-up, pull-down for PHx pins */
bogdanm 0:9b334a45a8ff 444 GPIOH->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Connect PIx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 447 GPIOI->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 448 GPIOI->AFR[1] = 0x00000CC0;
bogdanm 0:9b334a45a8ff 449 /* Configure PIx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 450 GPIOI->MODER = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 451 /* Configure PIx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 452 GPIOI->OSPEEDR = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 453 /* Configure PIx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 454 GPIOI->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 455 /* No pull-up, pull-down for PIx pins */
bogdanm 0:9b334a45a8ff 456 GPIOI->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 457 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /*-- FMC Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 460 /* Enable the FMC interface clock */
bogdanm 0:9b334a45a8ff 461 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 462 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 463 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /* Configure and enable SDRAM bank1 */
bogdanm 0:9b334a45a8ff 466 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 467 FMC_Bank5_6->SDCR[0] = 0x00001954;
bogdanm 0:9b334a45a8ff 468 #else
bogdanm 0:9b334a45a8ff 469 FMC_Bank5_6->SDCR[0] = 0x000019E4;
bogdanm 0:9b334a45a8ff 470 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 471 FMC_Bank5_6->SDTR[0] = 0x01115351;
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* SDRAM initialization sequence */
bogdanm 0:9b334a45a8ff 474 /* Clock enable command */
bogdanm 0:9b334a45a8ff 475 FMC_Bank5_6->SDCMR = 0x00000011;
bogdanm 0:9b334a45a8ff 476 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 477 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 480 }
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* Delay */
bogdanm 0:9b334a45a8ff 483 for (index = 0; index<1000; index++);
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* PALL command */
bogdanm 0:9b334a45a8ff 486 FMC_Bank5_6->SDCMR = 0x00000012;
bogdanm 0:9b334a45a8ff 487 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 488 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 491 }
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Auto refresh command */
bogdanm 0:9b334a45a8ff 494 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 495 FMC_Bank5_6->SDCMR = 0x000000F3;
bogdanm 0:9b334a45a8ff 496 #else
bogdanm 0:9b334a45a8ff 497 FMC_Bank5_6->SDCMR = 0x00000073;
bogdanm 0:9b334a45a8ff 498 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 499 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 500 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* MRD register program */
bogdanm 0:9b334a45a8ff 506 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 507 FMC_Bank5_6->SDCMR = 0x00044014;
bogdanm 0:9b334a45a8ff 508 #else
bogdanm 0:9b334a45a8ff 509 FMC_Bank5_6->SDCMR = 0x00046014;
bogdanm 0:9b334a45a8ff 510 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 511 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 512 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 515 }
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Set refresh count */
bogdanm 0:9b334a45a8ff 518 tmpreg = FMC_Bank5_6->SDRTR;
bogdanm 0:9b334a45a8ff 519 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 520 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
bogdanm 0:9b334a45a8ff 521 #else
bogdanm 0:9b334a45a8ff 522 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
bogdanm 0:9b334a45a8ff 523 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Disable write protection */
bogdanm 0:9b334a45a8ff 526 tmpreg = FMC_Bank5_6->SDCR[0];
bogdanm 0:9b334a45a8ff 527 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
bogdanm 0:9b334a45a8ff 528 #endif /* DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 529 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
bogdanm 0:9b334a45a8ff 532 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 #if defined(DATA_IN_ExtSRAM)
bogdanm 0:9b334a45a8ff 535 /*-- GPIOs Configuration -----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 536 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
bogdanm 0:9b334a45a8ff 537 RCC->AHB1ENR |= 0x00000078;
bogdanm 0:9b334a45a8ff 538 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 539 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 542 GPIOD->AFR[0] = 0x00CCC0CC;
bogdanm 0:9b334a45a8ff 543 GPIOD->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 544 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 545 GPIOD->MODER = 0xAAAA0A8A;
bogdanm 0:9b334a45a8ff 546 /* Configure PDx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 547 GPIOD->OSPEEDR = 0xFFFF0FCF;
bogdanm 0:9b334a45a8ff 548 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 549 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 550 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 551 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 554 GPIOE->AFR[0] = 0xC00CC0CC;
bogdanm 0:9b334a45a8ff 555 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 556 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 557 GPIOE->MODER = 0xAAAA828A;
bogdanm 0:9b334a45a8ff 558 /* Configure PEx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 559 GPIOE->OSPEEDR = 0xFFFFC3CF;
bogdanm 0:9b334a45a8ff 560 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 561 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 562 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 563 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 566 GPIOF->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 567 GPIOF->AFR[1] = 0xCCCC0000;
bogdanm 0:9b334a45a8ff 568 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 569 GPIOF->MODER = 0xAA000AAA;
bogdanm 0:9b334a45a8ff 570 /* Configure PFx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 571 GPIOF->OSPEEDR = 0xFF000FFF;
bogdanm 0:9b334a45a8ff 572 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 573 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 574 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 575 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 578 GPIOG->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 579 GPIOG->AFR[1] = 0x000000C0;
bogdanm 0:9b334a45a8ff 580 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 581 GPIOG->MODER = 0x00085AAA;
bogdanm 0:9b334a45a8ff 582 /* Configure PGx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 583 GPIOG->OSPEEDR = 0x000CAFFF;
bogdanm 0:9b334a45a8ff 584 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 585 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 586 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 587 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /*-- FMC/FSMC Configuration --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 590 /* Enable the FMC/FSMC interface clock */
bogdanm 0:9b334a45a8ff 591 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 594 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 595 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
bogdanm 0:9b334a45a8ff 596 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 597 FMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 598 FMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 599 FMC_Bank1E->BWTR[2] = 0x0fffffff;
bogdanm 0:9b334a45a8ff 600 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 603 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 604 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
bogdanm 0:9b334a45a8ff 605 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 606 FSMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 607 FSMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 608 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 609 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 612 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 613 (void)(tmp);
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /**
bogdanm 0:9b334a45a8ff 618 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 619 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 620 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 621 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 622 * @param None
bogdanm 0:9b334a45a8ff 623 * @retval None
bogdanm 0:9b334a45a8ff 624 */
bogdanm 0:9b334a45a8ff 625 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 626 {
bogdanm 0:9b334a45a8ff 627 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 628 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 629 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 630 #endif
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 633 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 634 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 635 #endif
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 638 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 while(1)
bogdanm 0:9b334a45a8ff 641 {
bogdanm 0:9b334a45a8ff 642 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644 }
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646 }
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 // Output clock on MCO2 pin(PC9) for debugging purpose
bogdanm 0:9b334a45a8ff 649 #if DEBUG_MCO == 1
bogdanm 0:9b334a45a8ff 650 HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
bogdanm 0:9b334a45a8ff 651 #endif
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 655 /******************************************************************************/
bogdanm 0:9b334a45a8ff 656 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 657 /******************************************************************************/
bogdanm 0:9b334a45a8ff 658 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 661 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 662 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 665 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 666 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 667 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 668 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 // Enable HSE oscillator and activate PLL with HSE as source
bogdanm 0:9b334a45a8ff 671 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 672 if (bypass == 0)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676 else
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 682 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 683 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
bogdanm 0:9b334a45a8ff 684 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
bogdanm 0:9b334a45a8ff 685 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
bogdanm 0:9b334a45a8ff 686 RCC_OscInitStruct.PLL.PLLQ = 7; //
bogdanm 0:9b334a45a8ff 687 RCC_OscInitStruct.PLL.PLLR = 2; //
bogdanm 0:9b334a45a8ff 688 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 689 {
bogdanm 0:9b334a45a8ff 690 return 0; // FAIL
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 // Activate the OverDrive to reach the 180 MHz Frequency
bogdanm 0:9b334a45a8ff 694 if (HAL_PWREx_ActivateOverDrive() != HAL_OK)
bogdanm 0:9b334a45a8ff 695 {
bogdanm 0:9b334a45a8ff 696 return 0; // FAIL
bogdanm 0:9b334a45a8ff 697 }
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 // Select PLLSAI output as USB clock source
bogdanm 0:9b334a45a8ff 700 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
bogdanm 0:9b334a45a8ff 701 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
bogdanm 0:9b334a45a8ff 702 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
bogdanm 0:9b334a45a8ff 703 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
bogdanm 0:9b334a45a8ff 704 PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLSAIP;
bogdanm 0:9b334a45a8ff 705 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 708 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 709 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
bogdanm 0:9b334a45a8ff 710 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
bogdanm 0:9b334a45a8ff 711 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
bogdanm 0:9b334a45a8ff 712 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
bogdanm 0:9b334a45a8ff 713 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
bogdanm 0:9b334a45a8ff 714 {
bogdanm 0:9b334a45a8ff 715 return 0; // FAIL
bogdanm 0:9b334a45a8ff 716 }
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 719 #if DEBUG_MCO == 1
bogdanm 0:9b334a45a8ff 720 if (bypass == 0)
bogdanm 0:9b334a45a8ff 721 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
bogdanm 0:9b334a45a8ff 722 else
bogdanm 0:9b334a45a8ff 723 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
bogdanm 0:9b334a45a8ff 724 #endif
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 return 1; // OK
bogdanm 0:9b334a45a8ff 727 }
bogdanm 0:9b334a45a8ff 728 #endif
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /******************************************************************************/
bogdanm 0:9b334a45a8ff 731 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 732 /******************************************************************************/
bogdanm 0:9b334a45a8ff 733 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 734 {
bogdanm 0:9b334a45a8ff 735 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 736 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 739 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 740 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 741 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 742 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 // Enable HSI oscillator and activate PLL with HSI as source
bogdanm 0:9b334a45a8ff 745 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 746 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 747 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 748 RCC_OscInitStruct.HSICalibrationValue = 16;
bogdanm 0:9b334a45a8ff 749 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 750 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
bogdanm 0:9b334a45a8ff 751 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
bogdanm 0:9b334a45a8ff 752 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
bogdanm 0:9b334a45a8ff 753 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
bogdanm 0:9b334a45a8ff 754 RCC_OscInitStruct.PLL.PLLQ = 7; //
bogdanm 0:9b334a45a8ff 755 RCC_OscInitStruct.PLL.PLLQ = 6; //
bogdanm 0:9b334a45a8ff 756 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 757 {
bogdanm 0:9b334a45a8ff 758 return 0; // FAIL
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 762 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 763 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
bogdanm 0:9b334a45a8ff 764 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
bogdanm 0:9b334a45a8ff 765 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
bogdanm 0:9b334a45a8ff 766 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
bogdanm 0:9b334a45a8ff 767 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 return 0; // FAIL
bogdanm 0:9b334a45a8ff 770 }
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 773 #if DEBUG_MCO == 1
bogdanm 0:9b334a45a8ff 774 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
bogdanm 0:9b334a45a8ff 775 #endif
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 return 1; // OK
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 /**
bogdanm 0:9b334a45a8ff 781 * @}
bogdanm 0:9b334a45a8ff 782 */
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /**
bogdanm 0:9b334a45a8ff 785 * @}
bogdanm 0:9b334a45a8ff 786 */
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /**
bogdanm 0:9b334a45a8ff 789 * @}
bogdanm 0:9b334a45a8ff 790 */
bogdanm 0:9b334a45a8ff 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/