en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f4xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.1.0
bogdanm 0:9b334a45a8ff 6 * @date 19-June-2014
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32f4xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 24 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 26 * | (external 8 MHz clock) | (internal 16 MHz)
bogdanm 0:9b334a45a8ff 27 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 28 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 29 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 30 * SYSCLK(MHz) | 84 | 84
bogdanm 0:9b334a45a8ff 31 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 32 * AHBCLK (MHz) | 84 | 84
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * APB1CLK (MHz) | 42 | 42
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * APB2CLK (MHz) | 84 | 84
bogdanm 0:9b334a45a8ff 37 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 * USB capable (48 MHz precise clock) | YES | NO
bogdanm 0:9b334a45a8ff 39 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 * @attention
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 44 *
bogdanm 0:9b334a45a8ff 45 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 46 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 47 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 48 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 50 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 51 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 53 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 54 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 55 *
bogdanm 0:9b334a45a8ff 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 66 *
bogdanm 0:9b334a45a8ff 67 ******************************************************************************
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 71 * @{
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @addtogroup stm32f4xx_system
bogdanm 0:9b334a45a8ff 75 * @{
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /** @addtogroup STM32F4xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 79 * @{
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 #include "stm32f4xx.h"
bogdanm 0:9b334a45a8ff 83 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 87 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 90 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 91 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
bogdanm 0:9b334a45a8ff 94 * @}
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /**
bogdanm 0:9b334a45a8ff 102 * @}
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** @addtogroup STM32F4xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 106 * @{
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 110 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
bogdanm 0:9b334a45a8ff 111 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
bogdanm 0:9b334a45a8ff 112 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 113 /* #define DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 114 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 117 /* #define DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 118 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 121 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
bogdanm 0:9b334a45a8ff 122 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 125 Internal SRAM. */
bogdanm 0:9b334a45a8ff 126 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 127 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 128 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 129 /******************************************************************************/
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @}
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @addtogroup STM32F4xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 136 * @{
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 140 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
bogdanm 0:9b334a45a8ff 141 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /**
bogdanm 0:9b334a45a8ff 144 * @}
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /** @addtogroup STM32F4xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 151 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 152 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 153 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 154 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 155 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 156 variable is updated automatically.
bogdanm 0:9b334a45a8ff 157 */
bogdanm 0:9b334a45a8ff 158 uint32_t SystemCoreClock = 84000000;
bogdanm 0:9b334a45a8ff 159 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /**
bogdanm 0:9b334a45a8ff 162 * @}
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 166 * @{
bogdanm 0:9b334a45a8ff 167 */
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 170 static void SystemInit_ExtMemCtl(void);
bogdanm 0:9b334a45a8ff 171 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 174 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 175 #endif
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /**
bogdanm 0:9b334a45a8ff 180 * @}
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /** @addtogroup STM32F4xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 184 * @{
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /**
bogdanm 0:9b334a45a8ff 188 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 189 * Initialize the FPU setting, vector table location and External memory
bogdanm 0:9b334a45a8ff 190 * configuration.
bogdanm 0:9b334a45a8ff 191 * @param None
bogdanm 0:9b334a45a8ff 192 * @retval None
bogdanm 0:9b334a45a8ff 193 */
bogdanm 0:9b334a45a8ff 194 void SystemInit(void)
bogdanm 0:9b334a45a8ff 195 {
bogdanm 0:9b334a45a8ff 196 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 197 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 198 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 199 #endif
bogdanm 0:9b334a45a8ff 200 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 201 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 202 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 205 RCC->CFGR = 0x00000000;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 208 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 211 RCC->PLLCFGR = 0x24003010;
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 214 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 217 RCC->CIR = 0x00000000;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 220 SystemInit_ExtMemCtl();
bogdanm 0:9b334a45a8ff 221 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 224 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 225 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 226 #else
bogdanm 0:9b334a45a8ff 227 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 228 #endif
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 231 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 232 HAL_Init();
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 235 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 236 SetSysClock();
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 239 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 240 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 246 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 247 * other parameters.
bogdanm 0:9b334a45a8ff 248 *
bogdanm 0:9b334a45a8ff 249 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 250 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 251 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 252 *
bogdanm 0:9b334a45a8ff 253 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 254 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 255 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 256 *
bogdanm 0:9b334a45a8ff 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 258 *
bogdanm 0:9b334a45a8ff 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 260 *
bogdanm 0:9b334a45a8ff 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 263 *
bogdanm 0:9b334a45a8ff 264 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 265 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 266 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 267 *
bogdanm 0:9b334a45a8ff 268 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
bogdanm 0:9b334a45a8ff 269 * depends on the application requirements), user has to ensure that HSE_VALUE
bogdanm 0:9b334a45a8ff 270 * is same as the real frequency of the crystal used. Otherwise, this function
bogdanm 0:9b334a45a8ff 271 * may have wrong result.
bogdanm 0:9b334a45a8ff 272 *
bogdanm 0:9b334a45a8ff 273 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 274 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 275 *
bogdanm 0:9b334a45a8ff 276 * @param None
bogdanm 0:9b334a45a8ff 277 * @retval None
bogdanm 0:9b334a45a8ff 278 */
bogdanm 0:9b334a45a8ff 279 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 280 {
bogdanm 0:9b334a45a8ff 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 switch (tmp)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 case 0x00: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 289 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 290 break;
bogdanm 0:9b334a45a8ff 291 case 0x04: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 292 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 293 break;
bogdanm 0:9b334a45a8ff 294 case 0x08: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
bogdanm 0:9b334a45a8ff 297 SYSCLK = PLL_VCO / PLL_P
bogdanm 0:9b334a45a8ff 298 */
bogdanm 0:9b334a45a8ff 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
bogdanm 0:9b334a45a8ff 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 if (pllsource != 0)
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 else
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
bogdanm 0:9b334a45a8ff 314 SystemCoreClock = pllvco/pllp;
bogdanm 0:9b334a45a8ff 315 break;
bogdanm 0:9b334a45a8ff 316 default:
bogdanm 0:9b334a45a8ff 317 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 318 break;
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320 /* Compute HCLK frequency --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 321 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 323 /* HCLK frequency */
bogdanm 0:9b334a45a8ff 324 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 328 /**
bogdanm 0:9b334a45a8ff 329 * @brief Setup the external memory controller.
bogdanm 0:9b334a45a8ff 330 * Called in startup_stm32f4xx.s before jump to main.
bogdanm 0:9b334a45a8ff 331 * This function configures the external memories (SRAM/SDRAM)
bogdanm 0:9b334a45a8ff 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
bogdanm 0:9b334a45a8ff 333 * @param None
bogdanm 0:9b334a45a8ff 334 * @retval None
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 void SystemInit_ExtMemCtl(void)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 339 #if defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 341 register uint32_t index;
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
bogdanm 0:9b334a45a8ff 344 clock */
bogdanm 0:9b334a45a8ff 345 RCC->AHB1ENR |= 0x000001F8;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 348 GPIOD->AFR[0] = 0x000000CC;
bogdanm 0:9b334a45a8ff 349 GPIOD->AFR[1] = 0xCC000CCC;
bogdanm 0:9b334a45a8ff 350 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 351 GPIOD->MODER = 0xA02A000A;
bogdanm 0:9b334a45a8ff 352 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 353 GPIOD->OSPEEDR = 0xA02A000A;
bogdanm 0:9b334a45a8ff 354 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 355 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 356 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 357 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 360 GPIOE->AFR[0] = 0xC00000CC;
bogdanm 0:9b334a45a8ff 361 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 362 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 363 GPIOE->MODER = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 364 /* Configure PEx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 365 GPIOE->OSPEEDR = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 366 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 367 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 368 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 369 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 372 GPIOF->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 373 GPIOF->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 374 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 375 GPIOF->MODER = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 376 /* Configure PFx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 377 GPIOF->OSPEEDR = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 378 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 379 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 380 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 381 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 384 GPIOG->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 385 GPIOG->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 386 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 387 GPIOG->MODER = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 388 /* Configure PGx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 389 GPIOG->OSPEEDR = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 390 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 391 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 392 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 393 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /* Connect PHx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 396 GPIOH->AFR[0] = 0x00C0CC00;
bogdanm 0:9b334a45a8ff 397 GPIOH->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 398 /* Configure PHx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 399 GPIOH->MODER = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 400 /* Configure PHx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 401 GPIOH->OSPEEDR = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 402 /* Configure PHx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 403 GPIOH->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 404 /* No pull-up, pull-down for PHx pins */
bogdanm 0:9b334a45a8ff 405 GPIOH->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Connect PIx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 408 GPIOI->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 409 GPIOI->AFR[1] = 0x00000CC0;
bogdanm 0:9b334a45a8ff 410 /* Configure PIx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 411 GPIOI->MODER = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 412 /* Configure PIx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 413 GPIOI->OSPEEDR = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 414 /* Configure PIx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 415 GPIOI->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 416 /* No pull-up, pull-down for PIx pins */
bogdanm 0:9b334a45a8ff 417 GPIOI->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /*-- FMC Configuration ------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 420 /* Enable the FMC interface clock */
bogdanm 0:9b334a45a8ff 421 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 /* Configure and enable SDRAM bank1 */
bogdanm 0:9b334a45a8ff 424 FMC_Bank5_6->SDCR[0] = 0x000019E0;
bogdanm 0:9b334a45a8ff 425 FMC_Bank5_6->SDTR[0] = 0x01115351;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* SDRAM initialization sequence */
bogdanm 0:9b334a45a8ff 428 /* Clock enable command */
bogdanm 0:9b334a45a8ff 429 FMC_Bank5_6->SDCMR = 0x00000011;
bogdanm 0:9b334a45a8ff 430 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 431 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 434 }
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Delay */
bogdanm 0:9b334a45a8ff 437 for (index = 0; index<1000; index++);
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* PALL command */
bogdanm 0:9b334a45a8ff 440 FMC_Bank5_6->SDCMR = 0x00000012;
bogdanm 0:9b334a45a8ff 441 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 442 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 443 {
bogdanm 0:9b334a45a8ff 444 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Auto refresh command */
bogdanm 0:9b334a45a8ff 448 FMC_Bank5_6->SDCMR = 0x00000073;
bogdanm 0:9b334a45a8ff 449 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 450 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* MRD register program */
bogdanm 0:9b334a45a8ff 456 FMC_Bank5_6->SDCMR = 0x00046014;
bogdanm 0:9b334a45a8ff 457 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 458 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 459 {
bogdanm 0:9b334a45a8ff 460 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /* Set refresh count */
bogdanm 0:9b334a45a8ff 464 tmpreg = FMC_Bank5_6->SDRTR;
bogdanm 0:9b334a45a8ff 465 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Disable write protection */
bogdanm 0:9b334a45a8ff 468 tmpreg = FMC_Bank5_6->SDCR[0];
bogdanm 0:9b334a45a8ff 469 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
bogdanm 0:9b334a45a8ff 470 #endif /* DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 471 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 474 #if defined(DATA_IN_ExtSRAM)
bogdanm 0:9b334a45a8ff 475 /*-- GPIOs Configuration -----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 476 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
bogdanm 0:9b334a45a8ff 477 RCC->AHB1ENR |= 0x00000078;
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 480 GPIOD->AFR[0] = 0x00CCC0CC;
bogdanm 0:9b334a45a8ff 481 GPIOD->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 482 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 483 GPIOD->MODER = 0xAAAA0A8A;
bogdanm 0:9b334a45a8ff 484 /* Configure PDx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 485 GPIOD->OSPEEDR = 0xFFFF0FCF;
bogdanm 0:9b334a45a8ff 486 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 487 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 488 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 489 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 492 GPIOE->AFR[0] = 0xC00CC0CC;
bogdanm 0:9b334a45a8ff 493 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 494 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 495 GPIOE->MODER = 0xAAAA828A;
bogdanm 0:9b334a45a8ff 496 /* Configure PEx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 497 GPIOE->OSPEEDR = 0xFFFFC3CF;
bogdanm 0:9b334a45a8ff 498 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 499 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 500 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 501 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 504 GPIOF->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 505 GPIOF->AFR[1] = 0xCCCC0000;
bogdanm 0:9b334a45a8ff 506 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 507 GPIOF->MODER = 0xAA000AAA;
bogdanm 0:9b334a45a8ff 508 /* Configure PFx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 509 GPIOF->OSPEEDR = 0xFF000FFF;
bogdanm 0:9b334a45a8ff 510 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 511 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 512 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 513 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 516 GPIOG->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 517 GPIOG->AFR[1] = 0x000000C0;
bogdanm 0:9b334a45a8ff 518 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 519 GPIOG->MODER = 0x00085AAA;
bogdanm 0:9b334a45a8ff 520 /* Configure PGx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 521 GPIOG->OSPEEDR = 0x000CAFFF;
bogdanm 0:9b334a45a8ff 522 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 523 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 524 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 525 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /*-- FMC/FSMC Configuration --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 528 /* Enable the FMC/FSMC interface clock */
bogdanm 0:9b334a45a8ff 529 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 532 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 533 FMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 534 FMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 535 FMC_Bank1E->BWTR[2] = 0x0fffffff;
bogdanm 0:9b334a45a8ff 536 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 539 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 540 FSMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 541 FSMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 542 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 546 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 547 }
bogdanm 0:9b334a45a8ff 548 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /**
bogdanm 0:9b334a45a8ff 551 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 552 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 553 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 554 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 555 * @param None
bogdanm 0:9b334a45a8ff 556 * @retval None
bogdanm 0:9b334a45a8ff 557 */
bogdanm 0:9b334a45a8ff 558 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 561 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 562 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 563 #endif
bogdanm 0:9b334a45a8ff 564 {
bogdanm 0:9b334a45a8ff 565 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 566 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 567 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 568 #endif
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 571 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 while(1)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578 }
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /* Output clock on MCO2 pin(PC9) for debugging purpose */
bogdanm 0:9b334a45a8ff 582 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 586 /******************************************************************************/
bogdanm 0:9b334a45a8ff 587 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 588 /******************************************************************************/
bogdanm 0:9b334a45a8ff 589 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 590 {
bogdanm 0:9b334a45a8ff 591 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 592 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 595 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 596 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 597 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 598 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* Enable HSE oscillator and activate PLL with HSE as source */
bogdanm 0:9b334a45a8ff 601 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 602 if (bypass == 0)
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 else
bogdanm 0:9b334a45a8ff 607 {
bogdanm 0:9b334a45a8ff 608 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 611 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 612 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
bogdanm 0:9b334a45a8ff 613 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
bogdanm 0:9b334a45a8ff 614 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
bogdanm 0:9b334a45a8ff 615 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
bogdanm 0:9b334a45a8ff 616 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 617 {
bogdanm 0:9b334a45a8ff 618 return 0; // FAIL
bogdanm 0:9b334a45a8ff 619 }
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 622 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 623 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
bogdanm 0:9b334a45a8ff 624 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
bogdanm 0:9b334a45a8ff 625 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
bogdanm 0:9b334a45a8ff 626 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
bogdanm 0:9b334a45a8ff 627 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
bogdanm 0:9b334a45a8ff 628 {
bogdanm 0:9b334a45a8ff 629 return 0; // FAIL
bogdanm 0:9b334a45a8ff 630 }
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 633 /*
bogdanm 0:9b334a45a8ff 634 if (bypass == 0)
bogdanm 0:9b334a45a8ff 635 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
bogdanm 0:9b334a45a8ff 636 else
bogdanm 0:9b334a45a8ff 637 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
bogdanm 0:9b334a45a8ff 638 */
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 return 1; // OK
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642 #endif
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /******************************************************************************/
bogdanm 0:9b334a45a8ff 645 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 646 /******************************************************************************/
bogdanm 0:9b334a45a8ff 647 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 648 {
bogdanm 0:9b334a45a8ff 649 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 650 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 /* The voltage scaling allows optimizing the power consumption when the device is
bogdanm 0:9b334a45a8ff 653 clocked below the maximum system frequency, to update the voltage scaling value
bogdanm 0:9b334a45a8ff 654 regarding system frequency refer to product datasheet. */
bogdanm 0:9b334a45a8ff 655 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 656 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 /* Enable HSI oscillator and activate PLL with HSI as source */
bogdanm 0:9b334a45a8ff 659 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 660 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 661 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 662 RCC_OscInitStruct.HSICalibrationValue = 16;
bogdanm 0:9b334a45a8ff 663 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 664 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
bogdanm 0:9b334a45a8ff 665 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
bogdanm 0:9b334a45a8ff 666 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
bogdanm 0:9b334a45a8ff 667 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
bogdanm 0:9b334a45a8ff 668 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
bogdanm 0:9b334a45a8ff 669 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 return 0; // FAIL
bogdanm 0:9b334a45a8ff 672 }
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 675 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 676 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
bogdanm 0:9b334a45a8ff 677 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
bogdanm 0:9b334a45a8ff 678 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
bogdanm 0:9b334a45a8ff 679 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
bogdanm 0:9b334a45a8ff 680 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 return 0; // FAIL
bogdanm 0:9b334a45a8ff 683 }
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 686 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 return 1; // OK
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 /**
bogdanm 0:9b334a45a8ff 692 * @}
bogdanm 0:9b334a45a8ff 693 */
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /**
bogdanm 0:9b334a45a8ff 696 * @}
bogdanm 0:9b334a45a8ff 697 */
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 /**
bogdanm 0:9b334a45a8ff 700 * @}
bogdanm 0:9b334a45a8ff 701 */
bogdanm 0:9b334a45a8ff 702 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/