en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_ll_fmc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief FMC Low Layer HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 ##### FMC peripheral features #####
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
bogdanm 0:9b334a45a8ff 20 (+) The NOR/PSRAM memory controller
bogdanm 0:9b334a45a8ff 21 (+) The NAND/PC Card memory controller
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 [..] The FMC functional block makes the interface with synchronous and asynchronous static
bogdanm 0:9b334a45a8ff 24 memories, and 16-bit PC memory cards. Its main purposes are:
bogdanm 0:9b334a45a8ff 25 (+) to translate AHB transactions into the appropriate external device protocol
bogdanm 0:9b334a45a8ff 26 (+) to meet the access time requirements of the external memory devices
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 [..] All external memories share the addresses, data and control signals with the controller.
bogdanm 0:9b334a45a8ff 29 Each external device is accessed by means of a unique Chip Select. The FMC performs
bogdanm 0:9b334a45a8ff 30 only one access at a time to an external device.
bogdanm 0:9b334a45a8ff 31 The main features of the FMC controller are the following:
bogdanm 0:9b334a45a8ff 32 (+) Interface with static-memory mapped devices including:
bogdanm 0:9b334a45a8ff 33 (++) Static random access memory (SRAM)
bogdanm 0:9b334a45a8ff 34 (++) Read-only memory (ROM)
bogdanm 0:9b334a45a8ff 35 (++) NOR Flash memory/OneNAND Flash memory
bogdanm 0:9b334a45a8ff 36 (++) PSRAM (4 memory banks)
bogdanm 0:9b334a45a8ff 37 (++) 16-bit PC Card compatible devices
bogdanm 0:9b334a45a8ff 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
bogdanm 0:9b334a45a8ff 39 data
bogdanm 0:9b334a45a8ff 40 (+) Independent Chip Select control for each memory bank
bogdanm 0:9b334a45a8ff 41 (+) Independent configuration for each memory bank
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 @endverbatim
bogdanm 0:9b334a45a8ff 44 ******************************************************************************
bogdanm 0:9b334a45a8ff 45 * @attention
bogdanm 0:9b334a45a8ff 46 *
bogdanm 0:9b334a45a8ff 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 48 *
bogdanm 0:9b334a45a8ff 49 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 50 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 51 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 52 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 54 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 55 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 57 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 58 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 ******************************************************************************
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 75 #include "stm32f3xx_hal.h"
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 78 * @{
bogdanm 0:9b334a45a8ff 79 */
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /** @defgroup FMC
bogdanm 0:9b334a45a8ff 82 * @brief FMC driver modules
bogdanm 0:9b334a45a8ff 83 * @{
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 91 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 92 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 93 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 94 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 95 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @defgroup FMC_Private_Functions
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @defgroup FMC_NORSRAM Controller functions
bogdanm 0:9b334a45a8ff 102 * @brief NORSRAM Controller functions
bogdanm 0:9b334a45a8ff 103 *
bogdanm 0:9b334a45a8ff 104 @verbatim
bogdanm 0:9b334a45a8ff 105 ==============================================================================
bogdanm 0:9b334a45a8ff 106 ##### How to use NORSRAM device driver #####
bogdanm 0:9b334a45a8ff 107 ==============================================================================
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 [..]
bogdanm 0:9b334a45a8ff 110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
bogdanm 0:9b334a45a8ff 111 to run the NORSRAM external devices.
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
bogdanm 0:9b334a45a8ff 114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
bogdanm 0:9b334a45a8ff 115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 116 (+) FMC NORSRAM bank extended timing configuration using the function
bogdanm 0:9b334a45a8ff 117 FMC_NORSRAM_Extended_Timing_Init()
bogdanm 0:9b334a45a8ff 118 (+) FMC NORSRAM bank enable/disable write operation using the functions
bogdanm 0:9b334a45a8ff 119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 @endverbatim
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /** @defgroup FMC_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 127 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 128 *
bogdanm 0:9b334a45a8ff 129 @verbatim
bogdanm 0:9b334a45a8ff 130 ==============================================================================
bogdanm 0:9b334a45a8ff 131 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 132 ==============================================================================
bogdanm 0:9b334a45a8ff 133 [..]
bogdanm 0:9b334a45a8ff 134 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 135 (+) Initialize and configure the FMC NORSRAM interface
bogdanm 0:9b334a45a8ff 136 (+) De-initialize the FMC NORSRAM interface
bogdanm 0:9b334a45a8ff 137 (+) Configure the FMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 @endverbatim
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /**
bogdanm 0:9b334a45a8ff 144 * @brief Initialize the FMC_NORSRAM device according to the specified
bogdanm 0:9b334a45a8ff 145 * control parameters in the FMC_NORSRAM_InitTypeDef
bogdanm 0:9b334a45a8ff 146 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 147 * @param Init: Pointer to NORSRAM Initialization structure
bogdanm 0:9b334a45a8ff 148 * @retval HAL status
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
bogdanm 0:9b334a45a8ff 151 {
bogdanm 0:9b334a45a8ff 152 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /* Check the parameters */
bogdanm 0:9b334a45a8ff 155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
bogdanm 0:9b334a45a8ff 157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
bogdanm 0:9b334a45a8ff 158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
bogdanm 0:9b334a45a8ff 159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm 0:9b334a45a8ff 160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
bogdanm 0:9b334a45a8ff 161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
bogdanm 0:9b334a45a8ff 162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
bogdanm 0:9b334a45a8ff 163 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
bogdanm 0:9b334a45a8ff 164 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
bogdanm 0:9b334a45a8ff 165 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
bogdanm 0:9b334a45a8ff 166 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
bogdanm 0:9b334a45a8ff 167 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
bogdanm 0:9b334a45a8ff 168 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
bogdanm 0:9b334a45a8ff 169 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Set NORSRAM device control parameters */
bogdanm 0:9b334a45a8ff 172 tmpr = (uint32_t)(Init->DataAddressMux |\
bogdanm 0:9b334a45a8ff 173 Init->MemoryType |\
bogdanm 0:9b334a45a8ff 174 Init->MemoryDataWidth |\
bogdanm 0:9b334a45a8ff 175 Init->BurstAccessMode |\
bogdanm 0:9b334a45a8ff 176 Init->WaitSignalPolarity |\
bogdanm 0:9b334a45a8ff 177 Init->WrapMode |\
bogdanm 0:9b334a45a8ff 178 Init->WaitSignalActive |\
bogdanm 0:9b334a45a8ff 179 Init->WriteOperation |\
bogdanm 0:9b334a45a8ff 180 Init->WaitSignal |\
bogdanm 0:9b334a45a8ff 181 Init->ExtendedMode |\
bogdanm 0:9b334a45a8ff 182 Init->AsynchronousWait |\
bogdanm 0:9b334a45a8ff 183 Init->WriteBurst |\
bogdanm 0:9b334a45a8ff 184 Init->ContinuousClock
bogdanm 0:9b334a45a8ff 185 );
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
bogdanm 0:9b334a45a8ff 188 {
bogdanm 0:9b334a45a8ff 189 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 Device->BTCR[Init->NSBank] = tmpr;
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
bogdanm 0:9b334a45a8ff 195 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
bogdanm 0:9b334a45a8ff 196 {
bogdanm 0:9b334a45a8ff 197 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
bogdanm 0:9b334a45a8ff 198 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
bogdanm 0:9b334a45a8ff 199 Init->ContinuousClock);
bogdanm 0:9b334a45a8ff 200 }
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 return HAL_OK;
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /**
bogdanm 0:9b334a45a8ff 207 * @brief DeInitialize the FMC_NORSRAM peripheral
bogdanm 0:9b334a45a8ff 208 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 209 * @param ExDevice: Pointer to NORSRAM extended mode device instance
bogdanm 0:9b334a45a8ff 210 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 211 * @retval HAL status
bogdanm 0:9b334a45a8ff 212 */
bogdanm 0:9b334a45a8ff 213 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 /* Check the parameters */
bogdanm 0:9b334a45a8ff 216 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 217 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
bogdanm 0:9b334a45a8ff 218 assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 /* Disable the FMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 221 __FMC_NORSRAM_DISABLE(Device, Bank);
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* De-initialize the FMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 224 /* FMC_NORSRAM_BANK1 */
bogdanm 0:9b334a45a8ff 225 if(Bank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 226 {
bogdanm 0:9b334a45a8ff 227 Device->BTCR[Bank] = 0x000030DB;
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 230 else
bogdanm 0:9b334a45a8ff 231 {
bogdanm 0:9b334a45a8ff 232 Device->BTCR[Bank] = 0x000030D2;
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 236 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 return HAL_OK;
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /**
bogdanm 0:9b334a45a8ff 243 * @brief Initialize the FMC_NORSRAM Timing according to the specified
bogdanm 0:9b334a45a8ff 244 * parameters in the FMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 245 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 246 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 247 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 248 * @retval HAL status
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 251 {
bogdanm 0:9b334a45a8ff 252 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /* Check the parameters */
bogdanm 0:9b334a45a8ff 255 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 256 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 257 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 258 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 259 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 260 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
bogdanm 0:9b334a45a8ff 261 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
bogdanm 0:9b334a45a8ff 262 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 263 assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /* Set FMC_NORSRAM device timing parameters */
bogdanm 0:9b334a45a8ff 266 tmpr = (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 267 ((Timing->AddressHoldTime) << 4) |\
bogdanm 0:9b334a45a8ff 268 ((Timing->DataSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 269 ((Timing->BusTurnAroundDuration) << 16) |\
bogdanm 0:9b334a45a8ff 270 (((Timing->CLKDivision)-1) << 20) |\
bogdanm 0:9b334a45a8ff 271 (((Timing->DataLatency)-2) << 24) |\
bogdanm 0:9b334a45a8ff 272 (Timing->AccessMode)
bogdanm 0:9b334a45a8ff 273 );
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 Device->BTCR[Bank + 1] = tmpr;
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
bogdanm 0:9b334a45a8ff 278 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
bogdanm 0:9b334a45a8ff 281 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
bogdanm 0:9b334a45a8ff 282 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 return HAL_OK;
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /**
bogdanm 0:9b334a45a8ff 289 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
bogdanm 0:9b334a45a8ff 290 * parameters in the FMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 291 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 292 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 293 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 294 * @retval HAL status
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
bogdanm 0:9b334a45a8ff 297 {
bogdanm 0:9b334a45a8ff 298 /* Check the parameters */
bogdanm 0:9b334a45a8ff 299 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
bogdanm 0:9b334a45a8ff 302 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* Check the parameters */
bogdanm 0:9b334a45a8ff 305 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
bogdanm 0:9b334a45a8ff 306 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 307 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 308 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 309 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 310 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
bogdanm 0:9b334a45a8ff 311 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
bogdanm 0:9b334a45a8ff 312 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 313 assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 316 ((Timing->AddressHoldTime) << 4) |\
bogdanm 0:9b334a45a8ff 317 ((Timing->DataSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 318 ((Timing->BusTurnAroundDuration) << 16) |\
bogdanm 0:9b334a45a8ff 319 (((Timing->CLKDivision)-1) << 20) |\
bogdanm 0:9b334a45a8ff 320 (((Timing->DataLatency)-2) << 24) |\
bogdanm 0:9b334a45a8ff 321 (Timing->AccessMode));
bogdanm 0:9b334a45a8ff 322 }
bogdanm 0:9b334a45a8ff 323 else
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 Device->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 326 }
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 return HAL_OK;
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @}
bogdanm 0:9b334a45a8ff 334 */
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /** @defgroup FMC_NORSRAM_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 338 * @brief management functions
bogdanm 0:9b334a45a8ff 339 *
bogdanm 0:9b334a45a8ff 340 @verbatim
bogdanm 0:9b334a45a8ff 341 ==============================================================================
bogdanm 0:9b334a45a8ff 342 ##### FMC_NORSRAM Control functions #####
bogdanm 0:9b334a45a8ff 343 ==============================================================================
bogdanm 0:9b334a45a8ff 344 [..]
bogdanm 0:9b334a45a8ff 345 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 346 the FMC NORSRAM interface.
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 @endverbatim
bogdanm 0:9b334a45a8ff 349 * @{
bogdanm 0:9b334a45a8ff 350 */
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @brief Enables dynamically FMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 354 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 355 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 356 * @retval HAL status
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 /* Check the parameters */
bogdanm 0:9b334a45a8ff 361 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 362 assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Enable write operation */
bogdanm 0:9b334a45a8ff 365 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 return HAL_OK;
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /**
bogdanm 0:9b334a45a8ff 371 * @brief Disables dynamically FMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 372 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 373 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 374 * @retval HAL status
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 377 {
bogdanm 0:9b334a45a8ff 378 /* Check the parameters */
bogdanm 0:9b334a45a8ff 379 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 380 assert_param(IS_FMC_NORSRAM_BANK(Bank));
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Disable write operation */
bogdanm 0:9b334a45a8ff 383 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 return HAL_OK;
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /**
bogdanm 0:9b334a45a8ff 389 * @}
bogdanm 0:9b334a45a8ff 390 */
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /**
bogdanm 0:9b334a45a8ff 393 * @}
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /** @defgroup FMC_NAND Controller functions
bogdanm 0:9b334a45a8ff 397 * @brief NAND Controller functions
bogdanm 0:9b334a45a8ff 398 *
bogdanm 0:9b334a45a8ff 399 @verbatim
bogdanm 0:9b334a45a8ff 400 ==============================================================================
bogdanm 0:9b334a45a8ff 401 ##### How to use NAND device driver #####
bogdanm 0:9b334a45a8ff 402 ==============================================================================
bogdanm 0:9b334a45a8ff 403 [..]
bogdanm 0:9b334a45a8ff 404 This driver contains a set of APIs to interface with the FMC NAND banks in order
bogdanm 0:9b334a45a8ff 405 to run the NAND external devices.
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
bogdanm 0:9b334a45a8ff 408 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
bogdanm 0:9b334a45a8ff 409 (+) FMC NAND bank common space timing configuration using the function
bogdanm 0:9b334a45a8ff 410 FMC_NAND_CommonSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 411 (+) FMC NAND bank attribute space timing configuration using the function
bogdanm 0:9b334a45a8ff 412 FMC_NAND_AttributeSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 413 (+) FMC NAND bank enable/disable ECC correction feature using the functions
bogdanm 0:9b334a45a8ff 414 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
bogdanm 0:9b334a45a8ff 415 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 @endverbatim
bogdanm 0:9b334a45a8ff 418 * @{
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 422 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 423 *
bogdanm 0:9b334a45a8ff 424 @verbatim
bogdanm 0:9b334a45a8ff 425 ==============================================================================
bogdanm 0:9b334a45a8ff 426 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 427 ==============================================================================
bogdanm 0:9b334a45a8ff 428 [..]
bogdanm 0:9b334a45a8ff 429 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 430 (+) Initialize and configure the FMC NAND interface
bogdanm 0:9b334a45a8ff 431 (+) De-initialize the FMC NAND interface
bogdanm 0:9b334a45a8ff 432 (+) Configure the FMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 @endverbatim
bogdanm 0:9b334a45a8ff 435 * @{
bogdanm 0:9b334a45a8ff 436 */
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /**
bogdanm 0:9b334a45a8ff 439 * @brief Initializes the FMC_NAND device according to the specified
bogdanm 0:9b334a45a8ff 440 * control parameters in the FMC_NAND_HandleTypeDef
bogdanm 0:9b334a45a8ff 441 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 442 * @param Init: Pointer to NAND Initialization structure
bogdanm 0:9b334a45a8ff 443 * @retval HAL status
bogdanm 0:9b334a45a8ff 444 */
bogdanm 0:9b334a45a8ff 445 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 uint32_t tmppcr = 0;
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Check the parameters */
bogdanm 0:9b334a45a8ff 450 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 451 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
bogdanm 0:9b334a45a8ff 452 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm 0:9b334a45a8ff 453 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm 0:9b334a45a8ff 454 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
bogdanm 0:9b334a45a8ff 455 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
bogdanm 0:9b334a45a8ff 456 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm 0:9b334a45a8ff 457 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /* Set NAND device control parameters */
bogdanm 0:9b334a45a8ff 460 tmppcr = (uint32_t)(Init->Waitfeature |\
bogdanm 0:9b334a45a8ff 461 FMC_PCR_MEMORY_TYPE_NAND |\
bogdanm 0:9b334a45a8ff 462 Init->MemoryDataWidth |\
bogdanm 0:9b334a45a8ff 463 Init->EccComputation |\
bogdanm 0:9b334a45a8ff 464 Init->ECCPageSize |\
bogdanm 0:9b334a45a8ff 465 ((Init->TCLRSetupTime) << 9) |\
bogdanm 0:9b334a45a8ff 466 ((Init->TARSetupTime) << 13)
bogdanm 0:9b334a45a8ff 467 );
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 if(Init->NandBank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 472 Device->PCR2 = tmppcr;
bogdanm 0:9b334a45a8ff 473 }
bogdanm 0:9b334a45a8ff 474 else
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 477 Device->PCR3 = tmppcr;
bogdanm 0:9b334a45a8ff 478 }
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 return HAL_OK;
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /**
bogdanm 0:9b334a45a8ff 485 * @brief Initializes the FMC_NAND Common space Timing according to the specified
bogdanm 0:9b334a45a8ff 486 * parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 487 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 488 * @param Timing: Pointer to NAND timing structure
bogdanm 0:9b334a45a8ff 489 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 490 * @retval HAL status
bogdanm 0:9b334a45a8ff 491 */
bogdanm 0:9b334a45a8ff 492 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 493 {
bogdanm 0:9b334a45a8ff 494 uint32_t tmppmem = 0;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Check the parameters */
bogdanm 0:9b334a45a8ff 497 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 498 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 499 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 500 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 501 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 502 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* Set FMC_NAND device timing parameters */
bogdanm 0:9b334a45a8ff 505 tmppmem = (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 506 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 507 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 508 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 509 );
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 514 Device->PMEM2 = tmppmem;
bogdanm 0:9b334a45a8ff 515 }
bogdanm 0:9b334a45a8ff 516 else
bogdanm 0:9b334a45a8ff 517 {
bogdanm 0:9b334a45a8ff 518 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 519 Device->PMEM3 = tmppmem;
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 return HAL_OK;
bogdanm 0:9b334a45a8ff 523 }
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /**
bogdanm 0:9b334a45a8ff 526 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
bogdanm 0:9b334a45a8ff 527 * parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 528 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 529 * @param Timing: Pointer to NAND timing structure
bogdanm 0:9b334a45a8ff 530 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 531 * @retval HAL status
bogdanm 0:9b334a45a8ff 532 */
bogdanm 0:9b334a45a8ff 533 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 534 {
bogdanm 0:9b334a45a8ff 535 uint32_t tmppatt = 0;
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /* Check the parameters */
bogdanm 0:9b334a45a8ff 538 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 539 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 540 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 541 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 542 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 543 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Set FMC_NAND device timing parameters */
bogdanm 0:9b334a45a8ff 546 tmppatt = (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 547 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 548 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 549 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 550 );
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 555 Device->PATT2 = tmppatt;
bogdanm 0:9b334a45a8ff 556 }
bogdanm 0:9b334a45a8ff 557 else
bogdanm 0:9b334a45a8ff 558 {
bogdanm 0:9b334a45a8ff 559 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 560 Device->PATT3 = tmppatt;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 return HAL_OK;
bogdanm 0:9b334a45a8ff 564 }
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /**
bogdanm 0:9b334a45a8ff 568 * @brief DeInitializes the FMC_NAND device
bogdanm 0:9b334a45a8ff 569 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 570 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 571 * @retval HAL status
bogdanm 0:9b334a45a8ff 572 */
bogdanm 0:9b334a45a8ff 573 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 /* Check the parameters */
bogdanm 0:9b334a45a8ff 576 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 577 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Disable the NAND Bank */
bogdanm 0:9b334a45a8ff 580 __FMC_NAND_DISABLE(Device, Bank);
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 /* De-initialize the NAND Bank */
bogdanm 0:9b334a45a8ff 583 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 584 {
bogdanm 0:9b334a45a8ff 585 /* Set the FMC_NAND_BANK2 registers to their reset values */
bogdanm 0:9b334a45a8ff 586 Device->PCR2 = 0x00000018;
bogdanm 0:9b334a45a8ff 587 Device->SR2 = 0x00000040;
bogdanm 0:9b334a45a8ff 588 Device->PMEM2 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 589 Device->PATT2 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591 /* FMC_Bank3_NAND */
bogdanm 0:9b334a45a8ff 592 else
bogdanm 0:9b334a45a8ff 593 {
bogdanm 0:9b334a45a8ff 594 /* Set the FMC_NAND_BANK3 registers to their reset values */
bogdanm 0:9b334a45a8ff 595 Device->PCR3 = 0x00000018;
bogdanm 0:9b334a45a8ff 596 Device->SR3 = 0x00000040;
bogdanm 0:9b334a45a8ff 597 Device->PMEM3 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 598 Device->PATT3 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 599 }
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 return HAL_OK;
bogdanm 0:9b334a45a8ff 602 }
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 /**
bogdanm 0:9b334a45a8ff 605 * @}
bogdanm 0:9b334a45a8ff 606 */
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 /** @defgroup FMC_NAND_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 610 * @brief management functions
bogdanm 0:9b334a45a8ff 611 *
bogdanm 0:9b334a45a8ff 612 @verbatim
bogdanm 0:9b334a45a8ff 613 ==============================================================================
bogdanm 0:9b334a45a8ff 614 ##### FMC_NAND Control functions #####
bogdanm 0:9b334a45a8ff 615 ==============================================================================
bogdanm 0:9b334a45a8ff 616 [..]
bogdanm 0:9b334a45a8ff 617 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 618 the FMC NAND interface.
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 @endverbatim
bogdanm 0:9b334a45a8ff 621 * @{
bogdanm 0:9b334a45a8ff 622 */
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624
bogdanm 0:9b334a45a8ff 625 /**
bogdanm 0:9b334a45a8ff 626 * @brief Enables dynamically FMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 627 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 628 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 629 * @retval HAL status
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 632 {
bogdanm 0:9b334a45a8ff 633 /* Check the parameters */
bogdanm 0:9b334a45a8ff 634 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 635 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Enable ECC feature */
bogdanm 0:9b334a45a8ff 638 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 Device->PCR2 |= FMC_PCR2_ECCEN;
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642 else
bogdanm 0:9b334a45a8ff 643 {
bogdanm 0:9b334a45a8ff 644 Device->PCR3 |= FMC_PCR3_ECCEN;
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 return HAL_OK;
bogdanm 0:9b334a45a8ff 648 }
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /**
bogdanm 0:9b334a45a8ff 652 * @brief Disables dynamically FMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 653 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 654 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 655 * @retval HAL status
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 658 {
bogdanm 0:9b334a45a8ff 659 /* Check the parameters */
bogdanm 0:9b334a45a8ff 660 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 661 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /* Disable ECC feature */
bogdanm 0:9b334a45a8ff 664 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 665 {
bogdanm 0:9b334a45a8ff 666 Device->PCR2 &= ~FMC_PCR2_ECCEN;
bogdanm 0:9b334a45a8ff 667 }
bogdanm 0:9b334a45a8ff 668 else
bogdanm 0:9b334a45a8ff 669 {
bogdanm 0:9b334a45a8ff 670 Device->PCR3 &= ~FMC_PCR3_ECCEN;
bogdanm 0:9b334a45a8ff 671 }
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 return HAL_OK;
bogdanm 0:9b334a45a8ff 674 }
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /**
bogdanm 0:9b334a45a8ff 677 * @brief Disables dynamically FMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 678 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 679 * @param ECCval: Pointer to ECC value
bogdanm 0:9b334a45a8ff 680 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 681 * @param Timeout: Timeout wait value
bogdanm 0:9b334a45a8ff 682 * @retval HAL status
bogdanm 0:9b334a45a8ff 683 */
bogdanm 0:9b334a45a8ff 684 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 685 {
bogdanm 0:9b334a45a8ff 686 uint32_t timeout = 0;
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /* Check the parameters */
bogdanm 0:9b334a45a8ff 689 assert_param(IS_FMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 690 assert_param(IS_FMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 timeout = HAL_GetTick() + Timeout;
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 /* Wait untill FIFO is empty */
bogdanm 0:9b334a45a8ff 695 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
bogdanm 0:9b334a45a8ff 696 {
bogdanm 0:9b334a45a8ff 697 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 698 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 if(HAL_GetTick() >= timeout)
bogdanm 0:9b334a45a8ff 701 {
bogdanm 0:9b334a45a8ff 702 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 703 }
bogdanm 0:9b334a45a8ff 704 }
bogdanm 0:9b334a45a8ff 705 }
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 if(Bank == FMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 708 {
bogdanm 0:9b334a45a8ff 709 /* Get the ECCR2 register value */
bogdanm 0:9b334a45a8ff 710 *ECCval = (uint32_t)Device->ECCR2;
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712 else
bogdanm 0:9b334a45a8ff 713 {
bogdanm 0:9b334a45a8ff 714 /* Get the ECCR3 register value */
bogdanm 0:9b334a45a8ff 715 *ECCval = (uint32_t)Device->ECCR3;
bogdanm 0:9b334a45a8ff 716 }
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 return HAL_OK;
bogdanm 0:9b334a45a8ff 719 }
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /**
bogdanm 0:9b334a45a8ff 722 * @}
bogdanm 0:9b334a45a8ff 723 */
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /**
bogdanm 0:9b334a45a8ff 726 * @}
bogdanm 0:9b334a45a8ff 727 */
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 /** @defgroup FMC_PCCARD Controller functions
bogdanm 0:9b334a45a8ff 730 * @brief PCCARD Controller functions
bogdanm 0:9b334a45a8ff 731 *
bogdanm 0:9b334a45a8ff 732 @verbatim
bogdanm 0:9b334a45a8ff 733 ==============================================================================
bogdanm 0:9b334a45a8ff 734 ##### How to use PCCARD device driver #####
bogdanm 0:9b334a45a8ff 735 ==============================================================================
bogdanm 0:9b334a45a8ff 736 [..]
bogdanm 0:9b334a45a8ff 737 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
bogdanm 0:9b334a45a8ff 738 to run the PCCARD/compact flash external devices.
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
bogdanm 0:9b334a45a8ff 741 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
bogdanm 0:9b334a45a8ff 742 (+) FMC PCCARD bank common space timing configuration using the function
bogdanm 0:9b334a45a8ff 743 FMC_PCCARD_CommonSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 744 (+) FMC PCCARD bank attribute space timing configuration using the function
bogdanm 0:9b334a45a8ff 745 FMC_PCCARD_AttributeSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 746 (+) FMC PCCARD bank IO space timing configuration using the function
bogdanm 0:9b334a45a8ff 747 FMC_PCCARD_IOSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 @endverbatim
bogdanm 0:9b334a45a8ff 751 * @{
bogdanm 0:9b334a45a8ff 752 */
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 755 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 756 *
bogdanm 0:9b334a45a8ff 757 @verbatim
bogdanm 0:9b334a45a8ff 758 ==============================================================================
bogdanm 0:9b334a45a8ff 759 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 760 ==============================================================================
bogdanm 0:9b334a45a8ff 761 [..]
bogdanm 0:9b334a45a8ff 762 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 763 (+) Initialize and configure the FMC PCCARD interface
bogdanm 0:9b334a45a8ff 764 (+) De-initialize the FMC PCCARD interface
bogdanm 0:9b334a45a8ff 765 (+) Configure the FMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 @endverbatim
bogdanm 0:9b334a45a8ff 768 * @{
bogdanm 0:9b334a45a8ff 769 */
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /**
bogdanm 0:9b334a45a8ff 772 * @brief Initializes the FMC_PCCARD device according to the specified
bogdanm 0:9b334a45a8ff 773 * control parameters in the FMC_PCCARD_HandleTypeDef
bogdanm 0:9b334a45a8ff 774 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 775 * @param Init: Pointer to PCCARD Initialization structure
bogdanm 0:9b334a45a8ff 776 * @retval HAL status
bogdanm 0:9b334a45a8ff 777 */
bogdanm 0:9b334a45a8ff 778 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 /* Check the parameters */
bogdanm 0:9b334a45a8ff 781 assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm 0:9b334a45a8ff 782 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm 0:9b334a45a8ff 783 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm 0:9b334a45a8ff 784 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /* Set FMC_PCCARD device control parameters */
bogdanm 0:9b334a45a8ff 787 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
bogdanm 0:9b334a45a8ff 788 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
bogdanm 0:9b334a45a8ff 789 (Init->TCLRSetupTime << 9) |\
bogdanm 0:9b334a45a8ff 790 (Init->TARSetupTime << 13));
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 return HAL_OK;
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /**
bogdanm 0:9b334a45a8ff 797 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
bogdanm 0:9b334a45a8ff 798 * parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 799 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 800 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 801 * @retval HAL status
bogdanm 0:9b334a45a8ff 802 */
bogdanm 0:9b334a45a8ff 803 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 804 {
bogdanm 0:9b334a45a8ff 805 /* Check the parameters */
bogdanm 0:9b334a45a8ff 806 assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm 0:9b334a45a8ff 807 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 808 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 809 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 810 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 /* Set PCCARD timing parameters */
bogdanm 0:9b334a45a8ff 813 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 814 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 815 (Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 816 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 817 );
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 return HAL_OK;
bogdanm 0:9b334a45a8ff 820 }
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /**
bogdanm 0:9b334a45a8ff 823 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
bogdanm 0:9b334a45a8ff 824 * parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 825 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 826 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 827 * @retval HAL status
bogdanm 0:9b334a45a8ff 828 */
bogdanm 0:9b334a45a8ff 829 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 830 {
bogdanm 0:9b334a45a8ff 831 /* Check the parameters */
bogdanm 0:9b334a45a8ff 832 assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm 0:9b334a45a8ff 833 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 834 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 835 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 836 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /* Set PCCARD timing parameters */
bogdanm 0:9b334a45a8ff 839 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 840 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 841 (Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 842 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 843 );
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 return HAL_OK;
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847
bogdanm 0:9b334a45a8ff 848 /**
bogdanm 0:9b334a45a8ff 849 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
bogdanm 0:9b334a45a8ff 850 * parameters in the FMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 851 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 852 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 853 * @retval HAL status
bogdanm 0:9b334a45a8ff 854 */
bogdanm 0:9b334a45a8ff 855 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 856 {
bogdanm 0:9b334a45a8ff 857 /* Check the parameters */
bogdanm 0:9b334a45a8ff 858 assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm 0:9b334a45a8ff 859 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 860 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 861 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 862 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Set FMC_PCCARD device timing parameters */
bogdanm 0:9b334a45a8ff 865 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 866 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 867 (Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 868 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 869 );
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 return HAL_OK;
bogdanm 0:9b334a45a8ff 872 }
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /**
bogdanm 0:9b334a45a8ff 875 * @brief DeInitializes the FMC_PCCARD device
bogdanm 0:9b334a45a8ff 876 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 877 * @retval HAL status
bogdanm 0:9b334a45a8ff 878 */
bogdanm 0:9b334a45a8ff 879 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
bogdanm 0:9b334a45a8ff 880 {
bogdanm 0:9b334a45a8ff 881 /* Check the parameters */
bogdanm 0:9b334a45a8ff 882 assert_param(IS_FMC_PCCARD_DEVICE(Device));
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 /* Disable the FMC_PCCARD device */
bogdanm 0:9b334a45a8ff 885 __FMC_PCCARD_DISABLE(Device);
bogdanm 0:9b334a45a8ff 886
bogdanm 0:9b334a45a8ff 887 /* De-initialize the FMC_PCCARD device */
bogdanm 0:9b334a45a8ff 888 Device->PCR4 = 0x00000018;
bogdanm 0:9b334a45a8ff 889 Device->SR4 = 0x00000000;
bogdanm 0:9b334a45a8ff 890 Device->PMEM4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 891 Device->PATT4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 892 Device->PIO4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 return HAL_OK;
bogdanm 0:9b334a45a8ff 895 }
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /**
bogdanm 0:9b334a45a8ff 898 * @}
bogdanm 0:9b334a45a8ff 899 */
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /**
bogdanm 0:9b334a45a8ff 902 * @}
bogdanm 0:9b334a45a8ff 903 */
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /**
bogdanm 0:9b334a45a8ff 906 * @}
bogdanm 0:9b334a45a8ff 907 */
bogdanm 0:9b334a45a8ff 908 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 #endif /* HAL_FMC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 /**
bogdanm 0:9b334a45a8ff 913 * @}
bogdanm 0:9b334a45a8ff 914 */
bogdanm 0:9b334a45a8ff 915
bogdanm 0:9b334a45a8ff 916 /**
bogdanm 0:9b334a45a8ff 917 * @}
bogdanm 0:9b334a45a8ff 918 */
bogdanm 0:9b334a45a8ff 919
bogdanm 0:9b334a45a8ff 920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/