mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_tim_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer Extended peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Hall Sensor Interface Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Hall Sensor Interface Start
bogdanm	0:9b334a45a8ff	12	* + Time Complementary signal bread and dead time configuration
bogdanm	0:9b334a45a8ff	13	* + Time Master and Slave synchronization configuration
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
bogdanm	0:9b334a45a8ff	15	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	16	* + Timer remapping capabilities configuration
bogdanm	0:9b334a45a8ff	17	@verbatim
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	##### TIMER Extended features #####
bogdanm	0:9b334a45a8ff	20	==============================================================================
bogdanm	0:9b334a45a8ff	21	[..]
bogdanm	0:9b334a45a8ff	22	The Timer Extended features include:
bogdanm	0:9b334a45a8ff	23	(#) Complementary outputs with programmable dead-time for :
bogdanm	0:9b334a45a8ff	24	(++) Output Compare
bogdanm	0:9b334a45a8ff	25	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	26	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	27	(#) Synchronization circuit to control the timer with external signals and to
bogdanm	0:9b334a45a8ff	28	interconnect several timers together.
bogdanm	0:9b334a45a8ff	29	(#) Break input to put the timer output signals in reset state or in a known state.
bogdanm	0:9b334a45a8ff	30	(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
bogdanm	0:9b334a45a8ff	31	positioning purposes
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	34	==============================================================================
bogdanm	0:9b334a45a8ff	35	[..]
bogdanm	0:9b334a45a8ff	36	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	37	depending from feature used :
bogdanm	0:9b334a45a8ff	38	(++) Complementary Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	39	(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	40	(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	41	(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	44	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	45	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	46	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	47	__GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	48	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	51	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	52	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	53	any start function.
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	56	initialization function of this driver:
bogdanm	0:9b334a45a8ff	57	(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
bogdanm	0:9b334a45a8ff	58	Timer Hall Sensor Interface and the commutation event with the corresponding
bogdanm	0:9b334a45a8ff	59	Interrupt and DMA request if needed (Note that One Timer is used to interface
bogdanm	0:9b334a45a8ff	60	with the Hall sensor Interface and another Timer should be used to use
bogdanm	0:9b334a45a8ff	61	the commutation event).
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	(#) Activate the TIM peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	64	(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
bogdanm	0:9b334a45a8ff	65	(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
bogdanm	0:9b334a45a8ff	66	(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
bogdanm	0:9b334a45a8ff	67	(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	@endverbatim
bogdanm	0:9b334a45a8ff	71	******************************************************************************
bogdanm	0:9b334a45a8ff	72	* @attention
bogdanm	0:9b334a45a8ff	73	*
bogdanm	0:9b334a45a8ff	74	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	75	*
bogdanm	0:9b334a45a8ff	76	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	77	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	78	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	79	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	80	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	81	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	82	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	83	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	84	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	85	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	86	*
bogdanm	0:9b334a45a8ff	87	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	88	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	89	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	90	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	91	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	92	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	93	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	94	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	95	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	96	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	97	*
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	*/
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	102	#include "stm32f3xx_hal.h"
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	105	* @{
bogdanm	0:9b334a45a8ff	106	*/
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	/** @defgroup TIMEx TIM Extended HAL module driver
bogdanm	0:9b334a45a8ff	109	* @brief TIM Extended HAL module driver
bogdanm	0:9b334a45a8ff	110	* @{
bogdanm	0:9b334a45a8ff	111	*/
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	116	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	117	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	118	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	119	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	120	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	#define BDTR_BKF_SHIFT (16)
bogdanm	0:9b334a45a8ff	123	#define BDTR_BK2F_SHIFT (20)
bogdanm	0:9b334a45a8ff	124	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	125	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	126	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	127	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	130	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	131	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	132	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	133	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	134	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	135	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	136	static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
bogdanm	0:9b334a45a8ff	137	TIM_OC_InitTypeDef *OC_Config);
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
bogdanm	0:9b334a45a8ff	140	TIM_OC_InitTypeDef *OC_Config);
bogdanm	0:9b334a45a8ff	141	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	142	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	143	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	144	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	149	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	150	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	151	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	152	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	153	/**
bogdanm	0:9b334a45a8ff	154	* @brief Timer Ouput Compare 5 configuration
bogdanm	0:9b334a45a8ff	155	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	156	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	157	* @retval None
bogdanm	0:9b334a45a8ff	158	*/
bogdanm	0:9b334a45a8ff	159	static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
bogdanm	0:9b334a45a8ff	160	TIM_OC_InitTypeDef *OC_Config)
bogdanm	0:9b334a45a8ff	161	{
bogdanm	0:9b334a45a8ff	162	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	163	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	164	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/* Disable the output: Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	167	TIMx->CCER &= ~TIM_CCER_CC5E;
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	170	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	171	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	172	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	173	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	174	tmpccmrx = TIMx->CCMR3;
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	177	tmpccmrx &= ~(TIM_CCMR3_OC5M);
bogdanm	0:9b334a45a8ff	178	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	179	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	182	tmpccer &= ~TIM_CCER_CC5P;
bogdanm	0:9b334a45a8ff	183	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	184	tmpccer \|= (OC_Config->OCPolarity << 16);
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	187	{
bogdanm	0:9b334a45a8ff	188	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	189	tmpcr2 &= ~TIM_CR2_OIS5;
bogdanm	0:9b334a45a8ff	190	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	191	tmpcr2 \|= (OC_Config->OCIdleState << 8);
bogdanm	0:9b334a45a8ff	192	}
bogdanm	0:9b334a45a8ff	193	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	194	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* Write to TIMx CCMR3 */
bogdanm	0:9b334a45a8ff	197	TIMx->CCMR3 = tmpccmrx;
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	200	TIMx->CCR5 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	203	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	204	}
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/**
bogdanm	0:9b334a45a8ff	207	* @brief Timer Ouput Compare 6 configuration
bogdanm	0:9b334a45a8ff	208	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	209	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	210	* @retval None
bogdanm	0:9b334a45a8ff	211	*/
bogdanm	0:9b334a45a8ff	212	static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
bogdanm	0:9b334a45a8ff	213	TIM_OC_InitTypeDef *OC_Config)
bogdanm	0:9b334a45a8ff	214	{
bogdanm	0:9b334a45a8ff	215	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	216	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	217	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/* Disable the output: Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	220	TIMx->CCER &= ~TIM_CCER_CC6E;
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	223	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	224	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	225	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	226	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	227	tmpccmrx = TIMx->CCMR3;
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	230	tmpccmrx &= ~(TIM_CCMR3_OC6M);
bogdanm	0:9b334a45a8ff	231	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	232	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	235	tmpccer &= (uint32_t)~TIM_CCER_CC6P;
bogdanm	0:9b334a45a8ff	236	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	237	tmpccer \|= (OC_Config->OCPolarity << 20);
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	242	tmpcr2 &= ~TIM_CR2_OIS6;
bogdanm	0:9b334a45a8ff	243	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	244	tmpcr2 \|= (OC_Config->OCIdleState << 10);
bogdanm	0:9b334a45a8ff	245	}
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	248	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/* Write to TIMx CCMR3 */
bogdanm	0:9b334a45a8ff	251	TIMx->CCMR3 = tmpccmrx;
bogdanm	0:9b334a45a8ff	252
bogdanm	0:9b334a45a8ff	253	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	254	TIMx->CCR6 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	257	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	258	}
bogdanm	0:9b334a45a8ff	259	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	260	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	261	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	262	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
bogdanm	0:9b334a45a8ff	265	* @{
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	269	* @brief Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	270	*
bogdanm	0:9b334a45a8ff	271	@verbatim
bogdanm	0:9b334a45a8ff	272	==============================================================================
bogdanm	0:9b334a45a8ff	273	##### Timer Hall Sensor functions #####
bogdanm	0:9b334a45a8ff	274	==============================================================================
bogdanm	0:9b334a45a8ff	275	[..]
bogdanm	0:9b334a45a8ff	276	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	277	(+) Initialize and configure TIM HAL Sensor.
bogdanm	0:9b334a45a8ff	278	(+) De-initialize TIM HAL Sensor.
bogdanm	0:9b334a45a8ff	279	(+) Start the Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	280	(+) Stop the Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	281	(+) Start the Hall Sensor Interface and enable interrupts.
bogdanm	0:9b334a45a8ff	282	(+) Stop the Hall Sensor Interface and disable interrupts.
bogdanm	0:9b334a45a8ff	283	(+) Start the Hall Sensor Interface and enable DMA transfers.
bogdanm	0:9b334a45a8ff	284	(+) Stop the Hall Sensor Interface and disable DMA transfers.
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	@endverbatim
bogdanm	0:9b334a45a8ff	287	* @{
bogdanm	0:9b334a45a8ff	288	*/
bogdanm	0:9b334a45a8ff	289	/**
bogdanm	0:9b334a45a8ff	290	* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	291	* @param htim: TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	292	* @param sConfig: TIM Hall Sensor configuration structure
bogdanm	0:9b334a45a8ff	293	* @retval HAL status
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	296	{
bogdanm	0:9b334a45a8ff	297	TIM_OC_InitTypeDef OC_Config;
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	300	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	301	{
bogdanm	0:9b334a45a8ff	302	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	303	}
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	306	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	307	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	308	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	309	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	310	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	313	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	316	HAL_TIMEx_HallSensor_MspInit(htim);
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	319	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
bogdanm	0:9b334a45a8ff	322	TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	325	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	326	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	327	htim->Instance->CCMR1 \|= sConfig->IC1Prescaler;
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/* Enable the Hall sensor interface (XOR function of the three inputs) */
bogdanm	0:9b334a45a8ff	330	htim->Instance->CR2 \|= TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
bogdanm	0:9b334a45a8ff	333	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	334	htim->Instance->SMCR \|= TIM_TS_TI1F_ED;
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
bogdanm	0:9b334a45a8ff	337	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	338	htim->Instance->SMCR \|= TIM_SLAVEMODE_RESET;
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
bogdanm	0:9b334a45a8ff	341	OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
bogdanm	0:9b334a45a8ff	342	OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
bogdanm	0:9b334a45a8ff	343	OC_Config.OCMode = TIM_OCMODE_PWM2;
bogdanm	0:9b334a45a8ff	344	OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
bogdanm	0:9b334a45a8ff	345	OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
bogdanm	0:9b334a45a8ff	346	OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
bogdanm	0:9b334a45a8ff	347	OC_Config.Pulse = sConfig->Commutation_Delay;
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	TIM_OC2_SetConfig(htim->Instance, &OC_Config);
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
bogdanm	0:9b334a45a8ff	352	register to 101 */
bogdanm	0:9b334a45a8ff	353	htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm	0:9b334a45a8ff	354	htim->Instance->CR2 \|= TIM_TRGO_OC2REF;
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	357	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	return HAL_OK;
bogdanm	0:9b334a45a8ff	360	}
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/**
bogdanm	0:9b334a45a8ff	363	* @brief DeInitializes the TIM Hall Sensor interface
bogdanm	0:9b334a45a8ff	364	* @param htim: TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	365	* @retval HAL status
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	368	{
bogdanm	0:9b334a45a8ff	369	/* Check the parameters */
bogdanm	0:9b334a45a8ff	370	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	371
bogdanm	0:9b334a45a8ff	372	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	375	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	378	HAL_TIMEx_HallSensor_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/* Change TIM state */
bogdanm	0:9b334a45a8ff	381	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/* Release Lock */
bogdanm	0:9b334a45a8ff	384	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386	return HAL_OK;
bogdanm	0:9b334a45a8ff	387	}
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/**
bogdanm	0:9b334a45a8ff	390	* @brief Initializes the TIM Hall Sensor MSP.
bogdanm	0:9b334a45a8ff	391	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	392	* @retval None
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394	__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	397	the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	398	*/
bogdanm	0:9b334a45a8ff	399	}
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	/**
bogdanm	0:9b334a45a8ff	402	* @brief DeInitializes TIM Hall Sensor MSP.
bogdanm	0:9b334a45a8ff	403	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	404	* @retval None
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406	__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	409	the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	410	*/
bogdanm	0:9b334a45a8ff	411	}
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	/**
bogdanm	0:9b334a45a8ff	414	* @brief Starts the TIM Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	415	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	416	* @retval HAL status
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	419	{
bogdanm	0:9b334a45a8ff	420	/* Check the parameters */
bogdanm	0:9b334a45a8ff	421	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Enable the Input Capture channels 1
bogdanm	0:9b334a45a8ff	424	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	425	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	428	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Return function status */
bogdanm	0:9b334a45a8ff	431	return HAL_OK;
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	/**
bogdanm	0:9b334a45a8ff	435	* @brief Stops the TIM Hall sensor Interface.
bogdanm	0:9b334a45a8ff	436	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	437	* @retval HAL status
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	440	{
bogdanm	0:9b334a45a8ff	441	/* Check the parameters */
bogdanm	0:9b334a45a8ff	442	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/* Disable the Input Capture channels 1, 2 and 3
bogdanm	0:9b334a45a8ff	445	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	446	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	449	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/* Return function status */
bogdanm	0:9b334a45a8ff	452	return HAL_OK;
bogdanm	0:9b334a45a8ff	453	}
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	/**
bogdanm	0:9b334a45a8ff	456	* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	457	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	458	* @retval HAL status
bogdanm	0:9b334a45a8ff	459	*/
bogdanm	0:9b334a45a8ff	460	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	461	{
bogdanm	0:9b334a45a8ff	462	/* Check the parameters */
bogdanm	0:9b334a45a8ff	463	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/* Enable the capture compare Interrupts 1 event */
bogdanm	0:9b334a45a8ff	466	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/* Enable the Input Capture channels 1
bogdanm	0:9b334a45a8ff	469	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	470	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	473	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/* Return function status */
bogdanm	0:9b334a45a8ff	476	return HAL_OK;
bogdanm	0:9b334a45a8ff	477	}
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/**
bogdanm	0:9b334a45a8ff	480	* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	481	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	482	* @retval HAL status
bogdanm	0:9b334a45a8ff	483	*/
bogdanm	0:9b334a45a8ff	484	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	/* Check the parameters */
bogdanm	0:9b334a45a8ff	487	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/* Disable the Input Capture channels 1
bogdanm	0:9b334a45a8ff	490	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	491	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/* Disable the capture compare Interrupts event */
bogdanm	0:9b334a45a8ff	494	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	497	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/* Return function status */
bogdanm	0:9b334a45a8ff	500	return HAL_OK;
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/**
bogdanm	0:9b334a45a8ff	504	* @brief Starts the TIM Hall Sensor Interface in DMA mode.
bogdanm	0:9b334a45a8ff	505	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	506	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	507	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	508	* @retval HAL status
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	511	{
bogdanm	0:9b334a45a8ff	512	/* Check the parameters */
bogdanm	0:9b334a45a8ff	513	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	518	}
bogdanm	0:9b334a45a8ff	519	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	522	{
bogdanm	0:9b334a45a8ff	523	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	524	}
bogdanm	0:9b334a45a8ff	525	else
bogdanm	0:9b334a45a8ff	526	{
bogdanm	0:9b334a45a8ff	527	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	528	}
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530	/* Enable the Input Capture channels 1
bogdanm	0:9b334a45a8ff	531	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	532	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/* Set the DMA Input Capture 1 Callback */
bogdanm	0:9b334a45a8ff	535	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	536	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	537	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/* Enable the DMA channel for Capture 1*/
bogdanm	0:9b334a45a8ff	540	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/* Enable the capture compare 1 Interrupt */
bogdanm	0:9b334a45a8ff	543	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	546	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/* Return function status */
bogdanm	0:9b334a45a8ff	549	return HAL_OK;
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/**
bogdanm	0:9b334a45a8ff	553	* @brief Stops the TIM Hall Sensor Interface in DMA mode.
bogdanm	0:9b334a45a8ff	554	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	555	* @retval HAL status
bogdanm	0:9b334a45a8ff	556	*/
bogdanm	0:9b334a45a8ff	557	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	/* Check the parameters */
bogdanm	0:9b334a45a8ff	560	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	/* Disable the Input Capture channels 1
bogdanm	0:9b334a45a8ff	563	(in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	564	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Disable the capture compare Interrupts 1 event */
bogdanm	0:9b334a45a8ff	568	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	571	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/* Return function status */
bogdanm	0:9b334a45a8ff	574	return HAL_OK;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @}
bogdanm	0:9b334a45a8ff	579	*/
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	582	* @brief Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	583	*
bogdanm	0:9b334a45a8ff	584	@verbatim
bogdanm	0:9b334a45a8ff	585	==============================================================================
bogdanm	0:9b334a45a8ff	586	##### Timer Complementary Output Compare functions #####
bogdanm	0:9b334a45a8ff	587	==============================================================================
bogdanm	0:9b334a45a8ff	588	[..]
bogdanm	0:9b334a45a8ff	589	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	590	(+) Start the Complementary Output Compare/PWM.
bogdanm	0:9b334a45a8ff	591	(+) Stop the Complementary Output Compare/PWM.
bogdanm	0:9b334a45a8ff	592	(+) Start the Complementary Output Compare/PWM and enable interrupts.
bogdanm	0:9b334a45a8ff	593	(+) Stop the Complementary Output Compare/PWM and disable interrupts.
bogdanm	0:9b334a45a8ff	594	(+) Start the Complementary Output Compare/PWM and enable DMA transfers.
bogdanm	0:9b334a45a8ff	595	(+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	@endverbatim
bogdanm	0:9b334a45a8ff	598	* @{
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/**
bogdanm	0:9b334a45a8ff	602	* @brief Starts the TIM Output Compare signal generation on the complementary
bogdanm	0:9b334a45a8ff	603	* output.
bogdanm	0:9b334a45a8ff	604	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	605	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	606	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	607	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	608	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	609	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	610	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	611	* @retval HAL status
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* Check the parameters */
bogdanm	0:9b334a45a8ff	616	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	619	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	622	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	625	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Return function status */
bogdanm	0:9b334a45a8ff	628	return HAL_OK;
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/**
bogdanm	0:9b334a45a8ff	632	* @brief Stops the TIM Output Compare signal generation on the complementary
bogdanm	0:9b334a45a8ff	633	* output.
bogdanm	0:9b334a45a8ff	634	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	635	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	636	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	637	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	638	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	639	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	640	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	641	* @retval HAL status
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	/* Check the parameters */
bogdanm	0:9b334a45a8ff	646	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	649	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	652	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	653
bogdanm	0:9b334a45a8ff	654	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	655	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/* Return function status */
bogdanm	0:9b334a45a8ff	658	return HAL_OK;
bogdanm	0:9b334a45a8ff	659	}
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/**
bogdanm	0:9b334a45a8ff	662	* @brief Starts the TIM Output Compare signal generation in interrupt mode
bogdanm	0:9b334a45a8ff	663	* on the complementary output.
bogdanm	0:9b334a45a8ff	664	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	665	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	666	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	667	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	668	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	669	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	670	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	671	* @retval HAL status
bogdanm	0:9b334a45a8ff	672	*/
bogdanm	0:9b334a45a8ff	673	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	674	{
bogdanm	0:9b334a45a8ff	675	/* Check the parameters */
bogdanm	0:9b334a45a8ff	676	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	switch (Channel)
bogdanm	0:9b334a45a8ff	679	{
bogdanm	0:9b334a45a8ff	680	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	681	{
bogdanm	0:9b334a45a8ff	682	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	683	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	684	}
bogdanm	0:9b334a45a8ff	685	break;
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	690	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	691	}
bogdanm	0:9b334a45a8ff	692	break;
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	695	{
bogdanm	0:9b334a45a8ff	696	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	697	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699	break;
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	702	{
bogdanm	0:9b334a45a8ff	703	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	704	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	705	}
bogdanm	0:9b334a45a8ff	706	break;
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	default:
bogdanm	0:9b334a45a8ff	709	break;
bogdanm	0:9b334a45a8ff	710	}
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	/* Enable the TIM Break interrupt */
bogdanm	0:9b334a45a8ff	713	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	716	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	719	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	722	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* Return function status */
bogdanm	0:9b334a45a8ff	725	return HAL_OK;
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/**
bogdanm	0:9b334a45a8ff	729	* @brief Stops the TIM Output Compare signal generation in interrupt mode
bogdanm	0:9b334a45a8ff	730	* on the complementary output.
bogdanm	0:9b334a45a8ff	731	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	732	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	733	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	734	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	735	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	736	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	737	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	738	* @retval HAL status
bogdanm	0:9b334a45a8ff	739	*/
bogdanm	0:9b334a45a8ff	740	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/* Check the parameters */
bogdanm	0:9b334a45a8ff	745	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	switch (Channel)
bogdanm	0:9b334a45a8ff	748	{
bogdanm	0:9b334a45a8ff	749	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	750	{
bogdanm	0:9b334a45a8ff	751	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	752	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754	break;
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	759	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	760	}
bogdanm	0:9b334a45a8ff	761	break;
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	764	{
bogdanm	0:9b334a45a8ff	765	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	766	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	767	}
bogdanm	0:9b334a45a8ff	768	break;
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	773	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775	break;
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	default:
bogdanm	0:9b334a45a8ff	778	break;
bogdanm	0:9b334a45a8ff	779	}
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	782	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm	0:9b334a45a8ff	785	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	786	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
bogdanm	0:9b334a45a8ff	787	{
bogdanm	0:9b334a45a8ff	788	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	789	}
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	792	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	795	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* Return function status */
bogdanm	0:9b334a45a8ff	798	return HAL_OK;
bogdanm	0:9b334a45a8ff	799	}
bogdanm	0:9b334a45a8ff	800
bogdanm	0:9b334a45a8ff	801	/**
bogdanm	0:9b334a45a8ff	802	* @brief Starts the TIM Output Compare signal generation in DMA mode
bogdanm	0:9b334a45a8ff	803	* on the complementary output.
bogdanm	0:9b334a45a8ff	804	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	805	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	806	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	807	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	808	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	809	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	810	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	811	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	812	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	813	* @retval HAL status
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	816	{
bogdanm	0:9b334a45a8ff	817	/* Check the parameters */
bogdanm	0:9b334a45a8ff	818	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	823	}
bogdanm	0:9b334a45a8ff	824	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	825	{
bogdanm	0:9b334a45a8ff	826	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	827	{
bogdanm	0:9b334a45a8ff	828	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	829	}
bogdanm	0:9b334a45a8ff	830	else
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	switch (Channel)
bogdanm	0:9b334a45a8ff	836	{
bogdanm	0:9b334a45a8ff	837	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	840	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	843	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	846	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	849	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851	break;
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	854	{
bogdanm	0:9b334a45a8ff	855	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	856	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	859	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	862	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	865	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	866	}
bogdanm	0:9b334a45a8ff	867	break;
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	870	{
bogdanm	0:9b334a45a8ff	871	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	872	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	875	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	878	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	881	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	882	}
bogdanm	0:9b334a45a8ff	883	break;
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	886	{
bogdanm	0:9b334a45a8ff	887	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	888	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	891	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	894	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	897	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899	break;
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	default:
bogdanm	0:9b334a45a8ff	902	break;
bogdanm	0:9b334a45a8ff	903	}
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	906	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	909	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	912	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	/* Return function status */
bogdanm	0:9b334a45a8ff	915	return HAL_OK;
bogdanm	0:9b334a45a8ff	916	}
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/**
bogdanm	0:9b334a45a8ff	919	* @brief Stops the TIM Output Compare signal generation in DMA mode
bogdanm	0:9b334a45a8ff	920	* on the complementary output.
bogdanm	0:9b334a45a8ff	921	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	922	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	923	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	924	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	925	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	926	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	927	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	928	* @retval HAL status
bogdanm	0:9b334a45a8ff	929	*/
bogdanm	0:9b334a45a8ff	930	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	/* Check the parameters */
bogdanm	0:9b334a45a8ff	933	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	switch (Channel)
bogdanm	0:9b334a45a8ff	936	{
bogdanm	0:9b334a45a8ff	937	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	938	{
bogdanm	0:9b334a45a8ff	939	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	940	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	941	}
bogdanm	0:9b334a45a8ff	942	break;
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	945	{
bogdanm	0:9b334a45a8ff	946	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	947	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	948	}
bogdanm	0:9b334a45a8ff	949	break;
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	954	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	955	}
bogdanm	0:9b334a45a8ff	956	break;
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	959	{
bogdanm	0:9b334a45a8ff	960	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	961	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	962	}
bogdanm	0:9b334a45a8ff	963	break;
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	default:
bogdanm	0:9b334a45a8ff	966	break;
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	970	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	973	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	976	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Change the htim state */
bogdanm	0:9b334a45a8ff	979	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/* Return function status */
bogdanm	0:9b334a45a8ff	982	return HAL_OK;
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/**
bogdanm	0:9b334a45a8ff	986	* @}
bogdanm	0:9b334a45a8ff	987	*/
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	990	* @brief Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	991	*
bogdanm	0:9b334a45a8ff	992	@verbatim
bogdanm	0:9b334a45a8ff	993	==============================================================================
bogdanm	0:9b334a45a8ff	994	##### Timer Complementary PWM functions #####
bogdanm	0:9b334a45a8ff	995	==============================================================================
bogdanm	0:9b334a45a8ff	996	[..]
bogdanm	0:9b334a45a8ff	997	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	998	(+) Start the Complementary PWM.
bogdanm	0:9b334a45a8ff	999	(+) Stop the Complementary PWM.
bogdanm	0:9b334a45a8ff	1000	(+) Start the Complementary PWM and enable interrupts.
bogdanm	0:9b334a45a8ff	1001	(+) Stop the Complementary PWM and disable interrupts.
bogdanm	0:9b334a45a8ff	1002	(+) Start the Complementary PWM and enable DMA transfers.
bogdanm	0:9b334a45a8ff	1003	(+) Stop the Complementary PWM and disable DMA transfers.
bogdanm	0:9b334a45a8ff	1004	(+) Start the Complementary Input Capture measurement.
bogdanm	0:9b334a45a8ff	1005	(+) Stop the Complementary Input Capture.
bogdanm	0:9b334a45a8ff	1006	(+) Start the Complementary Input Capture and enable interrupts.
bogdanm	0:9b334a45a8ff	1007	(+) Stop the Complementary Input Capture and disable interrupts.
bogdanm	0:9b334a45a8ff	1008	(+) Start the Complementary Input Capture and enable DMA transfers.
bogdanm	0:9b334a45a8ff	1009	(+) Stop the Complementary Input Capture and disable DMA transfers.
bogdanm	0:9b334a45a8ff	1010	(+) Start the Complementary One Pulse generation.
bogdanm	0:9b334a45a8ff	1011	(+) Stop the Complementary One Pulse.
bogdanm	0:9b334a45a8ff	1012	(+) Start the Complementary One Pulse and enable interrupts.
bogdanm	0:9b334a45a8ff	1013	(+) Stop the Complementary One Pulse and disable interrupts.
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	@endverbatim
bogdanm	0:9b334a45a8ff	1016	* @{
bogdanm	0:9b334a45a8ff	1017	*/
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	/**
bogdanm	0:9b334a45a8ff	1020	* @brief Starts the PWM signal generation on the complementary output.
bogdanm	0:9b334a45a8ff	1021	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1022	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1023	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1024	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1025	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1026	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1027	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1028	* @retval HAL status
bogdanm	0:9b334a45a8ff	1029	*/
bogdanm	0:9b334a45a8ff	1030	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1031	{
bogdanm	0:9b334a45a8ff	1032	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1033	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1036	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1039	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1042	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/* Return function status */
bogdanm	0:9b334a45a8ff	1045	return HAL_OK;
bogdanm	0:9b334a45a8ff	1046	}
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/**
bogdanm	0:9b334a45a8ff	1049	* @brief Stops the PWM signal generation on the complementary output.
bogdanm	0:9b334a45a8ff	1050	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1051	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1052	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1053	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1054	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1055	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1056	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1057	* @retval HAL status
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1062	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1065	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1068	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1071	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Return function status */
bogdanm	0:9b334a45a8ff	1074	return HAL_OK;
bogdanm	0:9b334a45a8ff	1075	}
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/**
bogdanm	0:9b334a45a8ff	1078	* @brief Starts the PWM signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1079	* complementary output.
bogdanm	0:9b334a45a8ff	1080	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1081	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1082	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1083	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1084	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1085	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1086	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1087	* @retval HAL status
bogdanm	0:9b334a45a8ff	1088	*/
bogdanm	0:9b334a45a8ff	1089	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1090	{
bogdanm	0:9b334a45a8ff	1091	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1092	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	switch (Channel)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1097	{
bogdanm	0:9b334a45a8ff	1098	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1099	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1100	}
bogdanm	0:9b334a45a8ff	1101	break;
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1104	{
bogdanm	0:9b334a45a8ff	1105	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1106	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1107	}
bogdanm	0:9b334a45a8ff	1108	break;
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1111	{
bogdanm	0:9b334a45a8ff	1112	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1113	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1114	}
bogdanm	0:9b334a45a8ff	1115	break;
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1120	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122	break;
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	default:
bogdanm	0:9b334a45a8ff	1125	break;
bogdanm	0:9b334a45a8ff	1126	}
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/* Enable the TIM Break interrupt */
bogdanm	0:9b334a45a8ff	1129	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1132	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1135	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1138	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/* Return function status */
bogdanm	0:9b334a45a8ff	1141	return HAL_OK;
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/**
bogdanm	0:9b334a45a8ff	1145	* @brief Stops the PWM signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1146	* complementary output.
bogdanm	0:9b334a45a8ff	1147	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1148	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1149	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1150	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1151	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1152	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1153	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1154	* @retval HAL status
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1157	{
bogdanm	0:9b334a45a8ff	1158	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1161	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	switch (Channel)
bogdanm	0:9b334a45a8ff	1164	{
bogdanm	0:9b334a45a8ff	1165	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1168	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1169	}
bogdanm	0:9b334a45a8ff	1170	break;
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1173	{
bogdanm	0:9b334a45a8ff	1174	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1175	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1176	}
bogdanm	0:9b334a45a8ff	1177	break;
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1180	{
bogdanm	0:9b334a45a8ff	1181	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1182	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1183	}
bogdanm	0:9b334a45a8ff	1184	break;
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1187	{
bogdanm	0:9b334a45a8ff	1188	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1189	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1190	}
bogdanm	0:9b334a45a8ff	1191	break;
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	default:
bogdanm	0:9b334a45a8ff	1194	break;
bogdanm	0:9b334a45a8ff	1195	}
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1198	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm	0:9b334a45a8ff	1201	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	1202	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
bogdanm	0:9b334a45a8ff	1203	{
bogdanm	0:9b334a45a8ff	1204	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1208	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1211	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* Return function status */
bogdanm	0:9b334a45a8ff	1214	return HAL_OK;
bogdanm	0:9b334a45a8ff	1215	}
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/**
bogdanm	0:9b334a45a8ff	1218	* @brief Starts the TIM PWM signal generation in DMA mode on the
bogdanm	0:9b334a45a8ff	1219	* complementary output
bogdanm	0:9b334a45a8ff	1220	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1221	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1222	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1223	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1224	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1225	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1226	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1227	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	1228	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1229	* @retval HAL status
bogdanm	0:9b334a45a8ff	1230	*/
bogdanm	0:9b334a45a8ff	1231	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1232	{
bogdanm	0:9b334a45a8ff	1233	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1234	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1235
bogdanm	0:9b334a45a8ff	1236	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1237	{
bogdanm	0:9b334a45a8ff	1238	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1239	}
bogdanm	0:9b334a45a8ff	1240	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1243	{
bogdanm	0:9b334a45a8ff	1244	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1245	}
bogdanm	0:9b334a45a8ff	1246	else
bogdanm	0:9b334a45a8ff	1247	{
bogdanm	0:9b334a45a8ff	1248	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1249	}
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251	switch (Channel)
bogdanm	0:9b334a45a8ff	1252	{
bogdanm	0:9b334a45a8ff	1253	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1254	{
bogdanm	0:9b334a45a8ff	1255	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1256	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1259	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1262	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1265	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1266	}
bogdanm	0:9b334a45a8ff	1267	break;
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1270	{
bogdanm	0:9b334a45a8ff	1271	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1272	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1275	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1278	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1281	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1282	}
bogdanm	0:9b334a45a8ff	1283	break;
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1286	{
bogdanm	0:9b334a45a8ff	1287	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1288	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1291	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1294	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1297	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1298	}
bogdanm	0:9b334a45a8ff	1299	break;
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1302	{
bogdanm	0:9b334a45a8ff	1303	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1304	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1307	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1310	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1313	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1314	}
bogdanm	0:9b334a45a8ff	1315	break;
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	default:
bogdanm	0:9b334a45a8ff	1318	break;
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1322	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1325	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1328	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/* Return function status */
bogdanm	0:9b334a45a8ff	1331	return HAL_OK;
bogdanm	0:9b334a45a8ff	1332	}
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/**
bogdanm	0:9b334a45a8ff	1335	* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
bogdanm	0:9b334a45a8ff	1336	* output
bogdanm	0:9b334a45a8ff	1337	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1338	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1339	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1340	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1341	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1342	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1343	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1344	* @retval HAL status
bogdanm	0:9b334a45a8ff	1345	*/
bogdanm	0:9b334a45a8ff	1346	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1347	{
bogdanm	0:9b334a45a8ff	1348	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1349	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	switch (Channel)
bogdanm	0:9b334a45a8ff	1352	{
bogdanm	0:9b334a45a8ff	1353	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1354	{
bogdanm	0:9b334a45a8ff	1355	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1356	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358	break;
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1361	{
bogdanm	0:9b334a45a8ff	1362	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1363	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1364	}
bogdanm	0:9b334a45a8ff	1365	break;
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1368	{
bogdanm	0:9b334a45a8ff	1369	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1370	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1371	}
bogdanm	0:9b334a45a8ff	1372	break;
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1375	{
bogdanm	0:9b334a45a8ff	1376	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1377	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379	break;
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	default:
bogdanm	0:9b334a45a8ff	1382	break;
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1386	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1389	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1390
bogdanm	0:9b334a45a8ff	1391	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1392	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1395	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/* Return function status */
bogdanm	0:9b334a45a8ff	1398	return HAL_OK;
bogdanm	0:9b334a45a8ff	1399	}
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/**
bogdanm	0:9b334a45a8ff	1402	* @}
bogdanm	0:9b334a45a8ff	1403	*/
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	1406	* @brief Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	1407	*
bogdanm	0:9b334a45a8ff	1408	@verbatim
bogdanm	0:9b334a45a8ff	1409	==============================================================================
bogdanm	0:9b334a45a8ff	1410	##### Timer Complementary One Pulse functions #####
bogdanm	0:9b334a45a8ff	1411	==============================================================================
bogdanm	0:9b334a45a8ff	1412	[..]
bogdanm	0:9b334a45a8ff	1413	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1414	(+) Start the Complementary One Pulse generation.
bogdanm	0:9b334a45a8ff	1415	(+) Stop the Complementary One Pulse.
bogdanm	0:9b334a45a8ff	1416	(+) Start the Complementary One Pulse and enable interrupts.
bogdanm	0:9b334a45a8ff	1417	(+) Stop the Complementary One Pulse and disable interrupts.
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	@endverbatim
bogdanm	0:9b334a45a8ff	1420	* @{
bogdanm	0:9b334a45a8ff	1421	*/
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	/**
bogdanm	0:9b334a45a8ff	1424	* @brief Starts the TIM One Pulse signal generation on the complemetary
bogdanm	0:9b334a45a8ff	1425	* output.
bogdanm	0:9b334a45a8ff	1426	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1427	* @param OutputChannel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1428	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1429	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1430	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1431	* @retval HAL status
bogdanm	0:9b334a45a8ff	1432	*/
bogdanm	0:9b334a45a8ff	1433	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1434	{
bogdanm	0:9b334a45a8ff	1435	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1436	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* Enable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1439	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1442	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/* Return function status */
bogdanm	0:9b334a45a8ff	1445	return HAL_OK;
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	/**
bogdanm	0:9b334a45a8ff	1449	* @brief Stops the TIM One Pulse signal generation on the complementary
bogdanm	0:9b334a45a8ff	1450	* output.
bogdanm	0:9b334a45a8ff	1451	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1452	* @param OutputChannel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1453	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1454	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1455	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1456	* @retval HAL status
bogdanm	0:9b334a45a8ff	1457	*/
bogdanm	0:9b334a45a8ff	1458	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1459	{
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1462	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* Disable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1465	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1468	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1471	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/* Return function status */
bogdanm	0:9b334a45a8ff	1474	return HAL_OK;
bogdanm	0:9b334a45a8ff	1475	}
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/**
bogdanm	0:9b334a45a8ff	1478	* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1479	* complementary channel.
bogdanm	0:9b334a45a8ff	1480	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1481	* @param OutputChannel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1482	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1483	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1484	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1485	* @retval HAL status
bogdanm	0:9b334a45a8ff	1486	*/
bogdanm	0:9b334a45a8ff	1487	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1488	{
bogdanm	0:9b334a45a8ff	1489	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1490	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1493	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1496	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/* Enable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1499	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1502	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1503
bogdanm	0:9b334a45a8ff	1504	/* Return function status */
bogdanm	0:9b334a45a8ff	1505	return HAL_OK;
bogdanm	0:9b334a45a8ff	1506	}
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/**
bogdanm	0:9b334a45a8ff	1509	* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1510	* complementary channel.
bogdanm	0:9b334a45a8ff	1511	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1512	* @param OutputChannel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1513	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1514	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1515	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1516	* @retval HAL status
bogdanm	0:9b334a45a8ff	1517	*/
bogdanm	0:9b334a45a8ff	1518	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1519	{
bogdanm	0:9b334a45a8ff	1520	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1521	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1524	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1527	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	/* Disable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1530	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1533	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1536	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Return function status */
bogdanm	0:9b334a45a8ff	1539	return HAL_OK;
bogdanm	0:9b334a45a8ff	1540	}
bogdanm	0:9b334a45a8ff	1541
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/**
bogdanm	0:9b334a45a8ff	1545	* @}
bogdanm	0:9b334a45a8ff	1546	*/
bogdanm	0:9b334a45a8ff	1547	/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1548	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1549	*
bogdanm	0:9b334a45a8ff	1550	@verbatim
bogdanm	0:9b334a45a8ff	1551	==============================================================================
bogdanm	0:9b334a45a8ff	1552	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1553	==============================================================================
bogdanm	0:9b334a45a8ff	1554	[..]
bogdanm	0:9b334a45a8ff	1555	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1556	(+) Configure the commutation event in case of use of the Hall sensor interface.
bogdanm	0:9b334a45a8ff	1557	(+) Configure Output channels for OC and PWM mode.
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	1560	(+) Configure Master synchronization.
bogdanm	0:9b334a45a8ff	1561	(+) Configure timer remapping capabilities.
bogdanm	0:9b334a45a8ff	1562	(+) Enable or disable channel grouping
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	@endverbatim
bogdanm	0:9b334a45a8ff	1565	* @{
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	1568	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	1569	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	1570	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	1571	/**
bogdanm	0:9b334a45a8ff	1572	* @brief Configure the TIM commutation event sequence.
bogdanm	0:9b334a45a8ff	1573	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1574	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1575	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1576	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1577	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1578	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1579	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1580	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1581	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1582	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1583	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1584	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1585	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1586	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1587	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1588	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1589	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1590	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1591	* @retval HAL status
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1594	{
bogdanm	0:9b334a45a8ff	1595	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1596	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1597	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1600
bogdanm	0:9b334a45a8ff	1601	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1602	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1603	{
bogdanm	0:9b334a45a8ff	1604	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1605	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1606	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1607	}
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1610	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1611	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1612	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1613	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	return HAL_OK;
bogdanm	0:9b334a45a8ff	1618	}
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	/**
bogdanm	0:9b334a45a8ff	1621	* @brief Configure the TIM commutation event sequence with interrupt.
bogdanm	0:9b334a45a8ff	1622	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1623	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1624	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1625	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1626	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1627	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1628	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1629	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1630	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1631	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1632	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1633	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1634	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1635	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1636	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1637	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1638	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1639	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1640	* @retval HAL status
bogdanm	0:9b334a45a8ff	1641	*/
bogdanm	0:9b334a45a8ff	1642	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1643	{
bogdanm	0:9b334a45a8ff	1644	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1645	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1646	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1649
bogdanm	0:9b334a45a8ff	1650	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1651	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1654	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1655	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1656	}
bogdanm	0:9b334a45a8ff	1657
bogdanm	0:9b334a45a8ff	1658	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1659	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1660	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1661	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1662	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/* Enable the Commutation Interrupt Request */
bogdanm	0:9b334a45a8ff	1665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1668
bogdanm	0:9b334a45a8ff	1669	return HAL_OK;
bogdanm	0:9b334a45a8ff	1670	}
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/**
bogdanm	0:9b334a45a8ff	1673	* @brief Configure the TIM commutation event sequence with DMA.
bogdanm	0:9b334a45a8ff	1674	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1675	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1676	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1677	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1678	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1679	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1680	* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
bogdanm	0:9b334a45a8ff	1681	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1682	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1683	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1684	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1685	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1686	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1687	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1688	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1689	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1690	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1691	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1692	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1693	* @retval HAL status
bogdanm	0:9b334a45a8ff	1694	*/
bogdanm	0:9b334a45a8ff	1695	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1696	{
bogdanm	0:9b334a45a8ff	1697	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1698	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1699	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1700
bogdanm	0:9b334a45a8ff	1701	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1704	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1707	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1708	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1709	}
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1712	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1713	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1714	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1715	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	/* Enable the Commutation DMA Request */
bogdanm	0:9b334a45a8ff	1718	/* Set the DMA Commutation Callback */
bogdanm	0:9b334a45a8ff	1719	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	1720	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1721	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	/* Enable the Commutation DMA Request */
bogdanm	0:9b334a45a8ff	1724	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	return HAL_OK;
bogdanm	0:9b334a45a8ff	1729	}
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	/**
bogdanm	0:9b334a45a8ff	1732	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	1733	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	1734	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	1735	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	1736	* @param Channel : TIM Channels to configure
bogdanm	0:9b334a45a8ff	1737	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1738	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1739	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1740	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1741	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1742	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	1743	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	1744	* @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
bogdanm	0:9b334a45a8ff	1745	* @retval HAL status
bogdanm	0:9b334a45a8ff	1746	*/
bogdanm	0:9b334a45a8ff	1747	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	1748	TIM_OC_InitTypeDef* sConfig,
bogdanm	0:9b334a45a8ff	1749	uint32_t Channel)
bogdanm	0:9b334a45a8ff	1750	{
bogdanm	0:9b334a45a8ff	1751	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1752	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	1753	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	1754	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	1755	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	1756	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	1757	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	1758
bogdanm	0:9b334a45a8ff	1759	/* Check input state */
bogdanm	0:9b334a45a8ff	1760	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	switch (Channel)
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1767	{
bogdanm	0:9b334a45a8ff	1768	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1769	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	1772	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1773	}
bogdanm	0:9b334a45a8ff	1774	break;
bogdanm	0:9b334a45a8ff	1775
bogdanm	0:9b334a45a8ff	1776	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1779	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	1782	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1783	}
bogdanm	0:9b334a45a8ff	1784	break;
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1787	{
bogdanm	0:9b334a45a8ff	1788	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1789	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	1792	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1793	}
bogdanm	0:9b334a45a8ff	1794	break;
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1797	{
bogdanm	0:9b334a45a8ff	1798	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1799	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	1802	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1803	}
bogdanm	0:9b334a45a8ff	1804	break;
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	case TIM_CHANNEL_5:
bogdanm	0:9b334a45a8ff	1807	{
bogdanm	0:9b334a45a8ff	1808	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1809	assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1810
bogdanm	0:9b334a45a8ff	1811	/* Configure the TIM Channel 5 in Output Compare */
bogdanm	0:9b334a45a8ff	1812	TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1813	}
bogdanm	0:9b334a45a8ff	1814	break;
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	case TIM_CHANNEL_6:
bogdanm	0:9b334a45a8ff	1817	{
bogdanm	0:9b334a45a8ff	1818	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1819	assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	/* Configure the TIM Channel 6 in Output Compare */
bogdanm	0:9b334a45a8ff	1822	TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1823	}
bogdanm	0:9b334a45a8ff	1824	break;
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	default:
bogdanm	0:9b334a45a8ff	1827	break;
bogdanm	0:9b334a45a8ff	1828	}
bogdanm	0:9b334a45a8ff	1829
bogdanm	0:9b334a45a8ff	1830	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	return HAL_OK;
bogdanm	0:9b334a45a8ff	1835	}
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/**
bogdanm	0:9b334a45a8ff	1838	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	1839	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	1840	* @param htim: TIM PWM handle
bogdanm	0:9b334a45a8ff	1841	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	1842	* @param Channel : TIM Channels to be configured
bogdanm	0:9b334a45a8ff	1843	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1844	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1845	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1846	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1847	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1848	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	1849	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	1850	* @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
bogdanm	0:9b334a45a8ff	1851	* @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 PWM channels can
bogdanm	0:9b334a45a8ff	1852	* be configured
bogdanm	0:9b334a45a8ff	1853	* @retval HAL status
bogdanm	0:9b334a45a8ff	1854	*/
bogdanm	0:9b334a45a8ff	1855	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	1856	TIM_OC_InitTypeDef* sConfig,
bogdanm	0:9b334a45a8ff	1857	uint32_t Channel)
bogdanm	0:9b334a45a8ff	1858	{
bogdanm	0:9b334a45a8ff	1859	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1860	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	1861	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	1862	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	1863	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	1864	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	1865	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	1866	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/* Check input state */
bogdanm	0:9b334a45a8ff	1869	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	switch (Channel)
bogdanm	0:9b334a45a8ff	1874	{
bogdanm	0:9b334a45a8ff	1875	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1876	{
bogdanm	0:9b334a45a8ff	1877	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1878	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	1881	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	1884	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	1885
bogdanm	0:9b334a45a8ff	1886	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1887	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	1888	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	1889	}
bogdanm	0:9b334a45a8ff	1890	break;
bogdanm	0:9b334a45a8ff	1891
bogdanm	0:9b334a45a8ff	1892	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1893	{
bogdanm	0:9b334a45a8ff	1894	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1895	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	1898	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1899
bogdanm	0:9b334a45a8ff	1900	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	1901	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	1902
bogdanm	0:9b334a45a8ff	1903	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1904	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	1905	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	break;
bogdanm	0:9b334a45a8ff	1908
bogdanm	0:9b334a45a8ff	1909	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1910	{
bogdanm	0:9b334a45a8ff	1911	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1912	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	1915	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1916
bogdanm	0:9b334a45a8ff	1917	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	1918	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	1919
bogdanm	0:9b334a45a8ff	1920	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1921	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	1922	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	1923	}
bogdanm	0:9b334a45a8ff	1924	break;
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1927	{
bogdanm	0:9b334a45a8ff	1928	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1929	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1930
bogdanm	0:9b334a45a8ff	1931	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	1932	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1933
bogdanm	0:9b334a45a8ff	1934	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	1935	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1938	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	1939	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941	break;
bogdanm	0:9b334a45a8ff	1942
bogdanm	0:9b334a45a8ff	1943	case TIM_CHANNEL_5:
bogdanm	0:9b334a45a8ff	1944	{
bogdanm	0:9b334a45a8ff	1945	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1946	assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/* Configure the Channel 5 in PWM mode */
bogdanm	0:9b334a45a8ff	1949	TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	/* Set the Preload enable bit for channel5*/
bogdanm	0:9b334a45a8ff	1952	htim->Instance->CCMR3 \|= TIM_CCMR3_OC5PE;
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1955	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
bogdanm	0:9b334a45a8ff	1956	htim->Instance->CCMR3 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	1957	}
bogdanm	0:9b334a45a8ff	1958	break;
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	case TIM_CHANNEL_6:
bogdanm	0:9b334a45a8ff	1961	{
bogdanm	0:9b334a45a8ff	1962	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1963	assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1964
bogdanm	0:9b334a45a8ff	1965	/* Configure the Channel 5 in PWM mode */
bogdanm	0:9b334a45a8ff	1966	TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	1967
bogdanm	0:9b334a45a8ff	1968	/* Set the Preload enable bit for channel6 */
bogdanm	0:9b334a45a8ff	1969	htim->Instance->CCMR3 \|= TIM_CCMR3_OC6PE;
bogdanm	0:9b334a45a8ff	1970
bogdanm	0:9b334a45a8ff	1971	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	1972	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
bogdanm	0:9b334a45a8ff	1973	htim->Instance->CCMR3 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975	break;
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	default:
bogdanm	0:9b334a45a8ff	1978	break;
bogdanm	0:9b334a45a8ff	1979	}
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1982
bogdanm	0:9b334a45a8ff	1983	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1984
bogdanm	0:9b334a45a8ff	1985	return HAL_OK;
bogdanm	0:9b334a45a8ff	1986	}
bogdanm	0:9b334a45a8ff	1987
bogdanm	0:9b334a45a8ff	1988	/**
bogdanm	0:9b334a45a8ff	1989	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	1990	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1991	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	1992	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	1993	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	1994	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1995	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	1996	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	1997	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	1998	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	1999	* @arg TIM_Channel_5: TIM Channel 5
bogdanm	0:9b334a45a8ff	2000	* @arg TIM_Channel_6: TIM Channel 6
bogdanm	0:9b334a45a8ff	2001	* @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 OC channels can
bogdanm	0:9b334a45a8ff	2002	* be configured
bogdanm	0:9b334a45a8ff	2003	* @retval None
bogdanm	0:9b334a45a8ff	2004	*/
bogdanm	0:9b334a45a8ff	2005	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	2006	TIM_ClearInputConfigTypeDef *sClearInputConfig,
bogdanm	0:9b334a45a8ff	2007	uint32_t Channel)
bogdanm	0:9b334a45a8ff	2008	{
bogdanm	0:9b334a45a8ff	2009	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2012	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2013	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	2014
bogdanm	0:9b334a45a8ff	2015	/* Check input state */
bogdanm	0:9b334a45a8ff	2016	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	switch (sClearInputConfig->ClearInputSource)
bogdanm	0:9b334a45a8ff	2019	{
bogdanm	0:9b334a45a8ff	2020	case TIM_CLEARINPUTSOURCE_NONE:
bogdanm	0:9b334a45a8ff	2021	{
bogdanm	0:9b334a45a8ff	2022	/* Clear the OCREF clear selection bit */
bogdanm	0:9b334a45a8ff	2023	tmpsmcr &= ~TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	2024
bogdanm	0:9b334a45a8ff	2025	/* Clear the ETR Bits */
bogdanm	0:9b334a45a8ff	2026	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	/* Set TIMx_SMCR */
bogdanm	0:9b334a45a8ff	2029	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2030	}
bogdanm	0:9b334a45a8ff	2031	break;
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	case TIM_CLEARINPUTSOURCE_OCREFCLR:
bogdanm	0:9b334a45a8ff	2034	{
bogdanm	0:9b334a45a8ff	2035	/* Clear the OCREF clear selection bit */
bogdanm	0:9b334a45a8ff	2036	htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	2037	}
bogdanm	0:9b334a45a8ff	2038	break;
bogdanm	0:9b334a45a8ff	2039
bogdanm	0:9b334a45a8ff	2040	case TIM_CLEARINPUTSOURCE_ETR:
bogdanm	0:9b334a45a8ff	2041	{
bogdanm	0:9b334a45a8ff	2042	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2043	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	2044	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	2045	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	2046
bogdanm	0:9b334a45a8ff	2047	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2048	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	2049	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	2050	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	2051
bogdanm	0:9b334a45a8ff	2052	/* Set the OCREF clear selection bit */
bogdanm	0:9b334a45a8ff	2053	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
bogdanm	0:9b334a45a8ff	2054	}
bogdanm	0:9b334a45a8ff	2055	break;
bogdanm	0:9b334a45a8ff	2056	}
bogdanm	0:9b334a45a8ff	2057
bogdanm	0:9b334a45a8ff	2058	switch (Channel)
bogdanm	0:9b334a45a8ff	2059	{
bogdanm	0:9b334a45a8ff	2060	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2061	{
bogdanm	0:9b334a45a8ff	2062	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2063	{
bogdanm	0:9b334a45a8ff	2064	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2065	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	2066	}
bogdanm	0:9b334a45a8ff	2067	else
bogdanm	0:9b334a45a8ff	2068	{
bogdanm	0:9b334a45a8ff	2069	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2070	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	2071	}
bogdanm	0:9b334a45a8ff	2072	}
bogdanm	0:9b334a45a8ff	2073	break;
bogdanm	0:9b334a45a8ff	2074	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2075	{
bogdanm	0:9b334a45a8ff	2076	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2077	{
bogdanm	0:9b334a45a8ff	2078	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	2079	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	2080	}
bogdanm	0:9b334a45a8ff	2081	else
bogdanm	0:9b334a45a8ff	2082	{
bogdanm	0:9b334a45a8ff	2083	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	2084	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	2085	}
bogdanm	0:9b334a45a8ff	2086	}
bogdanm	0:9b334a45a8ff	2087	break;
bogdanm	0:9b334a45a8ff	2088	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2089	{
bogdanm	0:9b334a45a8ff	2090	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2091	{
bogdanm	0:9b334a45a8ff	2092	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	2093	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	2094	}
bogdanm	0:9b334a45a8ff	2095	else
bogdanm	0:9b334a45a8ff	2096	{
bogdanm	0:9b334a45a8ff	2097	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	2098	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	2099	}
bogdanm	0:9b334a45a8ff	2100	}
bogdanm	0:9b334a45a8ff	2101	break;
bogdanm	0:9b334a45a8ff	2102	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2103	{
bogdanm	0:9b334a45a8ff	2104	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2105	{
bogdanm	0:9b334a45a8ff	2106	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	2107	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	2108	}
bogdanm	0:9b334a45a8ff	2109	else
bogdanm	0:9b334a45a8ff	2110	{
bogdanm	0:9b334a45a8ff	2111	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	2112	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	2113	}
bogdanm	0:9b334a45a8ff	2114	}
bogdanm	0:9b334a45a8ff	2115	break;
bogdanm	0:9b334a45a8ff	2116	case TIM_CHANNEL_5:
bogdanm	0:9b334a45a8ff	2117	{
bogdanm	0:9b334a45a8ff	2118	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2119	{
bogdanm	0:9b334a45a8ff	2120	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2121	htim->Instance->CCMR3 \|= TIM_CCMR3_OC5CE;
bogdanm	0:9b334a45a8ff	2122	}
bogdanm	0:9b334a45a8ff	2123	else
bogdanm	0:9b334a45a8ff	2124	{
bogdanm	0:9b334a45a8ff	2125	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2126	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
bogdanm	0:9b334a45a8ff	2127	}
bogdanm	0:9b334a45a8ff	2128	}
bogdanm	0:9b334a45a8ff	2129	break;
bogdanm	0:9b334a45a8ff	2130	case TIM_CHANNEL_6:
bogdanm	0:9b334a45a8ff	2131	{
bogdanm	0:9b334a45a8ff	2132	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	2133	{
bogdanm	0:9b334a45a8ff	2134	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2135	htim->Instance->CCMR3 \|= TIM_CCMR3_OC6CE;
bogdanm	0:9b334a45a8ff	2136	}
bogdanm	0:9b334a45a8ff	2137	else
bogdanm	0:9b334a45a8ff	2138	{
bogdanm	0:9b334a45a8ff	2139	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	2140	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
bogdanm	0:9b334a45a8ff	2141	}
bogdanm	0:9b334a45a8ff	2142	}
bogdanm	0:9b334a45a8ff	2143	break;
bogdanm	0:9b334a45a8ff	2144	default:
bogdanm	0:9b334a45a8ff	2145	break;
bogdanm	0:9b334a45a8ff	2146	}
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	return HAL_OK;
bogdanm	0:9b334a45a8ff	2151	}
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	/**
bogdanm	0:9b334a45a8ff	2154	* @brief Configures the TIM in master mode.
bogdanm	0:9b334a45a8ff	2155	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2156	* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	2157	* contains the selected trigger output (TRGO) and the Master/Slave
bogdanm	0:9b334a45a8ff	2158	* mode.
bogdanm	0:9b334a45a8ff	2159	* @retval HAL status
bogdanm	0:9b334a45a8ff	2160	*/
bogdanm	0:9b334a45a8ff	2161	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	2162	TIM_MasterConfigTypeDef * sMasterConfig)
bogdanm	0:9b334a45a8ff	2163	{
bogdanm	0:9b334a45a8ff	2164	uint32_t tmpcr2;
bogdanm	0:9b334a45a8ff	2165	uint32_t tmpsmcr;
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2168	assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2169	assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
bogdanm	0:9b334a45a8ff	2170	assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/* Check input state */
bogdanm	0:9b334a45a8ff	2173	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	2176	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	2177
bogdanm	0:9b334a45a8ff	2178	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2179	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2180
bogdanm	0:9b334a45a8ff	2181	/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
bogdanm	0:9b334a45a8ff	2182	if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
bogdanm	0:9b334a45a8ff	2183	{
bogdanm	0:9b334a45a8ff	2184	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2185	assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
bogdanm	0:9b334a45a8ff	2186
bogdanm	0:9b334a45a8ff	2187	/* Clear the MMS2 bits */
bogdanm	0:9b334a45a8ff	2188	tmpcr2 &= ~TIM_CR2_MMS2;
bogdanm	0:9b334a45a8ff	2189	/* Select the TRGO2 source*/
bogdanm	0:9b334a45a8ff	2190	tmpcr2 \|= sMasterConfig->MasterOutputTrigger2;
bogdanm	0:9b334a45a8ff	2191	}
bogdanm	0:9b334a45a8ff	2192
bogdanm	0:9b334a45a8ff	2193	/* Reset the MMS Bits */
bogdanm	0:9b334a45a8ff	2194	tmpcr2 &= ~TIM_CR2_MMS;
bogdanm	0:9b334a45a8ff	2195	/* Select the TRGO source */
bogdanm	0:9b334a45a8ff	2196	tmpcr2 \|= sMasterConfig->MasterOutputTrigger;
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198	/* Reset the MSM Bit */
bogdanm	0:9b334a45a8ff	2199	tmpsmcr &= ~TIM_SMCR_MSM;
bogdanm	0:9b334a45a8ff	2200	/* Set master mode */
bogdanm	0:9b334a45a8ff	2201	tmpsmcr \|= sMasterConfig->MasterSlaveMode;
bogdanm	0:9b334a45a8ff	2202
bogdanm	0:9b334a45a8ff	2203	/* Update TIMx CR2 */
bogdanm	0:9b334a45a8ff	2204	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	2205
bogdanm	0:9b334a45a8ff	2206	/* Update TIMx SMCR */
bogdanm	0:9b334a45a8ff	2207	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2210
bogdanm	0:9b334a45a8ff	2211	return HAL_OK;
bogdanm	0:9b334a45a8ff	2212	}
bogdanm	0:9b334a45a8ff	2213	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	2214	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	2215	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	2216	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	2219	/**
bogdanm	0:9b334a45a8ff	2220	* @brief Configures the TIM in master mode.
bogdanm	0:9b334a45a8ff	2221	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2222	* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	2223	* contains the selected trigger output (TRGO) and the Master/Slave
bogdanm	0:9b334a45a8ff	2224	* mode.
bogdanm	0:9b334a45a8ff	2225	* @retval HAL status
bogdanm	0:9b334a45a8ff	2226	*/
bogdanm	0:9b334a45a8ff	2227	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig)
bogdanm	0:9b334a45a8ff	2228	{
bogdanm	0:9b334a45a8ff	2229	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2230	assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2231	assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
bogdanm	0:9b334a45a8ff	2232	assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
bogdanm	0:9b334a45a8ff	2233
bogdanm	0:9b334a45a8ff	2234	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2237
bogdanm	0:9b334a45a8ff	2238	/* Reset the MMS Bits */
bogdanm	0:9b334a45a8ff	2239	htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm	0:9b334a45a8ff	2240	/* Select the TRGO source */
bogdanm	0:9b334a45a8ff	2241	htim->Instance->CR2 \|= sMasterConfig->MasterOutputTrigger;
bogdanm	0:9b334a45a8ff	2242
bogdanm	0:9b334a45a8ff	2243	/* Reset the MSM Bit */
bogdanm	0:9b334a45a8ff	2244	htim->Instance->SMCR &= ~TIM_SMCR_MSM;
bogdanm	0:9b334a45a8ff	2245	/* Set or Reset the MSM Bit */
bogdanm	0:9b334a45a8ff	2246	htim->Instance->SMCR \|= sMasterConfig->MasterSlaveMode;
bogdanm	0:9b334a45a8ff	2247
bogdanm	0:9b334a45a8ff	2248	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2249
bogdanm	0:9b334a45a8ff	2250	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2251
bogdanm	0:9b334a45a8ff	2252	return HAL_OK;
bogdanm	0:9b334a45a8ff	2253	}
bogdanm	0:9b334a45a8ff	2254	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	2257	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	2258	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	2259	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	2260	/**
bogdanm	0:9b334a45a8ff	2261	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
bogdanm	0:9b334a45a8ff	2262	* and the AOE(automatic output enable).
bogdanm	0:9b334a45a8ff	2263	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2264	* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	2265	* contains the BDTR Register configuration information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	2266	* @note For STM32F302xC, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx and STM32F303x8 two break inputs can be configured.
bogdanm	0:9b334a45a8ff	2267	* @retval HAL status
bogdanm	0:9b334a45a8ff	2268	*/
bogdanm	0:9b334a45a8ff	2269	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	2270	TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
bogdanm	0:9b334a45a8ff	2271	{
bogdanm	0:9b334a45a8ff	2272	uint32_t tmpbdtr = 0;
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2275	assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2276	assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
bogdanm	0:9b334a45a8ff	2277	assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
bogdanm	0:9b334a45a8ff	2278	assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
bogdanm	0:9b334a45a8ff	2279	assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
bogdanm	0:9b334a45a8ff	2280	assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
bogdanm	0:9b334a45a8ff	2281	assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
bogdanm	0:9b334a45a8ff	2282	assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
bogdanm	0:9b334a45a8ff	2283	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285	/* Check input state */
bogdanm	0:9b334a45a8ff	2286	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2287
bogdanm	0:9b334a45a8ff	2288	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
bogdanm	0:9b334a45a8ff	2289	the OSSI State, the dead time value and the Automatic Output Enable Bit */
bogdanm	0:9b334a45a8ff	2290	if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
bogdanm	0:9b334a45a8ff	2291	{
bogdanm	0:9b334a45a8ff	2292	assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
bogdanm	0:9b334a45a8ff	2293	assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
bogdanm	0:9b334a45a8ff	2294	assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
bogdanm	0:9b334a45a8ff	2295
bogdanm	0:9b334a45a8ff	2296	/* Clear the BDTR bits */
bogdanm	0:9b334a45a8ff	2297	tmpbdtr &= ~(TIM_BDTR_DTG \| TIM_BDTR_LOCK \| TIM_BDTR_OSSI \|
bogdanm	0:9b334a45a8ff	2298	TIM_BDTR_OSSR \| TIM_BDTR_BKE \| TIM_BDTR_BKP \|
bogdanm	0:9b334a45a8ff	2299	TIM_BDTR_AOE \| TIM_BDTR_MOE \| TIM_BDTR_BKF \|
bogdanm	0:9b334a45a8ff	2300	TIM_BDTR_BK2F \| TIM_BDTR_BK2E \| TIM_BDTR_BK2P);
bogdanm	0:9b334a45a8ff	2301
bogdanm	0:9b334a45a8ff	2302	/* Set the BDTR bits */
bogdanm	0:9b334a45a8ff	2303	tmpbdtr \|= sBreakDeadTimeConfig->DeadTime;
bogdanm	0:9b334a45a8ff	2304	tmpbdtr \|= sBreakDeadTimeConfig->LockLevel;
bogdanm	0:9b334a45a8ff	2305	tmpbdtr \|= sBreakDeadTimeConfig->OffStateIDLEMode;
bogdanm	0:9b334a45a8ff	2306	tmpbdtr \|= sBreakDeadTimeConfig->OffStateRunMode;
bogdanm	0:9b334a45a8ff	2307	tmpbdtr \|= sBreakDeadTimeConfig->BreakState;
bogdanm	0:9b334a45a8ff	2308	tmpbdtr \|= sBreakDeadTimeConfig->BreakPolarity;
bogdanm	0:9b334a45a8ff	2309	tmpbdtr \|= sBreakDeadTimeConfig->AutomaticOutput;
bogdanm	0:9b334a45a8ff	2310	tmpbdtr \|= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
bogdanm	0:9b334a45a8ff	2311	tmpbdtr \|= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
bogdanm	0:9b334a45a8ff	2312	tmpbdtr \|= sBreakDeadTimeConfig->Break2State;
bogdanm	0:9b334a45a8ff	2313	tmpbdtr \|= sBreakDeadTimeConfig->Break2Polarity;
bogdanm	0:9b334a45a8ff	2314	}
bogdanm	0:9b334a45a8ff	2315	else
bogdanm	0:9b334a45a8ff	2316	{
bogdanm	0:9b334a45a8ff	2317	/* Clear the BDTR bits */
bogdanm	0:9b334a45a8ff	2318	tmpbdtr &= ~(TIM_BDTR_DTG \| TIM_BDTR_LOCK \| TIM_BDTR_OSSI \|
bogdanm	0:9b334a45a8ff	2319	TIM_BDTR_OSSR \| TIM_BDTR_BKE \| TIM_BDTR_BKP \|
bogdanm	0:9b334a45a8ff	2320	TIM_BDTR_AOE \| TIM_BDTR_MOE \| TIM_BDTR_BKF);
bogdanm	0:9b334a45a8ff	2321
bogdanm	0:9b334a45a8ff	2322	/* Set the BDTR bits */
bogdanm	0:9b334a45a8ff	2323	tmpbdtr \|= sBreakDeadTimeConfig->DeadTime;
bogdanm	0:9b334a45a8ff	2324	tmpbdtr \|= sBreakDeadTimeConfig->LockLevel;
bogdanm	0:9b334a45a8ff	2325	tmpbdtr \|= sBreakDeadTimeConfig->OffStateIDLEMode;
bogdanm	0:9b334a45a8ff	2326	tmpbdtr \|= sBreakDeadTimeConfig->OffStateRunMode;
bogdanm	0:9b334a45a8ff	2327	tmpbdtr \|= sBreakDeadTimeConfig->BreakState;
bogdanm	0:9b334a45a8ff	2328	tmpbdtr \|= sBreakDeadTimeConfig->BreakPolarity;
bogdanm	0:9b334a45a8ff	2329	tmpbdtr \|= sBreakDeadTimeConfig->AutomaticOutput;
bogdanm	0:9b334a45a8ff	2330	tmpbdtr \|= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
bogdanm	0:9b334a45a8ff	2331	}
bogdanm	0:9b334a45a8ff	2332
bogdanm	0:9b334a45a8ff	2333	/* Set TIMx_BDTR */
bogdanm	0:9b334a45a8ff	2334	htim->Instance->BDTR = tmpbdtr;
bogdanm	0:9b334a45a8ff	2335
bogdanm	0:9b334a45a8ff	2336	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2337
bogdanm	0:9b334a45a8ff	2338	return HAL_OK;
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	2341	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	2342	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	2343	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	2344
bogdanm	0:9b334a45a8ff	2345	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	2346	/**
bogdanm	0:9b334a45a8ff	2347	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
bogdanm	0:9b334a45a8ff	2348	* and the AOE(automatic output enable).
bogdanm	0:9b334a45a8ff	2349	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2350	* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	2351	* contains the BDTR Register configuration information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	2352	* @retval HAL status
bogdanm	0:9b334a45a8ff	2353	*/
bogdanm	0:9b334a45a8ff	2354	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	2355	TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
bogdanm	0:9b334a45a8ff	2356	{
bogdanm	0:9b334a45a8ff	2357	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2358	assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2359	assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
bogdanm	0:9b334a45a8ff	2360	assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
bogdanm	0:9b334a45a8ff	2361	assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
bogdanm	0:9b334a45a8ff	2362	assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
bogdanm	0:9b334a45a8ff	2363	assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
bogdanm	0:9b334a45a8ff	2364	assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
bogdanm	0:9b334a45a8ff	2365	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
bogdanm	0:9b334a45a8ff	2366
bogdanm	0:9b334a45a8ff	2367	/* Process Locked */
bogdanm	0:9b334a45a8ff	2368	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2369
bogdanm	0:9b334a45a8ff	2370	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2371
bogdanm	0:9b334a45a8ff	2372	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
bogdanm	0:9b334a45a8ff	2373	the OSSI State, the dead time value and the Automatic Output Enable Bit */
bogdanm	0:9b334a45a8ff	2374	htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode \|
bogdanm	0:9b334a45a8ff	2375	sBreakDeadTimeConfig->OffStateIDLEMode \|
bogdanm	0:9b334a45a8ff	2376	sBreakDeadTimeConfig->LockLevel \|
bogdanm	0:9b334a45a8ff	2377	sBreakDeadTimeConfig->DeadTime \|
bogdanm	0:9b334a45a8ff	2378	sBreakDeadTimeConfig->BreakState \|
bogdanm	0:9b334a45a8ff	2379	sBreakDeadTimeConfig->BreakPolarity \|
bogdanm	0:9b334a45a8ff	2380	sBreakDeadTimeConfig->AutomaticOutput;
bogdanm	0:9b334a45a8ff	2381
bogdanm	0:9b334a45a8ff	2382
bogdanm	0:9b334a45a8ff	2383	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2386
bogdanm	0:9b334a45a8ff	2387	return HAL_OK;
bogdanm	0:9b334a45a8ff	2388	}
bogdanm	0:9b334a45a8ff	2389	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	2390
bogdanm	0:9b334a45a8ff	2391	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	2392	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	0:9b334a45a8ff	2393	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	0:9b334a45a8ff	2394	/**
bogdanm	0:9b334a45a8ff	2395	* @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
bogdanm	0:9b334a45a8ff	2396	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2397	* @param Remap1: specifies the first TIM remapping source.
bogdanm	0:9b334a45a8ff	2398	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2399	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2400	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
bogdanm	0:9b334a45a8ff	2401	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
bogdanm	0:9b334a45a8ff	2402	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
bogdanm	0:9b334a45a8ff	2403	* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
bogdanm	0:9b334a45a8ff	2404	* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
bogdanm	0:9b334a45a8ff	2405	* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
bogdanm	0:9b334a45a8ff	2406	* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
bogdanm	0:9b334a45a8ff	2407	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
bogdanm	0:9b334a45a8ff	2408	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
bogdanm	0:9b334a45a8ff	2409	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
bogdanm	0:9b334a45a8ff	2410	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
bogdanm	0:9b334a45a8ff	2411	* @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2412	* @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
bogdanm	0:9b334a45a8ff	2413	* @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
bogdanm	0:9b334a45a8ff	2414	* @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
bogdanm	0:9b334a45a8ff	2415	* @param Remap2: specifies the second TIMremapping source (if any).
bogdanm	0:9b334a45a8ff	2416	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2417	* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2418	* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
bogdanm	0:9b334a45a8ff	2419	* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
bogdanm	0:9b334a45a8ff	2420	* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
bogdanm	0:9b334a45a8ff	2421	* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
bogdanm	0:9b334a45a8ff	2422	* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
bogdanm	0:9b334a45a8ff	2423	* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
bogdanm	0:9b334a45a8ff	2424	* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
bogdanm	0:9b334a45a8ff	2425	* @arg TIM_TIM16_NONE: Non significant value for TIM16
bogdanm	0:9b334a45a8ff	2426	* @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
bogdanm	0:9b334a45a8ff	2427	* @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
bogdanm	0:9b334a45a8ff	2428	* @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
bogdanm	0:9b334a45a8ff	2429	* @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
bogdanm	0:9b334a45a8ff	2430	* @retval HAL status
bogdanm	0:9b334a45a8ff	2431	*/
bogdanm	0:9b334a45a8ff	2432	#else /* STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	2433	/**
bogdanm	0:9b334a45a8ff	2434	* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
bogdanm	0:9b334a45a8ff	2435	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2436	* @param Remap1: specifies the first TIM remapping source.
bogdanm	0:9b334a45a8ff	2437	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2438	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2439	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
bogdanm	0:9b334a45a8ff	2440	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
bogdanm	0:9b334a45a8ff	2441	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
bogdanm	0:9b334a45a8ff	2442	* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
bogdanm	0:9b334a45a8ff	2443	* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
bogdanm	0:9b334a45a8ff	2444	* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
bogdanm	0:9b334a45a8ff	2445	* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
bogdanm	0:9b334a45a8ff	2446	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
bogdanm	0:9b334a45a8ff	2447	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
bogdanm	0:9b334a45a8ff	2448	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
bogdanm	0:9b334a45a8ff	2449	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
bogdanm	0:9b334a45a8ff	2450	* @param Remap2: specifies the second TIMremapping source (if any).
bogdanm	0:9b334a45a8ff	2451	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2452	* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2453	* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
bogdanm	0:9b334a45a8ff	2454	* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
bogdanm	0:9b334a45a8ff	2455	* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
bogdanm	0:9b334a45a8ff	2456	* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
bogdanm	0:9b334a45a8ff	2457	* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
bogdanm	0:9b334a45a8ff	2458	* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
bogdanm	0:9b334a45a8ff	2459	* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
bogdanm	0:9b334a45a8ff	2460	* @retval HAL status
bogdanm	0:9b334a45a8ff	2461	*/
bogdanm	0:9b334a45a8ff	2462	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	2463	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
bogdanm	0:9b334a45a8ff	2464	{
bogdanm	0:9b334a45a8ff	2465	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2466
bogdanm	0:9b334a45a8ff	2467	/* Check parameters */
bogdanm	0:9b334a45a8ff	2468	assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2469	assert_param(IS_TIM_REMAP(Remap1));
bogdanm	0:9b334a45a8ff	2470	assert_param(IS_TIM_REMAP2(Remap2));
bogdanm	0:9b334a45a8ff	2471
bogdanm	0:9b334a45a8ff	2472	/* Set the Timer remapping configuration */
bogdanm	0:9b334a45a8ff	2473	htim->Instance->OR = Remap1 \| Remap2;
bogdanm	0:9b334a45a8ff	2474
bogdanm	0:9b334a45a8ff	2475	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2476
bogdanm	0:9b334a45a8ff	2477	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2478
bogdanm	0:9b334a45a8ff	2479	return HAL_OK;
bogdanm	0:9b334a45a8ff	2480	}
bogdanm	0:9b334a45a8ff	2481	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	2482	/* STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	2483
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	#if defined(STM32F302xE) \|\| \
bogdanm	0:9b334a45a8ff	2486	defined(STM32F302xC) \|\| \
bogdanm	0:9b334a45a8ff	2487	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	2488	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	0:9b334a45a8ff	2489	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	2490	#if defined(STM32F302xE) \|\| \
bogdanm	0:9b334a45a8ff	2491	defined(STM32F302xC) \|\| \
bogdanm	0:9b334a45a8ff	2492	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	2493	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	2494	/**
bogdanm	0:9b334a45a8ff	2495	* @brief Configures the TIM1 and TIM16 Remapping input capabilities.
bogdanm	0:9b334a45a8ff	2496	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2497	* @param Remap: specifies the TIM remapping source.
bogdanm	0:9b334a45a8ff	2498	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2499	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
bogdanm	0:9b334a45a8ff	2500	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
bogdanm	0:9b334a45a8ff	2501	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
bogdanm	0:9b334a45a8ff	2502	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
bogdanm	0:9b334a45a8ff	2503	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
bogdanm	0:9b334a45a8ff	2504	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
bogdanm	0:9b334a45a8ff	2505	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
bogdanm	0:9b334a45a8ff	2506	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
bogdanm	0:9b334a45a8ff	2507	* @retval HAL status
bogdanm	0:9b334a45a8ff	2508	*/
bogdanm	0:9b334a45a8ff	2509	#else /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	2510	/**
bogdanm	0:9b334a45a8ff	2511	* @brief Configures the TIM2 and TIM14 Remapping input capabilities.
bogdanm	0:9b334a45a8ff	2512	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2513	* @param Remap: specifies the TIM remapping source.
bogdanm	0:9b334a45a8ff	2514	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2515	* STM32F373xC, STM32F378xx:
bogdanm	0:9b334a45a8ff	2516	* @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
bogdanm	0:9b334a45a8ff	2517	* @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
bogdanm	0:9b334a45a8ff	2518	* @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
bogdanm	0:9b334a45a8ff	2519	* @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
bogdanm	0:9b334a45a8ff	2520	* @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
bogdanm	0:9b334a45a8ff	2521	* @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
bogdanm	0:9b334a45a8ff	2522	* @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
bogdanm	0:9b334a45a8ff	2523	* @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
bogdanm	0:9b334a45a8ff	2524	* @retval HAL status
bogdanm	0:9b334a45a8ff	2525	*/
bogdanm	0:9b334a45a8ff	2526	#endif /* STM32F302xE \|\| */
bogdanm	0:9b334a45a8ff	2527	/* STM32F302xC \|\| */
bogdanm	0:9b334a45a8ff	2528	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	2529	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
bogdanm	0:9b334a45a8ff	2530	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
bogdanm	0:9b334a45a8ff	2531	{
bogdanm	0:9b334a45a8ff	2532	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2533
bogdanm	0:9b334a45a8ff	2534	/* Check parameters */
bogdanm	0:9b334a45a8ff	2535	assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2536	assert_param(IS_TIM_REMAP(Remap));
bogdanm	0:9b334a45a8ff	2537
bogdanm	0:9b334a45a8ff	2538	/* Set the Timer remapping configuration */
bogdanm	0:9b334a45a8ff	2539	htim->Instance->OR = Remap;
bogdanm	0:9b334a45a8ff	2540
bogdanm	0:9b334a45a8ff	2541	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2542
bogdanm	0:9b334a45a8ff	2543	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	return HAL_OK;
bogdanm	0:9b334a45a8ff	2546	}
bogdanm	0:9b334a45a8ff	2547	#endif /* STM32F302xE \|\| */
bogdanm	0:9b334a45a8ff	2548	/* STM32F302xC \|\| */
bogdanm	0:9b334a45a8ff	2549	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	2550	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
bogdanm	0:9b334a45a8ff	2551	/* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	2552
bogdanm	0:9b334a45a8ff	2553
bogdanm	0:9b334a45a8ff	2554	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	2555	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	2556	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	2557	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	2558	/**
bogdanm	0:9b334a45a8ff	2559	* @brief Group channel 5 and channel 1, 2 or 3
bogdanm	0:9b334a45a8ff	2560	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	2561	* @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
bogdanm	0:9b334a45a8ff	2562	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2563	* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
bogdanm	0:9b334a45a8ff	2564	* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
bogdanm	0:9b334a45a8ff	2565	* TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
bogdanm	0:9b334a45a8ff	2566	* TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
bogdanm	0:9b334a45a8ff	2567	* @retval HAL status
bogdanm	0:9b334a45a8ff	2568	*/
bogdanm	0:9b334a45a8ff	2569	HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
bogdanm	0:9b334a45a8ff	2570	{
bogdanm	0:9b334a45a8ff	2571	/* Check parameters */
bogdanm	0:9b334a45a8ff	2572	assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2573	assert_param(IS_TIM_GROUPCH5(OCRef));
bogdanm	0:9b334a45a8ff	2574
bogdanm	0:9b334a45a8ff	2575	/* Process Locked */
bogdanm	0:9b334a45a8ff	2576	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2577
bogdanm	0:9b334a45a8ff	2578	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2579
bogdanm	0:9b334a45a8ff	2580	/* Clear GC5Cx bit fields */
bogdanm	0:9b334a45a8ff	2581	htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3\|TIM_CCR5_GC5C2\|TIM_CCR5_GC5C1);
bogdanm	0:9b334a45a8ff	2582
bogdanm	0:9b334a45a8ff	2583	/* Set GC5Cx bit fields */
bogdanm	0:9b334a45a8ff	2584	htim->Instance->CCR5 \|= OCRef;
bogdanm	0:9b334a45a8ff	2585
bogdanm	0:9b334a45a8ff	2586	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2589
bogdanm	0:9b334a45a8ff	2590	return HAL_OK;
bogdanm	0:9b334a45a8ff	2591	}
bogdanm	0:9b334a45a8ff	2592	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	2593	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	2594	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	2595	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	2596
bogdanm	0:9b334a45a8ff	2597	/**
bogdanm	0:9b334a45a8ff	2598	* @}
bogdanm	0:9b334a45a8ff	2599	*/
bogdanm	0:9b334a45a8ff	2600
bogdanm	0:9b334a45a8ff	2601	/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
bogdanm	0:9b334a45a8ff	2602	* @brief Extended Callbacks functions
bogdanm	0:9b334a45a8ff	2603	*
bogdanm	0:9b334a45a8ff	2604	@verbatim
bogdanm	0:9b334a45a8ff	2605	==============================================================================
bogdanm	0:9b334a45a8ff	2606	##### Extended Callbacks functions #####
bogdanm	0:9b334a45a8ff	2607	==============================================================================
bogdanm	0:9b334a45a8ff	2608	[..]
bogdanm	0:9b334a45a8ff	2609	This section provides Extended TIM callback functions:
bogdanm	0:9b334a45a8ff	2610	(+) Timer Commutation callback
bogdanm	0:9b334a45a8ff	2611	(+) Timer Break callback
bogdanm	0:9b334a45a8ff	2612
bogdanm	0:9b334a45a8ff	2613	@endverbatim
bogdanm	0:9b334a45a8ff	2614	* @{
bogdanm	0:9b334a45a8ff	2615	*/
bogdanm	0:9b334a45a8ff	2616
bogdanm	0:9b334a45a8ff	2617	/**
bogdanm	0:9b334a45a8ff	2618	* @brief Hall commutation changed callback in non blocking mode
bogdanm	0:9b334a45a8ff	2619	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2620	* @retval None
bogdanm	0:9b334a45a8ff	2621	*/
bogdanm	0:9b334a45a8ff	2622	__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2623	{
bogdanm	0:9b334a45a8ff	2624	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2625	the HAL_TIMEx_CommutationCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2626	*/
bogdanm	0:9b334a45a8ff	2627	}
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	/**
bogdanm	0:9b334a45a8ff	2630	* @brief Hall Break detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	2631	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	2632	* @retval None
bogdanm	0:9b334a45a8ff	2633	*/
bogdanm	0:9b334a45a8ff	2634	__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2635	{
bogdanm	0:9b334a45a8ff	2636	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2637	the HAL_TIMEx_BreakCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2638	*/
bogdanm	0:9b334a45a8ff	2639	}
bogdanm	0:9b334a45a8ff	2640
bogdanm	0:9b334a45a8ff	2641	/**
bogdanm	0:9b334a45a8ff	2642	* @}
bogdanm	0:9b334a45a8ff	2643	*/
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
bogdanm	0:9b334a45a8ff	2646	* @brief Extended Peripheral State functions
bogdanm	0:9b334a45a8ff	2647	*
bogdanm	0:9b334a45a8ff	2648	@verbatim
bogdanm	0:9b334a45a8ff	2649	==============================================================================
bogdanm	0:9b334a45a8ff	2650	##### Extended Peripheral State functions #####
bogdanm	0:9b334a45a8ff	2651	==============================================================================
bogdanm	0:9b334a45a8ff	2652	[..]
bogdanm	0:9b334a45a8ff	2653	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	2654	and the data flow.
bogdanm	0:9b334a45a8ff	2655
bogdanm	0:9b334a45a8ff	2656	@endverbatim
bogdanm	0:9b334a45a8ff	2657	* @{
bogdanm	0:9b334a45a8ff	2658	*/
bogdanm	0:9b334a45a8ff	2659
bogdanm	0:9b334a45a8ff	2660	/**
bogdanm	0:9b334a45a8ff	2661	* @brief Return the TIM Hall Sensor interface state
bogdanm	0:9b334a45a8ff	2662	* @param htim: TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	2663	* @retval HAL state
bogdanm	0:9b334a45a8ff	2664	*/
bogdanm	0:9b334a45a8ff	2665	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2666	{
bogdanm	0:9b334a45a8ff	2667	return htim->State;
bogdanm	0:9b334a45a8ff	2668	}
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	/**
bogdanm	0:9b334a45a8ff	2671	* @}
bogdanm	0:9b334a45a8ff	2672	*/
bogdanm	0:9b334a45a8ff	2673
bogdanm	0:9b334a45a8ff	2674	/**
bogdanm	0:9b334a45a8ff	2675	* @brief TIM DMA Commutation callback.
bogdanm	0:9b334a45a8ff	2676	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2677	* @retval None
bogdanm	0:9b334a45a8ff	2678	*/
bogdanm	0:9b334a45a8ff	2679	void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2680	{
bogdanm	0:9b334a45a8ff	2681	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2682
bogdanm	0:9b334a45a8ff	2683	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2684
bogdanm	0:9b334a45a8ff	2685	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2686	}
bogdanm	0:9b334a45a8ff	2687
bogdanm	0:9b334a45a8ff	2688	/**
bogdanm	0:9b334a45a8ff	2689	* @brief Enables or disables the TIM Capture Compare Channel xN.
bogdanm	0:9b334a45a8ff	2690	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	2691	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	2692	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2693	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	2694	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	2695	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	2696	* @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
bogdanm	0:9b334a45a8ff	2697	* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
bogdanm	0:9b334a45a8ff	2698	* @retval None
bogdanm	0:9b334a45a8ff	2699	*/
bogdanm	0:9b334a45a8ff	2700	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
bogdanm	0:9b334a45a8ff	2701	{
bogdanm	0:9b334a45a8ff	2702	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	2703
bogdanm	0:9b334a45a8ff	2704	tmp = TIM_CCER_CC1NE << Channel;
bogdanm	0:9b334a45a8ff	2705
bogdanm	0:9b334a45a8ff	2706	/* Reset the CCxNE Bit */
bogdanm	0:9b334a45a8ff	2707	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	2708
bogdanm	0:9b334a45a8ff	2709	/* Set or reset the CCxNE Bit */
bogdanm	0:9b334a45a8ff	2710	TIMx->CCER \|= (uint32_t)(ChannelNState << Channel);
bogdanm	0:9b334a45a8ff	2711	}
bogdanm	0:9b334a45a8ff	2712
bogdanm	0:9b334a45a8ff	2713	/**
bogdanm	0:9b334a45a8ff	2714	* @}
bogdanm	0:9b334a45a8ff	2715	*/
bogdanm	0:9b334a45a8ff	2716
bogdanm	0:9b334a45a8ff	2717	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2718	/**
bogdanm	0:9b334a45a8ff	2719	* @}
bogdanm	0:9b334a45a8ff	2720	*/
bogdanm	0:9b334a45a8ff	2721
bogdanm	0:9b334a45a8ff	2722	/**
bogdanm	0:9b334a45a8ff	2723	* @}
bogdanm	0:9b334a45a8ff	2724	*/
bogdanm	0:9b334a45a8ff	2725
bogdanm	0:9b334a45a8ff	2726	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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