mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Base Start
bogdanm	0:9b334a45a8ff	12	* + Time Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Time Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Time Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Time Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Time Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Time Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Time Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Time Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Time Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Time Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Time Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Time One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Time One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Time One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Time Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Time Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Time Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Time Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Commutation Event configuration with Interruption and DMA
bogdanm	0:9b334a45a8ff	32	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	33	* + Time External Clock configuration
bogdanm	0:9b334a45a8ff	34	@verbatim
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	37	==============================================================================
bogdanm	0:9b334a45a8ff	38	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	39	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm	0:9b334a45a8ff	41	counter clock frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	42	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	43	(++) Input Capture
bogdanm	0:9b334a45a8ff	44	(++) Output Compare
bogdanm	0:9b334a45a8ff	45	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	46	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	49	==============================================================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	52	depending from feature used :
bogdanm	0:9b334a45a8ff	53	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	54	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	55	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	62	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	63	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	64	__GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	68	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	70	any start function.
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	73	Initialization function of this driver:
bogdanm	0:9b334a45a8ff	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	76	Output Compare signal.
bogdanm	0:9b334a45a8ff	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	78	PWM signal.
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	80	external signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm	0:9b334a45a8ff	82	in One Pulse Mode.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm	0:9b334a45a8ff	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm	0:9b334a45a8ff	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm	0:9b334a45a8ff	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm	0:9b334a45a8ff	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm	0:9b334a45a8ff	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm	0:9b334a45a8ff	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	94	HAL_TIM_DMABurst_WriteStart()
bogdanm	0:9b334a45a8ff	95	HAL_TIM_DMABurst_ReadStart()
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
bogdanm	0:9b334a45a8ff	101	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32f3xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIM TIM HAL module driver
bogdanm	0:9b334a45a8ff	136	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	145	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	147	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	148	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	149	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	150	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	151	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	152	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	153	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	154	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	155	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
bogdanm	0:9b334a45a8ff	156	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	157	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	158	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	161	* @{
bogdanm	0:9b334a45a8ff	162	*/
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	165	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	166	*
bogdanm	0:9b334a45a8ff	167	@verbatim
bogdanm	0:9b334a45a8ff	168	==============================================================================
bogdanm	0:9b334a45a8ff	169	##### Time Base functions #####
bogdanm	0:9b334a45a8ff	170	==============================================================================
bogdanm	0:9b334a45a8ff	171	[..]
bogdanm	0:9b334a45a8ff	172	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	173	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	174	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	175	(+) Start the Time Base.
bogdanm	0:9b334a45a8ff	176	(+) Stop the Time Base.
bogdanm	0:9b334a45a8ff	177	(+) Start the Time Base and enable interrupt.
bogdanm	0:9b334a45a8ff	178	(+) Stop the Time Base and disable interrupt.
bogdanm	0:9b334a45a8ff	179	(+) Start the Time Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	180	(+) Stop the Time Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	@endverbatim
bogdanm	0:9b334a45a8ff	183	* @{
bogdanm	0:9b334a45a8ff	184	*/
bogdanm	0:9b334a45a8ff	185	/**
bogdanm	0:9b334a45a8ff	186	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	187	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	188	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	189	* @retval HAL status
bogdanm	0:9b334a45a8ff	190	*/
bogdanm	0:9b334a45a8ff	191	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	192	{
bogdanm	0:9b334a45a8ff	193	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	194	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	195	{
bogdanm	0:9b334a45a8ff	196	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	197	}
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	/* Check the parameters */
bogdanm	0:9b334a45a8ff	200	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	201	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	202	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	205	{
bogdanm	0:9b334a45a8ff	206	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	207	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	208	}
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	211	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	214	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	217	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	return HAL_OK;
bogdanm	0:9b334a45a8ff	220	}
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	/**
bogdanm	0:9b334a45a8ff	223	* @brief DeInitializes the TIM Base peripheral
bogdanm	0:9b334a45a8ff	224	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	225	* @retval HAL status
bogdanm	0:9b334a45a8ff	226	*/
bogdanm	0:9b334a45a8ff	227	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	228	{
bogdanm	0:9b334a45a8ff	229	/* Check the parameters */
bogdanm	0:9b334a45a8ff	230	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	235	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	238	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	/* Change TIM state */
bogdanm	0:9b334a45a8ff	241	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/* Release Lock */
bogdanm	0:9b334a45a8ff	244	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	return HAL_OK;
bogdanm	0:9b334a45a8ff	247	}
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	/**
bogdanm	0:9b334a45a8ff	250	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	251	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	252	* @retval None
bogdanm	0:9b334a45a8ff	253	*/
bogdanm	0:9b334a45a8ff	254	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	255	{
bogdanm	0:9b334a45a8ff	256	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	257	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259	}
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/**
bogdanm	0:9b334a45a8ff	262	* @brief DeInitializes TIM Base MSP.
bogdanm	0:9b334a45a8ff	263	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	264	* @retval None
bogdanm	0:9b334a45a8ff	265	*/
bogdanm	0:9b334a45a8ff	266	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	269	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271	}
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/**
bogdanm	0:9b334a45a8ff	275	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	276	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	277	* @retval HAL status
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	280	{
bogdanm	0:9b334a45a8ff	281	/* Check the parameters */
bogdanm	0:9b334a45a8ff	282	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	285	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	288	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	291	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	/* Return function status */
bogdanm	0:9b334a45a8ff	294	return HAL_OK;
bogdanm	0:9b334a45a8ff	295	}
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/**
bogdanm	0:9b334a45a8ff	298	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	299	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	300	* @retval HAL status
bogdanm	0:9b334a45a8ff	301	*/
bogdanm	0:9b334a45a8ff	302	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	303	{
bogdanm	0:9b334a45a8ff	304	/* Check the parameters */
bogdanm	0:9b334a45a8ff	305	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	308	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	311	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	314	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/* Return function status */
bogdanm	0:9b334a45a8ff	317	return HAL_OK;
bogdanm	0:9b334a45a8ff	318	}
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/**
bogdanm	0:9b334a45a8ff	321	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	322	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	323	* @retval HAL status
bogdanm	0:9b334a45a8ff	324	*/
bogdanm	0:9b334a45a8ff	325	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	326	{
bogdanm	0:9b334a45a8ff	327	/* Check the parameters */
bogdanm	0:9b334a45a8ff	328	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	331	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	334	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* Return function status */
bogdanm	0:9b334a45a8ff	337	return HAL_OK;
bogdanm	0:9b334a45a8ff	338	}
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/**
bogdanm	0:9b334a45a8ff	341	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	342	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	343	* @retval HAL status
bogdanm	0:9b334a45a8ff	344	*/
bogdanm	0:9b334a45a8ff	345	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	346	{
bogdanm	0:9b334a45a8ff	347	/* Check the parameters */
bogdanm	0:9b334a45a8ff	348	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	349	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	350	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	353	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Return function status */
bogdanm	0:9b334a45a8ff	356	return HAL_OK;
bogdanm	0:9b334a45a8ff	357	}
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/**
bogdanm	0:9b334a45a8ff	360	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	361	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	362	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	363	* @param Length: The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	364	* @retval HAL status
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	367	{
bogdanm	0:9b334a45a8ff	368	/* Check the parameters */
bogdanm	0:9b334a45a8ff	369	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	374	}
bogdanm	0:9b334a45a8ff	375	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	376	{
bogdanm	0:9b334a45a8ff	377	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	378	{
bogdanm	0:9b334a45a8ff	379	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	380	}
bogdanm	0:9b334a45a8ff	381	else
bogdanm	0:9b334a45a8ff	382	{
bogdanm	0:9b334a45a8ff	383	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	384	}
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	387	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	390	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	393	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	396	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	399	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	/* Return function status */
bogdanm	0:9b334a45a8ff	402	return HAL_OK;
bogdanm	0:9b334a45a8ff	403	}
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	/**
bogdanm	0:9b334a45a8ff	406	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	407	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	408	* @retval HAL status
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	411	{
bogdanm	0:9b334a45a8ff	412	/* Check the parameters */
bogdanm	0:9b334a45a8ff	413	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	416	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	419	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* Change the htim state */
bogdanm	0:9b334a45a8ff	422	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* Return function status */
bogdanm	0:9b334a45a8ff	425	return HAL_OK;
bogdanm	0:9b334a45a8ff	426	}
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @}
bogdanm	0:9b334a45a8ff	430	*/
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	433	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	434	*
bogdanm	0:9b334a45a8ff	435	@verbatim
bogdanm	0:9b334a45a8ff	436	==============================================================================
bogdanm	0:9b334a45a8ff	437	##### Time Output Compare functions #####
bogdanm	0:9b334a45a8ff	438	==============================================================================
bogdanm	0:9b334a45a8ff	439	[..]
bogdanm	0:9b334a45a8ff	440	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	441	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	442	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	443	(+) Start the Time Output Compare.
bogdanm	0:9b334a45a8ff	444	(+) Stop the Time Output Compare.
bogdanm	0:9b334a45a8ff	445	(+) Start the Time Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	446	(+) Stop the Time Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	447	(+) Start the Time Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	448	(+) Stop the Time Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	@endverbatim
bogdanm	0:9b334a45a8ff	451	* @{
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453	/**
bogdanm	0:9b334a45a8ff	454	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	455	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	456	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	457	* @retval HAL status
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	462	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	463	{
bogdanm	0:9b334a45a8ff	464	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	465	}
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Check the parameters */
bogdanm	0:9b334a45a8ff	468	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	469	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	470	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	473	{
bogdanm	0:9b334a45a8ff	474	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	475	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	479	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	482	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	485	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	return HAL_OK;
bogdanm	0:9b334a45a8ff	488	}
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/**
bogdanm	0:9b334a45a8ff	491	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	492	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	493	* @retval HAL status
bogdanm	0:9b334a45a8ff	494	*/
bogdanm	0:9b334a45a8ff	495	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	/* Check the parameters */
bogdanm	0:9b334a45a8ff	498	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	503	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	506	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	/* Change TIM state */
bogdanm	0:9b334a45a8ff	509	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/* Release Lock */
bogdanm	0:9b334a45a8ff	512	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	return HAL_OK;
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/**
bogdanm	0:9b334a45a8ff	518	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	519	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	520	* @retval None
bogdanm	0:9b334a45a8ff	521	*/
bogdanm	0:9b334a45a8ff	522	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	523	{
bogdanm	0:9b334a45a8ff	524	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	525	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	526	*/
bogdanm	0:9b334a45a8ff	527	}
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/**
bogdanm	0:9b334a45a8ff	530	* @brief DeInitializes TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	531	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	532	* @retval None
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	537	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	538	*/
bogdanm	0:9b334a45a8ff	539	}
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/**
bogdanm	0:9b334a45a8ff	542	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	543	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	544	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	545	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	546	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	547	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	548	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	549	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	550	* @retval HAL status
bogdanm	0:9b334a45a8ff	551	*/
bogdanm	0:9b334a45a8ff	552	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	/* Check the parameters */
bogdanm	0:9b334a45a8ff	555	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	558	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	561	{
bogdanm	0:9b334a45a8ff	562	/* Enable the main output */
bogdanm	0:9b334a45a8ff	563	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	567	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/* Return function status */
bogdanm	0:9b334a45a8ff	570	return HAL_OK;
bogdanm	0:9b334a45a8ff	571	}
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/**
bogdanm	0:9b334a45a8ff	574	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	575	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	576	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	577	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	580	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	581	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	582	* @retval HAL status
bogdanm	0:9b334a45a8ff	583	*/
bogdanm	0:9b334a45a8ff	584	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	/* Check the parameters */
bogdanm	0:9b334a45a8ff	587	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	590	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	595	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	596	}
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	599	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Return function status */
bogdanm	0:9b334a45a8ff	602	return HAL_OK;
bogdanm	0:9b334a45a8ff	603	}
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/**
bogdanm	0:9b334a45a8ff	606	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	607	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	608	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	609	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	610	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	611	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	612	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	613	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	614	* @retval HAL status
bogdanm	0:9b334a45a8ff	615	*/
bogdanm	0:9b334a45a8ff	616	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	617	{
bogdanm	0:9b334a45a8ff	618	/* Check the parameters */
bogdanm	0:9b334a45a8ff	619	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	switch (Channel)
bogdanm	0:9b334a45a8ff	622	{
bogdanm	0:9b334a45a8ff	623	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	624	{
bogdanm	0:9b334a45a8ff	625	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	626	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	627	}
bogdanm	0:9b334a45a8ff	628	break;
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	633	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	634	}
bogdanm	0:9b334a45a8ff	635	break;
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	640	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	break;
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	645	{
bogdanm	0:9b334a45a8ff	646	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	647	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649	break;
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	default:
bogdanm	0:9b334a45a8ff	652	break;
bogdanm	0:9b334a45a8ff	653	}
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	656	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	659	{
bogdanm	0:9b334a45a8ff	660	/* Enable the main output */
bogdanm	0:9b334a45a8ff	661	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	665	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	/* Return function status */
bogdanm	0:9b334a45a8ff	668	return HAL_OK;
bogdanm	0:9b334a45a8ff	669	}
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/**
bogdanm	0:9b334a45a8ff	672	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	673	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	674	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	675	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	676	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	677	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	678	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	679	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	680	* @retval HAL status
bogdanm	0:9b334a45a8ff	681	*/
bogdanm	0:9b334a45a8ff	682	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	683	{
bogdanm	0:9b334a45a8ff	684	/* Check the parameters */
bogdanm	0:9b334a45a8ff	685	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	switch (Channel)
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	690	{
bogdanm	0:9b334a45a8ff	691	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	692	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694	break;
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	697	{
bogdanm	0:9b334a45a8ff	698	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	699	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	700	}
bogdanm	0:9b334a45a8ff	701	break;
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	704	{
bogdanm	0:9b334a45a8ff	705	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	706	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	707	}
bogdanm	0:9b334a45a8ff	708	break;
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	713	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	714	}
bogdanm	0:9b334a45a8ff	715	break;
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	default:
bogdanm	0:9b334a45a8ff	718	break;
bogdanm	0:9b334a45a8ff	719	}
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	722	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	725	{
bogdanm	0:9b334a45a8ff	726	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	727	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	731	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	/* Return function status */
bogdanm	0:9b334a45a8ff	734	return HAL_OK;
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/**
bogdanm	0:9b334a45a8ff	738	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	739	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	740	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	741	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	742	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	743	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	744	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	745	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	746	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	747	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	748	* @retval HAL status
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	/* Check the parameters */
bogdanm	0:9b334a45a8ff	753	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	756	{
bogdanm	0:9b334a45a8ff	757	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	758	}
bogdanm	0:9b334a45a8ff	759	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	760	{
bogdanm	0:9b334a45a8ff	761	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	764	}
bogdanm	0:9b334a45a8ff	765	else
bogdanm	0:9b334a45a8ff	766	{
bogdanm	0:9b334a45a8ff	767	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	768	}
bogdanm	0:9b334a45a8ff	769	}
bogdanm	0:9b334a45a8ff	770	switch (Channel)
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	773	{
bogdanm	0:9b334a45a8ff	774	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	775	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	778	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	781	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	782
bogdanm	0:9b334a45a8ff	783	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	784	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	785	}
bogdanm	0:9b334a45a8ff	786	break;
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	791	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	794	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	797	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	800	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	801	}
bogdanm	0:9b334a45a8ff	802	break;
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	805	{
bogdanm	0:9b334a45a8ff	806	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	807	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	810	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	813	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	816	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	817	}
bogdanm	0:9b334a45a8ff	818	break;
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	823	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	826	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	829	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	832	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834	break;
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	default:
bogdanm	0:9b334a45a8ff	837	break;
bogdanm	0:9b334a45a8ff	838	}
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	841	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	844	{
bogdanm	0:9b334a45a8ff	845	/* Enable the main output */
bogdanm	0:9b334a45a8ff	846	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	847	}
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	850	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/* Return function status */
bogdanm	0:9b334a45a8ff	853	return HAL_OK;
bogdanm	0:9b334a45a8ff	854	}
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/**
bogdanm	0:9b334a45a8ff	857	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	858	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	859	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	860	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	861	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	862	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	863	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	864	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	865	* @retval HAL status
bogdanm	0:9b334a45a8ff	866	*/
bogdanm	0:9b334a45a8ff	867	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	868	{
bogdanm	0:9b334a45a8ff	869	/* Check the parameters */
bogdanm	0:9b334a45a8ff	870	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	switch (Channel)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	875	{
bogdanm	0:9b334a45a8ff	876	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	877	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	878	}
bogdanm	0:9b334a45a8ff	879	break;
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	884	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886	break;
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	889	{
bogdanm	0:9b334a45a8ff	890	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	891	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893	break;
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	896	{
bogdanm	0:9b334a45a8ff	897	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	899	}
bogdanm	0:9b334a45a8ff	900	break;
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	default:
bogdanm	0:9b334a45a8ff	903	break;
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	907	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	910	{
bogdanm	0:9b334a45a8ff	911	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	912	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	913	}
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	916	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/* Change the htim state */
bogdanm	0:9b334a45a8ff	919	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/* Return function status */
bogdanm	0:9b334a45a8ff	922	return HAL_OK;
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	/**
bogdanm	0:9b334a45a8ff	926	* @}
bogdanm	0:9b334a45a8ff	927	*/
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	930	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	931	*
bogdanm	0:9b334a45a8ff	932	@verbatim
bogdanm	0:9b334a45a8ff	933	==============================================================================
bogdanm	0:9b334a45a8ff	934	##### Time PWM functions #####
bogdanm	0:9b334a45a8ff	935	==============================================================================
bogdanm	0:9b334a45a8ff	936	[..]
bogdanm	0:9b334a45a8ff	937	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	938	(+) Initialize and configure the TIM OPWM.
bogdanm	0:9b334a45a8ff	939	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	940	(+) Start the Time PWM.
bogdanm	0:9b334a45a8ff	941	(+) Stop the Time PWM.
bogdanm	0:9b334a45a8ff	942	(+) Start the Time PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	943	(+) Stop the Time PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	944	(+) Start the Time PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	945	(+) Stop the Time PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	@endverbatim
bogdanm	0:9b334a45a8ff	948	* @{
bogdanm	0:9b334a45a8ff	949	*/
bogdanm	0:9b334a45a8ff	950	/**
bogdanm	0:9b334a45a8ff	951	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	952	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	953	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	954	* @retval HAL status
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	957	{
bogdanm	0:9b334a45a8ff	958	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	959	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	960	{
bogdanm	0:9b334a45a8ff	961	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	962	}
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	/* Check the parameters */
bogdanm	0:9b334a45a8ff	965	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	966	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	967	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	970	{
bogdanm	0:9b334a45a8ff	971	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	972	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	973	}
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	976	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	979	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	982	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	return HAL_OK;
bogdanm	0:9b334a45a8ff	985	}
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	/**
bogdanm	0:9b334a45a8ff	988	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	989	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	990	* @retval HAL status
bogdanm	0:9b334a45a8ff	991	*/
bogdanm	0:9b334a45a8ff	992	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	993	{
bogdanm	0:9b334a45a8ff	994	/* Check the parameters */
bogdanm	0:9b334a45a8ff	995	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1000	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1003	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1006	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/* Release Lock */
bogdanm	0:9b334a45a8ff	1009	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	return HAL_OK;
bogdanm	0:9b334a45a8ff	1012	}
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1016	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1017	* @retval None
bogdanm	0:9b334a45a8ff	1018	*/
bogdanm	0:9b334a45a8ff	1019	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1022	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1023	*/
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/**
bogdanm	0:9b334a45a8ff	1027	* @brief DeInitializes TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1028	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1029	* @retval None
bogdanm	0:9b334a45a8ff	1030	*/
bogdanm	0:9b334a45a8ff	1031	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1034	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1035	*/
bogdanm	0:9b334a45a8ff	1036	}
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	/**
bogdanm	0:9b334a45a8ff	1039	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1040	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1041	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1042	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1043	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1044	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1045	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1046	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1047	* @retval HAL status
bogdanm	0:9b334a45a8ff	1048	*/
bogdanm	0:9b334a45a8ff	1049	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1050	{
bogdanm	0:9b334a45a8ff	1051	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1052	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1055	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1058	{
bogdanm	0:9b334a45a8ff	1059	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1060	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1061	}
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1064	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	/* Return function status */
bogdanm	0:9b334a45a8ff	1067	return HAL_OK;
bogdanm	0:9b334a45a8ff	1068	}
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/**
bogdanm	0:9b334a45a8ff	1071	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1072	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1073	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1074	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1075	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1076	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1077	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1078	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1079	* @retval HAL status
bogdanm	0:9b334a45a8ff	1080	*/
bogdanm	0:9b334a45a8ff	1081	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1082	{
bogdanm	0:9b334a45a8ff	1083	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1084	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1087	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1090	{
bogdanm	0:9b334a45a8ff	1091	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1092	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1096	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1099	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Return function status */
bogdanm	0:9b334a45a8ff	1102	return HAL_OK;
bogdanm	0:9b334a45a8ff	1103	}
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1107	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1108	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1109	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1110	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1111	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1112	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1113	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1114	* @retval HAL status
bogdanm	0:9b334a45a8ff	1115	*/
bogdanm	0:9b334a45a8ff	1116	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1117	{
bogdanm	0:9b334a45a8ff	1118	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1119	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	switch (Channel)
bogdanm	0:9b334a45a8ff	1122	{
bogdanm	0:9b334a45a8ff	1123	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1124	{
bogdanm	0:9b334a45a8ff	1125	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1126	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1127	}
bogdanm	0:9b334a45a8ff	1128	break;
bogdanm	0:9b334a45a8ff	1129
bogdanm	0:9b334a45a8ff	1130	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1131	{
bogdanm	0:9b334a45a8ff	1132	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1133	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1134	}
bogdanm	0:9b334a45a8ff	1135	break;
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1138	{
bogdanm	0:9b334a45a8ff	1139	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1140	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142	break;
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1145	{
bogdanm	0:9b334a45a8ff	1146	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1147	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1148	}
bogdanm	0:9b334a45a8ff	1149	break;
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	default:
bogdanm	0:9b334a45a8ff	1152	break;
bogdanm	0:9b334a45a8ff	1153	}
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1156	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1161	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1162	}
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1165	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	/* Return function status */
bogdanm	0:9b334a45a8ff	1168	return HAL_OK;
bogdanm	0:9b334a45a8ff	1169	}
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/**
bogdanm	0:9b334a45a8ff	1172	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1173	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1174	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1175	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1176	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1177	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1178	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1179	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1180	* @retval HAL status
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1183	{
bogdanm	0:9b334a45a8ff	1184	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1185	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	switch (Channel)
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1192	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1193	}
bogdanm	0:9b334a45a8ff	1194	break;
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1197	{
bogdanm	0:9b334a45a8ff	1198	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1199	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1200	}
bogdanm	0:9b334a45a8ff	1201	break;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1204	{
bogdanm	0:9b334a45a8ff	1205	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1206	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208	break;
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1211	{
bogdanm	0:9b334a45a8ff	1212	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1213	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1214	}
bogdanm	0:9b334a45a8ff	1215	break;
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	default:
bogdanm	0:9b334a45a8ff	1218	break;
bogdanm	0:9b334a45a8ff	1219	}
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1222	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1225	{
bogdanm	0:9b334a45a8ff	1226	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1227	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1228	}
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1231	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	/* Return function status */
bogdanm	0:9b334a45a8ff	1234	return HAL_OK;
bogdanm	0:9b334a45a8ff	1235	}
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/**
bogdanm	0:9b334a45a8ff	1238	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1239	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1240	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1241	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1242	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1243	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1244	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1245	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1246	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	1247	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1248	* @retval HAL status
bogdanm	0:9b334a45a8ff	1249	*/
bogdanm	0:9b334a45a8ff	1250	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1251	{
bogdanm	0:9b334a45a8ff	1252	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1253	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1256	{
bogdanm	0:9b334a45a8ff	1257	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1258	}
bogdanm	0:9b334a45a8ff	1259	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1260	{
bogdanm	0:9b334a45a8ff	1261	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1262	{
bogdanm	0:9b334a45a8ff	1263	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1264	}
bogdanm	0:9b334a45a8ff	1265	else
bogdanm	0:9b334a45a8ff	1266	{
bogdanm	0:9b334a45a8ff	1267	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1268	}
bogdanm	0:9b334a45a8ff	1269	}
bogdanm	0:9b334a45a8ff	1270	switch (Channel)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1273	{
bogdanm	0:9b334a45a8ff	1274	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1275	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1278	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1281	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1284	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	break;
bogdanm	0:9b334a45a8ff	1287
bogdanm	0:9b334a45a8ff	1288	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1289	{
bogdanm	0:9b334a45a8ff	1290	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1291	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1294	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1297	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1300	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1301	}
bogdanm	0:9b334a45a8ff	1302	break;
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1307	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1310	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1313	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1316	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1317	}
bogdanm	0:9b334a45a8ff	1318	break;
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1321	{
bogdanm	0:9b334a45a8ff	1322	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1323	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1326	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1329	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1332	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1333	}
bogdanm	0:9b334a45a8ff	1334	break;
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	default:
bogdanm	0:9b334a45a8ff	1337	break;
bogdanm	0:9b334a45a8ff	1338	}
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1341	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1344	{
bogdanm	0:9b334a45a8ff	1345	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1346	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1347	}
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1350	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Return function status */
bogdanm	0:9b334a45a8ff	1353	return HAL_OK;
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/**
bogdanm	0:9b334a45a8ff	1357	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1358	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1359	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1360	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1361	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1362	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1363	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1364	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1365	* @retval HAL status
bogdanm	0:9b334a45a8ff	1366	*/
bogdanm	0:9b334a45a8ff	1367	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1368	{
bogdanm	0:9b334a45a8ff	1369	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1370	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	switch (Channel)
bogdanm	0:9b334a45a8ff	1373	{
bogdanm	0:9b334a45a8ff	1374	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1375	{
bogdanm	0:9b334a45a8ff	1376	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1377	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379	break;
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1382	{
bogdanm	0:9b334a45a8ff	1383	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1384	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1385	}
bogdanm	0:9b334a45a8ff	1386	break;
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1389	{
bogdanm	0:9b334a45a8ff	1390	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1391	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1392	}
bogdanm	0:9b334a45a8ff	1393	break;
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1396	{
bogdanm	0:9b334a45a8ff	1397	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1398	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1399	}
bogdanm	0:9b334a45a8ff	1400	break;
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	default:
bogdanm	0:9b334a45a8ff	1403	break;
bogdanm	0:9b334a45a8ff	1404	}
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1407	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1412	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1416	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1419	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Return function status */
bogdanm	0:9b334a45a8ff	1422	return HAL_OK;
bogdanm	0:9b334a45a8ff	1423	}
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/**
bogdanm	0:9b334a45a8ff	1426	* @}
bogdanm	0:9b334a45a8ff	1427	*/
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1430	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1431	*
bogdanm	0:9b334a45a8ff	1432	@verbatim
bogdanm	0:9b334a45a8ff	1433	==============================================================================
bogdanm	0:9b334a45a8ff	1434	##### Time Input Capture functions #####
bogdanm	0:9b334a45a8ff	1435	==============================================================================
bogdanm	0:9b334a45a8ff	1436	[..]
bogdanm	0:9b334a45a8ff	1437	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1438	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1439	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1440	(+) Start the Time Input Capture.
bogdanm	0:9b334a45a8ff	1441	(+) Stop the Time Input Capture.
bogdanm	0:9b334a45a8ff	1442	(+) Start the Time Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1443	(+) Stop the Time Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1444	(+) Start the Time Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1445	(+) Stop the Time Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	@endverbatim
bogdanm	0:9b334a45a8ff	1448	* @{
bogdanm	0:9b334a45a8ff	1449	*/
bogdanm	0:9b334a45a8ff	1450	/**
bogdanm	0:9b334a45a8ff	1451	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1452	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1453	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1454	* @retval HAL status
bogdanm	0:9b334a45a8ff	1455	*/
bogdanm	0:9b334a45a8ff	1456	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1457	{
bogdanm	0:9b334a45a8ff	1458	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1459	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	1460	{
bogdanm	0:9b334a45a8ff	1461	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1462	}
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1465	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1466	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1467	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1470	{
bogdanm	0:9b334a45a8ff	1471	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1472	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1476	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1479	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1482	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	return HAL_OK;
bogdanm	0:9b334a45a8ff	1485	}
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/**
bogdanm	0:9b334a45a8ff	1488	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1489	* @param htim: TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1490	* @retval HAL status
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1495	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1498
bogdanm	0:9b334a45a8ff	1499	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1500	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1503	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1506	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	/* Release Lock */
bogdanm	0:9b334a45a8ff	1509	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	return HAL_OK;
bogdanm	0:9b334a45a8ff	1512	}
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	/**
bogdanm	0:9b334a45a8ff	1515	* @brief Initializes the TIM INput Capture MSP.
bogdanm	0:9b334a45a8ff	1516	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1517	* @retval None
bogdanm	0:9b334a45a8ff	1518	*/
bogdanm	0:9b334a45a8ff	1519	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1520	{
bogdanm	0:9b334a45a8ff	1521	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1522	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1523	*/
bogdanm	0:9b334a45a8ff	1524	}
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/**
bogdanm	0:9b334a45a8ff	1527	* @brief DeInitializes TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1528	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1529	* @retval None
bogdanm	0:9b334a45a8ff	1530	*/
bogdanm	0:9b334a45a8ff	1531	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1532	{
bogdanm	0:9b334a45a8ff	1533	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1534	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1535	*/
bogdanm	0:9b334a45a8ff	1536	}
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/**
bogdanm	0:9b334a45a8ff	1539	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1540	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1541	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1542	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1543	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1544	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1545	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1546	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1547	* @retval HAL status
bogdanm	0:9b334a45a8ff	1548	*/
bogdanm	0:9b334a45a8ff	1549	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1550	{
bogdanm	0:9b334a45a8ff	1551	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1552	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1555	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1558	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	/* Return function status */
bogdanm	0:9b334a45a8ff	1561	return HAL_OK;
bogdanm	0:9b334a45a8ff	1562	}
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	/**
bogdanm	0:9b334a45a8ff	1565	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1566	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1567	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1568	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1569	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1570	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1571	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1572	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1573	* @retval HAL status
bogdanm	0:9b334a45a8ff	1574	*/
bogdanm	0:9b334a45a8ff	1575	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1576	{
bogdanm	0:9b334a45a8ff	1577	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1578	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1581	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1584	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/* Return function status */
bogdanm	0:9b334a45a8ff	1587	return HAL_OK;
bogdanm	0:9b334a45a8ff	1588	}
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/**
bogdanm	0:9b334a45a8ff	1591	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1592	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1593	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1594	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1595	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1596	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1597	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1598	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1599	* @retval HAL status
bogdanm	0:9b334a45a8ff	1600	*/
bogdanm	0:9b334a45a8ff	1601	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1602	{
bogdanm	0:9b334a45a8ff	1603	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1604	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	switch (Channel)
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1609	{
bogdanm	0:9b334a45a8ff	1610	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1611	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1612	}
bogdanm	0:9b334a45a8ff	1613	break;
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1616	{
bogdanm	0:9b334a45a8ff	1617	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1618	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1619	}
bogdanm	0:9b334a45a8ff	1620	break;
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1623	{
bogdanm	0:9b334a45a8ff	1624	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1625	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1626	}
bogdanm	0:9b334a45a8ff	1627	break;
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1630	{
bogdanm	0:9b334a45a8ff	1631	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1632	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1633	}
bogdanm	0:9b334a45a8ff	1634	break;
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	default:
bogdanm	0:9b334a45a8ff	1637	break;
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1640	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1641
bogdanm	0:9b334a45a8ff	1642	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1643	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* Return function status */
bogdanm	0:9b334a45a8ff	1646	return HAL_OK;
bogdanm	0:9b334a45a8ff	1647	}
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/**
bogdanm	0:9b334a45a8ff	1650	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1651	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1652	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1653	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1654	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1655	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1656	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1657	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1658	* @retval HAL status
bogdanm	0:9b334a45a8ff	1659	*/
bogdanm	0:9b334a45a8ff	1660	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1661	{
bogdanm	0:9b334a45a8ff	1662	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1663	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	switch (Channel)
bogdanm	0:9b334a45a8ff	1666	{
bogdanm	0:9b334a45a8ff	1667	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1668	{
bogdanm	0:9b334a45a8ff	1669	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1670	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1671	}
bogdanm	0:9b334a45a8ff	1672	break;
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1675	{
bogdanm	0:9b334a45a8ff	1676	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1677	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1678	}
bogdanm	0:9b334a45a8ff	1679	break;
bogdanm	0:9b334a45a8ff	1680
bogdanm	0:9b334a45a8ff	1681	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1682	{
bogdanm	0:9b334a45a8ff	1683	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1684	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1685	}
bogdanm	0:9b334a45a8ff	1686	break;
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1689	{
bogdanm	0:9b334a45a8ff	1690	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1691	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1692	}
bogdanm	0:9b334a45a8ff	1693	break;
bogdanm	0:9b334a45a8ff	1694
bogdanm	0:9b334a45a8ff	1695	default:
bogdanm	0:9b334a45a8ff	1696	break;
bogdanm	0:9b334a45a8ff	1697	}
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1700	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1703	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	/* Return function status */
bogdanm	0:9b334a45a8ff	1706	return HAL_OK;
bogdanm	0:9b334a45a8ff	1707	}
bogdanm	0:9b334a45a8ff	1708
bogdanm	0:9b334a45a8ff	1709	/**
bogdanm	0:9b334a45a8ff	1710	* @brief Starts the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1711	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1712	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	1713	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1714	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1715	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1716	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1717	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1718	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1719	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1720	* @retval HAL status
bogdanm	0:9b334a45a8ff	1721	*/
bogdanm	0:9b334a45a8ff	1722	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1723	{
bogdanm	0:9b334a45a8ff	1724	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1725	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1726	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1729	{
bogdanm	0:9b334a45a8ff	1730	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1731	}
bogdanm	0:9b334a45a8ff	1732	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1733	{
bogdanm	0:9b334a45a8ff	1734	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1735	{
bogdanm	0:9b334a45a8ff	1736	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738	else
bogdanm	0:9b334a45a8ff	1739	{
bogdanm	0:9b334a45a8ff	1740	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1741	}
bogdanm	0:9b334a45a8ff	1742	}
bogdanm	0:9b334a45a8ff	1743
bogdanm	0:9b334a45a8ff	1744	switch (Channel)
bogdanm	0:9b334a45a8ff	1745	{
bogdanm	0:9b334a45a8ff	1746	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1747	{
bogdanm	0:9b334a45a8ff	1748	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1749	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1752	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1753
bogdanm	0:9b334a45a8ff	1754	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1755	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1758	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1759	}
bogdanm	0:9b334a45a8ff	1760	break;
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1763	{
bogdanm	0:9b334a45a8ff	1764	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1765	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1768	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1771	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1772
bogdanm	0:9b334a45a8ff	1773	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1774	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1775	}
bogdanm	0:9b334a45a8ff	1776	break;
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1779	{
bogdanm	0:9b334a45a8ff	1780	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1781	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1784	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1787	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1790	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1791	}
bogdanm	0:9b334a45a8ff	1792	break;
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1795	{
bogdanm	0:9b334a45a8ff	1796	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1797	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1798
bogdanm	0:9b334a45a8ff	1799	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1800	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1801
bogdanm	0:9b334a45a8ff	1802	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1803	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1806	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1807	}
bogdanm	0:9b334a45a8ff	1808	break;
bogdanm	0:9b334a45a8ff	1809
bogdanm	0:9b334a45a8ff	1810	default:
bogdanm	0:9b334a45a8ff	1811	break;
bogdanm	0:9b334a45a8ff	1812	}
bogdanm	0:9b334a45a8ff	1813
bogdanm	0:9b334a45a8ff	1814	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1815	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1816
bogdanm	0:9b334a45a8ff	1817	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1818	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/* Return function status */
bogdanm	0:9b334a45a8ff	1821	return HAL_OK;
bogdanm	0:9b334a45a8ff	1822	}
bogdanm	0:9b334a45a8ff	1823
bogdanm	0:9b334a45a8ff	1824	/**
bogdanm	0:9b334a45a8ff	1825	* @brief Stops the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1826	* @param htim : TIM Input Capture handle
bogdanm	0:9b334a45a8ff	1827	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	1828	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1829	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1830	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1831	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1832	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1833	* @retval HAL status
bogdanm	0:9b334a45a8ff	1834	*/
bogdanm	0:9b334a45a8ff	1835	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1836	{
bogdanm	0:9b334a45a8ff	1837	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1838	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1839	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	switch (Channel)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1844	{
bogdanm	0:9b334a45a8ff	1845	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1846	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1847	}
bogdanm	0:9b334a45a8ff	1848	break;
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1851	{
bogdanm	0:9b334a45a8ff	1852	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1853	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1854	}
bogdanm	0:9b334a45a8ff	1855	break;
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1858	{
bogdanm	0:9b334a45a8ff	1859	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1860	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1861	}
bogdanm	0:9b334a45a8ff	1862	break;
bogdanm	0:9b334a45a8ff	1863
bogdanm	0:9b334a45a8ff	1864	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1867	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1868	}
bogdanm	0:9b334a45a8ff	1869	break;
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	default:
bogdanm	0:9b334a45a8ff	1872	break;
bogdanm	0:9b334a45a8ff	1873	}
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1876	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1877
bogdanm	0:9b334a45a8ff	1878	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1879	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1880
bogdanm	0:9b334a45a8ff	1881	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1882	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1883
bogdanm	0:9b334a45a8ff	1884	/* Return function status */
bogdanm	0:9b334a45a8ff	1885	return HAL_OK;
bogdanm	0:9b334a45a8ff	1886	}
bogdanm	0:9b334a45a8ff	1887	/**
bogdanm	0:9b334a45a8ff	1888	* @}
bogdanm	0:9b334a45a8ff	1889	*/
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1892	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1893	*
bogdanm	0:9b334a45a8ff	1894	@verbatim
bogdanm	0:9b334a45a8ff	1895	==============================================================================
bogdanm	0:9b334a45a8ff	1896	##### Time One Pulse functions #####
bogdanm	0:9b334a45a8ff	1897	==============================================================================
bogdanm	0:9b334a45a8ff	1898	[..]
bogdanm	0:9b334a45a8ff	1899	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1900	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1901	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1902	(+) Start the Time One Pulse.
bogdanm	0:9b334a45a8ff	1903	(+) Stop the Time One Pulse.
bogdanm	0:9b334a45a8ff	1904	(+) Start the Time One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1905	(+) Stop the Time One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1906	(+) Start the Time One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1907	(+) Stop the Time One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1908
bogdanm	0:9b334a45a8ff	1909	@endverbatim
bogdanm	0:9b334a45a8ff	1910	* @{
bogdanm	0:9b334a45a8ff	1911	*/
bogdanm	0:9b334a45a8ff	1912	/**
bogdanm	0:9b334a45a8ff	1913	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1914	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1915	* @param htim: TIM OnePulse handle
bogdanm	0:9b334a45a8ff	1916	* @param OnePulseMode: Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1917	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1918	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1919	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
bogdanm	0:9b334a45a8ff	1920	* @retval HAL status
bogdanm	0:9b334a45a8ff	1921	*/
bogdanm	0:9b334a45a8ff	1922	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	1923	{
bogdanm	0:9b334a45a8ff	1924	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1925	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	1926	{
bogdanm	0:9b334a45a8ff	1927	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1928	}
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1931	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1932	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1933	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1934	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1937	{
bogdanm	0:9b334a45a8ff	1938	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1939	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1943	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	1946	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	1949	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	1952	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1955	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	return HAL_OK;
bogdanm	0:9b334a45a8ff	1958	}
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	/**
bogdanm	0:9b334a45a8ff	1961	* @brief DeInitializes the TIM One Pulse
bogdanm	0:9b334a45a8ff	1962	* @param htim: TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1963	* @retval HAL status
bogdanm	0:9b334a45a8ff	1964	*/
bogdanm	0:9b334a45a8ff	1965	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1966	{
bogdanm	0:9b334a45a8ff	1967	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1968	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1971
bogdanm	0:9b334a45a8ff	1972	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1973	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	1976	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1979	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	/* Release Lock */
bogdanm	0:9b334a45a8ff	1982	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	return HAL_OK;
bogdanm	0:9b334a45a8ff	1985	}
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	/**
bogdanm	0:9b334a45a8ff	1988	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	1989	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	1990	* @retval None
bogdanm	0:9b334a45a8ff	1991	*/
bogdanm	0:9b334a45a8ff	1992	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1993	{
bogdanm	0:9b334a45a8ff	1994	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1995	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1996	*/
bogdanm	0:9b334a45a8ff	1997	}
bogdanm	0:9b334a45a8ff	1998
bogdanm	0:9b334a45a8ff	1999	/**
bogdanm	0:9b334a45a8ff	2000	* @brief DeInitializes TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2001	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2002	* @retval None
bogdanm	0:9b334a45a8ff	2003	*/
bogdanm	0:9b334a45a8ff	2004	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2005	{
bogdanm	0:9b334a45a8ff	2006	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2007	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2008	*/
bogdanm	0:9b334a45a8ff	2009	}
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	/**
bogdanm	0:9b334a45a8ff	2012	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2013	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2014	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2015	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2016	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2017	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2018	* @retval HAL status
bogdanm	0:9b334a45a8ff	2019	*/
bogdanm	0:9b334a45a8ff	2020	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2021	{
bogdanm	0:9b334a45a8ff	2022	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2023	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2024	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2025	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2026	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2029	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2030
bogdanm	0:9b334a45a8ff	2031	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2032	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2033
bogdanm	0:9b334a45a8ff	2034	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2035	{
bogdanm	0:9b334a45a8ff	2036	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2037	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2038	}
bogdanm	0:9b334a45a8ff	2039
bogdanm	0:9b334a45a8ff	2040	/* Return function status */
bogdanm	0:9b334a45a8ff	2041	return HAL_OK;
bogdanm	0:9b334a45a8ff	2042	}
bogdanm	0:9b334a45a8ff	2043
bogdanm	0:9b334a45a8ff	2044	/**
bogdanm	0:9b334a45a8ff	2045	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2046	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2047	* @param OutputChannel : TIM Channels to be disable
bogdanm	0:9b334a45a8ff	2048	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2049	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2050	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2051	* @retval HAL status
bogdanm	0:9b334a45a8ff	2052	*/
bogdanm	0:9b334a45a8ff	2053	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2054	{
bogdanm	0:9b334a45a8ff	2055	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2056	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2057	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2058	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2059	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2062	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2063
bogdanm	0:9b334a45a8ff	2064	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2065	{
bogdanm	0:9b334a45a8ff	2066	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2067	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2068	}
bogdanm	0:9b334a45a8ff	2069
bogdanm	0:9b334a45a8ff	2070	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2071	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2072
bogdanm	0:9b334a45a8ff	2073	/* Return function status */
bogdanm	0:9b334a45a8ff	2074	return HAL_OK;
bogdanm	0:9b334a45a8ff	2075	}
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	/**
bogdanm	0:9b334a45a8ff	2078	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2079	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2080	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2081	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2082	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2083	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2084	* @retval HAL status
bogdanm	0:9b334a45a8ff	2085	*/
bogdanm	0:9b334a45a8ff	2086	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2087	{
bogdanm	0:9b334a45a8ff	2088	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2089	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2090	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2091	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2092	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2095	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2096
bogdanm	0:9b334a45a8ff	2097	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2098	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2099
bogdanm	0:9b334a45a8ff	2100	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2101	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2104	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2107	{
bogdanm	0:9b334a45a8ff	2108	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2109	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2110	}
bogdanm	0:9b334a45a8ff	2111
bogdanm	0:9b334a45a8ff	2112	/* Return function status */
bogdanm	0:9b334a45a8ff	2113	return HAL_OK;
bogdanm	0:9b334a45a8ff	2114	}
bogdanm	0:9b334a45a8ff	2115
bogdanm	0:9b334a45a8ff	2116	/**
bogdanm	0:9b334a45a8ff	2117	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2118	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	2119	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2120	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2121	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2122	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2123	* @retval HAL status
bogdanm	0:9b334a45a8ff	2124	*/
bogdanm	0:9b334a45a8ff	2125	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2126	{
bogdanm	0:9b334a45a8ff	2127	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2128	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2131	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2134	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2135	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2136	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2137	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2138	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2139	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2142	{
bogdanm	0:9b334a45a8ff	2143	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	2144	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2145	}
bogdanm	0:9b334a45a8ff	2146
bogdanm	0:9b334a45a8ff	2147	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2148	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	/* Return function status */
bogdanm	0:9b334a45a8ff	2151	return HAL_OK;
bogdanm	0:9b334a45a8ff	2152	}
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	/**
bogdanm	0:9b334a45a8ff	2155	* @}
bogdanm	0:9b334a45a8ff	2156	*/
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	2159	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2160	*
bogdanm	0:9b334a45a8ff	2161	@verbatim
bogdanm	0:9b334a45a8ff	2162	==============================================================================
bogdanm	0:9b334a45a8ff	2163	##### Time Encoder functions #####
bogdanm	0:9b334a45a8ff	2164	==============================================================================
bogdanm	0:9b334a45a8ff	2165	[..]
bogdanm	0:9b334a45a8ff	2166	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2167	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2168	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2169	(+) Start the Time Encoder.
bogdanm	0:9b334a45a8ff	2170	(+) Stop the Time Encoder.
bogdanm	0:9b334a45a8ff	2171	(+) Start the Time Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2172	(+) Stop the Time Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2173	(+) Start the Time Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2174	(+) Stop the Time Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2175
bogdanm	0:9b334a45a8ff	2176	@endverbatim
bogdanm	0:9b334a45a8ff	2177	* @{
bogdanm	0:9b334a45a8ff	2178	*/
bogdanm	0:9b334a45a8ff	2179	/**
bogdanm	0:9b334a45a8ff	2180	* @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	2181	* @param htim: TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2182	* @param sConfig: TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2183	* @retval HAL status
bogdanm	0:9b334a45a8ff	2184	*/
bogdanm	0:9b334a45a8ff	2185	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2186	{
bogdanm	0:9b334a45a8ff	2187	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2188	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2189	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2192	if(htim == HAL_NULL)
bogdanm	0:9b334a45a8ff	2193	{
bogdanm	0:9b334a45a8ff	2194	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2195	}
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2198	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2199	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2200	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2201	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2202	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2203	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2204	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2205	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2206	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2207	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2210	{
bogdanm	0:9b334a45a8ff	2211	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2212	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2213	}
bogdanm	0:9b334a45a8ff	2214
bogdanm	0:9b334a45a8ff	2215	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2216	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2219	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2222	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2225	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2228	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2229
bogdanm	0:9b334a45a8ff	2230	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2231	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2232
bogdanm	0:9b334a45a8ff	2233	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2234	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2237	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2238	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2239
bogdanm	0:9b334a45a8ff	2240	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2241	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2242	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2243	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2244	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2247	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2248	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2249	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2250
bogdanm	0:9b334a45a8ff	2251	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2252	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2253
bogdanm	0:9b334a45a8ff	2254	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2255	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2256
bogdanm	0:9b334a45a8ff	2257	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2258	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2259
bogdanm	0:9b334a45a8ff	2260	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2261	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2262
bogdanm	0:9b334a45a8ff	2263	return HAL_OK;
bogdanm	0:9b334a45a8ff	2264	}
bogdanm	0:9b334a45a8ff	2265
bogdanm	0:9b334a45a8ff	2266
bogdanm	0:9b334a45a8ff	2267	/**
bogdanm	0:9b334a45a8ff	2268	* @brief DeInitializes the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2269	* @param htim: TIM Encoder handle
bogdanm	0:9b334a45a8ff	2270	* @retval HAL status
bogdanm	0:9b334a45a8ff	2271	*/
bogdanm	0:9b334a45a8ff	2272	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2273	{
bogdanm	0:9b334a45a8ff	2274	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2275	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2278
bogdanm	0:9b334a45a8ff	2279	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2280	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2281
bogdanm	0:9b334a45a8ff	2282	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2283	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2286	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2287
bogdanm	0:9b334a45a8ff	2288	/* Release Lock */
bogdanm	0:9b334a45a8ff	2289	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2290
bogdanm	0:9b334a45a8ff	2291	return HAL_OK;
bogdanm	0:9b334a45a8ff	2292	}
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	/**
bogdanm	0:9b334a45a8ff	2295	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2296	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2297	* @retval None
bogdanm	0:9b334a45a8ff	2298	*/
bogdanm	0:9b334a45a8ff	2299	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2300	{
bogdanm	0:9b334a45a8ff	2301	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2302	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2303	*/
bogdanm	0:9b334a45a8ff	2304	}
bogdanm	0:9b334a45a8ff	2305
bogdanm	0:9b334a45a8ff	2306	/**
bogdanm	0:9b334a45a8ff	2307	* @brief DeInitializes TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2308	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2309	* @retval None
bogdanm	0:9b334a45a8ff	2310	*/
bogdanm	0:9b334a45a8ff	2311	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2312	{
bogdanm	0:9b334a45a8ff	2313	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2314	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2315	*/
bogdanm	0:9b334a45a8ff	2316	}
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/**
bogdanm	0:9b334a45a8ff	2319	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2320	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2321	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2322	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2323	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2324	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2325	* @retval HAL status
bogdanm	0:9b334a45a8ff	2326	*/
bogdanm	0:9b334a45a8ff	2327	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2328	{
bogdanm	0:9b334a45a8ff	2329	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2330	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2331
bogdanm	0:9b334a45a8ff	2332	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2333	switch (Channel)
bogdanm	0:9b334a45a8ff	2334	{
bogdanm	0:9b334a45a8ff	2335	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2336	{
bogdanm	0:9b334a45a8ff	2337	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2338	break;
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2341	{
bogdanm	0:9b334a45a8ff	2342	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2343	break;
bogdanm	0:9b334a45a8ff	2344	}
bogdanm	0:9b334a45a8ff	2345	default :
bogdanm	0:9b334a45a8ff	2346	{
bogdanm	0:9b334a45a8ff	2347	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2348	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2349	break;
bogdanm	0:9b334a45a8ff	2350	}
bogdanm	0:9b334a45a8ff	2351	}
bogdanm	0:9b334a45a8ff	2352	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2353	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2354
bogdanm	0:9b334a45a8ff	2355	/* Return function status */
bogdanm	0:9b334a45a8ff	2356	return HAL_OK;
bogdanm	0:9b334a45a8ff	2357	}
bogdanm	0:9b334a45a8ff	2358
bogdanm	0:9b334a45a8ff	2359	/**
bogdanm	0:9b334a45a8ff	2360	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2361	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2362	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2363	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2364	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2365	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2366	* @retval HAL status
bogdanm	0:9b334a45a8ff	2367	*/
bogdanm	0:9b334a45a8ff	2368	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2369	{
bogdanm	0:9b334a45a8ff	2370	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2371	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2372
bogdanm	0:9b334a45a8ff	2373	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2374	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2375	switch (Channel)
bogdanm	0:9b334a45a8ff	2376	{
bogdanm	0:9b334a45a8ff	2377	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2378	{
bogdanm	0:9b334a45a8ff	2379	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2380	break;
bogdanm	0:9b334a45a8ff	2381	}
bogdanm	0:9b334a45a8ff	2382	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2383	{
bogdanm	0:9b334a45a8ff	2384	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2385	break;
bogdanm	0:9b334a45a8ff	2386	}
bogdanm	0:9b334a45a8ff	2387	default :
bogdanm	0:9b334a45a8ff	2388	{
bogdanm	0:9b334a45a8ff	2389	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2390	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2391	break;
bogdanm	0:9b334a45a8ff	2392	}
bogdanm	0:9b334a45a8ff	2393	}
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2396	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	/* Return function status */
bogdanm	0:9b334a45a8ff	2399	return HAL_OK;
bogdanm	0:9b334a45a8ff	2400	}
bogdanm	0:9b334a45a8ff	2401
bogdanm	0:9b334a45a8ff	2402	/**
bogdanm	0:9b334a45a8ff	2403	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2404	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2405	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2406	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2407	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2408	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2409	* @retval HAL status
bogdanm	0:9b334a45a8ff	2410	*/
bogdanm	0:9b334a45a8ff	2411	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2412	{
bogdanm	0:9b334a45a8ff	2413	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2414	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2415
bogdanm	0:9b334a45a8ff	2416	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2417	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2418	switch (Channel)
bogdanm	0:9b334a45a8ff	2419	{
bogdanm	0:9b334a45a8ff	2420	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2421	{
bogdanm	0:9b334a45a8ff	2422	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2423	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2424	break;
bogdanm	0:9b334a45a8ff	2425	}
bogdanm	0:9b334a45a8ff	2426	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2427	{
bogdanm	0:9b334a45a8ff	2428	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2429	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2430	break;
bogdanm	0:9b334a45a8ff	2431	}
bogdanm	0:9b334a45a8ff	2432	default :
bogdanm	0:9b334a45a8ff	2433	{
bogdanm	0:9b334a45a8ff	2434	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2435	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2436	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2437	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2438	break;
bogdanm	0:9b334a45a8ff	2439	}
bogdanm	0:9b334a45a8ff	2440	}
bogdanm	0:9b334a45a8ff	2441
bogdanm	0:9b334a45a8ff	2442	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2443	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2444
bogdanm	0:9b334a45a8ff	2445	/* Return function status */
bogdanm	0:9b334a45a8ff	2446	return HAL_OK;
bogdanm	0:9b334a45a8ff	2447	}
bogdanm	0:9b334a45a8ff	2448
bogdanm	0:9b334a45a8ff	2449	/**
bogdanm	0:9b334a45a8ff	2450	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2451	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2452	* @param Channel : TIM Channels to be disabled
bogdanm	0:9b334a45a8ff	2453	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2454	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2455	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2456	* @retval HAL status
bogdanm	0:9b334a45a8ff	2457	*/
bogdanm	0:9b334a45a8ff	2458	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2459	{
bogdanm	0:9b334a45a8ff	2460	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2461	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2462
bogdanm	0:9b334a45a8ff	2463	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2464	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2465	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2466	{
bogdanm	0:9b334a45a8ff	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2468
bogdanm	0:9b334a45a8ff	2469	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2470	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2471	}
bogdanm	0:9b334a45a8ff	2472	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2473	{
bogdanm	0:9b334a45a8ff	2474	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2475
bogdanm	0:9b334a45a8ff	2476	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2477	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2478	}
bogdanm	0:9b334a45a8ff	2479	else
bogdanm	0:9b334a45a8ff	2480	{
bogdanm	0:9b334a45a8ff	2481	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2482	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2483
bogdanm	0:9b334a45a8ff	2484	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2485	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2486	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2487	}
bogdanm	0:9b334a45a8ff	2488
bogdanm	0:9b334a45a8ff	2489	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2490	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2491
bogdanm	0:9b334a45a8ff	2492	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2493	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2494
bogdanm	0:9b334a45a8ff	2495	/* Return function status */
bogdanm	0:9b334a45a8ff	2496	return HAL_OK;
bogdanm	0:9b334a45a8ff	2497	}
bogdanm	0:9b334a45a8ff	2498
bogdanm	0:9b334a45a8ff	2499	/**
bogdanm	0:9b334a45a8ff	2500	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2501	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2502	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2503	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2504	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2505	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2506	* @param pData1: The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2507	* @param pData2: The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2508	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2509	* @retval HAL status
bogdanm	0:9b334a45a8ff	2510	*/
bogdanm	0:9b334a45a8ff	2511	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2512	{
bogdanm	0:9b334a45a8ff	2513	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2514	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2515
bogdanm	0:9b334a45a8ff	2516	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2517	{
bogdanm	0:9b334a45a8ff	2518	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2519	}
bogdanm	0:9b334a45a8ff	2520	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2521	{
bogdanm	0:9b334a45a8ff	2522	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2523	{
bogdanm	0:9b334a45a8ff	2524	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2525	}
bogdanm	0:9b334a45a8ff	2526	else
bogdanm	0:9b334a45a8ff	2527	{
bogdanm	0:9b334a45a8ff	2528	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2529	}
bogdanm	0:9b334a45a8ff	2530	}
bogdanm	0:9b334a45a8ff	2531
bogdanm	0:9b334a45a8ff	2532	switch (Channel)
bogdanm	0:9b334a45a8ff	2533	{
bogdanm	0:9b334a45a8ff	2534	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2535	{
bogdanm	0:9b334a45a8ff	2536	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2537	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2540	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2541
bogdanm	0:9b334a45a8ff	2542	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2543	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2546	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2547
bogdanm	0:9b334a45a8ff	2548	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2549	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2550
bogdanm	0:9b334a45a8ff	2551	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2552	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2553	}
bogdanm	0:9b334a45a8ff	2554	break;
bogdanm	0:9b334a45a8ff	2555
bogdanm	0:9b334a45a8ff	2556	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2557	{
bogdanm	0:9b334a45a8ff	2558	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2559	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2560
bogdanm	0:9b334a45a8ff	2561	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2562	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
bogdanm	0:9b334a45a8ff	2563	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2564	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2565
bogdanm	0:9b334a45a8ff	2566	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2567	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2568
bogdanm	0:9b334a45a8ff	2569	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2570	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2571
bogdanm	0:9b334a45a8ff	2572	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2573	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2574	}
bogdanm	0:9b334a45a8ff	2575	break;
bogdanm	0:9b334a45a8ff	2576
bogdanm	0:9b334a45a8ff	2577	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2578	{
bogdanm	0:9b334a45a8ff	2579	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2580	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2581
bogdanm	0:9b334a45a8ff	2582	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2583	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2584
bogdanm	0:9b334a45a8ff	2585	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2586	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2589	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2590
bogdanm	0:9b334a45a8ff	2591	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2592	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2595	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2596
bogdanm	0:9b334a45a8ff	2597	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2598	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2599
bogdanm	0:9b334a45a8ff	2600	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2601	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2602	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2605	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2606	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2607	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2608	}
bogdanm	0:9b334a45a8ff	2609	break;
bogdanm	0:9b334a45a8ff	2610
bogdanm	0:9b334a45a8ff	2611	default:
bogdanm	0:9b334a45a8ff	2612	break;
bogdanm	0:9b334a45a8ff	2613	}
bogdanm	0:9b334a45a8ff	2614	/* Return function status */
bogdanm	0:9b334a45a8ff	2615	return HAL_OK;
bogdanm	0:9b334a45a8ff	2616	}
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	/**
bogdanm	0:9b334a45a8ff	2619	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2620	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	2621	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2622	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2623	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2624	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2625	* @retval HAL status
bogdanm	0:9b334a45a8ff	2626	*/
bogdanm	0:9b334a45a8ff	2627	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2628	{
bogdanm	0:9b334a45a8ff	2629	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2630	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2631
bogdanm	0:9b334a45a8ff	2632	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2633	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2634	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2635	{
bogdanm	0:9b334a45a8ff	2636	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2637
bogdanm	0:9b334a45a8ff	2638	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2639	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2640	}
bogdanm	0:9b334a45a8ff	2641	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2642	{
bogdanm	0:9b334a45a8ff	2643	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2646	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2647	}
bogdanm	0:9b334a45a8ff	2648	else
bogdanm	0:9b334a45a8ff	2649	{
bogdanm	0:9b334a45a8ff	2650	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2651	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2654	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2655	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2656	}
bogdanm	0:9b334a45a8ff	2657
bogdanm	0:9b334a45a8ff	2658	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2659	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2660
bogdanm	0:9b334a45a8ff	2661	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2662	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2663
bogdanm	0:9b334a45a8ff	2664	/* Return function status */
bogdanm	0:9b334a45a8ff	2665	return HAL_OK;
bogdanm	0:9b334a45a8ff	2666	}
bogdanm	0:9b334a45a8ff	2667
bogdanm	0:9b334a45a8ff	2668	/**
bogdanm	0:9b334a45a8ff	2669	* @}
bogdanm	0:9b334a45a8ff	2670	*/
bogdanm	0:9b334a45a8ff	2671	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	2672	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2673	*
bogdanm	0:9b334a45a8ff	2674	@verbatim
bogdanm	0:9b334a45a8ff	2675	==============================================================================
bogdanm	0:9b334a45a8ff	2676	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2677	==============================================================================
bogdanm	0:9b334a45a8ff	2678	[..]
bogdanm	0:9b334a45a8ff	2679	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2680
bogdanm	0:9b334a45a8ff	2681	@endverbatim
bogdanm	0:9b334a45a8ff	2682	* @{
bogdanm	0:9b334a45a8ff	2683	*/
bogdanm	0:9b334a45a8ff	2684	/**
bogdanm	0:9b334a45a8ff	2685	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2686	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	2687	* @retval None
bogdanm	0:9b334a45a8ff	2688	*/
bogdanm	0:9b334a45a8ff	2689	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2690	{
bogdanm	0:9b334a45a8ff	2691	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2692	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2693	{
bogdanm	0:9b334a45a8ff	2694	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2695	{
bogdanm	0:9b334a45a8ff	2696	{
bogdanm	0:9b334a45a8ff	2697	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2698	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2699
bogdanm	0:9b334a45a8ff	2700	/* Input capture event */
bogdanm	0:9b334a45a8ff	2701	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2702	{
bogdanm	0:9b334a45a8ff	2703	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2704	}
bogdanm	0:9b334a45a8ff	2705	/* Output compare event */
bogdanm	0:9b334a45a8ff	2706	else
bogdanm	0:9b334a45a8ff	2707	{
bogdanm	0:9b334a45a8ff	2708	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2709	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2710	}
bogdanm	0:9b334a45a8ff	2711	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2712	}
bogdanm	0:9b334a45a8ff	2713	}
bogdanm	0:9b334a45a8ff	2714	}
bogdanm	0:9b334a45a8ff	2715	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2716	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2717	{
bogdanm	0:9b334a45a8ff	2718	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2719	{
bogdanm	0:9b334a45a8ff	2720	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2721	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2722	/* Input capture event */
bogdanm	0:9b334a45a8ff	2723	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2724	{
bogdanm	0:9b334a45a8ff	2725	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2726	}
bogdanm	0:9b334a45a8ff	2727	/* Output compare event */
bogdanm	0:9b334a45a8ff	2728	else
bogdanm	0:9b334a45a8ff	2729	{
bogdanm	0:9b334a45a8ff	2730	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2731	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2732	}
bogdanm	0:9b334a45a8ff	2733	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2734	}
bogdanm	0:9b334a45a8ff	2735	}
bogdanm	0:9b334a45a8ff	2736	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2737	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2738	{
bogdanm	0:9b334a45a8ff	2739	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2740	{
bogdanm	0:9b334a45a8ff	2741	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2742	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2743	/* Input capture event */
bogdanm	0:9b334a45a8ff	2744	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2745	{
bogdanm	0:9b334a45a8ff	2746	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2747	}
bogdanm	0:9b334a45a8ff	2748	/* Output compare event */
bogdanm	0:9b334a45a8ff	2749	else
bogdanm	0:9b334a45a8ff	2750	{
bogdanm	0:9b334a45a8ff	2751	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2752	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2753	}
bogdanm	0:9b334a45a8ff	2754	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2755	}
bogdanm	0:9b334a45a8ff	2756	}
bogdanm	0:9b334a45a8ff	2757	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2758	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2759	{
bogdanm	0:9b334a45a8ff	2760	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2761	{
bogdanm	0:9b334a45a8ff	2762	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2763	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2764	/* Input capture event */
bogdanm	0:9b334a45a8ff	2765	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2766	{
bogdanm	0:9b334a45a8ff	2767	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2768	}
bogdanm	0:9b334a45a8ff	2769	/* Output compare event */
bogdanm	0:9b334a45a8ff	2770	else
bogdanm	0:9b334a45a8ff	2771	{
bogdanm	0:9b334a45a8ff	2772	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2773	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2774	}
bogdanm	0:9b334a45a8ff	2775	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2776	}
bogdanm	0:9b334a45a8ff	2777	}
bogdanm	0:9b334a45a8ff	2778	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2779	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2780	{
bogdanm	0:9b334a45a8ff	2781	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2782	{
bogdanm	0:9b334a45a8ff	2783	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2784	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2785	}
bogdanm	0:9b334a45a8ff	2786	}
bogdanm	0:9b334a45a8ff	2787	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2788	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm	0:9b334a45a8ff	2789	{
bogdanm	0:9b334a45a8ff	2790	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2791	{
bogdanm	0:9b334a45a8ff	2792	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2793	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2794	}
bogdanm	0:9b334a45a8ff	2795	}
bogdanm	0:9b334a45a8ff	2796	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2797	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2798	{
bogdanm	0:9b334a45a8ff	2799	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2800	{
bogdanm	0:9b334a45a8ff	2801	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2802	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2803	}
bogdanm	0:9b334a45a8ff	2804	}
bogdanm	0:9b334a45a8ff	2805	/* TIM commutation event */
bogdanm	0:9b334a45a8ff	2806	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm	0:9b334a45a8ff	2807	{
bogdanm	0:9b334a45a8ff	2808	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
bogdanm	0:9b334a45a8ff	2809	{
bogdanm	0:9b334a45a8ff	2810	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm	0:9b334a45a8ff	2811	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2812	}
bogdanm	0:9b334a45a8ff	2813	}
bogdanm	0:9b334a45a8ff	2814	}
bogdanm	0:9b334a45a8ff	2815
bogdanm	0:9b334a45a8ff	2816	/**
bogdanm	0:9b334a45a8ff	2817	* @}
bogdanm	0:9b334a45a8ff	2818	*/
bogdanm	0:9b334a45a8ff	2819
bogdanm	0:9b334a45a8ff	2820	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2821	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2822	*
bogdanm	0:9b334a45a8ff	2823	@verbatim
bogdanm	0:9b334a45a8ff	2824	==============================================================================
bogdanm	0:9b334a45a8ff	2825	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2826	==============================================================================
bogdanm	0:9b334a45a8ff	2827	[..]
bogdanm	0:9b334a45a8ff	2828	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2829	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2830	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2831	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	2832	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2833	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2834
bogdanm	0:9b334a45a8ff	2835	@endverbatim
bogdanm	0:9b334a45a8ff	2836	* @{
bogdanm	0:9b334a45a8ff	2837	*/
bogdanm	0:9b334a45a8ff	2838
bogdanm	0:9b334a45a8ff	2839	/**
bogdanm	0:9b334a45a8ff	2840	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2841	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2842	* @param htim: TIM Output Compare handle
bogdanm	0:9b334a45a8ff	2843	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2844	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2845	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2846	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2847	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2848	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2849	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2850	* @retval HAL status
bogdanm	0:9b334a45a8ff	2851	*/
bogdanm	0:9b334a45a8ff	2852	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2853	{
bogdanm	0:9b334a45a8ff	2854	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2855	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2856	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2857	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2858	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	2859	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	2860	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	2861
bogdanm	0:9b334a45a8ff	2862	/* Check input state */
bogdanm	0:9b334a45a8ff	2863	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2864
bogdanm	0:9b334a45a8ff	2865	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2866
bogdanm	0:9b334a45a8ff	2867	switch (Channel)
bogdanm	0:9b334a45a8ff	2868	{
bogdanm	0:9b334a45a8ff	2869	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2870	{
bogdanm	0:9b334a45a8ff	2871	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2872	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2873	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2874	}
bogdanm	0:9b334a45a8ff	2875	break;
bogdanm	0:9b334a45a8ff	2876
bogdanm	0:9b334a45a8ff	2877	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2878	{
bogdanm	0:9b334a45a8ff	2879	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2880	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	2881	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2882	}
bogdanm	0:9b334a45a8ff	2883	break;
bogdanm	0:9b334a45a8ff	2884
bogdanm	0:9b334a45a8ff	2885	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2886	{
bogdanm	0:9b334a45a8ff	2887	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2888	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	2889	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2890	}
bogdanm	0:9b334a45a8ff	2891	break;
bogdanm	0:9b334a45a8ff	2892
bogdanm	0:9b334a45a8ff	2893	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2894	{
bogdanm	0:9b334a45a8ff	2895	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2896	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	2897	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2898	}
bogdanm	0:9b334a45a8ff	2899	break;
bogdanm	0:9b334a45a8ff	2900
bogdanm	0:9b334a45a8ff	2901	default:
bogdanm	0:9b334a45a8ff	2902	break;
bogdanm	0:9b334a45a8ff	2903	}
bogdanm	0:9b334a45a8ff	2904	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2905
bogdanm	0:9b334a45a8ff	2906	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2907
bogdanm	0:9b334a45a8ff	2908	return HAL_OK;
bogdanm	0:9b334a45a8ff	2909	}
bogdanm	0:9b334a45a8ff	2910
bogdanm	0:9b334a45a8ff	2911	/**
bogdanm	0:9b334a45a8ff	2912	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	2913	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2914	* @param htim: TIM IC handle
bogdanm	0:9b334a45a8ff	2915	* @param sConfig: TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	2916	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	2917	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2918	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2919	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2920	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2921	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2922	* @retval HAL status
bogdanm	0:9b334a45a8ff	2923	*/
bogdanm	0:9b334a45a8ff	2924	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2925	{
bogdanm	0:9b334a45a8ff	2926	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2927	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2928	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	2929	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	2930	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	2931	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	2932
bogdanm	0:9b334a45a8ff	2933	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2934
bogdanm	0:9b334a45a8ff	2935	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2938	{
bogdanm	0:9b334a45a8ff	2939	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	2940	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2941	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2942	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2943	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	2946	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	2947
bogdanm	0:9b334a45a8ff	2948	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	2949	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	2950	}
bogdanm	0:9b334a45a8ff	2951	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2952	{
bogdanm	0:9b334a45a8ff	2953	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	2954	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2955
bogdanm	0:9b334a45a8ff	2956	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2957	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2958	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2959	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2960
bogdanm	0:9b334a45a8ff	2961	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	2962	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	2963
bogdanm	0:9b334a45a8ff	2964	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	2965	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	2966	}
bogdanm	0:9b334a45a8ff	2967	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	2968	{
bogdanm	0:9b334a45a8ff	2969	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	2970	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2971
bogdanm	0:9b334a45a8ff	2972	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2973	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2974	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2975	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	2978	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	2979
bogdanm	0:9b334a45a8ff	2980	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	2981	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	2982	}
bogdanm	0:9b334a45a8ff	2983	else
bogdanm	0:9b334a45a8ff	2984	{
bogdanm	0:9b334a45a8ff	2985	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	2986	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2987
bogdanm	0:9b334a45a8ff	2988	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	2989	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	2990	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	2991	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	2992
bogdanm	0:9b334a45a8ff	2993	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	2994	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	2995
bogdanm	0:9b334a45a8ff	2996	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	2997	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	2998	}
bogdanm	0:9b334a45a8ff	2999
bogdanm	0:9b334a45a8ff	3000	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3001
bogdanm	0:9b334a45a8ff	3002	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3003
bogdanm	0:9b334a45a8ff	3004	return HAL_OK;
bogdanm	0:9b334a45a8ff	3005	}
bogdanm	0:9b334a45a8ff	3006
bogdanm	0:9b334a45a8ff	3007	/**
bogdanm	0:9b334a45a8ff	3008	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	3009	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3010	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3011	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	3012	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3013	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3014	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3015	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3016	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3017	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3018	* @retval HAL status
bogdanm	0:9b334a45a8ff	3019	*/
bogdanm	0:9b334a45a8ff	3020	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3021	{
bogdanm	0:9b334a45a8ff	3022	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3023
bogdanm	0:9b334a45a8ff	3024	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3025	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3026	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3027	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3028	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	3029	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3030	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	3031	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	3032
bogdanm	0:9b334a45a8ff	3033	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3034
bogdanm	0:9b334a45a8ff	3035	switch (Channel)
bogdanm	0:9b334a45a8ff	3036	{
bogdanm	0:9b334a45a8ff	3037	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3038	{
bogdanm	0:9b334a45a8ff	3039	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3040	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3041	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3042
bogdanm	0:9b334a45a8ff	3043	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3044	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3045
bogdanm	0:9b334a45a8ff	3046	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3047	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3048	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3049	}
bogdanm	0:9b334a45a8ff	3050	break;
bogdanm	0:9b334a45a8ff	3051
bogdanm	0:9b334a45a8ff	3052	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3053	{
bogdanm	0:9b334a45a8ff	3054	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3055	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3056	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3057
bogdanm	0:9b334a45a8ff	3058	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3059	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3060
bogdanm	0:9b334a45a8ff	3061	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3062	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3063	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3064	}
bogdanm	0:9b334a45a8ff	3065	break;
bogdanm	0:9b334a45a8ff	3066
bogdanm	0:9b334a45a8ff	3067	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3068	{
bogdanm	0:9b334a45a8ff	3069	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3070	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3071	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3072
bogdanm	0:9b334a45a8ff	3073	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3074	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3075
bogdanm	0:9b334a45a8ff	3076	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3077	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3078	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3079	}
bogdanm	0:9b334a45a8ff	3080	break;
bogdanm	0:9b334a45a8ff	3081
bogdanm	0:9b334a45a8ff	3082	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3083	{
bogdanm	0:9b334a45a8ff	3084	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3085	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3086	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3087
bogdanm	0:9b334a45a8ff	3088	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3089	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3090
bogdanm	0:9b334a45a8ff	3091	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3092	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3093	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3094	}
bogdanm	0:9b334a45a8ff	3095	break;
bogdanm	0:9b334a45a8ff	3096
bogdanm	0:9b334a45a8ff	3097	default:
bogdanm	0:9b334a45a8ff	3098	break;
bogdanm	0:9b334a45a8ff	3099	}
bogdanm	0:9b334a45a8ff	3100
bogdanm	0:9b334a45a8ff	3101	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3102
bogdanm	0:9b334a45a8ff	3103	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3104
bogdanm	0:9b334a45a8ff	3105	return HAL_OK;
bogdanm	0:9b334a45a8ff	3106	}
bogdanm	0:9b334a45a8ff	3107
bogdanm	0:9b334a45a8ff	3108	/**
bogdanm	0:9b334a45a8ff	3109	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3110	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3111	* @param htim: TIM One Pulse handle
bogdanm	0:9b334a45a8ff	3112	* @param sConfig: TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3113	* @param OutputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3114	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3115	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3116	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3117	* @param InputChannel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	3118	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3119	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3120	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3121	* @retval HAL status
bogdanm	0:9b334a45a8ff	3122	*/
bogdanm	0:9b334a45a8ff	3123	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3124	{
bogdanm	0:9b334a45a8ff	3125	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3126
bogdanm	0:9b334a45a8ff	3127	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3128	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3129	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3130
bogdanm	0:9b334a45a8ff	3131	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3132	{
bogdanm	0:9b334a45a8ff	3133	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3134
bogdanm	0:9b334a45a8ff	3135	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3136
bogdanm	0:9b334a45a8ff	3137	/* Extract the Ouput compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3138	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3139	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3140	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3141	temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm	0:9b334a45a8ff	3142	temp1.OCIdleState = sConfig->OCIdleState;
bogdanm	0:9b334a45a8ff	3143	temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm	0:9b334a45a8ff	3144
bogdanm	0:9b334a45a8ff	3145	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3146	{
bogdanm	0:9b334a45a8ff	3147	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3148	{
bogdanm	0:9b334a45a8ff	3149	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3150
bogdanm	0:9b334a45a8ff	3151	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3152	}
bogdanm	0:9b334a45a8ff	3153	break;
bogdanm	0:9b334a45a8ff	3154	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3155	{
bogdanm	0:9b334a45a8ff	3156	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3157
bogdanm	0:9b334a45a8ff	3158	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3159	}
bogdanm	0:9b334a45a8ff	3160	break;
bogdanm	0:9b334a45a8ff	3161	default:
bogdanm	0:9b334a45a8ff	3162	break;
bogdanm	0:9b334a45a8ff	3163	}
bogdanm	0:9b334a45a8ff	3164	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3165	{
bogdanm	0:9b334a45a8ff	3166	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3167	{
bogdanm	0:9b334a45a8ff	3168	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3169
bogdanm	0:9b334a45a8ff	3170	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3171	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3172
bogdanm	0:9b334a45a8ff	3173	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3174	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3175
bogdanm	0:9b334a45a8ff	3176	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3177	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3178	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3179
bogdanm	0:9b334a45a8ff	3180	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3181	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3182	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3183	}
bogdanm	0:9b334a45a8ff	3184	break;
bogdanm	0:9b334a45a8ff	3185	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3186	{
bogdanm	0:9b334a45a8ff	3187	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3188
bogdanm	0:9b334a45a8ff	3189	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3190	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3191
bogdanm	0:9b334a45a8ff	3192	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3193	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3194
bogdanm	0:9b334a45a8ff	3195	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3196	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3197	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3198
bogdanm	0:9b334a45a8ff	3199	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3200	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3201	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3202	}
bogdanm	0:9b334a45a8ff	3203	break;
bogdanm	0:9b334a45a8ff	3204
bogdanm	0:9b334a45a8ff	3205	default:
bogdanm	0:9b334a45a8ff	3206	break;
bogdanm	0:9b334a45a8ff	3207	}
bogdanm	0:9b334a45a8ff	3208
bogdanm	0:9b334a45a8ff	3209	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3210
bogdanm	0:9b334a45a8ff	3211	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3212
bogdanm	0:9b334a45a8ff	3213	return HAL_OK;
bogdanm	0:9b334a45a8ff	3214	}
bogdanm	0:9b334a45a8ff	3215	else
bogdanm	0:9b334a45a8ff	3216	{
bogdanm	0:9b334a45a8ff	3217	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3218	}
bogdanm	0:9b334a45a8ff	3219	}
bogdanm	0:9b334a45a8ff	3220
bogdanm	0:9b334a45a8ff	3221	/**
bogdanm	0:9b334a45a8ff	3222	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3223	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3224	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
bogdanm	0:9b334a45a8ff	3225	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3226	* @arg TIM_DMABase_CR1
bogdanm	0:9b334a45a8ff	3227	* @arg TIM_DMABase_CR2
bogdanm	0:9b334a45a8ff	3228	* @arg TIM_DMABase_SMCR
bogdanm	0:9b334a45a8ff	3229	* @arg TIM_DMABase_DIER
bogdanm	0:9b334a45a8ff	3230	* @arg TIM_DMABase_SR
bogdanm	0:9b334a45a8ff	3231	* @arg TIM_DMABase_EGR
bogdanm	0:9b334a45a8ff	3232	* @arg TIM_DMABase_CCMR1
bogdanm	0:9b334a45a8ff	3233	* @arg TIM_DMABase_CCMR2
bogdanm	0:9b334a45a8ff	3234	* @arg TIM_DMABase_CCER
bogdanm	0:9b334a45a8ff	3235	* @arg TIM_DMABase_CNT
bogdanm	0:9b334a45a8ff	3236	* @arg TIM_DMABase_PSC
bogdanm	0:9b334a45a8ff	3237	* @arg TIM_DMABase_ARR
bogdanm	0:9b334a45a8ff	3238	* @arg TIM_DMABase_RCR
bogdanm	0:9b334a45a8ff	3239	* @arg TIM_DMABase_CCR1
bogdanm	0:9b334a45a8ff	3240	* @arg TIM_DMABase_CCR2
bogdanm	0:9b334a45a8ff	3241	* @arg TIM_DMABase_CCR3
bogdanm	0:9b334a45a8ff	3242	* @arg TIM_DMABase_CCR4
bogdanm	0:9b334a45a8ff	3243	* @arg TIM_DMABase_BDTR
bogdanm	0:9b334a45a8ff	3244	* @arg TIM_DMABase_DCR
bogdanm	0:9b334a45a8ff	3245	* @param BurstRequestSrc: TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3246	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3247	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3248	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3249	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3250	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3251	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3252	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3253	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3254	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3255	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3256	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
bogdanm	0:9b334a45a8ff	3257	* @retval HAL status
bogdanm	0:9b334a45a8ff	3258	*/
bogdanm	0:9b334a45a8ff	3259	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3260	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3261	{
bogdanm	0:9b334a45a8ff	3262	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3263	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3264	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3265	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3266	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3267
bogdanm	0:9b334a45a8ff	3268	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3269	{
bogdanm	0:9b334a45a8ff	3270	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3271	}
bogdanm	0:9b334a45a8ff	3272	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3273	{
bogdanm	0:9b334a45a8ff	3274	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3275	{
bogdanm	0:9b334a45a8ff	3276	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3277	}
bogdanm	0:9b334a45a8ff	3278	else
bogdanm	0:9b334a45a8ff	3279	{
bogdanm	0:9b334a45a8ff	3280	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3281	}
bogdanm	0:9b334a45a8ff	3282	}
bogdanm	0:9b334a45a8ff	3283	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3284	{
bogdanm	0:9b334a45a8ff	3285	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3286	{
bogdanm	0:9b334a45a8ff	3287	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3288	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3289
bogdanm	0:9b334a45a8ff	3290	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3291	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3292
bogdanm	0:9b334a45a8ff	3293	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3294	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3295	}
bogdanm	0:9b334a45a8ff	3296	break;
bogdanm	0:9b334a45a8ff	3297	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3298	{
bogdanm	0:9b334a45a8ff	3299	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3300	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3301
bogdanm	0:9b334a45a8ff	3302	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3303	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3304
bogdanm	0:9b334a45a8ff	3305	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3306	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3307	}
bogdanm	0:9b334a45a8ff	3308	break;
bogdanm	0:9b334a45a8ff	3309	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3310	{
bogdanm	0:9b334a45a8ff	3311	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3312	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3313
bogdanm	0:9b334a45a8ff	3314	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3315	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3316
bogdanm	0:9b334a45a8ff	3317	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3318	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3319	}
bogdanm	0:9b334a45a8ff	3320	break;
bogdanm	0:9b334a45a8ff	3321	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3322	{
bogdanm	0:9b334a45a8ff	3323	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3324	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3325
bogdanm	0:9b334a45a8ff	3326	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3327	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3328
bogdanm	0:9b334a45a8ff	3329	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3330	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3331	}
bogdanm	0:9b334a45a8ff	3332	break;
bogdanm	0:9b334a45a8ff	3333	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3334	{
bogdanm	0:9b334a45a8ff	3335	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3336	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3337
bogdanm	0:9b334a45a8ff	3338	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3339	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3340
bogdanm	0:9b334a45a8ff	3341	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3342	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3343	}
bogdanm	0:9b334a45a8ff	3344	break;
bogdanm	0:9b334a45a8ff	3345	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3346	{
bogdanm	0:9b334a45a8ff	3347	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3348	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3349
bogdanm	0:9b334a45a8ff	3350	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3351	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3352
bogdanm	0:9b334a45a8ff	3353	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3354	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3355	}
bogdanm	0:9b334a45a8ff	3356	break;
bogdanm	0:9b334a45a8ff	3357	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3358	{
bogdanm	0:9b334a45a8ff	3359	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3360	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3361
bogdanm	0:9b334a45a8ff	3362	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3363	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3364
bogdanm	0:9b334a45a8ff	3365	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3366	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3367	}
bogdanm	0:9b334a45a8ff	3368	break;
bogdanm	0:9b334a45a8ff	3369	default:
bogdanm	0:9b334a45a8ff	3370	break;
bogdanm	0:9b334a45a8ff	3371	}
bogdanm	0:9b334a45a8ff	3372	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3373	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3374
bogdanm	0:9b334a45a8ff	3375	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3376	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3377
bogdanm	0:9b334a45a8ff	3378	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3379
bogdanm	0:9b334a45a8ff	3380	/* Return function status */
bogdanm	0:9b334a45a8ff	3381	return HAL_OK;
bogdanm	0:9b334a45a8ff	3382	}
bogdanm	0:9b334a45a8ff	3383
bogdanm	0:9b334a45a8ff	3384	/**
bogdanm	0:9b334a45a8ff	3385	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3386	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3387	* @param BurstRequestSrc: TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3388	* @retval HAL status
bogdanm	0:9b334a45a8ff	3389	*/
bogdanm	0:9b334a45a8ff	3390	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3391	{
bogdanm	0:9b334a45a8ff	3392	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3393	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3394
bogdanm	0:9b334a45a8ff	3395	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3396	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3397	{
bogdanm	0:9b334a45a8ff	3398	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3399	{
bogdanm	0:9b334a45a8ff	3400	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3401	}
bogdanm	0:9b334a45a8ff	3402	break;
bogdanm	0:9b334a45a8ff	3403	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3404	{
bogdanm	0:9b334a45a8ff	3405	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3406	}
bogdanm	0:9b334a45a8ff	3407	break;
bogdanm	0:9b334a45a8ff	3408	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3409	{
bogdanm	0:9b334a45a8ff	3410	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3411	}
bogdanm	0:9b334a45a8ff	3412	break;
bogdanm	0:9b334a45a8ff	3413	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3414	{
bogdanm	0:9b334a45a8ff	3415	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3416	}
bogdanm	0:9b334a45a8ff	3417	break;
bogdanm	0:9b334a45a8ff	3418	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3419	{
bogdanm	0:9b334a45a8ff	3420	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3421	}
bogdanm	0:9b334a45a8ff	3422	break;
bogdanm	0:9b334a45a8ff	3423	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3424	{
bogdanm	0:9b334a45a8ff	3425	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3426	}
bogdanm	0:9b334a45a8ff	3427	break;
bogdanm	0:9b334a45a8ff	3428	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3429	{
bogdanm	0:9b334a45a8ff	3430	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3431	}
bogdanm	0:9b334a45a8ff	3432	break;
bogdanm	0:9b334a45a8ff	3433	default:
bogdanm	0:9b334a45a8ff	3434	break;
bogdanm	0:9b334a45a8ff	3435	}
bogdanm	0:9b334a45a8ff	3436
bogdanm	0:9b334a45a8ff	3437	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3438	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3439
bogdanm	0:9b334a45a8ff	3440	/* Return function status */
bogdanm	0:9b334a45a8ff	3441	return HAL_OK;
bogdanm	0:9b334a45a8ff	3442	}
bogdanm	0:9b334a45a8ff	3443
bogdanm	0:9b334a45a8ff	3444	/**
bogdanm	0:9b334a45a8ff	3445	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3446	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3447	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
bogdanm	0:9b334a45a8ff	3448	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3449	* @arg TIM_DMABase_CR1
bogdanm	0:9b334a45a8ff	3450	* @arg TIM_DMABase_CR2
bogdanm	0:9b334a45a8ff	3451	* @arg TIM_DMABase_SMCR
bogdanm	0:9b334a45a8ff	3452	* @arg TIM_DMABase_DIER
bogdanm	0:9b334a45a8ff	3453	* @arg TIM_DMABase_SR
bogdanm	0:9b334a45a8ff	3454	* @arg TIM_DMABase_EGR
bogdanm	0:9b334a45a8ff	3455	* @arg TIM_DMABase_CCMR1
bogdanm	0:9b334a45a8ff	3456	* @arg TIM_DMABase_CCMR2
bogdanm	0:9b334a45a8ff	3457	* @arg TIM_DMABase_CCER
bogdanm	0:9b334a45a8ff	3458	* @arg TIM_DMABase_CNT
bogdanm	0:9b334a45a8ff	3459	* @arg TIM_DMABase_PSC
bogdanm	0:9b334a45a8ff	3460	* @arg TIM_DMABase_ARR
bogdanm	0:9b334a45a8ff	3461	* @arg TIM_DMABase_RCR
bogdanm	0:9b334a45a8ff	3462	* @arg TIM_DMABase_CCR1
bogdanm	0:9b334a45a8ff	3463	* @arg TIM_DMABase_CCR2
bogdanm	0:9b334a45a8ff	3464	* @arg TIM_DMABase_CCR3
bogdanm	0:9b334a45a8ff	3465	* @arg TIM_DMABase_CCR4
bogdanm	0:9b334a45a8ff	3466	* @arg TIM_DMABase_BDTR
bogdanm	0:9b334a45a8ff	3467	* @arg TIM_DMABase_DCR
bogdanm	0:9b334a45a8ff	3468	* @param BurstRequestSrc: TIM DMA Request sources
bogdanm	0:9b334a45a8ff	3469	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3470	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3471	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3472	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3473	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3474	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3475	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3476	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3477	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3478	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3479	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
bogdanm	0:9b334a45a8ff	3480	* @retval HAL status
bogdanm	0:9b334a45a8ff	3481	*/
bogdanm	0:9b334a45a8ff	3482	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3483	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3484	{
bogdanm	0:9b334a45a8ff	3485	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3486	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3487	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3488	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3489	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3490
bogdanm	0:9b334a45a8ff	3491	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3492	{
bogdanm	0:9b334a45a8ff	3493	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3494	}
bogdanm	0:9b334a45a8ff	3495	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3496	{
bogdanm	0:9b334a45a8ff	3497	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3498	{
bogdanm	0:9b334a45a8ff	3499	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3500	}
bogdanm	0:9b334a45a8ff	3501	else
bogdanm	0:9b334a45a8ff	3502	{
bogdanm	0:9b334a45a8ff	3503	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3504	}
bogdanm	0:9b334a45a8ff	3505	}
bogdanm	0:9b334a45a8ff	3506	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3507	{
bogdanm	0:9b334a45a8ff	3508	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3509	{
bogdanm	0:9b334a45a8ff	3510	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3511	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3512
bogdanm	0:9b334a45a8ff	3513	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3514	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3515
bogdanm	0:9b334a45a8ff	3516	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3517	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3518	}
bogdanm	0:9b334a45a8ff	3519	break;
bogdanm	0:9b334a45a8ff	3520	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3521	{
bogdanm	0:9b334a45a8ff	3522	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3523	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3524
bogdanm	0:9b334a45a8ff	3525	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3526	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3527
bogdanm	0:9b334a45a8ff	3528	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3529	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3530	}
bogdanm	0:9b334a45a8ff	3531	break;
bogdanm	0:9b334a45a8ff	3532	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3533	{
bogdanm	0:9b334a45a8ff	3534	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3535	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3536
bogdanm	0:9b334a45a8ff	3537	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3538	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3539
bogdanm	0:9b334a45a8ff	3540	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3541	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3542	}
bogdanm	0:9b334a45a8ff	3543	break;
bogdanm	0:9b334a45a8ff	3544	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3545	{
bogdanm	0:9b334a45a8ff	3546	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3547	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3548
bogdanm	0:9b334a45a8ff	3549	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3550	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3551
bogdanm	0:9b334a45a8ff	3552	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3553	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3554	}
bogdanm	0:9b334a45a8ff	3555	break;
bogdanm	0:9b334a45a8ff	3556	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3557	{
bogdanm	0:9b334a45a8ff	3558	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3559	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3560
bogdanm	0:9b334a45a8ff	3561	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3562	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3563
bogdanm	0:9b334a45a8ff	3564	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3565	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3566	}
bogdanm	0:9b334a45a8ff	3567	break;
bogdanm	0:9b334a45a8ff	3568	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3569	{
bogdanm	0:9b334a45a8ff	3570	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3571	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3572
bogdanm	0:9b334a45a8ff	3573	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3574	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3575
bogdanm	0:9b334a45a8ff	3576	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3577	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3578	}
bogdanm	0:9b334a45a8ff	3579	break;
bogdanm	0:9b334a45a8ff	3580	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3581	{
bogdanm	0:9b334a45a8ff	3582	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3583	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3584
bogdanm	0:9b334a45a8ff	3585	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3586	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3587
bogdanm	0:9b334a45a8ff	3588	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3589	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3590	}
bogdanm	0:9b334a45a8ff	3591	break;
bogdanm	0:9b334a45a8ff	3592	default:
bogdanm	0:9b334a45a8ff	3593	break;
bogdanm	0:9b334a45a8ff	3594	}
bogdanm	0:9b334a45a8ff	3595
bogdanm	0:9b334a45a8ff	3596	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3597	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3598
bogdanm	0:9b334a45a8ff	3599	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3600	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3601
bogdanm	0:9b334a45a8ff	3602	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3603
bogdanm	0:9b334a45a8ff	3604	/* Return function status */
bogdanm	0:9b334a45a8ff	3605	return HAL_OK;
bogdanm	0:9b334a45a8ff	3606	}
bogdanm	0:9b334a45a8ff	3607
bogdanm	0:9b334a45a8ff	3608	/**
bogdanm	0:9b334a45a8ff	3609	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3610	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3611	* @param BurstRequestSrc: TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3612	* @retval HAL status
bogdanm	0:9b334a45a8ff	3613	*/
bogdanm	0:9b334a45a8ff	3614	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3615	{
bogdanm	0:9b334a45a8ff	3616	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3617	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3618
bogdanm	0:9b334a45a8ff	3619	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3620	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3621	{
bogdanm	0:9b334a45a8ff	3622	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3623	{
bogdanm	0:9b334a45a8ff	3624	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3625	}
bogdanm	0:9b334a45a8ff	3626	break;
bogdanm	0:9b334a45a8ff	3627	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3628	{
bogdanm	0:9b334a45a8ff	3629	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3630	}
bogdanm	0:9b334a45a8ff	3631	break;
bogdanm	0:9b334a45a8ff	3632	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3633	{
bogdanm	0:9b334a45a8ff	3634	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3635	}
bogdanm	0:9b334a45a8ff	3636	break;
bogdanm	0:9b334a45a8ff	3637	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3638	{
bogdanm	0:9b334a45a8ff	3639	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3640	}
bogdanm	0:9b334a45a8ff	3641	break;
bogdanm	0:9b334a45a8ff	3642	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3643	{
bogdanm	0:9b334a45a8ff	3644	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3645	}
bogdanm	0:9b334a45a8ff	3646	break;
bogdanm	0:9b334a45a8ff	3647	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3648	{
bogdanm	0:9b334a45a8ff	3649	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3650	}
bogdanm	0:9b334a45a8ff	3651	break;
bogdanm	0:9b334a45a8ff	3652	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3653	{
bogdanm	0:9b334a45a8ff	3654	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3655	}
bogdanm	0:9b334a45a8ff	3656	break;
bogdanm	0:9b334a45a8ff	3657	default:
bogdanm	0:9b334a45a8ff	3658	break;
bogdanm	0:9b334a45a8ff	3659	}
bogdanm	0:9b334a45a8ff	3660
bogdanm	0:9b334a45a8ff	3661	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3662	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3663
bogdanm	0:9b334a45a8ff	3664	/* Return function status */
bogdanm	0:9b334a45a8ff	3665	return HAL_OK;
bogdanm	0:9b334a45a8ff	3666	}
bogdanm	0:9b334a45a8ff	3667
bogdanm	0:9b334a45a8ff	3668	/**
bogdanm	0:9b334a45a8ff	3669	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3670	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3671	* @param EventSource: specifies the event source.
bogdanm	0:9b334a45a8ff	3672	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3673	* @arg TIM_EventSource_Update: Timer update Event source
bogdanm	0:9b334a45a8ff	3674	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3675	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3676	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3677	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3678	* @arg TIM_EventSource_COM: Timer COM event source
bogdanm	0:9b334a45a8ff	3679	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3680	* @arg TIM_EventSource_Break: Timer Break event source
bogdanm	0:9b334a45a8ff	3681	* @arg TIM_EventSource_Break2: Timer Break2 event source
bogdanm	0:9b334a45a8ff	3682	* @retval None
bogdanm	0:9b334a45a8ff	3683	* @note TIM_EventSource_Break2 isn't relevant for STM32F37xx and STM32F38xx
bogdanm	0:9b334a45a8ff	3684	* devices
bogdanm	0:9b334a45a8ff	3685	*/
bogdanm	0:9b334a45a8ff	3686
bogdanm	0:9b334a45a8ff	3687	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3688	{
bogdanm	0:9b334a45a8ff	3689	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3690	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3691	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3692
bogdanm	0:9b334a45a8ff	3693	/* Process Locked */
bogdanm	0:9b334a45a8ff	3694	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3695
bogdanm	0:9b334a45a8ff	3696	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3697	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3698
bogdanm	0:9b334a45a8ff	3699	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3700	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3701
bogdanm	0:9b334a45a8ff	3702	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3703	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3704
bogdanm	0:9b334a45a8ff	3705	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3706
bogdanm	0:9b334a45a8ff	3707	/* Return function status */
bogdanm	0:9b334a45a8ff	3708	return HAL_OK;
bogdanm	0:9b334a45a8ff	3709	}
bogdanm	0:9b334a45a8ff	3710
bogdanm	0:9b334a45a8ff	3711	/**
bogdanm	0:9b334a45a8ff	3712	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3713	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3714	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3715	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3716	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	3717	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3718	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	3719	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	3720	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	3721	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	3722	* @retval HAL status
bogdanm	0:9b334a45a8ff	3723	*/
bogdanm	0:9b334a45a8ff	3724	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3725	{
bogdanm	0:9b334a45a8ff	3726	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3727	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3728	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3729	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3730
bogdanm	0:9b334a45a8ff	3731	/* Process Locked */
bogdanm	0:9b334a45a8ff	3732	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3733
bogdanm	0:9b334a45a8ff	3734	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3735
bogdanm	0:9b334a45a8ff	3736	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
bogdanm	0:9b334a45a8ff	3737	{
bogdanm	0:9b334a45a8ff	3738	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3739	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3740	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3741	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3742
bogdanm	0:9b334a45a8ff	3743	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3744	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3745	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3746	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	3747	}
bogdanm	0:9b334a45a8ff	3748
bogdanm	0:9b334a45a8ff	3749	switch (Channel)
bogdanm	0:9b334a45a8ff	3750	{
bogdanm	0:9b334a45a8ff	3751	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3752	{
bogdanm	0:9b334a45a8ff	3753	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3754	{
bogdanm	0:9b334a45a8ff	3755	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3756	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3757	}
bogdanm	0:9b334a45a8ff	3758	else
bogdanm	0:9b334a45a8ff	3759	{
bogdanm	0:9b334a45a8ff	3760	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3761	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3762	}
bogdanm	0:9b334a45a8ff	3763	}
bogdanm	0:9b334a45a8ff	3764	break;
bogdanm	0:9b334a45a8ff	3765	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3766	{
bogdanm	0:9b334a45a8ff	3767	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3768	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3769	{
bogdanm	0:9b334a45a8ff	3770	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3771	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3772	}
bogdanm	0:9b334a45a8ff	3773	else
bogdanm	0:9b334a45a8ff	3774	{
bogdanm	0:9b334a45a8ff	3775	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3776	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3777	}
bogdanm	0:9b334a45a8ff	3778	}
bogdanm	0:9b334a45a8ff	3779	break;
bogdanm	0:9b334a45a8ff	3780	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3781	{
bogdanm	0:9b334a45a8ff	3782	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3783	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3784	{
bogdanm	0:9b334a45a8ff	3785	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3786	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3787	}
bogdanm	0:9b334a45a8ff	3788	else
bogdanm	0:9b334a45a8ff	3789	{
bogdanm	0:9b334a45a8ff	3790	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3791	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3792	}
bogdanm	0:9b334a45a8ff	3793	}
bogdanm	0:9b334a45a8ff	3794	break;
bogdanm	0:9b334a45a8ff	3795	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3796	{
bogdanm	0:9b334a45a8ff	3797	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3798	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3799	{
bogdanm	0:9b334a45a8ff	3800	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3801	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3802	}
bogdanm	0:9b334a45a8ff	3803	else
bogdanm	0:9b334a45a8ff	3804	{
bogdanm	0:9b334a45a8ff	3805	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3806	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3807	}
bogdanm	0:9b334a45a8ff	3808	}
bogdanm	0:9b334a45a8ff	3809	break;
bogdanm	0:9b334a45a8ff	3810	default:
bogdanm	0:9b334a45a8ff	3811	break;
bogdanm	0:9b334a45a8ff	3812	}
bogdanm	0:9b334a45a8ff	3813
bogdanm	0:9b334a45a8ff	3814	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3815
bogdanm	0:9b334a45a8ff	3816	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3817
bogdanm	0:9b334a45a8ff	3818	return HAL_OK;
bogdanm	0:9b334a45a8ff	3819	}
bogdanm	0:9b334a45a8ff	3820
bogdanm	0:9b334a45a8ff	3821	/**
bogdanm	0:9b334a45a8ff	3822	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3823	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	3824	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3825	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3826	* @retval HAL status
bogdanm	0:9b334a45a8ff	3827	*/
bogdanm	0:9b334a45a8ff	3828	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3829	{
bogdanm	0:9b334a45a8ff	3830	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3831
bogdanm	0:9b334a45a8ff	3832	/* Process Locked */
bogdanm	0:9b334a45a8ff	3833	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3834
bogdanm	0:9b334a45a8ff	3835	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3836
bogdanm	0:9b334a45a8ff	3837	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3838	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3839	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
bogdanm	0:9b334a45a8ff	3840	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
bogdanm	0:9b334a45a8ff	3841	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3842
bogdanm	0:9b334a45a8ff	3843	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3844	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3845	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3846	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3847	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3848
bogdanm	0:9b334a45a8ff	3849	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3850	{
bogdanm	0:9b334a45a8ff	3851	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3852	{
bogdanm	0:9b334a45a8ff	3853	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3854	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3855	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3856	}
bogdanm	0:9b334a45a8ff	3857	break;
bogdanm	0:9b334a45a8ff	3858
bogdanm	0:9b334a45a8ff	3859	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3860	{
bogdanm	0:9b334a45a8ff	3861	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3862	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3863
bogdanm	0:9b334a45a8ff	3864	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3865	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3866	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3867	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3868	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3869	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	3870	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3871	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	3872	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3873	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	3874	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	3875	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	3876	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3877	}
bogdanm	0:9b334a45a8ff	3878	break;
bogdanm	0:9b334a45a8ff	3879
bogdanm	0:9b334a45a8ff	3880	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	3881	{
bogdanm	0:9b334a45a8ff	3882	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
bogdanm	0:9b334a45a8ff	3883	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3884
bogdanm	0:9b334a45a8ff	3885	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3886	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3887	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3888	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3889	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3890	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	3891	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	3892	}
bogdanm	0:9b334a45a8ff	3893	break;
bogdanm	0:9b334a45a8ff	3894
bogdanm	0:9b334a45a8ff	3895	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	3896	{
bogdanm	0:9b334a45a8ff	3897	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3898	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3899
bogdanm	0:9b334a45a8ff	3900	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3901	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3902	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3903	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	3904	}
bogdanm	0:9b334a45a8ff	3905	break;
bogdanm	0:9b334a45a8ff	3906	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	3907	{
bogdanm	0:9b334a45a8ff	3908	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
bogdanm	0:9b334a45a8ff	3909	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3910
bogdanm	0:9b334a45a8ff	3911	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3912	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3913	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3914	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	3915	}
bogdanm	0:9b334a45a8ff	3916	break;
bogdanm	0:9b334a45a8ff	3917	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	3918	{
bogdanm	0:9b334a45a8ff	3919	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3920	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3921
bogdanm	0:9b334a45a8ff	3922	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3923	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3924	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3925	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	3926	}
bogdanm	0:9b334a45a8ff	3927	break;
bogdanm	0:9b334a45a8ff	3928	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	3929	{
bogdanm	0:9b334a45a8ff	3930	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3931	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3932
bogdanm	0:9b334a45a8ff	3933	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	3934	}
bogdanm	0:9b334a45a8ff	3935	break;
bogdanm	0:9b334a45a8ff	3936	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	3937	{
bogdanm	0:9b334a45a8ff	3938	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3939	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3940
bogdanm	0:9b334a45a8ff	3941	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	3942	}
bogdanm	0:9b334a45a8ff	3943	break;
bogdanm	0:9b334a45a8ff	3944	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	3945	{
bogdanm	0:9b334a45a8ff	3946	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3947	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3948
bogdanm	0:9b334a45a8ff	3949	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	3950	}
bogdanm	0:9b334a45a8ff	3951	break;
bogdanm	0:9b334a45a8ff	3952	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	3953	{
bogdanm	0:9b334a45a8ff	3954	/* Check whether or not the timer instance supports external clock mode 1 */
bogdanm	0:9b334a45a8ff	3955	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3956
bogdanm	0:9b334a45a8ff	3957	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	3958	}
bogdanm	0:9b334a45a8ff	3959	break;
bogdanm	0:9b334a45a8ff	3960
bogdanm	0:9b334a45a8ff	3961	default:
bogdanm	0:9b334a45a8ff	3962	break;
bogdanm	0:9b334a45a8ff	3963	}
bogdanm	0:9b334a45a8ff	3964	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3965
bogdanm	0:9b334a45a8ff	3966	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3967
bogdanm	0:9b334a45a8ff	3968	return HAL_OK;
bogdanm	0:9b334a45a8ff	3969	}
bogdanm	0:9b334a45a8ff	3970
bogdanm	0:9b334a45a8ff	3971	/**
bogdanm	0:9b334a45a8ff	3972	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	3973	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	3974	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	3975	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	3976	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	3977	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3978	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	3979	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	3980	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	3981	* @retval HAL status
bogdanm	0:9b334a45a8ff	3982	*/
bogdanm	0:9b334a45a8ff	3983	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	3984	{
bogdanm	0:9b334a45a8ff	3985	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	3986
bogdanm	0:9b334a45a8ff	3987	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3988	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3989	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	3990
bogdanm	0:9b334a45a8ff	3991	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	3992	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	3993
bogdanm	0:9b334a45a8ff	3994	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	3995	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	3996
bogdanm	0:9b334a45a8ff	3997	/* Set the the TI1 selection */
bogdanm	0:9b334a45a8ff	3998	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	3999
bogdanm	0:9b334a45a8ff	4000	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	4001	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4002
bogdanm	0:9b334a45a8ff	4003	return HAL_OK;
bogdanm	0:9b334a45a8ff	4004	}
bogdanm	0:9b334a45a8ff	4005
bogdanm	0:9b334a45a8ff	4006	/**
bogdanm	0:9b334a45a8ff	4007	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	4008	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4009	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4010	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4011	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4012	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4013	* @retval HAL status
bogdanm	0:9b334a45a8ff	4014	*/
bogdanm	0:9b334a45a8ff	4015	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	4016	{
bogdanm	0:9b334a45a8ff	4017	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4018	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4019	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4020
bogdanm	0:9b334a45a8ff	4021	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4022	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4023	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4024	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4025
bogdanm	0:9b334a45a8ff	4026	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4027
bogdanm	0:9b334a45a8ff	4028	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4029
bogdanm	0:9b334a45a8ff	4030	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4031	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4032
bogdanm	0:9b334a45a8ff	4033	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4034	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4035	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4036	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4037
bogdanm	0:9b334a45a8ff	4038	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4039	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4040	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4041	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4042
bogdanm	0:9b334a45a8ff	4043	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4044	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4045
bogdanm	0:9b334a45a8ff	4046	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4047	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4048	{
bogdanm	0:9b334a45a8ff	4049	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4050	{
bogdanm	0:9b334a45a8ff	4051	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4052	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4053	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4054	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4055	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4056	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4057	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4058	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4059	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4060	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4061	}
bogdanm	0:9b334a45a8ff	4062	break;
bogdanm	0:9b334a45a8ff	4063
bogdanm	0:9b334a45a8ff	4064	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	4065	{
bogdanm	0:9b334a45a8ff	4066	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4067	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4068	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4069	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4070
bogdanm	0:9b334a45a8ff	4071	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4072	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	4073	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4074	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	4075
bogdanm	0:9b334a45a8ff	4076	/* Set the filter */
bogdanm	0:9b334a45a8ff	4077	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4078	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	4079
bogdanm	0:9b334a45a8ff	4080	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4081	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4082	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4083
bogdanm	0:9b334a45a8ff	4084	}
bogdanm	0:9b334a45a8ff	4085	break;
bogdanm	0:9b334a45a8ff	4086
bogdanm	0:9b334a45a8ff	4087	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	4088	{
bogdanm	0:9b334a45a8ff	4089	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4090	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4091	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4092	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4093
bogdanm	0:9b334a45a8ff	4094	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4095	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4096	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4097	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4098	}
bogdanm	0:9b334a45a8ff	4099	break;
bogdanm	0:9b334a45a8ff	4100
bogdanm	0:9b334a45a8ff	4101	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	4102	{
bogdanm	0:9b334a45a8ff	4103	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4104	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4105	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4106	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4107
bogdanm	0:9b334a45a8ff	4108	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4109	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4110	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4111	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4112	}
bogdanm	0:9b334a45a8ff	4113	break;
bogdanm	0:9b334a45a8ff	4114
bogdanm	0:9b334a45a8ff	4115	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	4116	{
bogdanm	0:9b334a45a8ff	4117	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4118	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4119	}
bogdanm	0:9b334a45a8ff	4120	break;
bogdanm	0:9b334a45a8ff	4121
bogdanm	0:9b334a45a8ff	4122	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	4123	{
bogdanm	0:9b334a45a8ff	4124	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4125	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4126	}
bogdanm	0:9b334a45a8ff	4127	break;
bogdanm	0:9b334a45a8ff	4128
bogdanm	0:9b334a45a8ff	4129	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	4130	{
bogdanm	0:9b334a45a8ff	4131	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4132	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4133	}
bogdanm	0:9b334a45a8ff	4134	break;
bogdanm	0:9b334a45a8ff	4135
bogdanm	0:9b334a45a8ff	4136	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	4137	{
bogdanm	0:9b334a45a8ff	4138	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4139	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4140	}
bogdanm	0:9b334a45a8ff	4141	break;
bogdanm	0:9b334a45a8ff	4142
bogdanm	0:9b334a45a8ff	4143	default:
bogdanm	0:9b334a45a8ff	4144	break;
bogdanm	0:9b334a45a8ff	4145	}
bogdanm	0:9b334a45a8ff	4146
bogdanm	0:9b334a45a8ff	4147	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4148
bogdanm	0:9b334a45a8ff	4149	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4150
bogdanm	0:9b334a45a8ff	4151	return HAL_OK;
bogdanm	0:9b334a45a8ff	4152	}
bogdanm	0:9b334a45a8ff	4153
bogdanm	0:9b334a45a8ff	4154	/**
bogdanm	0:9b334a45a8ff	4155	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	4156	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4157	* @param Channel : TIM Channels to be enabled
bogdanm	0:9b334a45a8ff	4158	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4159	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	4160	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4161	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4162	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4163	* @retval Captured value
bogdanm	0:9b334a45a8ff	4164	*/
bogdanm	0:9b334a45a8ff	4165	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4166	{
bogdanm	0:9b334a45a8ff	4167	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4168
bogdanm	0:9b334a45a8ff	4169	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4170
bogdanm	0:9b334a45a8ff	4171	switch (Channel)
bogdanm	0:9b334a45a8ff	4172	{
bogdanm	0:9b334a45a8ff	4173	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4174	{
bogdanm	0:9b334a45a8ff	4175	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4176	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4177
bogdanm	0:9b334a45a8ff	4178	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4179	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4180
bogdanm	0:9b334a45a8ff	4181	break;
bogdanm	0:9b334a45a8ff	4182	}
bogdanm	0:9b334a45a8ff	4183	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4184	{
bogdanm	0:9b334a45a8ff	4185	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4186	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4187
bogdanm	0:9b334a45a8ff	4188	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4189	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4190
bogdanm	0:9b334a45a8ff	4191	break;
bogdanm	0:9b334a45a8ff	4192	}
bogdanm	0:9b334a45a8ff	4193
bogdanm	0:9b334a45a8ff	4194	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4195	{
bogdanm	0:9b334a45a8ff	4196	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4197	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4198
bogdanm	0:9b334a45a8ff	4199	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4200	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4201
bogdanm	0:9b334a45a8ff	4202	break;
bogdanm	0:9b334a45a8ff	4203	}
bogdanm	0:9b334a45a8ff	4204
bogdanm	0:9b334a45a8ff	4205	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4206	{
bogdanm	0:9b334a45a8ff	4207	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4208	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4209
bogdanm	0:9b334a45a8ff	4210	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4211	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4212
bogdanm	0:9b334a45a8ff	4213	break;
bogdanm	0:9b334a45a8ff	4214	}
bogdanm	0:9b334a45a8ff	4215
bogdanm	0:9b334a45a8ff	4216	default:
bogdanm	0:9b334a45a8ff	4217	break;
bogdanm	0:9b334a45a8ff	4218	}
bogdanm	0:9b334a45a8ff	4219
bogdanm	0:9b334a45a8ff	4220	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4221	return tmpreg;
bogdanm	0:9b334a45a8ff	4222	}
bogdanm	0:9b334a45a8ff	4223
bogdanm	0:9b334a45a8ff	4224	/**
bogdanm	0:9b334a45a8ff	4225	* @}
bogdanm	0:9b334a45a8ff	4226	*/
bogdanm	0:9b334a45a8ff	4227
bogdanm	0:9b334a45a8ff	4228	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4229	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4230	*
bogdanm	0:9b334a45a8ff	4231	@verbatim
bogdanm	0:9b334a45a8ff	4232	==============================================================================
bogdanm	0:9b334a45a8ff	4233	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4234	==============================================================================
bogdanm	0:9b334a45a8ff	4235	[..]
bogdanm	0:9b334a45a8ff	4236	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4237	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4238	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4239	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4240	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4241	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4242
bogdanm	0:9b334a45a8ff	4243	@endverbatim
bogdanm	0:9b334a45a8ff	4244	* @{
bogdanm	0:9b334a45a8ff	4245	*/
bogdanm	0:9b334a45a8ff	4246
bogdanm	0:9b334a45a8ff	4247	/**
bogdanm	0:9b334a45a8ff	4248	* @brief Period elapsed callback in non blocking mode
bogdanm	0:9b334a45a8ff	4249	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4250	* @retval None
bogdanm	0:9b334a45a8ff	4251	*/
bogdanm	0:9b334a45a8ff	4252	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4253	{
bogdanm	0:9b334a45a8ff	4254	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4255	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4256	*/
bogdanm	0:9b334a45a8ff	4257
bogdanm	0:9b334a45a8ff	4258	}
bogdanm	0:9b334a45a8ff	4259	/**
bogdanm	0:9b334a45a8ff	4260	* @brief Output Compare callback in non blocking mode
bogdanm	0:9b334a45a8ff	4261	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	4262	* @retval None
bogdanm	0:9b334a45a8ff	4263	*/
bogdanm	0:9b334a45a8ff	4264	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4265	{
bogdanm	0:9b334a45a8ff	4266	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4267	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4268	*/
bogdanm	0:9b334a45a8ff	4269	}
bogdanm	0:9b334a45a8ff	4270	/**
bogdanm	0:9b334a45a8ff	4271	* @brief Input Capture callback in non blocking mode
bogdanm	0:9b334a45a8ff	4272	* @param htim : TIM IC handle
bogdanm	0:9b334a45a8ff	4273	* @retval None
bogdanm	0:9b334a45a8ff	4274	*/
bogdanm	0:9b334a45a8ff	4275	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4276	{
bogdanm	0:9b334a45a8ff	4277	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4278	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4279	*/
bogdanm	0:9b334a45a8ff	4280	}
bogdanm	0:9b334a45a8ff	4281
bogdanm	0:9b334a45a8ff	4282	/**
bogdanm	0:9b334a45a8ff	4283	* @brief PWM Pulse finished callback in non blocking mode
bogdanm	0:9b334a45a8ff	4284	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4285	* @retval None
bogdanm	0:9b334a45a8ff	4286	*/
bogdanm	0:9b334a45a8ff	4287	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4288	{
bogdanm	0:9b334a45a8ff	4289	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4290	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4291	*/
bogdanm	0:9b334a45a8ff	4292	}
bogdanm	0:9b334a45a8ff	4293
bogdanm	0:9b334a45a8ff	4294	/**
bogdanm	0:9b334a45a8ff	4295	* @brief Hall Trigger detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	4296	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4297	* @retval None
bogdanm	0:9b334a45a8ff	4298	*/
bogdanm	0:9b334a45a8ff	4299	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4300	{
bogdanm	0:9b334a45a8ff	4301	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4302	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4303	*/
bogdanm	0:9b334a45a8ff	4304	}
bogdanm	0:9b334a45a8ff	4305
bogdanm	0:9b334a45a8ff	4306	/**
bogdanm	0:9b334a45a8ff	4307	* @brief Timer error callback in non blocking mode
bogdanm	0:9b334a45a8ff	4308	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	4309	* @retval None
bogdanm	0:9b334a45a8ff	4310	*/
bogdanm	0:9b334a45a8ff	4311	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4312	{
bogdanm	0:9b334a45a8ff	4313	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4314	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4315	*/
bogdanm	0:9b334a45a8ff	4316	}
bogdanm	0:9b334a45a8ff	4317
bogdanm	0:9b334a45a8ff	4318	/**
bogdanm	0:9b334a45a8ff	4319	* @}
bogdanm	0:9b334a45a8ff	4320	*/
bogdanm	0:9b334a45a8ff	4321
bogdanm	0:9b334a45a8ff	4322	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	4323	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4324	*
bogdanm	0:9b334a45a8ff	4325	@verbatim
bogdanm	0:9b334a45a8ff	4326	==============================================================================
bogdanm	0:9b334a45a8ff	4327	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4328	==============================================================================
bogdanm	0:9b334a45a8ff	4329	[..]
bogdanm	0:9b334a45a8ff	4330	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4331	and the data flow.
bogdanm	0:9b334a45a8ff	4332
bogdanm	0:9b334a45a8ff	4333	@endverbatim
bogdanm	0:9b334a45a8ff	4334	* @{
bogdanm	0:9b334a45a8ff	4335	*/
bogdanm	0:9b334a45a8ff	4336
bogdanm	0:9b334a45a8ff	4337	/**
bogdanm	0:9b334a45a8ff	4338	* @brief Return the TIM Base state
bogdanm	0:9b334a45a8ff	4339	* @param htim: TIM Base handle
bogdanm	0:9b334a45a8ff	4340	* @retval HAL state
bogdanm	0:9b334a45a8ff	4341	*/
bogdanm	0:9b334a45a8ff	4342	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4343	{
bogdanm	0:9b334a45a8ff	4344	return htim->State;
bogdanm	0:9b334a45a8ff	4345	}
bogdanm	0:9b334a45a8ff	4346
bogdanm	0:9b334a45a8ff	4347	/**
bogdanm	0:9b334a45a8ff	4348	* @brief Return the TIM OC state
bogdanm	0:9b334a45a8ff	4349	* @param htim: TIM Ouput Compare handle
bogdanm	0:9b334a45a8ff	4350	* @retval HAL state
bogdanm	0:9b334a45a8ff	4351	*/
bogdanm	0:9b334a45a8ff	4352	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4353	{
bogdanm	0:9b334a45a8ff	4354	return htim->State;
bogdanm	0:9b334a45a8ff	4355	}
bogdanm	0:9b334a45a8ff	4356
bogdanm	0:9b334a45a8ff	4357	/**
bogdanm	0:9b334a45a8ff	4358	* @brief Return the TIM PWM state
bogdanm	0:9b334a45a8ff	4359	* @param htim: TIM handle
bogdanm	0:9b334a45a8ff	4360	* @retval HAL state
bogdanm	0:9b334a45a8ff	4361	*/
bogdanm	0:9b334a45a8ff	4362	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4363	{
bogdanm	0:9b334a45a8ff	4364	return htim->State;
bogdanm	0:9b334a45a8ff	4365	}
bogdanm	0:9b334a45a8ff	4366
bogdanm	0:9b334a45a8ff	4367	/**
bogdanm	0:9b334a45a8ff	4368	* @brief Return the TIM Input Capture state
bogdanm	0:9b334a45a8ff	4369	* @param htim: TIM IC handle
bogdanm	0:9b334a45a8ff	4370	* @retval HAL state
bogdanm	0:9b334a45a8ff	4371	*/
bogdanm	0:9b334a45a8ff	4372	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4373	{
bogdanm	0:9b334a45a8ff	4374	return htim->State;
bogdanm	0:9b334a45a8ff	4375	}
bogdanm	0:9b334a45a8ff	4376
bogdanm	0:9b334a45a8ff	4377	/**
bogdanm	0:9b334a45a8ff	4378	* @brief Return the TIM One Pulse Mode state
bogdanm	0:9b334a45a8ff	4379	* @param htim: TIM OPM handle
bogdanm	0:9b334a45a8ff	4380	* @retval HAL state
bogdanm	0:9b334a45a8ff	4381	*/
bogdanm	0:9b334a45a8ff	4382	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4383	{
bogdanm	0:9b334a45a8ff	4384	return htim->State;
bogdanm	0:9b334a45a8ff	4385	}
bogdanm	0:9b334a45a8ff	4386
bogdanm	0:9b334a45a8ff	4387	/**
bogdanm	0:9b334a45a8ff	4388	* @brief Return the TIM Encoder Mode state
bogdanm	0:9b334a45a8ff	4389	* @param htim: TIM Encoder handle
bogdanm	0:9b334a45a8ff	4390	* @retval HAL state
bogdanm	0:9b334a45a8ff	4391	*/
bogdanm	0:9b334a45a8ff	4392	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4393	{
bogdanm	0:9b334a45a8ff	4394	return htim->State;
bogdanm	0:9b334a45a8ff	4395	}
bogdanm	0:9b334a45a8ff	4396
bogdanm	0:9b334a45a8ff	4397	/**
bogdanm	0:9b334a45a8ff	4398	* @}
bogdanm	0:9b334a45a8ff	4399	*/
bogdanm	0:9b334a45a8ff	4400
bogdanm	0:9b334a45a8ff	4401	/**
bogdanm	0:9b334a45a8ff	4402	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4403	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4404	* @retval None
bogdanm	0:9b334a45a8ff	4405	*/
bogdanm	0:9b334a45a8ff	4406	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4407	{
bogdanm	0:9b334a45a8ff	4408	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4409
bogdanm	0:9b334a45a8ff	4410	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4411
bogdanm	0:9b334a45a8ff	4412	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4413	}
bogdanm	0:9b334a45a8ff	4414
bogdanm	0:9b334a45a8ff	4415	/**
bogdanm	0:9b334a45a8ff	4416	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4417	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4418	* @retval None
bogdanm	0:9b334a45a8ff	4419	*/
bogdanm	0:9b334a45a8ff	4420	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4421	{
bogdanm	0:9b334a45a8ff	4422	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4423
bogdanm	0:9b334a45a8ff	4424	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4425
bogdanm	0:9b334a45a8ff	4426	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4427	{
bogdanm	0:9b334a45a8ff	4428	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4429	}
bogdanm	0:9b334a45a8ff	4430	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4431	{
bogdanm	0:9b334a45a8ff	4432	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4433	}
bogdanm	0:9b334a45a8ff	4434	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4435	{
bogdanm	0:9b334a45a8ff	4436	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4437	}
bogdanm	0:9b334a45a8ff	4438	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4439	{
bogdanm	0:9b334a45a8ff	4440	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4441	}
bogdanm	0:9b334a45a8ff	4442
bogdanm	0:9b334a45a8ff	4443	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4444
bogdanm	0:9b334a45a8ff	4445	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4446	}
bogdanm	0:9b334a45a8ff	4447	/**
bogdanm	0:9b334a45a8ff	4448	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4449	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4450	* @retval None
bogdanm	0:9b334a45a8ff	4451	*/
bogdanm	0:9b334a45a8ff	4452	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4453	{
bogdanm	0:9b334a45a8ff	4454	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4455
bogdanm	0:9b334a45a8ff	4456	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4457
bogdanm	0:9b334a45a8ff	4458	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4459	{
bogdanm	0:9b334a45a8ff	4460	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4461	}
bogdanm	0:9b334a45a8ff	4462	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4463	{
bogdanm	0:9b334a45a8ff	4464	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4465	}
bogdanm	0:9b334a45a8ff	4466	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4467	{
bogdanm	0:9b334a45a8ff	4468	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4469	}
bogdanm	0:9b334a45a8ff	4470	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4471	{
bogdanm	0:9b334a45a8ff	4472	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4473	}
bogdanm	0:9b334a45a8ff	4474
bogdanm	0:9b334a45a8ff	4475	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4476
bogdanm	0:9b334a45a8ff	4477	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4478	}
bogdanm	0:9b334a45a8ff	4479
bogdanm	0:9b334a45a8ff	4480	/**
bogdanm	0:9b334a45a8ff	4481	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4482	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4483	* @retval None
bogdanm	0:9b334a45a8ff	4484	*/
bogdanm	0:9b334a45a8ff	4485	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4486	{
bogdanm	0:9b334a45a8ff	4487	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4488
bogdanm	0:9b334a45a8ff	4489	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4490
bogdanm	0:9b334a45a8ff	4491	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4492	}
bogdanm	0:9b334a45a8ff	4493
bogdanm	0:9b334a45a8ff	4494	/**
bogdanm	0:9b334a45a8ff	4495	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4496	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	4497	* @retval None
bogdanm	0:9b334a45a8ff	4498	*/
bogdanm	0:9b334a45a8ff	4499	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4500	{
bogdanm	0:9b334a45a8ff	4501	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4502
bogdanm	0:9b334a45a8ff	4503	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4504
bogdanm	0:9b334a45a8ff	4505	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4506	}
bogdanm	0:9b334a45a8ff	4507
bogdanm	0:9b334a45a8ff	4508	/**
bogdanm	0:9b334a45a8ff	4509	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4510	* @param TIMx: TIM periheral
bogdanm	0:9b334a45a8ff	4511	* @param Structure: TIM Base configuration structure
bogdanm	0:9b334a45a8ff	4512	* @retval None
bogdanm	0:9b334a45a8ff	4513	*/
bogdanm	0:9b334a45a8ff	4514	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4515	{
bogdanm	0:9b334a45a8ff	4516	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4517	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4518
bogdanm	0:9b334a45a8ff	4519	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4520	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4521	{
bogdanm	0:9b334a45a8ff	4522	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4523	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4524	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4525	}
bogdanm	0:9b334a45a8ff	4526
bogdanm	0:9b334a45a8ff	4527	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4528	{
bogdanm	0:9b334a45a8ff	4529	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4530	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4531	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4532	}
bogdanm	0:9b334a45a8ff	4533
bogdanm	0:9b334a45a8ff	4534	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4535
bogdanm	0:9b334a45a8ff	4536	/* Set the Autoreload value */
bogdanm	0:9b334a45a8ff	4537	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4538
bogdanm	0:9b334a45a8ff	4539	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4540	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4541
bogdanm	0:9b334a45a8ff	4542	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4543	{
bogdanm	0:9b334a45a8ff	4544	/* Set the Repetition Counter value */
bogdanm	0:9b334a45a8ff	4545	TIMx->RCR = Structure->RepetitionCounter;
bogdanm	0:9b334a45a8ff	4546	}
bogdanm	0:9b334a45a8ff	4547
bogdanm	0:9b334a45a8ff	4548	/* Generate an update event to reload the Prescaler
bogdanm	0:9b334a45a8ff	4549	and the repetition counter(only for TIM1 and TIM8) value immediatly */
bogdanm	0:9b334a45a8ff	4550	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4551	}
bogdanm	0:9b334a45a8ff	4552
bogdanm	0:9b334a45a8ff	4553	/**
bogdanm	0:9b334a45a8ff	4554	* @brief Time Ouput Compare 1 configuration
bogdanm	0:9b334a45a8ff	4555	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4556	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4557	* @retval None
bogdanm	0:9b334a45a8ff	4558	*/
bogdanm	0:9b334a45a8ff	4559	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4560	{
bogdanm	0:9b334a45a8ff	4561	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4562	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4563	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4564
bogdanm	0:9b334a45a8ff	4565	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4566	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4567
bogdanm	0:9b334a45a8ff	4568	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4569	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4570	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4571	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4572
bogdanm	0:9b334a45a8ff	4573	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4574	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4575
bogdanm	0:9b334a45a8ff	4576	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4577	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4578	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4579	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4580	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4581
bogdanm	0:9b334a45a8ff	4582	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4583	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4584	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4585	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4586
bogdanm	0:9b334a45a8ff	4587	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
bogdanm	0:9b334a45a8ff	4588	{
bogdanm	0:9b334a45a8ff	4589	/* Check parameters */
bogdanm	0:9b334a45a8ff	4590	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4591
bogdanm	0:9b334a45a8ff	4592	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4593	tmpccer &= ~TIM_CCER_CC1NP;
bogdanm	0:9b334a45a8ff	4594	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4595	tmpccer \|= OC_Config->OCNPolarity;
bogdanm	0:9b334a45a8ff	4596	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4597	tmpccer &= ~TIM_CCER_CC1NE;
bogdanm	0:9b334a45a8ff	4598	}
bogdanm	0:9b334a45a8ff	4599
bogdanm	0:9b334a45a8ff	4600	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4601	{
bogdanm	0:9b334a45a8ff	4602	/* Check parameters */
bogdanm	0:9b334a45a8ff	4603	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4604	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4605
bogdanm	0:9b334a45a8ff	4606	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4607	tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm	0:9b334a45a8ff	4608	tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm	0:9b334a45a8ff	4609	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4610	tmpcr2 \|= OC_Config->OCIdleState;
bogdanm	0:9b334a45a8ff	4611	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4612	tmpcr2 \|= OC_Config->OCNIdleState;
bogdanm	0:9b334a45a8ff	4613	}
bogdanm	0:9b334a45a8ff	4614	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4615	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4616
bogdanm	0:9b334a45a8ff	4617	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4618	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4619
bogdanm	0:9b334a45a8ff	4620	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4621	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4622
bogdanm	0:9b334a45a8ff	4623	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4624	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4625	}
bogdanm	0:9b334a45a8ff	4626
bogdanm	0:9b334a45a8ff	4627	/**
bogdanm	0:9b334a45a8ff	4628	* @brief Time Ouput Compare 2 configuration
bogdanm	0:9b334a45a8ff	4629	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4630	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4631	* @retval None
bogdanm	0:9b334a45a8ff	4632	*/
bogdanm	0:9b334a45a8ff	4633	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4634	{
bogdanm	0:9b334a45a8ff	4635	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4636	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4637	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4638
bogdanm	0:9b334a45a8ff	4639	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4640	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4641
bogdanm	0:9b334a45a8ff	4642	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4643	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4644	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4645	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4646
bogdanm	0:9b334a45a8ff	4647	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4648	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4649
bogdanm	0:9b334a45a8ff	4650	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4651	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4652	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4653
bogdanm	0:9b334a45a8ff	4654	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4655	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4656
bogdanm	0:9b334a45a8ff	4657	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4658	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4659	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4660	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4661
bogdanm	0:9b334a45a8ff	4662	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	4663	{
bogdanm	0:9b334a45a8ff	4664	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4665	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4666	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4667
bogdanm	0:9b334a45a8ff	4668	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4669	tmpccer &= ~TIM_CCER_CC2NP;
bogdanm	0:9b334a45a8ff	4670	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4671	tmpccer \|= (OC_Config->OCNPolarity << 4);
bogdanm	0:9b334a45a8ff	4672	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4673	tmpccer &= ~TIM_CCER_CC2NE;
bogdanm	0:9b334a45a8ff	4674
bogdanm	0:9b334a45a8ff	4675	}
bogdanm	0:9b334a45a8ff	4676
bogdanm	0:9b334a45a8ff	4677	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4678	{
bogdanm	0:9b334a45a8ff	4679	/* Check parameters */
bogdanm	0:9b334a45a8ff	4680	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4681	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4682
bogdanm	0:9b334a45a8ff	4683	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4684	tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm	0:9b334a45a8ff	4685	tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm	0:9b334a45a8ff	4686	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4687	tmpcr2 \|= (OC_Config->OCIdleState << 2);
bogdanm	0:9b334a45a8ff	4688	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4689	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
bogdanm	0:9b334a45a8ff	4690	}
bogdanm	0:9b334a45a8ff	4691
bogdanm	0:9b334a45a8ff	4692	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4693	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4694
bogdanm	0:9b334a45a8ff	4695	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4696	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4697
bogdanm	0:9b334a45a8ff	4698	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4699	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4700
bogdanm	0:9b334a45a8ff	4701	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4702	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4703	}
bogdanm	0:9b334a45a8ff	4704
bogdanm	0:9b334a45a8ff	4705	/**
bogdanm	0:9b334a45a8ff	4706	* @brief Time Ouput Compare 3 configuration
bogdanm	0:9b334a45a8ff	4707	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4708	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4709	* @retval None
bogdanm	0:9b334a45a8ff	4710	*/
bogdanm	0:9b334a45a8ff	4711	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4712	{
bogdanm	0:9b334a45a8ff	4713	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4714	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4715	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4716
bogdanm	0:9b334a45a8ff	4717	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4718	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4719
bogdanm	0:9b334a45a8ff	4720	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4721	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4722	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4723	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4724
bogdanm	0:9b334a45a8ff	4725	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4726	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4727
bogdanm	0:9b334a45a8ff	4728	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4729	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4730	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4731	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4732	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4733
bogdanm	0:9b334a45a8ff	4734	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4735	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4736	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4737	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4738
bogdanm	0:9b334a45a8ff	4739	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	4740	{
bogdanm	0:9b334a45a8ff	4741	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4742	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4743	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4744
bogdanm	0:9b334a45a8ff	4745	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4746	tmpccer &= ~TIM_CCER_CC3NP;
bogdanm	0:9b334a45a8ff	4747	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4748	tmpccer \|= (OC_Config->OCNPolarity << 8);
bogdanm	0:9b334a45a8ff	4749	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4750	tmpccer &= ~TIM_CCER_CC3NE;
bogdanm	0:9b334a45a8ff	4751	}
bogdanm	0:9b334a45a8ff	4752
bogdanm	0:9b334a45a8ff	4753	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4754	{
bogdanm	0:9b334a45a8ff	4755	/* Check parameters */
bogdanm	0:9b334a45a8ff	4756	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4757	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4758
bogdanm	0:9b334a45a8ff	4759	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4760	tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm	0:9b334a45a8ff	4761	tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm	0:9b334a45a8ff	4762	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4763	tmpcr2 \|= (OC_Config->OCIdleState << 4);
bogdanm	0:9b334a45a8ff	4764	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4765	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
bogdanm	0:9b334a45a8ff	4766	}
bogdanm	0:9b334a45a8ff	4767
bogdanm	0:9b334a45a8ff	4768	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4769	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4770
bogdanm	0:9b334a45a8ff	4771	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4772	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4773
bogdanm	0:9b334a45a8ff	4774	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4775	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4776
bogdanm	0:9b334a45a8ff	4777	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4778	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4779	}
bogdanm	0:9b334a45a8ff	4780
bogdanm	0:9b334a45a8ff	4781	/**
bogdanm	0:9b334a45a8ff	4782	* @brief Time Ouput Compare 4 configuration
bogdanm	0:9b334a45a8ff	4783	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4784	* @param OC_Config: The ouput configuration structure
bogdanm	0:9b334a45a8ff	4785	* @retval None
bogdanm	0:9b334a45a8ff	4786	*/
bogdanm	0:9b334a45a8ff	4787	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4788	{
bogdanm	0:9b334a45a8ff	4789	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4790	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4791	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4792
bogdanm	0:9b334a45a8ff	4793	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4794	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4795
bogdanm	0:9b334a45a8ff	4796	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4797	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4798	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4799	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4800
bogdanm	0:9b334a45a8ff	4801	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4802	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4803
bogdanm	0:9b334a45a8ff	4804	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4805	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4806	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4807
bogdanm	0:9b334a45a8ff	4808	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4809	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4810
bogdanm	0:9b334a45a8ff	4811	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4812	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4813	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4814	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4815
bogdanm	0:9b334a45a8ff	4816	if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm	0:9b334a45a8ff	4817	{
bogdanm	0:9b334a45a8ff	4818	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4819
bogdanm	0:9b334a45a8ff	4820	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	4821	tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm	0:9b334a45a8ff	4822	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4823	tmpcr2 \|= (OC_Config->OCIdleState << 6);
bogdanm	0:9b334a45a8ff	4824	}
bogdanm	0:9b334a45a8ff	4825
bogdanm	0:9b334a45a8ff	4826	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4827	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4828
bogdanm	0:9b334a45a8ff	4829	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4830	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4831
bogdanm	0:9b334a45a8ff	4832	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4833	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4834
bogdanm	0:9b334a45a8ff	4835	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4836	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4837	}
bogdanm	0:9b334a45a8ff	4838
bogdanm	0:9b334a45a8ff	4839	/**
bogdanm	0:9b334a45a8ff	4840	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	4841	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4842	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4843	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4844	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4845	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4846	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4847	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4848	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4849	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	4850	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	4851	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4852	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4853	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4854	* @retval None
bogdanm	0:9b334a45a8ff	4855	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm	0:9b334a45a8ff	4856	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	4857	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	4858	*/
bogdanm	0:9b334a45a8ff	4859	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4860	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4861	{
bogdanm	0:9b334a45a8ff	4862	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4863	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4864
bogdanm	0:9b334a45a8ff	4865	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4866	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4867	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4868	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4869
bogdanm	0:9b334a45a8ff	4870	/* Select the Input */
bogdanm	0:9b334a45a8ff	4871	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4872	{
bogdanm	0:9b334a45a8ff	4873	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4874	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	4875	}
bogdanm	0:9b334a45a8ff	4876	else
bogdanm	0:9b334a45a8ff	4877	{
bogdanm	0:9b334a45a8ff	4878	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	4879	}
bogdanm	0:9b334a45a8ff	4880
bogdanm	0:9b334a45a8ff	4881	/* Set the filter */
bogdanm	0:9b334a45a8ff	4882	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4883	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	4884
bogdanm	0:9b334a45a8ff	4885	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	4886	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	4887	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	4888
bogdanm	0:9b334a45a8ff	4889	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4890	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4891	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4892	}
bogdanm	0:9b334a45a8ff	4893
bogdanm	0:9b334a45a8ff	4894	/**
bogdanm	0:9b334a45a8ff	4895	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	4896	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4897	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4898	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4899	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4900	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4901	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4902	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4903	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4904	* @retval None
bogdanm	0:9b334a45a8ff	4905	*/
bogdanm	0:9b334a45a8ff	4906	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4907	{
bogdanm	0:9b334a45a8ff	4908	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4909	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4910
bogdanm	0:9b334a45a8ff	4911	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4912	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4913	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4914	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4915
bogdanm	0:9b334a45a8ff	4916	/* Set the filter */
bogdanm	0:9b334a45a8ff	4917	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4918	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	4919
bogdanm	0:9b334a45a8ff	4920	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	4921	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	4922	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	4923
bogdanm	0:9b334a45a8ff	4924	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4925	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4926	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4927	}
bogdanm	0:9b334a45a8ff	4928
bogdanm	0:9b334a45a8ff	4929	/**
bogdanm	0:9b334a45a8ff	4930	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	4931	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4932	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4933	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4934	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4935	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4936	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4937	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	4938	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4939	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	4940	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	4941	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	4942	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4943	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4944	* @retval None
bogdanm	0:9b334a45a8ff	4945	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm	0:9b334a45a8ff	4946	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	4947	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	4948	*/
bogdanm	0:9b334a45a8ff	4949	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	4950	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4951	{
bogdanm	0:9b334a45a8ff	4952	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4953	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4954
bogdanm	0:9b334a45a8ff	4955	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4956	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4957	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4958	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4959
bogdanm	0:9b334a45a8ff	4960	/* Select the Input */
bogdanm	0:9b334a45a8ff	4961	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4962	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	4963
bogdanm	0:9b334a45a8ff	4964	/* Set the filter */
bogdanm	0:9b334a45a8ff	4965	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	4966	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	4967
bogdanm	0:9b334a45a8ff	4968	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	4969	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	4970	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	4971
bogdanm	0:9b334a45a8ff	4972	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4973	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	4974	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4975	}
bogdanm	0:9b334a45a8ff	4976
bogdanm	0:9b334a45a8ff	4977	/**
bogdanm	0:9b334a45a8ff	4978	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	4979	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	4980	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	4981	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4982	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	4983	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	4984	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	4985	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	4986	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	4987	* @retval None
bogdanm	0:9b334a45a8ff	4988	*/
bogdanm	0:9b334a45a8ff	4989	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	4990	{
bogdanm	0:9b334a45a8ff	4991	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4992	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4993
bogdanm	0:9b334a45a8ff	4994	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4995	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4996	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4997	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4998
bogdanm	0:9b334a45a8ff	4999	/* Set the filter */
bogdanm	0:9b334a45a8ff	5000	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5001	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	5002
bogdanm	0:9b334a45a8ff	5003	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5004	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5005	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	5006
bogdanm	0:9b334a45a8ff	5007	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5008	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5009	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5010	}
bogdanm	0:9b334a45a8ff	5011
bogdanm	0:9b334a45a8ff	5012	/**
bogdanm	0:9b334a45a8ff	5013	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	5014	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5015	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5016	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5017	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5018	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5019	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5020	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5021	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5022	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5023	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5024	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5025	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5026	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5027	* @retval None
bogdanm	0:9b334a45a8ff	5028	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm	0:9b334a45a8ff	5029	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5030	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5031	*/
bogdanm	0:9b334a45a8ff	5032	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5033	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5034	{
bogdanm	0:9b334a45a8ff	5035	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5036	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5037
bogdanm	0:9b334a45a8ff	5038	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	5039	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	5040	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5041	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5042
bogdanm	0:9b334a45a8ff	5043	/* Select the Input */
bogdanm	0:9b334a45a8ff	5044	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	5045	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5046
bogdanm	0:9b334a45a8ff	5047	/* Set the filter */
bogdanm	0:9b334a45a8ff	5048	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	5049	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	5050
bogdanm	0:9b334a45a8ff	5051	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	5052	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	5053	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	5054
bogdanm	0:9b334a45a8ff	5055	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5056	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5057	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5058	}
bogdanm	0:9b334a45a8ff	5059
bogdanm	0:9b334a45a8ff	5060	/**
bogdanm	0:9b334a45a8ff	5061	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	5062	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5063	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5064	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5065	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5066	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5067	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5068	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5069	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5070	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5071	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5072	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5073	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5074	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5075	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm	0:9b334a45a8ff	5076	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5077	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5078	* @retval None
bogdanm	0:9b334a45a8ff	5079	*/
bogdanm	0:9b334a45a8ff	5080	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5081	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5082	{
bogdanm	0:9b334a45a8ff	5083	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5084	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5085
bogdanm	0:9b334a45a8ff	5086	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	5087	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	5088	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5089	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5090
bogdanm	0:9b334a45a8ff	5091	/* Select the Input */
bogdanm	0:9b334a45a8ff	5092	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	5093	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5094
bogdanm	0:9b334a45a8ff	5095	/* Set the filter */
bogdanm	0:9b334a45a8ff	5096	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	5097	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	5098
bogdanm	0:9b334a45a8ff	5099	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	5100	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	5101	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	5102
bogdanm	0:9b334a45a8ff	5103	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5104	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5105	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	5106	}
bogdanm	0:9b334a45a8ff	5107
bogdanm	0:9b334a45a8ff	5108	/**
bogdanm	0:9b334a45a8ff	5109	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	5110	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5111	* @param InputTriggerSource: The Input Trigger source.
bogdanm	0:9b334a45a8ff	5112	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5113	* @arg TIM_TS_ITR0: Internal Trigger 0
bogdanm	0:9b334a45a8ff	5114	* @arg TIM_TS_ITR1: Internal Trigger 1
bogdanm	0:9b334a45a8ff	5115	* @arg TIM_TS_ITR2: Internal Trigger 2
bogdanm	0:9b334a45a8ff	5116	* @arg TIM_TS_ITR3: Internal Trigger 3
bogdanm	0:9b334a45a8ff	5117	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
bogdanm	0:9b334a45a8ff	5118	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	5119	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	5120	* @arg TIM_TS_ETRF: External Trigger input
bogdanm	0:9b334a45a8ff	5121	* @retval None
bogdanm	0:9b334a45a8ff	5122	*/
bogdanm	0:9b334a45a8ff	5123	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
bogdanm	0:9b334a45a8ff	5124	{
bogdanm	0:9b334a45a8ff	5125	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5126
bogdanm	0:9b334a45a8ff	5127	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5128	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5129	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	5130	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5131	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	5132	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	5133	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5134	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5135	}
bogdanm	0:9b334a45a8ff	5136	/**
bogdanm	0:9b334a45a8ff	5137	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	5138	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5139	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	5140	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5141	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
bogdanm	0:9b334a45a8ff	5142	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
bogdanm	0:9b334a45a8ff	5143	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
bogdanm	0:9b334a45a8ff	5144	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	5145	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	5146	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5147	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
bogdanm	0:9b334a45a8ff	5148	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
bogdanm	0:9b334a45a8ff	5149	* @param ExtTRGFilter: External Trigger Filter.
bogdanm	0:9b334a45a8ff	5150	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	5151	* @retval None
bogdanm	0:9b334a45a8ff	5152	*/
bogdanm	0:9b334a45a8ff	5153	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	5154	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	5155	{
bogdanm	0:9b334a45a8ff	5156	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5157
bogdanm	0:9b334a45a8ff	5158	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5159
bogdanm	0:9b334a45a8ff	5160	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	5161	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	5162
bogdanm	0:9b334a45a8ff	5163	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	5164	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	5165
bogdanm	0:9b334a45a8ff	5166	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5167	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5168	}
bogdanm	0:9b334a45a8ff	5169
bogdanm	0:9b334a45a8ff	5170	/**
bogdanm	0:9b334a45a8ff	5171	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	5172	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5173	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	5174	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5175	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	5176	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	5177	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	5178	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	5179	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	5180	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	5181	* @retval None
bogdanm	0:9b334a45a8ff	5182	*/
bogdanm	0:9b334a45a8ff	5183	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	5184	{
bogdanm	0:9b334a45a8ff	5185	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	5186
bogdanm	0:9b334a45a8ff	5187	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5188	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm	0:9b334a45a8ff	5189	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	5190
bogdanm	0:9b334a45a8ff	5191	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	5192
bogdanm	0:9b334a45a8ff	5193	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5194	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	5195
bogdanm	0:9b334a45a8ff	5196	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5197	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	5198	}
bogdanm	0:9b334a45a8ff	5199
bogdanm	0:9b334a45a8ff	5200
bogdanm	0:9b334a45a8ff	5201	/**
bogdanm	0:9b334a45a8ff	5202	* @}
bogdanm	0:9b334a45a8ff	5203	*/
bogdanm	0:9b334a45a8ff	5204
bogdanm	0:9b334a45a8ff	5205	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	5206	/**
bogdanm	0:9b334a45a8ff	5207	* @}
bogdanm	0:9b334a45a8ff	5208	*/
bogdanm	0:9b334a45a8ff	5209
bogdanm	0:9b334a45a8ff	5210	/**
bogdanm	0:9b334a45a8ff	5211	* @}
bogdanm	0:9b334a45a8ff	5212	*/
bogdanm	0:9b334a45a8ff	5213	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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