en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_hal_smbus.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief SMBUS HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the System Management Bus (SMBus) peripheral,
bogdanm 0:9b334a45a8ff 11 * based on I2C principales of operation :
bogdanm 0:9b334a45a8ff 12 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 13 * + IO operation functions
bogdanm 0:9b334a45a8ff 14 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 @verbatim
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 19 ==============================================================================
bogdanm 0:9b334a45a8ff 20 [..]
bogdanm 0:9b334a45a8ff 21 The SMBUS HAL driver can be used as follows:
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 24 SMBUS_HandleTypeDef hsmbus;
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API:
bogdanm 0:9b334a45a8ff 27 (##) Enable the SMBUSx interface clock
bogdanm 0:9b334a45a8ff 28 (##) SMBUS pins configuration
bogdanm 0:9b334a45a8ff 29 (+++) Enable the clock for the SMBUS GPIOs
bogdanm 0:9b334a45a8ff 30 (+++) Configure SMBUS pins as alternate function open-drain
bogdanm 0:9b334a45a8ff 31 (##) NVIC configuration if you need to use interrupt process
bogdanm 0:9b334a45a8ff 32 (+++) Configure the SMBUSx interrupt priority
bogdanm 0:9b334a45a8ff 33 (+++) Enable the NVIC SMBUS IRQ Channel
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode,
bogdanm 0:9b334a45a8ff 36 Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
bogdanm 0:9b334a45a8ff 37 Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
bogdanm 0:9b334a45a8ff 40 (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm 0:9b334a45a8ff 41 by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 (#) For SMBUS IO operations, only one mode of operations is available within this driver :
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 48 ===================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT()
bogdanm 0:9b334a45a8ff 51 (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 52 add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback
bogdanm 0:9b334a45a8ff 53 (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT()
bogdanm 0:9b334a45a8ff 54 (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 55 add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback
bogdanm 0:9b334a45a8ff 56 (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT()
bogdanm 0:9b334a45a8ff 57 (++) The associated previous transfer callback is called at the end of abort process
bogdanm 0:9b334a45a8ff 58 (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit
bogdanm 0:9b334a45a8ff 59 (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive
bogdanm 0:9b334a45a8ff 60 (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
bogdanm 0:9b334a45a8ff 61 using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT()
bogdanm 0:9b334a45a8ff 62 (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can
bogdanm 0:9b334a45a8ff 63 add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
bogdanm 0:9b334a45a8ff 64 (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 65 add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback
bogdanm 0:9b334a45a8ff 66 (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT()
bogdanm 0:9b334a45a8ff 67 (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 68 add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback
bogdanm 0:9b334a45a8ff 69 (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT()
bogdanm 0:9b334a45a8ff 70 (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 71 add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback
bogdanm 0:9b334a45a8ff 72 (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
bogdanm 0:9b334a45a8ff 73 (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
bogdanm 0:9b334a45a8ff 74 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm 0:9b334a45a8ff 75 to check the Alert Error Code using function HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 76 (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 77 (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 78 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm 0:9b334a45a8ff 79 to check the Error Code using function HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 *** SMBUS HAL driver macros list ***
bogdanm 0:9b334a45a8ff 82 ==================================
bogdanm 0:9b334a45a8ff 83 [..]
bogdanm 0:9b334a45a8ff 84 Below the list of most used macros in SMBUS HAL driver.
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
bogdanm 0:9b334a45a8ff 87 (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
bogdanm 0:9b334a45a8ff 88 (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
bogdanm 0:9b334a45a8ff 89 (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
bogdanm 0:9b334a45a8ff 90 (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
bogdanm 0:9b334a45a8ff 91 (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 [..]
bogdanm 0:9b334a45a8ff 94 (@) You can refer to the SMBUS HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 @endverbatim
bogdanm 0:9b334a45a8ff 98 ******************************************************************************
bogdanm 0:9b334a45a8ff 99 * @attention
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 102 *
bogdanm 0:9b334a45a8ff 103 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 104 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 105 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 106 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 108 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 109 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 111 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 112 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 113 *
bogdanm 0:9b334a45a8ff 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 124 *
bogdanm 0:9b334a45a8ff 125 ******************************************************************************
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 #include "stm32f3xx_hal.h"
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @defgroup SMBUS SMBUS HAL module driver
bogdanm 0:9b334a45a8ff 136 * @brief SMBUS HAL module driver
bogdanm 0:9b334a45a8ff 137 * @{
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #ifdef HAL_SMBUS_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 143 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 144 /** @defgroup SMBUS_Private_Define SMBUS Private Define
bogdanm 0:9b334a45a8ff 145 * @{
bogdanm 0:9b334a45a8ff 146 */
bogdanm 0:9b334a45a8ff 147 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
bogdanm 0:9b334a45a8ff 148 #define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
bogdanm 0:9b334a45a8ff 149 #define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 150 #define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 151 #define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 152 #define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 153 #define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 154 #define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 155 #define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 156 #define MAX_NBYTE_SIZE 255
bogdanm 0:9b334a45a8ff 157 /**
bogdanm 0:9b334a45a8ff 158 * @}
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 162 /** @defgroup SMBUS_Private_Macro SMBUS Private Macro
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165 #define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
bogdanm 0:9b334a45a8ff 166 #define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
bogdanm 0:9b334a45a8ff 167 /**
bogdanm 0:9b334a45a8ff 168 * @}
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 172 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 173 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
bogdanm 0:9b334a45a8ff 174 * @{
bogdanm 0:9b334a45a8ff 175 */
bogdanm 0:9b334a45a8ff 176 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm 0:9b334a45a8ff 179 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm 0:9b334a45a8ff 180 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm 0:9b334a45a8ff 181 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
bogdanm 0:9b334a45a8ff 184 /**
bogdanm 0:9b334a45a8ff 185 * @}
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
bogdanm 0:9b334a45a8ff 191 * @{
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 195 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 196 *
bogdanm 0:9b334a45a8ff 197 @verbatim
bogdanm 0:9b334a45a8ff 198 ===============================================================================
bogdanm 0:9b334a45a8ff 199 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 200 ===============================================================================
bogdanm 0:9b334a45a8ff 201 [..] This subsection provides a set of functions allowing to initialize and
bogdanm 0:9b334a45a8ff 202 de-initialiaze the SMBUSx peripheral:
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
bogdanm 0:9b334a45a8ff 205 all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 (+) Call the function HAL_SMBUS_Init() to configure the selected device with
bogdanm 0:9b334a45a8ff 208 the selected configuration:
bogdanm 0:9b334a45a8ff 209 (++) Clock Timing
bogdanm 0:9b334a45a8ff 210 (++) Bus Timeout
bogdanm 0:9b334a45a8ff 211 (++) Analog Filer mode
bogdanm 0:9b334a45a8ff 212 (++) Own Address 1
bogdanm 0:9b334a45a8ff 213 (++) Addressing mode (Master, Slave)
bogdanm 0:9b334a45a8ff 214 (++) Dual Addressing mode
bogdanm 0:9b334a45a8ff 215 (++) Own Address 2
bogdanm 0:9b334a45a8ff 216 (++) Own Address 2 Mask
bogdanm 0:9b334a45a8ff 217 (++) General call mode
bogdanm 0:9b334a45a8ff 218 (++) Nostretch mode
bogdanm 0:9b334a45a8ff 219 (++) Packet Error Check mode
bogdanm 0:9b334a45a8ff 220 (++) Peripheral mode
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
bogdanm 0:9b334a45a8ff 224 of the selected SMBUSx periperal.
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 @endverbatim
bogdanm 0:9b334a45a8ff 227 * @{
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /**
bogdanm 0:9b334a45a8ff 231 * @brief Initializes the SMBUS according to the specified parameters
bogdanm 0:9b334a45a8ff 232 * in the SMBUS_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 233 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 234 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 235 * @retval HAL status
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 /* Check the SMBUS handle allocation */
bogdanm 0:9b334a45a8ff 240 if(hsmbus == HAL_NULL)
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Check the parameters */
bogdanm 0:9b334a45a8ff 246 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 247 assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
bogdanm 0:9b334a45a8ff 248 assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
bogdanm 0:9b334a45a8ff 249 assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
bogdanm 0:9b334a45a8ff 250 assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
bogdanm 0:9b334a45a8ff 251 assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
bogdanm 0:9b334a45a8ff 252 assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
bogdanm 0:9b334a45a8ff 253 assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
bogdanm 0:9b334a45a8ff 254 assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
bogdanm 0:9b334a45a8ff 255 assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
bogdanm 0:9b334a45a8ff 256 assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 if(hsmbus->State == HAL_SMBUS_STATE_RESET)
bogdanm 0:9b334a45a8ff 259 {
bogdanm 0:9b334a45a8ff 260 /* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 261 HAL_SMBUS_MspInit(hsmbus);
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Disable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 267 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 270 /* Configure SMBUSx: Frequency range */
bogdanm 0:9b334a45a8ff 271 hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 274 /* Configure SMBUSx: Bus Timeout */
bogdanm 0:9b334a45a8ff 275 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
bogdanm 0:9b334a45a8ff 276 hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
bogdanm 0:9b334a45a8ff 277 hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 280 /* Configure SMBUSx: Own Address1 and ack own address1 mode */
bogdanm 0:9b334a45a8ff 281 hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 if(hsmbus->Init.OwnAddress1 != 0)
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289 else /* SMBUS_ADDRESSINGMODE_10BIT */
bogdanm 0:9b334a45a8ff 290 {
bogdanm 0:9b334a45a8ff 291 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
bogdanm 0:9b334a45a8ff 292 }
bogdanm 0:9b334a45a8ff 293 }
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 296 /* Configure SMBUSx: Addressing Master mode */
bogdanm 0:9b334a45a8ff 297 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
bogdanm 0:9b334a45a8ff 302 /* AUTOEND and NACK bit will be manage during Transfer process */
bogdanm 0:9b334a45a8ff 303 hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 306 /* Configure SMBUSx: Dual mode and Own Address2 */
bogdanm 0:9b334a45a8ff 307 hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 310 /* Configure SMBUSx: Generalcall and NoStretch mode */
bogdanm 0:9b334a45a8ff 311 hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
bogdanm 0:9b334a45a8ff 314 if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED)
bogdanm 0:9b334a45a8ff 315 && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
bogdanm 0:9b334a45a8ff 318 }
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Enable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 321 __HAL_SMBUS_ENABLE(hsmbus);
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 324 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 325 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 return HAL_OK;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /**
bogdanm 0:9b334a45a8ff 331 * @brief DeInitializes the SMBUS peripheral.
bogdanm 0:9b334a45a8ff 332 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 333 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 334 * @retval HAL status
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 /* Check the SMBUS handle allocation */
bogdanm 0:9b334a45a8ff 339 if(hsmbus == HAL_NULL)
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 342 }
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /* Check the parameters */
bogdanm 0:9b334a45a8ff 345 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /* Disable the SMBUS Peripheral Clock */
bogdanm 0:9b334a45a8ff 350 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 353 HAL_SMBUS_MspDeInit(hsmbus);
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 356 hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
bogdanm 0:9b334a45a8ff 357 hsmbus->State = HAL_SMBUS_STATE_RESET;
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Release Lock */
bogdanm 0:9b334a45a8ff 360 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 return HAL_OK;
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /**
bogdanm 0:9b334a45a8ff 366 * @brief SMBUS MSP Init.
bogdanm 0:9b334a45a8ff 367 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 368 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 369 * @retval None
bogdanm 0:9b334a45a8ff 370 */
bogdanm 0:9b334a45a8ff 371 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 372 {
bogdanm 0:9b334a45a8ff 373 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 374 the HAL_SMBUS_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /**
bogdanm 0:9b334a45a8ff 379 * @brief SMBUS MSP DeInit
bogdanm 0:9b334a45a8ff 380 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 381 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 382 * @retval None
bogdanm 0:9b334a45a8ff 383 */
bogdanm 0:9b334a45a8ff 384 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 385 {
bogdanm 0:9b334a45a8ff 386 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 387 the HAL_SMBUS_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 388 */
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /**
bogdanm 0:9b334a45a8ff 392 * @}
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
bogdanm 0:9b334a45a8ff 396 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 397 *
bogdanm 0:9b334a45a8ff 398 @verbatim
bogdanm 0:9b334a45a8ff 399 ===============================================================================
bogdanm 0:9b334a45a8ff 400 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 401 ===============================================================================
bogdanm 0:9b334a45a8ff 402 [..]
bogdanm 0:9b334a45a8ff 403 This subsection provides a set of functions allowing to manage the SMBUS data
bogdanm 0:9b334a45a8ff 404 transfers.
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 (#) Blocking mode function to check if device is ready for usage is :
bogdanm 0:9b334a45a8ff 407 (++) HAL_SMBUS_IsDeviceReady()
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 (#) There is only one mode of transfer:
bogdanm 0:9b334a45a8ff 410 (++) No-Blocking mode : The communication is performed using Interrupts.
bogdanm 0:9b334a45a8ff 411 These functions return the status of the transfer startup.
bogdanm 0:9b334a45a8ff 412 The end of the data processing will be indicated through the
bogdanm 0:9b334a45a8ff 413 dedicated SMBUS IRQ when using Interrupt mode.
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 (#) No-Blocking mode functions with Interrupt are :
bogdanm 0:9b334a45a8ff 416 (++) HAL_SMBUS_Master_Transmit_IT()
bogdanm 0:9b334a45a8ff 417 (++) HAL_SMBUS_Master_Receive_IT()
bogdanm 0:9b334a45a8ff 418 (++) HAL_SMBUS_Slave_Transmit_IT()
bogdanm 0:9b334a45a8ff 419 (++) HAL_SMBUS_Slave_Receive_IT()
bogdanm 0:9b334a45a8ff 420 (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT()
bogdanm 0:9b334a45a8ff 421 (++) HAL_SMBUS_DisableListen_IT()
bogdanm 0:9b334a45a8ff 422 (++) HAL_SMBUS_EnableAlert_IT()
bogdanm 0:9b334a45a8ff 423 (++) HAL_SMBUS_DisableAlert_IT()
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
bogdanm 0:9b334a45a8ff 426 (++) HAL_SMBUS_MasterTxCpltCallback()
bogdanm 0:9b334a45a8ff 427 (++) HAL_SMBUS_MasterRxCpltCallback()
bogdanm 0:9b334a45a8ff 428 (++) HAL_SMBUS_SlaveTxCpltCallback()
bogdanm 0:9b334a45a8ff 429 (++) HAL_SMBUS_SlaveRxCpltCallback()
bogdanm 0:9b334a45a8ff 430 (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback()
bogdanm 0:9b334a45a8ff 431 (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback()
bogdanm 0:9b334a45a8ff 432 (++) HAL_SMBUS_ErrorCallback()
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 @endverbatim
bogdanm 0:9b334a45a8ff 435 * @{
bogdanm 0:9b334a45a8ff 436 */
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /** @defgroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
bogdanm 0:9b334a45a8ff 439 * @{
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /**
bogdanm 0:9b334a45a8ff 443 * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 444 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 445 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 446 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 447 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 448 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 449 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 450 * @retval HAL status
bogdanm 0:9b334a45a8ff 451 */
bogdanm 0:9b334a45a8ff 452 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 453 {
bogdanm 0:9b334a45a8ff 454 /* Check the parameters */
bogdanm 0:9b334a45a8ff 455 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 /* Process Locked */
bogdanm 0:9b334a45a8ff 460 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm 0:9b334a45a8ff 463 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 464 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 465 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 466 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 467 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* In case of Quick command, remove autoend mode */
bogdanm 0:9b334a45a8ff 470 /* Manage the stop generation by software */
bogdanm 0:9b334a45a8ff 471 if(hsmbus->pBuffPtr == HAL_NULL)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 if(Size > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480 else
bogdanm 0:9b334a45a8ff 481 {
bogdanm 0:9b334a45a8ff 482 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* Send Slave Address */
bogdanm 0:9b334a45a8ff 486 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm 0:9b334a45a8ff 487 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491 else
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 /* If transfer direction not change, do not generate Restart Condition */
bogdanm 0:9b334a45a8ff 494 /* Mean Previous state is same as current state */
bogdanm 0:9b334a45a8ff 495 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 /* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm 0:9b334a45a8ff 500 else
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 506 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 507 if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 510 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 511 }
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 515 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 518 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 519 process unlock */
bogdanm 0:9b334a45a8ff 520 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 return HAL_OK;
bogdanm 0:9b334a45a8ff 523 }
bogdanm 0:9b334a45a8ff 524 else
bogdanm 0:9b334a45a8ff 525 {
bogdanm 0:9b334a45a8ff 526 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 527 }
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /**
bogdanm 0:9b334a45a8ff 531 * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 532 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 533 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 534 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 535 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 536 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 537 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 538 * @retval HAL status
bogdanm 0:9b334a45a8ff 539 */
bogdanm 0:9b334a45a8ff 540 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 /* Check the parameters */
bogdanm 0:9b334a45a8ff 543 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 /* Process Locked */
bogdanm 0:9b334a45a8ff 548 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm 0:9b334a45a8ff 551 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 554 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 555 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 556 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 /* In case of Quick command, remove autoend mode */
bogdanm 0:9b334a45a8ff 559 /* Manage the stop generation by software */
bogdanm 0:9b334a45a8ff 560 if(hsmbus->pBuffPtr == HAL_NULL)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm 0:9b334a45a8ff 563 }
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 if(Size > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 else
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 572 }
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /* Send Slave Address */
bogdanm 0:9b334a45a8ff 575 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm 0:9b334a45a8ff 576 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm 0:9b334a45a8ff 577 {
bogdanm 0:9b334a45a8ff 578 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580 else
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 /* If transfer direction not change, do not generate Restart Condition */
bogdanm 0:9b334a45a8ff 583 /* Mean Previous state is same as current state */
bogdanm 0:9b334a45a8ff 584 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 585 {
bogdanm 0:9b334a45a8ff 586 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588 /* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm 0:9b334a45a8ff 589 else
bogdanm 0:9b334a45a8ff 590 {
bogdanm 0:9b334a45a8ff 591 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
bogdanm 0:9b334a45a8ff 592 }
bogdanm 0:9b334a45a8ff 593 }
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 596 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 599 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 600 process unlock */
bogdanm 0:9b334a45a8ff 601 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 return HAL_OK;
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605 else
bogdanm 0:9b334a45a8ff 606 {
bogdanm 0:9b334a45a8ff 607 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 608 }
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 /**
bogdanm 0:9b334a45a8ff 612 * @brief Abort a master/host SMBUS process commnunication with Interrupt
bogdanm 0:9b334a45a8ff 613 * @note : This abort can be called only if state is ready
bogdanm 0:9b334a45a8ff 614 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 615 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 616 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 617 * @retval HAL status
bogdanm 0:9b334a45a8ff 618 */
bogdanm 0:9b334a45a8ff 619 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
bogdanm 0:9b334a45a8ff 620 {
bogdanm 0:9b334a45a8ff 621 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 622 {
bogdanm 0:9b334a45a8ff 623 /* Process Locked */
bogdanm 0:9b334a45a8ff 624 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Keep the same state as previous */
bogdanm 0:9b334a45a8ff 627 /* to perform as well the call of the corresponding end of transfer callback */
bogdanm 0:9b334a45a8ff 628 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 629 {
bogdanm 0:9b334a45a8ff 630 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm 0:9b334a45a8ff 631 }
bogdanm 0:9b334a45a8ff 632 else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 633 {
bogdanm 0:9b334a45a8ff 634 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636 else
bogdanm 0:9b334a45a8ff 637 {
bogdanm 0:9b334a45a8ff 638 /* Wrong usage of abort function */
bogdanm 0:9b334a45a8ff 639 /* This function should be used only in case of abort monitored by master device */
bogdanm 0:9b334a45a8ff 640 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
bogdanm 0:9b334a45a8ff 645 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
bogdanm 0:9b334a45a8ff 646 SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 649 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 652 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 653 process unlock */
bogdanm 0:9b334a45a8ff 654 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 655 {
bogdanm 0:9b334a45a8ff 656 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 return HAL_OK;
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 else
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /**
bogdanm 0:9b334a45a8ff 672 * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 673 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 674 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 675 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 676 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 677 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 678 * @retval HAL status
bogdanm 0:9b334a45a8ff 679 */
bogdanm 0:9b334a45a8ff 680 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 /* Check the parameters */
bogdanm 0:9b334a45a8ff 683 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 if((pData == HAL_NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm 0:9b334a45a8ff 693 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Process Locked */
bogdanm 0:9b334a45a8ff 696 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
bogdanm 0:9b334a45a8ff 699 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Set SBC bit to manage Acknowledge at each bit */
bogdanm 0:9b334a45a8ff 702 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Enable Address Acknowledge */
bogdanm 0:9b334a45a8ff 705 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 708 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 709 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 710 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 711 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 if(Size > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 714 {
bogdanm 0:9b334a45a8ff 715 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 716 }
bogdanm 0:9b334a45a8ff 717 else
bogdanm 0:9b334a45a8ff 718 {
bogdanm 0:9b334a45a8ff 719 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 720 }
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm 0:9b334a45a8ff 723 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm 0:9b334a45a8ff 724 {
bogdanm 0:9b334a45a8ff 725 SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 726 }
bogdanm 0:9b334a45a8ff 727 else
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 /* Set NBYTE to transmit */
bogdanm 0:9b334a45a8ff 730 SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 733 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 734 if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 735 {
bogdanm 0:9b334a45a8ff 736 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 737 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 738 }
bogdanm 0:9b334a45a8ff 739 }
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741 /* Clear ADDR flag after prepare the transfer parameters */
bogdanm 0:9b334a45a8ff 742 /* This action will generate an acknowledge to the HOST */
bogdanm 0:9b334a45a8ff 743 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 746 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 749 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 750 process unlock */
bogdanm 0:9b334a45a8ff 751 /* REnable ADDR interrupt */
bogdanm 0:9b334a45a8ff 752 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 return HAL_OK;
bogdanm 0:9b334a45a8ff 755 }
bogdanm 0:9b334a45a8ff 756 else
bogdanm 0:9b334a45a8ff 757 {
bogdanm 0:9b334a45a8ff 758 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 /**
bogdanm 0:9b334a45a8ff 763 * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 764 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 765 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 766 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 767 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 768 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 769 * @retval HAL status
bogdanm 0:9b334a45a8ff 770 */
bogdanm 0:9b334a45a8ff 771 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 772 {
bogdanm 0:9b334a45a8ff 773 /* Check the parameters */
bogdanm 0:9b334a45a8ff 774 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 775
bogdanm 0:9b334a45a8ff 776 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 777 {
bogdanm 0:9b334a45a8ff 778 if((pData == HAL_NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm 0:9b334a45a8ff 784 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /* Process Locked */
bogdanm 0:9b334a45a8ff 787 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
bogdanm 0:9b334a45a8ff 790 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /* Set SBC bit to manage Acknowledge at each bit */
bogdanm 0:9b334a45a8ff 793 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Enable Address Acknowledge */
bogdanm 0:9b334a45a8ff 796 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 799 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 800 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 801 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 802 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* Set NBYTE to receive */
bogdanm 0:9b334a45a8ff 805 /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
bogdanm 0:9b334a45a8ff 806 /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
bogdanm 0:9b334a45a8ff 807 /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
bogdanm 0:9b334a45a8ff 808 /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
bogdanm 0:9b334a45a8ff 809 if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
bogdanm 0:9b334a45a8ff 810 {
bogdanm 0:9b334a45a8ff 811 SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 812 }
bogdanm 0:9b334a45a8ff 813 else
bogdanm 0:9b334a45a8ff 814 {
bogdanm 0:9b334a45a8ff 815 SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 816 }
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /* Clear ADDR flag after prepare the transfer parameters */
bogdanm 0:9b334a45a8ff 819 /* This action will generate an acknowledge to the HOST */
bogdanm 0:9b334a45a8ff 820 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 823 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 826 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 827 process unlock */
bogdanm 0:9b334a45a8ff 828 /* REnable ADDR interrupt */
bogdanm 0:9b334a45a8ff 829 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831 return HAL_OK;
bogdanm 0:9b334a45a8ff 832 }
bogdanm 0:9b334a45a8ff 833 else
bogdanm 0:9b334a45a8ff 834 {
bogdanm 0:9b334a45a8ff 835 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 836 }
bogdanm 0:9b334a45a8ff 837 }
bogdanm 0:9b334a45a8ff 838
bogdanm 0:9b334a45a8ff 839 /**
bogdanm 0:9b334a45a8ff 840 * @brief This function enable the Address listen mode
bogdanm 0:9b334a45a8ff 841 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 842 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 843 * @retval HAL status
bogdanm 0:9b334a45a8ff 844 */
bogdanm 0:9b334a45a8ff 845 HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /* Enable the Address Match interrupt */
bogdanm 0:9b334a45a8ff 850 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 return HAL_OK;
bogdanm 0:9b334a45a8ff 853 }
bogdanm 0:9b334a45a8ff 854
bogdanm 0:9b334a45a8ff 855 /**
bogdanm 0:9b334a45a8ff 856 * @brief This function disable the Address listen mode
bogdanm 0:9b334a45a8ff 857 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 858 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 859 * @retval HAL status
bogdanm 0:9b334a45a8ff 860 */
bogdanm 0:9b334a45a8ff 861 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 862 {
bogdanm 0:9b334a45a8ff 863 /* Disable Address listen mode only if a transfer is not ongoing */
bogdanm 0:9b334a45a8ff 864 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 865 {
bogdanm 0:9b334a45a8ff 866 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /* Disable the Address Match interrupt */
bogdanm 0:9b334a45a8ff 869 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 return HAL_OK;
bogdanm 0:9b334a45a8ff 872 }
bogdanm 0:9b334a45a8ff 873 else
bogdanm 0:9b334a45a8ff 874 {
bogdanm 0:9b334a45a8ff 875 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 876 }
bogdanm 0:9b334a45a8ff 877 }
bogdanm 0:9b334a45a8ff 878
bogdanm 0:9b334a45a8ff 879 /**
bogdanm 0:9b334a45a8ff 880 * @brief This function enable the SMBUS alert mode.
bogdanm 0:9b334a45a8ff 881 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 882 * the configuration information for the specified SMBUSx peripheral.
bogdanm 0:9b334a45a8ff 883 * @retval HAL status
bogdanm 0:9b334a45a8ff 884 */
bogdanm 0:9b334a45a8ff 885 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 886 {
bogdanm 0:9b334a45a8ff 887 /* Enable SMBus alert */
bogdanm 0:9b334a45a8ff 888 hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Clear ALERT flag */
bogdanm 0:9b334a45a8ff 891 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893 /* Enable Alert Interrupt */
bogdanm 0:9b334a45a8ff 894 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 return HAL_OK;
bogdanm 0:9b334a45a8ff 897 }
bogdanm 0:9b334a45a8ff 898 /**
bogdanm 0:9b334a45a8ff 899 * @brief This function disable the SMBUS alert mode.
bogdanm 0:9b334a45a8ff 900 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 901 * the configuration information for the specified SMBUSx peripheral.
bogdanm 0:9b334a45a8ff 902 * @retval HAL status
bogdanm 0:9b334a45a8ff 903 */
bogdanm 0:9b334a45a8ff 904 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 905 {
bogdanm 0:9b334a45a8ff 906 /* Enable SMBus alert */
bogdanm 0:9b334a45a8ff 907 hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 /* Disable Alert Interrupt */
bogdanm 0:9b334a45a8ff 910 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 return HAL_OK;
bogdanm 0:9b334a45a8ff 913 }
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 /**
bogdanm 0:9b334a45a8ff 916 * @}
bogdanm 0:9b334a45a8ff 917 */
bogdanm 0:9b334a45a8ff 918
bogdanm 0:9b334a45a8ff 919 /** @defgroup Blocking_mode_Polling Blocking mode Polling
bogdanm 0:9b334a45a8ff 920 * @{
bogdanm 0:9b334a45a8ff 921 */
bogdanm 0:9b334a45a8ff 922 /**
bogdanm 0:9b334a45a8ff 923 * @brief Checks if target device is ready for communication.
bogdanm 0:9b334a45a8ff 924 * @note This function is used with Memory devices
bogdanm 0:9b334a45a8ff 925 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 926 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 927 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 928 * @param Trials: Number of trials
bogdanm 0:9b334a45a8ff 929 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 930 * @retval HAL status
bogdanm 0:9b334a45a8ff 931 */
bogdanm 0:9b334a45a8ff 932 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 933 {
bogdanm 0:9b334a45a8ff 934 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 935
bogdanm 0:9b334a45a8ff 936 __IO uint32_t SMBUS_Trials = 0;
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 939 {
bogdanm 0:9b334a45a8ff 940 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
bogdanm 0:9b334a45a8ff 941 {
bogdanm 0:9b334a45a8ff 942 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 943 }
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 /* Process Locked */
bogdanm 0:9b334a45a8ff 946 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 947
bogdanm 0:9b334a45a8ff 948 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 949 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 do
bogdanm 0:9b334a45a8ff 952 {
bogdanm 0:9b334a45a8ff 953 /* Generate Start */
bogdanm 0:9b334a45a8ff 954 hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm 0:9b334a45a8ff 957 /* Wait until STOPF flag is set or a NACK flag is set*/
bogdanm 0:9b334a45a8ff 958 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 959 while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
bogdanm 0:9b334a45a8ff 960 {
bogdanm 0:9b334a45a8ff 961 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 962 {
bogdanm 0:9b334a45a8ff 963 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 964 {
bogdanm 0:9b334a45a8ff 965 /* Device is ready */
bogdanm 0:9b334a45a8ff 966 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 967
bogdanm 0:9b334a45a8ff 968 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 969 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 970 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 971 }
bogdanm 0:9b334a45a8ff 972 }
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 /* Check if the NACKF flag has not been set */
bogdanm 0:9b334a45a8ff 976 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
bogdanm 0:9b334a45a8ff 977 {
bogdanm 0:9b334a45a8ff 978 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 979 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 980 {
bogdanm 0:9b334a45a8ff 981 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 982 }
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 985 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 /* Device is ready */
bogdanm 0:9b334a45a8ff 988 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 989
bogdanm 0:9b334a45a8ff 990 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 991 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 return HAL_OK;
bogdanm 0:9b334a45a8ff 994 }
bogdanm 0:9b334a45a8ff 995 else
bogdanm 0:9b334a45a8ff 996 {
bogdanm 0:9b334a45a8ff 997 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 998 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1004 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /* Clear STOP Flag, auto generated with autoend*/
bogdanm 0:9b334a45a8ff 1007 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1008 }
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 /* Check if the maximum allowed number of trials has been reached */
bogdanm 0:9b334a45a8ff 1011 if (SMBUS_Trials++ == Trials)
bogdanm 0:9b334a45a8ff 1012 {
bogdanm 0:9b334a45a8ff 1013 /* Generate Stop */
bogdanm 0:9b334a45a8ff 1014 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 1017 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 1018 {
bogdanm 0:9b334a45a8ff 1019 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1020 }
bogdanm 0:9b334a45a8ff 1021
bogdanm 0:9b334a45a8ff 1022 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1023 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1024 }
bogdanm 0:9b334a45a8ff 1025 }while(SMBUS_Trials < Trials);
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1030 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1033 }
bogdanm 0:9b334a45a8ff 1034 else
bogdanm 0:9b334a45a8ff 1035 {
bogdanm 0:9b334a45a8ff 1036 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038 }
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @}
bogdanm 0:9b334a45a8ff 1041 */
bogdanm 0:9b334a45a8ff 1042
bogdanm 0:9b334a45a8ff 1043 /** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
bogdanm 0:9b334a45a8ff 1044 * @{
bogdanm 0:9b334a45a8ff 1045 */
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 /**
bogdanm 0:9b334a45a8ff 1048 * @brief This function handles SMBUS event interrupt request.
bogdanm 0:9b334a45a8ff 1049 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1050 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1051 * @retval None
bogdanm 0:9b334a45a8ff 1052 */
bogdanm 0:9b334a45a8ff 1053 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1054 {
bogdanm 0:9b334a45a8ff 1055 uint32_t tmpisrvalue = 0;
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /* Use a local variable to store the current ISR flags */
bogdanm 0:9b334a45a8ff 1058 /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
bogdanm 0:9b334a45a8ff 1059 tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus);
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 /* SMBUS in mode Transmitter ---------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1062 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
bogdanm 0:9b334a45a8ff 1063 {
bogdanm 0:9b334a45a8ff 1064 /* Slave mode selected */
bogdanm 0:9b334a45a8ff 1065 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
bogdanm 0:9b334a45a8ff 1066 {
bogdanm 0:9b334a45a8ff 1067 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1068 }
bogdanm 0:9b334a45a8ff 1069 /* Master mode selected */
bogdanm 0:9b334a45a8ff 1070 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1071 {
bogdanm 0:9b334a45a8ff 1072 SMBUS_Master_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1073 }
bogdanm 0:9b334a45a8ff 1074 }
bogdanm 0:9b334a45a8ff 1075
bogdanm 0:9b334a45a8ff 1076 /* SMBUS in mode Receiver ----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1077 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
bogdanm 0:9b334a45a8ff 1078 {
bogdanm 0:9b334a45a8ff 1079 /* Slave mode selected */
bogdanm 0:9b334a45a8ff 1080 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
bogdanm 0:9b334a45a8ff 1081 {
bogdanm 0:9b334a45a8ff 1082 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1083 }
bogdanm 0:9b334a45a8ff 1084 /* Master mode selected */
bogdanm 0:9b334a45a8ff 1085 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1086 {
bogdanm 0:9b334a45a8ff 1087 SMBUS_Master_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1088 }
bogdanm 0:9b334a45a8ff 1089 }
bogdanm 0:9b334a45a8ff 1090
bogdanm 0:9b334a45a8ff 1091 /* SMBUS in mode Listener Only --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1092 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
bogdanm 0:9b334a45a8ff 1093 && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
bogdanm 0:9b334a45a8ff 1094 {
bogdanm 0:9b334a45a8ff 1095 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1096 {
bogdanm 0:9b334a45a8ff 1097 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1098 }
bogdanm 0:9b334a45a8ff 1099 }
bogdanm 0:9b334a45a8ff 1100 }
bogdanm 0:9b334a45a8ff 1101
bogdanm 0:9b334a45a8ff 1102 /**
bogdanm 0:9b334a45a8ff 1103 * @brief This function handles SMBUS error interrupt request.
bogdanm 0:9b334a45a8ff 1104 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1105 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1106 * @retval None
bogdanm 0:9b334a45a8ff 1107 */
bogdanm 0:9b334a45a8ff 1108 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1109 {
bogdanm 0:9b334a45a8ff 1110 /* SMBUS Bus error interrupt occurred ------------------------------------*/
bogdanm 0:9b334a45a8ff 1111 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1112 {
bogdanm 0:9b334a45a8ff 1113 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
bogdanm 0:9b334a45a8ff 1114
bogdanm 0:9b334a45a8ff 1115 /* Clear BERR flag */
bogdanm 0:9b334a45a8ff 1116 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
bogdanm 0:9b334a45a8ff 1117 }
bogdanm 0:9b334a45a8ff 1118
bogdanm 0:9b334a45a8ff 1119 /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
bogdanm 0:9b334a45a8ff 1120 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1121 {
bogdanm 0:9b334a45a8ff 1122 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
bogdanm 0:9b334a45a8ff 1123
bogdanm 0:9b334a45a8ff 1124 /* Clear OVR flag */
bogdanm 0:9b334a45a8ff 1125 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
bogdanm 0:9b334a45a8ff 1126 }
bogdanm 0:9b334a45a8ff 1127
bogdanm 0:9b334a45a8ff 1128 /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
bogdanm 0:9b334a45a8ff 1129 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1130 {
bogdanm 0:9b334a45a8ff 1131 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 /* Clear ARLO flag */
bogdanm 0:9b334a45a8ff 1134 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
bogdanm 0:9b334a45a8ff 1135 }
bogdanm 0:9b334a45a8ff 1136
bogdanm 0:9b334a45a8ff 1137 /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 1138 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1139 {
bogdanm 0:9b334a45a8ff 1140 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
bogdanm 0:9b334a45a8ff 1141
bogdanm 0:9b334a45a8ff 1142 /* Clear TIMEOUT flag */
bogdanm 0:9b334a45a8ff 1143 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
bogdanm 0:9b334a45a8ff 1144 }
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1147 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1148 {
bogdanm 0:9b334a45a8ff 1149 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
bogdanm 0:9b334a45a8ff 1150
bogdanm 0:9b334a45a8ff 1151 /* Clear ALERT flag */
bogdanm 0:9b334a45a8ff 1152 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm 0:9b334a45a8ff 1153 }
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
bogdanm 0:9b334a45a8ff 1156 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1157 {
bogdanm 0:9b334a45a8ff 1158 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
bogdanm 0:9b334a45a8ff 1159
bogdanm 0:9b334a45a8ff 1160 /* Clear PEC error flag */
bogdanm 0:9b334a45a8ff 1161 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
bogdanm 0:9b334a45a8ff 1162 }
bogdanm 0:9b334a45a8ff 1163
bogdanm 0:9b334a45a8ff 1164 /* Call the Error Callback in case of Error detected */
bogdanm 0:9b334a45a8ff 1165 if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
bogdanm 0:9b334a45a8ff 1166 {
bogdanm 0:9b334a45a8ff 1167 /* Do not Reset the the HAL state in case of ALERT error */
bogdanm 0:9b334a45a8ff 1168 if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
bogdanm 0:9b334a45a8ff 1169 {
bogdanm 0:9b334a45a8ff 1170 if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
bogdanm 0:9b334a45a8ff 1171 || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
bogdanm 0:9b334a45a8ff 1172 {
bogdanm 0:9b334a45a8ff 1173 /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
bogdanm 0:9b334a45a8ff 1174 /* keep HAL_SMBUS_STATE_LISTEN if set */
bogdanm 0:9b334a45a8ff 1175 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1176 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
bogdanm 0:9b334a45a8ff 1177 }
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179
bogdanm 0:9b334a45a8ff 1180 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1181 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1182 }
bogdanm 0:9b334a45a8ff 1183 }
bogdanm 0:9b334a45a8ff 1184
bogdanm 0:9b334a45a8ff 1185 /**
bogdanm 0:9b334a45a8ff 1186 * @brief Master Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1187 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1188 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1189 * @retval None
bogdanm 0:9b334a45a8ff 1190 */
bogdanm 0:9b334a45a8ff 1191 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1192 {
bogdanm 0:9b334a45a8ff 1193 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1194 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1195 */
bogdanm 0:9b334a45a8ff 1196 }
bogdanm 0:9b334a45a8ff 1197
bogdanm 0:9b334a45a8ff 1198 /**
bogdanm 0:9b334a45a8ff 1199 * @brief Master Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1200 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1201 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1202 * @retval None
bogdanm 0:9b334a45a8ff 1203 */
bogdanm 0:9b334a45a8ff 1204 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1205 {
bogdanm 0:9b334a45a8ff 1206 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1207 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1208 */
bogdanm 0:9b334a45a8ff 1209 }
bogdanm 0:9b334a45a8ff 1210
bogdanm 0:9b334a45a8ff 1211 /** @brief Slave Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1212 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1213 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1214 * @retval None
bogdanm 0:9b334a45a8ff 1215 */
bogdanm 0:9b334a45a8ff 1216 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1217 {
bogdanm 0:9b334a45a8ff 1218 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1219 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1220 */
bogdanm 0:9b334a45a8ff 1221 }
bogdanm 0:9b334a45a8ff 1222
bogdanm 0:9b334a45a8ff 1223 /**
bogdanm 0:9b334a45a8ff 1224 * @brief Slave Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1225 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1226 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1227 * @retval None
bogdanm 0:9b334a45a8ff 1228 */
bogdanm 0:9b334a45a8ff 1229 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1230 {
bogdanm 0:9b334a45a8ff 1231 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1232 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1233 */
bogdanm 0:9b334a45a8ff 1234 }
bogdanm 0:9b334a45a8ff 1235
bogdanm 0:9b334a45a8ff 1236 /**
bogdanm 0:9b334a45a8ff 1237 * @brief Slave Address Match callbacks.
bogdanm 0:9b334a45a8ff 1238 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1239 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1240 * @param TransferDirection: Master request Transfer Direction (Write/Read)
bogdanm 0:9b334a45a8ff 1241 * @param AddrMatchCode: Address Match Code
bogdanm 0:9b334a45a8ff 1242 * @retval None
bogdanm 0:9b334a45a8ff 1243 */
bogdanm 0:9b334a45a8ff 1244 __weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
bogdanm 0:9b334a45a8ff 1245 {
bogdanm 0:9b334a45a8ff 1246 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1247 the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1248 */
bogdanm 0:9b334a45a8ff 1249 }
bogdanm 0:9b334a45a8ff 1250
bogdanm 0:9b334a45a8ff 1251 /**
bogdanm 0:9b334a45a8ff 1252 * @brief Listen Complete callbacks.
bogdanm 0:9b334a45a8ff 1253 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1254 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1255 * @retval None
bogdanm 0:9b334a45a8ff 1256 */
bogdanm 0:9b334a45a8ff 1257 __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1258 {
bogdanm 0:9b334a45a8ff 1259 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1260 the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1261 */
bogdanm 0:9b334a45a8ff 1262 }
bogdanm 0:9b334a45a8ff 1263
bogdanm 0:9b334a45a8ff 1264 /**
bogdanm 0:9b334a45a8ff 1265 * @brief SMBUS error callbacks.
bogdanm 0:9b334a45a8ff 1266 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1267 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1268 * @retval None
bogdanm 0:9b334a45a8ff 1269 */
bogdanm 0:9b334a45a8ff 1270 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1271 {
bogdanm 0:9b334a45a8ff 1272 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1273 the HAL_SMBUS_ErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1274 */
bogdanm 0:9b334a45a8ff 1275 }
bogdanm 0:9b334a45a8ff 1276
bogdanm 0:9b334a45a8ff 1277 /**
bogdanm 0:9b334a45a8ff 1278 * @}
bogdanm 0:9b334a45a8ff 1279 */
bogdanm 0:9b334a45a8ff 1280
bogdanm 0:9b334a45a8ff 1281 /**
bogdanm 0:9b334a45a8ff 1282 * @}
bogdanm 0:9b334a45a8ff 1283 */
bogdanm 0:9b334a45a8ff 1284
bogdanm 0:9b334a45a8ff 1285 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 1286 * @brief Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 1287 *
bogdanm 0:9b334a45a8ff 1288 @verbatim
bogdanm 0:9b334a45a8ff 1289 ===============================================================================
bogdanm 0:9b334a45a8ff 1290 ##### Peripheral State and Errors functions #####
bogdanm 0:9b334a45a8ff 1291 ===============================================================================
bogdanm 0:9b334a45a8ff 1292 [..]
bogdanm 0:9b334a45a8ff 1293 This subsection permit to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1294 and the data flow.
bogdanm 0:9b334a45a8ff 1295
bogdanm 0:9b334a45a8ff 1296 @endverbatim
bogdanm 0:9b334a45a8ff 1297 * @{
bogdanm 0:9b334a45a8ff 1298 */
bogdanm 0:9b334a45a8ff 1299
bogdanm 0:9b334a45a8ff 1300 /**
bogdanm 0:9b334a45a8ff 1301 * @brief Returns the SMBUS state.
bogdanm 0:9b334a45a8ff 1302 * @param hsmbus : SMBUS handle
bogdanm 0:9b334a45a8ff 1303 * @retval HAL state
bogdanm 0:9b334a45a8ff 1304 */
bogdanm 0:9b334a45a8ff 1305 HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1306 {
bogdanm 0:9b334a45a8ff 1307 return hsmbus->State;
bogdanm 0:9b334a45a8ff 1308 }
bogdanm 0:9b334a45a8ff 1309
bogdanm 0:9b334a45a8ff 1310 /**
bogdanm 0:9b334a45a8ff 1311 * @brief Return the SMBUS error code
bogdanm 0:9b334a45a8ff 1312 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1313 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1314 * @retval SMBUS Error Code
bogdanm 0:9b334a45a8ff 1315 */
bogdanm 0:9b334a45a8ff 1316 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1317 {
bogdanm 0:9b334a45a8ff 1318 return hsmbus->ErrorCode;
bogdanm 0:9b334a45a8ff 1319 }
bogdanm 0:9b334a45a8ff 1320
bogdanm 0:9b334a45a8ff 1321 /**
bogdanm 0:9b334a45a8ff 1322 * @}
bogdanm 0:9b334a45a8ff 1323 */
bogdanm 0:9b334a45a8ff 1324
bogdanm 0:9b334a45a8ff 1325 /**
bogdanm 0:9b334a45a8ff 1326 * @}
bogdanm 0:9b334a45a8ff 1327 */
bogdanm 0:9b334a45a8ff 1328
bogdanm 0:9b334a45a8ff 1329 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
bogdanm 0:9b334a45a8ff 1330 * @brief Data transfers Private functions
bogdanm 0:9b334a45a8ff 1331 * @{
bogdanm 0:9b334a45a8ff 1332 */
bogdanm 0:9b334a45a8ff 1333
bogdanm 0:9b334a45a8ff 1334 /**
bogdanm 0:9b334a45a8ff 1335 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
bogdanm 0:9b334a45a8ff 1336 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1337 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1338 * @retval HAL status
bogdanm 0:9b334a45a8ff 1339 */
bogdanm 0:9b334a45a8ff 1340 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1341 {
bogdanm 0:9b334a45a8ff 1342 uint16_t DevAddress;
bogdanm 0:9b334a45a8ff 1343
bogdanm 0:9b334a45a8ff 1344 /* Process Locked */
bogdanm 0:9b334a45a8ff 1345 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1346
bogdanm 0:9b334a45a8ff 1347 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm 0:9b334a45a8ff 1348 {
bogdanm 0:9b334a45a8ff 1349 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1350 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1351
bogdanm 0:9b334a45a8ff 1352 /* Set corresponding Error Code */
bogdanm 0:9b334a45a8ff 1353 /* No need to generate STOP, it is automatically done */
bogdanm 0:9b334a45a8ff 1354 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
bogdanm 0:9b334a45a8ff 1355
bogdanm 0:9b334a45a8ff 1356 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1357 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1358
bogdanm 0:9b334a45a8ff 1359 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1360 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1361 }
bogdanm 0:9b334a45a8ff 1362 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm 0:9b334a45a8ff 1363 {
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1366 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1367 {
bogdanm 0:9b334a45a8ff 1368 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1369 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1370
bogdanm 0:9b334a45a8ff 1371 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1372 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1373
bogdanm 0:9b334a45a8ff 1374 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1375 __HAL_SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377 /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
bogdanm 0:9b334a45a8ff 1378 /* Disable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 1379 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 1380
bogdanm 0:9b334a45a8ff 1381 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1382 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1383
bogdanm 0:9b334a45a8ff 1384 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1385 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1386
bogdanm 0:9b334a45a8ff 1387 /* REenable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 1388 __HAL_SMBUS_ENABLE(hsmbus);
bogdanm 0:9b334a45a8ff 1389
bogdanm 0:9b334a45a8ff 1390 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1391 }
bogdanm 0:9b334a45a8ff 1392 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1393 {
bogdanm 0:9b334a45a8ff 1394 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1395 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1396
bogdanm 0:9b334a45a8ff 1397 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1398 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1399
bogdanm 0:9b334a45a8ff 1400 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1401 __HAL_SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1402
bogdanm 0:9b334a45a8ff 1403 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1404 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1405
bogdanm 0:9b334a45a8ff 1406 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1407 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1408
bogdanm 0:9b334a45a8ff 1409 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1410 }
bogdanm 0:9b334a45a8ff 1411 }
bogdanm 0:9b334a45a8ff 1412 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
bogdanm 0:9b334a45a8ff 1413 {
bogdanm 0:9b334a45a8ff 1414 /* Read data from RXDR */
bogdanm 0:9b334a45a8ff 1415 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm 0:9b334a45a8ff 1416 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1417 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1418 }
bogdanm 0:9b334a45a8ff 1419 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm 0:9b334a45a8ff 1420 {
bogdanm 0:9b334a45a8ff 1421 /* Write data to TXDR */
bogdanm 0:9b334a45a8ff 1422 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm 0:9b334a45a8ff 1423 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1424 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1425 }
bogdanm 0:9b334a45a8ff 1426 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
bogdanm 0:9b334a45a8ff 1427 {
bogdanm 0:9b334a45a8ff 1428 if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
bogdanm 0:9b334a45a8ff 1429 {
bogdanm 0:9b334a45a8ff 1430 DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
bogdanm 0:9b334a45a8ff 1431
bogdanm 0:9b334a45a8ff 1432 if(hsmbus->XferCount > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 1433 {
bogdanm 0:9b334a45a8ff 1434 SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1435 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 1436 }
bogdanm 0:9b334a45a8ff 1437 else
bogdanm 0:9b334a45a8ff 1438 {
bogdanm 0:9b334a45a8ff 1439 hsmbus->XferSize = hsmbus->XferCount;
bogdanm 0:9b334a45a8ff 1440 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1441 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 1442 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 1443 if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 1444 {
bogdanm 0:9b334a45a8ff 1445 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1446 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1447 }
bogdanm 0:9b334a45a8ff 1448 }
bogdanm 0:9b334a45a8ff 1449 }
bogdanm 0:9b334a45a8ff 1450 else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
bogdanm 0:9b334a45a8ff 1451 {
bogdanm 0:9b334a45a8ff 1452 /* Call TxCpltCallback if no stop mode is set */
bogdanm 0:9b334a45a8ff 1453 if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm 0:9b334a45a8ff 1454 {
bogdanm 0:9b334a45a8ff 1455 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1456 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1457 {
bogdanm 0:9b334a45a8ff 1458 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1459 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1460 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1461 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1462
bogdanm 0:9b334a45a8ff 1463 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1464 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1465
bogdanm 0:9b334a45a8ff 1466 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1467 }
bogdanm 0:9b334a45a8ff 1468 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1469 {
bogdanm 0:9b334a45a8ff 1470 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1471 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1472 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1473
bogdanm 0:9b334a45a8ff 1474 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1475 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1476
bogdanm 0:9b334a45a8ff 1477 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1478 }
bogdanm 0:9b334a45a8ff 1479 }
bogdanm 0:9b334a45a8ff 1480 }
bogdanm 0:9b334a45a8ff 1481 }
bogdanm 0:9b334a45a8ff 1482 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
bogdanm 0:9b334a45a8ff 1483 {
bogdanm 0:9b334a45a8ff 1484 if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1485 {
bogdanm 0:9b334a45a8ff 1486 /* Specific use case for Quick command */
bogdanm 0:9b334a45a8ff 1487 if(hsmbus->pBuffPtr == HAL_NULL)
bogdanm 0:9b334a45a8ff 1488 {
bogdanm 0:9b334a45a8ff 1489 /* Generate a Stop command */
bogdanm 0:9b334a45a8ff 1490 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
bogdanm 0:9b334a45a8ff 1491 }
bogdanm 0:9b334a45a8ff 1492 /* Call TxCpltCallback if no stop mode is set */
bogdanm 0:9b334a45a8ff 1493 else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm 0:9b334a45a8ff 1494 {
bogdanm 0:9b334a45a8ff 1495 /* No Generate Stop, to permit restart mode */
bogdanm 0:9b334a45a8ff 1496 /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
bogdanm 0:9b334a45a8ff 1497
bogdanm 0:9b334a45a8ff 1498 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1499 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1500 {
bogdanm 0:9b334a45a8ff 1501 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1502 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1503 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1504 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1507 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1508
bogdanm 0:9b334a45a8ff 1509 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1510 }
bogdanm 0:9b334a45a8ff 1511 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1512 {
bogdanm 0:9b334a45a8ff 1513 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1514 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1515 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1516
bogdanm 0:9b334a45a8ff 1517 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1518 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1519
bogdanm 0:9b334a45a8ff 1520 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1521 }
bogdanm 0:9b334a45a8ff 1522 }
bogdanm 0:9b334a45a8ff 1523 }
bogdanm 0:9b334a45a8ff 1524 }
bogdanm 0:9b334a45a8ff 1525
bogdanm 0:9b334a45a8ff 1526 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1527 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1528
bogdanm 0:9b334a45a8ff 1529 return HAL_OK;
bogdanm 0:9b334a45a8ff 1530 }
bogdanm 0:9b334a45a8ff 1531 /**
bogdanm 0:9b334a45a8ff 1532 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode
bogdanm 0:9b334a45a8ff 1533 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1534 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1535 * @retval HAL status
bogdanm 0:9b334a45a8ff 1536 */
bogdanm 0:9b334a45a8ff 1537 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1538 {
bogdanm 0:9b334a45a8ff 1539 uint8_t TransferDirection = 0;
bogdanm 0:9b334a45a8ff 1540 uint16_t SlaveAddrCode = 0;
bogdanm 0:9b334a45a8ff 1541
bogdanm 0:9b334a45a8ff 1542 /* Process Locked */
bogdanm 0:9b334a45a8ff 1543 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1544
bogdanm 0:9b334a45a8ff 1545 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm 0:9b334a45a8ff 1546 {
bogdanm 0:9b334a45a8ff 1547 /* Check that SMBUS transfer finished */
bogdanm 0:9b334a45a8ff 1548 /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
bogdanm 0:9b334a45a8ff 1549 /* Mean XferCount == 0*/
bogdanm 0:9b334a45a8ff 1550 /* So clear Flag NACKF only */
bogdanm 0:9b334a45a8ff 1551 if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1552 {
bogdanm 0:9b334a45a8ff 1553 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1554 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1555
bogdanm 0:9b334a45a8ff 1556 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1557 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1558 }
bogdanm 0:9b334a45a8ff 1559 else
bogdanm 0:9b334a45a8ff 1560 {
bogdanm 0:9b334a45a8ff 1561 /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
bogdanm 0:9b334a45a8ff 1562 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1563 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1564
bogdanm 0:9b334a45a8ff 1565 /* Set HAL State to "Idle" State, mean to LISTEN state */
bogdanm 0:9b334a45a8ff 1566 /* So reset Slave Busy state */
bogdanm 0:9b334a45a8ff 1567 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1568 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm 0:9b334a45a8ff 1569 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm 0:9b334a45a8ff 1570
bogdanm 0:9b334a45a8ff 1571 /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
bogdanm 0:9b334a45a8ff 1572 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1573
bogdanm 0:9b334a45a8ff 1574 /* Set ErrorCode corresponding to a Non-Acknowledge */
bogdanm 0:9b334a45a8ff 1575 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
bogdanm 0:9b334a45a8ff 1576
bogdanm 0:9b334a45a8ff 1577 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1578 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1579
bogdanm 0:9b334a45a8ff 1580 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1581 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1582 }
bogdanm 0:9b334a45a8ff 1583 }
bogdanm 0:9b334a45a8ff 1584 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
bogdanm 0:9b334a45a8ff 1585 {
bogdanm 0:9b334a45a8ff 1586 TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus);
bogdanm 0:9b334a45a8ff 1587 SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus);
bogdanm 0:9b334a45a8ff 1588
bogdanm 0:9b334a45a8ff 1589 /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
bogdanm 0:9b334a45a8ff 1590 /* Other ADDRInterrupt will be treat in next Listen usecase */
bogdanm 0:9b334a45a8ff 1591 __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
bogdanm 0:9b334a45a8ff 1592
bogdanm 0:9b334a45a8ff 1593 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1594 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1595
bogdanm 0:9b334a45a8ff 1596 /* Call Slave Addr callback */
bogdanm 0:9b334a45a8ff 1597 HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
bogdanm 0:9b334a45a8ff 1598 }
bogdanm 0:9b334a45a8ff 1599 else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
bogdanm 0:9b334a45a8ff 1600 {
bogdanm 0:9b334a45a8ff 1601 if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
bogdanm 0:9b334a45a8ff 1602 {
bogdanm 0:9b334a45a8ff 1603 /* Read data from RXDR */
bogdanm 0:9b334a45a8ff 1604 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm 0:9b334a45a8ff 1605 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1606 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1607
bogdanm 0:9b334a45a8ff 1608 if(hsmbus->XferCount == 1)
bogdanm 0:9b334a45a8ff 1609 {
bogdanm 0:9b334a45a8ff 1610 /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
bogdanm 0:9b334a45a8ff 1611 /* or only the last Byte of Transfer */
bogdanm 0:9b334a45a8ff 1612 /* So reset the RELOAD bit mode */
bogdanm 0:9b334a45a8ff 1613 hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
bogdanm 0:9b334a45a8ff 1614 SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1615 }
bogdanm 0:9b334a45a8ff 1616 else if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1617 {
bogdanm 0:9b334a45a8ff 1618 /* Last Byte is received, disable Interrupt */
bogdanm 0:9b334a45a8ff 1619 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1620
bogdanm 0:9b334a45a8ff 1621 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm 0:9b334a45a8ff 1622 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1623 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm 0:9b334a45a8ff 1624
bogdanm 0:9b334a45a8ff 1625 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1626 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1627
bogdanm 0:9b334a45a8ff 1628 /* Call the Rx complete callback to inform upper layer of the end of receive process */
bogdanm 0:9b334a45a8ff 1629 HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1630 }
bogdanm 0:9b334a45a8ff 1631 else
bogdanm 0:9b334a45a8ff 1632 {
bogdanm 0:9b334a45a8ff 1633 /* Set Reload for next Bytes */
bogdanm 0:9b334a45a8ff 1634 SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1635
bogdanm 0:9b334a45a8ff 1636 /* Ack last Byte Read */
bogdanm 0:9b334a45a8ff 1637 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 1638 }
bogdanm 0:9b334a45a8ff 1639 }
bogdanm 0:9b334a45a8ff 1640 else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
bogdanm 0:9b334a45a8ff 1641 {
bogdanm 0:9b334a45a8ff 1642 if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
bogdanm 0:9b334a45a8ff 1643 {
bogdanm 0:9b334a45a8ff 1644 if(hsmbus->XferCount > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 1645 {
bogdanm 0:9b334a45a8ff 1646 SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1647 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 1648 }
bogdanm 0:9b334a45a8ff 1649 else
bogdanm 0:9b334a45a8ff 1650 {
bogdanm 0:9b334a45a8ff 1651 hsmbus->XferSize = hsmbus->XferCount;
bogdanm 0:9b334a45a8ff 1652 SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1653 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 1654 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 1655 if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 1656 {
bogdanm 0:9b334a45a8ff 1657 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1658 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1659 }
bogdanm 0:9b334a45a8ff 1660 }
bogdanm 0:9b334a45a8ff 1661 }
bogdanm 0:9b334a45a8ff 1662 }
bogdanm 0:9b334a45a8ff 1663 }
bogdanm 0:9b334a45a8ff 1664 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm 0:9b334a45a8ff 1665 {
bogdanm 0:9b334a45a8ff 1666 /* Write data to TXDR only if XferCount not reach "0" */
bogdanm 0:9b334a45a8ff 1667 /* A TXIS flag can be set, during STOP treatment */
bogdanm 0:9b334a45a8ff 1668 /* Check if all Datas have already been sent */
bogdanm 0:9b334a45a8ff 1669 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
bogdanm 0:9b334a45a8ff 1670 if(hsmbus->XferCount > 0)
bogdanm 0:9b334a45a8ff 1671 {
bogdanm 0:9b334a45a8ff 1672 /* Write data to TXDR */
bogdanm 0:9b334a45a8ff 1673 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm 0:9b334a45a8ff 1674 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1675 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1676 }
bogdanm 0:9b334a45a8ff 1677
bogdanm 0:9b334a45a8ff 1678 if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1679 {
bogdanm 0:9b334a45a8ff 1680 /* Last Byte is Transmitted */
bogdanm 0:9b334a45a8ff 1681 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm 0:9b334a45a8ff 1682 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1683 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1684 hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm 0:9b334a45a8ff 1685
bogdanm 0:9b334a45a8ff 1686 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1687 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1688
bogdanm 0:9b334a45a8ff 1689 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
bogdanm 0:9b334a45a8ff 1690 HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1691 }
bogdanm 0:9b334a45a8ff 1692 }
bogdanm 0:9b334a45a8ff 1693
bogdanm 0:9b334a45a8ff 1694 /* Check if STOPF is set */
bogdanm 0:9b334a45a8ff 1695 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm 0:9b334a45a8ff 1696 {
bogdanm 0:9b334a45a8ff 1697 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1698 {
bogdanm 0:9b334a45a8ff 1699 /* Disable RX and TX Interrupts */
bogdanm 0:9b334a45a8ff 1700 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1701
bogdanm 0:9b334a45a8ff 1702 /* Disable ADDR Interrupt */
bogdanm 0:9b334a45a8ff 1703 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 1704
bogdanm 0:9b334a45a8ff 1705 /* Disable Address Acknowledge */
bogdanm 0:9b334a45a8ff 1706 hsmbus->Instance->CR2 |= I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 1707
bogdanm 0:9b334a45a8ff 1708 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1709 __HAL_SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1710
bogdanm 0:9b334a45a8ff 1711 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1712 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1713
bogdanm 0:9b334a45a8ff 1714 /* Clear ADDR flag */
bogdanm 0:9b334a45a8ff 1715 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 1716
bogdanm 0:9b334a45a8ff 1717 hsmbus->XferOptions = 0;
bogdanm 0:9b334a45a8ff 1718 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1719 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1720
bogdanm 0:9b334a45a8ff 1721 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1722 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1723
bogdanm 0:9b334a45a8ff 1724 /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
bogdanm 0:9b334a45a8ff 1725 HAL_SMBUS_SlaveListenCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1726 }
bogdanm 0:9b334a45a8ff 1727 }
bogdanm 0:9b334a45a8ff 1728
bogdanm 0:9b334a45a8ff 1729 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1730 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1731
bogdanm 0:9b334a45a8ff 1732 return HAL_OK;
bogdanm 0:9b334a45a8ff 1733 }
bogdanm 0:9b334a45a8ff 1734 /**
bogdanm 0:9b334a45a8ff 1735 * @brief Manage the enabling of Interrupts
bogdanm 0:9b334a45a8ff 1736 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1737 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1738 * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm 0:9b334a45a8ff 1739 * @retval HAL status
bogdanm 0:9b334a45a8ff 1740 */
bogdanm 0:9b334a45a8ff 1741 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm 0:9b334a45a8ff 1742 {
bogdanm 0:9b334a45a8ff 1743 uint32_t tmpisr = 0;
bogdanm 0:9b334a45a8ff 1744
bogdanm 0:9b334a45a8ff 1745 if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
bogdanm 0:9b334a45a8ff 1746 {
bogdanm 0:9b334a45a8ff 1747 /* Enable ERR interrupt */
bogdanm 0:9b334a45a8ff 1748 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1749 }
bogdanm 0:9b334a45a8ff 1750
bogdanm 0:9b334a45a8ff 1751 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm 0:9b334a45a8ff 1752 {
bogdanm 0:9b334a45a8ff 1753 /* Enable ADDR, STOP interrupt */
bogdanm 0:9b334a45a8ff 1754 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1755 }
bogdanm 0:9b334a45a8ff 1756
bogdanm 0:9b334a45a8ff 1757 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm 0:9b334a45a8ff 1758 {
bogdanm 0:9b334a45a8ff 1759 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm 0:9b334a45a8ff 1760 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
bogdanm 0:9b334a45a8ff 1761 }
bogdanm 0:9b334a45a8ff 1762
bogdanm 0:9b334a45a8ff 1763 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm 0:9b334a45a8ff 1764 {
bogdanm 0:9b334a45a8ff 1765 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm 0:9b334a45a8ff 1766 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
bogdanm 0:9b334a45a8ff 1767 }
bogdanm 0:9b334a45a8ff 1768
bogdanm 0:9b334a45a8ff 1769 /* Enable interrupts only at the end */
bogdanm 0:9b334a45a8ff 1770 /* to avoid the risk of SMBUS interrupt handle execution before */
bogdanm 0:9b334a45a8ff 1771 /* all interrupts requested done */
bogdanm 0:9b334a45a8ff 1772 __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
bogdanm 0:9b334a45a8ff 1773
bogdanm 0:9b334a45a8ff 1774 return HAL_OK;
bogdanm 0:9b334a45a8ff 1775 }
bogdanm 0:9b334a45a8ff 1776 /**
bogdanm 0:9b334a45a8ff 1777 * @brief Manage the disabling of Interrupts
bogdanm 0:9b334a45a8ff 1778 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1779 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1780 * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm 0:9b334a45a8ff 1781 * @retval HAL status
bogdanm 0:9b334a45a8ff 1782 */
bogdanm 0:9b334a45a8ff 1783 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm 0:9b334a45a8ff 1784 {
bogdanm 0:9b334a45a8ff 1785 uint32_t tmpisr = 0;
bogdanm 0:9b334a45a8ff 1786
bogdanm 0:9b334a45a8ff 1787 if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
bogdanm 0:9b334a45a8ff 1788 {
bogdanm 0:9b334a45a8ff 1789 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1790 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1791 }
bogdanm 0:9b334a45a8ff 1792
bogdanm 0:9b334a45a8ff 1793 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm 0:9b334a45a8ff 1794 {
bogdanm 0:9b334a45a8ff 1795 /* Disable TC, STOP, NACK, TXI interrupt */
bogdanm 0:9b334a45a8ff 1796 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1799 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm 0:9b334a45a8ff 1800 {
bogdanm 0:9b334a45a8ff 1801 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1802 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1803 }
bogdanm 0:9b334a45a8ff 1804
bogdanm 0:9b334a45a8ff 1805 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1806 {
bogdanm 0:9b334a45a8ff 1807 /* Disable STOPI, NACKI */
bogdanm 0:9b334a45a8ff 1808 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1809 }
bogdanm 0:9b334a45a8ff 1810 }
bogdanm 0:9b334a45a8ff 1811
bogdanm 0:9b334a45a8ff 1812 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm 0:9b334a45a8ff 1813 {
bogdanm 0:9b334a45a8ff 1814 /* Disable TC, STOP, NACK, RXI interrupt */
bogdanm 0:9b334a45a8ff 1815 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
bogdanm 0:9b334a45a8ff 1816
bogdanm 0:9b334a45a8ff 1817 if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1818 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm 0:9b334a45a8ff 1819 {
bogdanm 0:9b334a45a8ff 1820 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1821 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1822 }
bogdanm 0:9b334a45a8ff 1823
bogdanm 0:9b334a45a8ff 1824 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1825 {
bogdanm 0:9b334a45a8ff 1826 /* Disable STOPI, NACKI */
bogdanm 0:9b334a45a8ff 1827 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1828 }
bogdanm 0:9b334a45a8ff 1829 }
bogdanm 0:9b334a45a8ff 1830
bogdanm 0:9b334a45a8ff 1831 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm 0:9b334a45a8ff 1832 {
bogdanm 0:9b334a45a8ff 1833 /* Enable ADDR, STOP interrupt */
bogdanm 0:9b334a45a8ff 1834 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1835
bogdanm 0:9b334a45a8ff 1836 if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1837 {
bogdanm 0:9b334a45a8ff 1838 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1839 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1840 }
bogdanm 0:9b334a45a8ff 1841 }
bogdanm 0:9b334a45a8ff 1842
bogdanm 0:9b334a45a8ff 1843 /* Disable interrupts only at the end */
bogdanm 0:9b334a45a8ff 1844 /* to avoid a breaking situation like at "t" time */
bogdanm 0:9b334a45a8ff 1845 /* all disable interrupts request are not done */
bogdanm 0:9b334a45a8ff 1846 __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
bogdanm 0:9b334a45a8ff 1847
bogdanm 0:9b334a45a8ff 1848 return HAL_OK;
bogdanm 0:9b334a45a8ff 1849 }
bogdanm 0:9b334a45a8ff 1850 /**
bogdanm 0:9b334a45a8ff 1851 * @brief This function handles SMBUS Communication Timeout.
bogdanm 0:9b334a45a8ff 1852 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1853 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1854 * @param Flag: specifies the SMBUS flag to check.
bogdanm 0:9b334a45a8ff 1855 * @param Status: The new Flag status (SET or RESET).
bogdanm 0:9b334a45a8ff 1856 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 1857 * @retval HAL status
bogdanm 0:9b334a45a8ff 1858 */
bogdanm 0:9b334a45a8ff 1859 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1860 {
bogdanm 0:9b334a45a8ff 1861 uint32_t tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1862
bogdanm 0:9b334a45a8ff 1863 /* Wait until flag is set */
bogdanm 0:9b334a45a8ff 1864 if(Status == RESET)
bogdanm 0:9b334a45a8ff 1865 {
bogdanm 0:9b334a45a8ff 1866 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
bogdanm 0:9b334a45a8ff 1867 {
bogdanm 0:9b334a45a8ff 1868 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1869 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1870 {
bogdanm 0:9b334a45a8ff 1871 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 1872 {
bogdanm 0:9b334a45a8ff 1873 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1874 hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1875
bogdanm 0:9b334a45a8ff 1876 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1877 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1878
bogdanm 0:9b334a45a8ff 1879 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1880 }
bogdanm 0:9b334a45a8ff 1881 }
bogdanm 0:9b334a45a8ff 1882 }
bogdanm 0:9b334a45a8ff 1883 }
bogdanm 0:9b334a45a8ff 1884 else
bogdanm 0:9b334a45a8ff 1885 {
bogdanm 0:9b334a45a8ff 1886 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
bogdanm 0:9b334a45a8ff 1887 {
bogdanm 0:9b334a45a8ff 1888 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1889 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1890 {
bogdanm 0:9b334a45a8ff 1891 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 1892 {
bogdanm 0:9b334a45a8ff 1893 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1894 hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1895
bogdanm 0:9b334a45a8ff 1896 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1897 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1898
bogdanm 0:9b334a45a8ff 1899 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1900 }
bogdanm 0:9b334a45a8ff 1901 }
bogdanm 0:9b334a45a8ff 1902 }
bogdanm 0:9b334a45a8ff 1903 }
bogdanm 0:9b334a45a8ff 1904 return HAL_OK;
bogdanm 0:9b334a45a8ff 1905 }
bogdanm 0:9b334a45a8ff 1906
bogdanm 0:9b334a45a8ff 1907 /**
bogdanm 0:9b334a45a8ff 1908 * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
bogdanm 0:9b334a45a8ff 1909 * @param hsmbus: SMBUS handle.
bogdanm 0:9b334a45a8ff 1910 * @param DevAddress: specifies the slave address to be programmed.
bogdanm 0:9b334a45a8ff 1911 * @param Size: specifies the number of bytes to be programmed.
bogdanm 0:9b334a45a8ff 1912 * This parameter must be a value between 0 and 255.
bogdanm 0:9b334a45a8ff 1913 * @param Mode: new state of the SMBUS START condition generation.
bogdanm 0:9b334a45a8ff 1914 * This parameter can be one or a combination of the following values:
bogdanm 0:9b334a45a8ff 1915 * @arg SMBUS_NO_MODE: No specific mode enabled.
bogdanm 0:9b334a45a8ff 1916 * @arg SMBUS_RELOAD_MODE: Enable Reload mode.
bogdanm 0:9b334a45a8ff 1917 * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
bogdanm 0:9b334a45a8ff 1918 * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
bogdanm 0:9b334a45a8ff 1919 * @param Request: new state of the SMBUS START condition generation.
bogdanm 0:9b334a45a8ff 1920 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1921 * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
bogdanm 0:9b334a45a8ff 1922 * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
bogdanm 0:9b334a45a8ff 1923 * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
bogdanm 0:9b334a45a8ff 1924 * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
bogdanm 0:9b334a45a8ff 1925 * @retval None
bogdanm 0:9b334a45a8ff 1926 */
bogdanm 0:9b334a45a8ff 1927 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
bogdanm 0:9b334a45a8ff 1928 {
bogdanm 0:9b334a45a8ff 1929 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 1930
bogdanm 0:9b334a45a8ff 1931 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1932 assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 1933 assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
bogdanm 0:9b334a45a8ff 1934 assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
bogdanm 0:9b334a45a8ff 1935
bogdanm 0:9b334a45a8ff 1936 /* Get the CR2 register value */
bogdanm 0:9b334a45a8ff 1937 tmpreg = hsmbus->Instance->CR2;
bogdanm 0:9b334a45a8ff 1938
bogdanm 0:9b334a45a8ff 1939 /* clear tmpreg specific bits */
bogdanm 0:9b334a45a8ff 1940 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
bogdanm 0:9b334a45a8ff 1941
bogdanm 0:9b334a45a8ff 1942 /* update tmpreg */
bogdanm 0:9b334a45a8ff 1943 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
bogdanm 0:9b334a45a8ff 1944 (uint32_t)Mode | (uint32_t)Request);
bogdanm 0:9b334a45a8ff 1945
bogdanm 0:9b334a45a8ff 1946 /* update CR2 register */
bogdanm 0:9b334a45a8ff 1947 hsmbus->Instance->CR2 = tmpreg;
bogdanm 0:9b334a45a8ff 1948 }
bogdanm 0:9b334a45a8ff 1949 /**
bogdanm 0:9b334a45a8ff 1950 * @}
bogdanm 0:9b334a45a8ff 1951 */
bogdanm 0:9b334a45a8ff 1952
bogdanm 0:9b334a45a8ff 1953 #endif /* HAL_SMBUS_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1954 /**
bogdanm 0:9b334a45a8ff 1955 * @}
bogdanm 0:9b334a45a8ff 1956 */
bogdanm 0:9b334a45a8ff 1957
bogdanm 0:9b334a45a8ff 1958 /**
bogdanm 0:9b334a45a8ff 1959 * @}
bogdanm 0:9b334a45a8ff 1960 */
bogdanm 0:9b334a45a8ff 1961
bogdanm 0:9b334a45a8ff 1962 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/