en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_hal_gpio.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief GPIO HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + IO operation functions
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 @verbatim
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 ##### GPIO specific features #####
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 Each port bit of the general-purpose I/O (GPIO) ports can be individually
bogdanm 0:9b334a45a8ff 20 configured by software in several modes:
bogdanm 0:9b334a45a8ff 21 (+) Input mode
bogdanm 0:9b334a45a8ff 22 (+) Analog mode
bogdanm 0:9b334a45a8ff 23 (+) Output mode
bogdanm 0:9b334a45a8ff 24 (+) Alternate function mode
bogdanm 0:9b334a45a8ff 25 (+) External interrupt/event lines
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 [..]
bogdanm 0:9b334a45a8ff 28 During and just after reset, the alternate functions and external interrupt
bogdanm 0:9b334a45a8ff 29 lines are not active and the I/O ports are configured in input floating mode.
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 [..]
bogdanm 0:9b334a45a8ff 32 All GPIO pins have weak internal pull-up and pull-down resistors, which can be
bogdanm 0:9b334a45a8ff 33 activated or not.
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 [..]
bogdanm 0:9b334a45a8ff 36 In Output or Alternate mode, each IO can be configured on open-drain or push-pull
bogdanm 0:9b334a45a8ff 37 type and the IO speed can be selected depending on the VDD value.
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 [..]
bogdanm 0:9b334a45a8ff 40 The microcontroller IO pins are connected to onboard peripherals/modules through a
bogdanm 0:9b334a45a8ff 41 multiplexer that allows only one peripheral’s alternate function (AF) connected
bogdanm 0:9b334a45a8ff 42 to an IO pin at a time. In this way, there can be no conflict between peripherals
bogdanm 0:9b334a45a8ff 43 sharing the same IO pin.
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 [..]
bogdanm 0:9b334a45a8ff 46 All ports have external interrupt/event capability. To use external interrupt
bogdanm 0:9b334a45a8ff 47 lines, the port must be configured in input mode. All available GPIO pins are
bogdanm 0:9b334a45a8ff 48 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 The external interrupt/event controller consists of up to 23 edge detectors
bogdanm 0:9b334a45a8ff 52 (16 lines are connected to GPIO) for generating event/interrupt requests (each
bogdanm 0:9b334a45a8ff 53 input line can be independently configured to select the type (interrupt or event)
bogdanm 0:9b334a45a8ff 54 and the corresponding trigger event (rising or falling or both). Each line can
bogdanm 0:9b334a45a8ff 55 also be masked independently.
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 58 ==============================================================================
bogdanm 0:9b334a45a8ff 59 [..]
bogdanm 0:9b334a45a8ff 60 (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
bogdanm 0:9b334a45a8ff 63 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
bogdanm 0:9b334a45a8ff 64 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
bogdanm 0:9b334a45a8ff 65 structure.
bogdanm 0:9b334a45a8ff 66 (++) In case of Output or alternate function mode selection: the speed is
bogdanm 0:9b334a45a8ff 67 configured through "Speed" member from GPIO_InitTypeDef structure,
bogdanm 0:9b334a45a8ff 68 the speed is configurable: 2 MHz, 10 MHz and 50 MHz.
bogdanm 0:9b334a45a8ff 69 (++) If alternate mode is selected, the alternate function connected to the IO
bogdanm 0:9b334a45a8ff 70 is configured through "Alternate" member from GPIO_InitTypeDef structure
bogdanm 0:9b334a45a8ff 71 (++) Analog mode is required when a pin is to be used as ADC channel
bogdanm 0:9b334a45a8ff 72 or DAC output.
bogdanm 0:9b334a45a8ff 73 (++) In case of external interrupt/event selection the "Mode" member from
bogdanm 0:9b334a45a8ff 74 GPIO_InitTypeDef structure select the type (interrupt or event) and
bogdanm 0:9b334a45a8ff 75 the corresponding trigger event (rising or falling or both).
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
bogdanm 0:9b334a45a8ff 78 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
bogdanm 0:9b334a45a8ff 79 HAL_NVIC_EnableIRQ().
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 (#) To set/reset the level of a pin configured in output mode use
bogdanm 0:9b334a45a8ff 84 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 (#) During and just after reset, the alternate functions are not
bogdanm 0:9b334a45a8ff 89 active and the GPIO pins are configured in input floating mode (except JTAG
bogdanm 0:9b334a45a8ff 90 pins).
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
bogdanm 0:9b334a45a8ff 93 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
bogdanm 0:9b334a45a8ff 94 priority over the GPIO function.
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
bogdanm 0:9b334a45a8ff 97 general purpose Px0 and Px1, respectively, when the HSE oscillator is off.
bogdanm 0:9b334a45a8ff 98 The HSE has priority over the GPIO function.
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 @endverbatim
bogdanm 0:9b334a45a8ff 101 ******************************************************************************
bogdanm 0:9b334a45a8ff 102 * @attention
bogdanm 0:9b334a45a8ff 103 *
bogdanm 0:9b334a45a8ff 104 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 105 *
bogdanm 0:9b334a45a8ff 106 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 107 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 108 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 109 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 110 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 111 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 112 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 114 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 115 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 116 *
bogdanm 0:9b334a45a8ff 117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 127 *
bogdanm 0:9b334a45a8ff 128 ******************************************************************************
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 132 #include "stm32f3xx_hal.h"
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 135 * @{
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /** @defgroup GPIO GPIO HAL module driver
bogdanm 0:9b334a45a8ff 139 * @brief GPIO HAL module driver
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 #ifdef HAL_GPIO_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 146 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 148 /** @defgroup GPIO_Private_Macros GPIO Private Macros
bogdanm 0:9b334a45a8ff 149 * @{
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151 #define GET_GPIO_SOURCE(__GPIOx__) \
bogdanm 0:9b334a45a8ff 152 (((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? 0U :\
bogdanm 0:9b334a45a8ff 153 ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? 1U :\
bogdanm 0:9b334a45a8ff 154 ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? 2U :\
bogdanm 0:9b334a45a8ff 155 ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? 3U :\
bogdanm 0:9b334a45a8ff 156 ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? 4U :\
bogdanm 0:9b334a45a8ff 157 ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? 5U : 6U)
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 #define GPIO_MODE ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 160 #define EXTI_MODE ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 161 #define GPIO_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 162 #define GPIO_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 163 #define RISING_EDGE ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 164 #define FALLING_EDGE ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 165 #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 #define GPIO_NUMBER ((uint32_t)16)
bogdanm 0:9b334a45a8ff 168 /**
bogdanm 0:9b334a45a8ff 169 * @}
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 173 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 174 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 175 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
bogdanm 0:9b334a45a8ff 176 * @{
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 180 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 181 *
bogdanm 0:9b334a45a8ff 182 @verbatim
bogdanm 0:9b334a45a8ff 183 ===============================================================================
bogdanm 0:9b334a45a8ff 184 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 185 ===============================================================================
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 @endverbatim
bogdanm 0:9b334a45a8ff 188 * @{
bogdanm 0:9b334a45a8ff 189 */
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /**
bogdanm 0:9b334a45a8ff 192 * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
bogdanm 0:9b334a45a8ff 193 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
bogdanm 0:9b334a45a8ff 194 * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
bogdanm 0:9b334a45a8ff 195 * the configuration information for the specified GPIO peripheral.
bogdanm 0:9b334a45a8ff 196 * @retval None
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 uint32_t position;
bogdanm 0:9b334a45a8ff 201 uint32_t ioposition = 0x00;
bogdanm 0:9b334a45a8ff 202 uint32_t iocurrent = 0x00;
bogdanm 0:9b334a45a8ff 203 uint32_t temp = 0x00;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Check the parameters */
bogdanm 0:9b334a45a8ff 206 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
bogdanm 0:9b334a45a8ff 207 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
bogdanm 0:9b334a45a8ff 208 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Configure the port pins */
bogdanm 0:9b334a45a8ff 211 for (position = 0; position < GPIO_NUMBER; position++)
bogdanm 0:9b334a45a8ff 212 {
bogdanm 0:9b334a45a8ff 213 /* Get the IO position */
bogdanm 0:9b334a45a8ff 214 ioposition = ((uint32_t)0x01) << position;
bogdanm 0:9b334a45a8ff 215 /* Get the current IO position */
bogdanm 0:9b334a45a8ff 216 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 if (iocurrent == ioposition)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 /*--------------------- GPIO Mode Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 221 /* In case of Alternate function mode selection */
bogdanm 0:9b334a45a8ff 222 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
bogdanm 0:9b334a45a8ff 223 {
bogdanm 0:9b334a45a8ff 224 /* Check the Alternate function parameter */
bogdanm 0:9b334a45a8ff 225 assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
bogdanm 0:9b334a45a8ff 226 /* Configure Alternate function mapped with the current IO */
bogdanm 0:9b334a45a8ff 227 temp = GPIOx->AFR[position >> 3];
bogdanm 0:9b334a45a8ff 228 temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
bogdanm 0:9b334a45a8ff 229 temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
bogdanm 0:9b334a45a8ff 230 GPIOx->AFR[position >> 3] = temp;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
bogdanm 0:9b334a45a8ff 234 temp = GPIOx->MODER;
bogdanm 0:9b334a45a8ff 235 temp &= ~(GPIO_MODER_MODER0 << (position * 2));
bogdanm 0:9b334a45a8ff 236 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
bogdanm 0:9b334a45a8ff 237 GPIOx->MODER = temp;
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* In case of Output or Alternate function mode selection */
bogdanm 0:9b334a45a8ff 240 if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
bogdanm 0:9b334a45a8ff 241 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 /* Check the Speed parameter */
bogdanm 0:9b334a45a8ff 244 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
bogdanm 0:9b334a45a8ff 245 /* Configure the IO Speed */
bogdanm 0:9b334a45a8ff 246 temp = GPIOx->OSPEEDR;
bogdanm 0:9b334a45a8ff 247 temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
bogdanm 0:9b334a45a8ff 248 temp |= (GPIO_Init->Speed << (position * 2));
bogdanm 0:9b334a45a8ff 249 GPIOx->OSPEEDR = temp;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Configure the IO Output Type */
bogdanm 0:9b334a45a8ff 252 temp = GPIOx->OTYPER;
bogdanm 0:9b334a45a8ff 253 temp &= ~(GPIO_OTYPER_OT_0 << position) ;
bogdanm 0:9b334a45a8ff 254 temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
bogdanm 0:9b334a45a8ff 255 GPIOx->OTYPER = temp;
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* Activate the Pull-up or Pull down resistor for the current IO */
bogdanm 0:9b334a45a8ff 259 temp = GPIOx->PUPDR;
bogdanm 0:9b334a45a8ff 260 temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
bogdanm 0:9b334a45a8ff 261 temp |= ((GPIO_Init->Pull) << (position * 2));
bogdanm 0:9b334a45a8ff 262 GPIOx->PUPDR = temp;
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /*--------------------- EXTI Mode Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 265 /* Configure the External Interrupt or event for the current IO */
bogdanm 0:9b334a45a8ff 266 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 /* Enable SYSCFG Clock */
bogdanm 0:9b334a45a8ff 269 __SYSCFG_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 temp = SYSCFG->EXTICR[position >> 2];
bogdanm 0:9b334a45a8ff 272 temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
bogdanm 0:9b334a45a8ff 273 temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
bogdanm 0:9b334a45a8ff 274 SYSCFG->EXTICR[position >> 2] = temp;
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Clear EXTI line configuration */
bogdanm 0:9b334a45a8ff 277 temp = EXTI->IMR;
bogdanm 0:9b334a45a8ff 278 temp &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 279 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
bogdanm 0:9b334a45a8ff 280 {
bogdanm 0:9b334a45a8ff 281 temp |= iocurrent;
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283 EXTI->IMR = temp;
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 temp = EXTI->EMR;
bogdanm 0:9b334a45a8ff 286 temp &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 287 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
bogdanm 0:9b334a45a8ff 288 {
bogdanm 0:9b334a45a8ff 289 temp |= iocurrent;
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291 EXTI->EMR = temp;
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /* Clear Rising Falling edge configuration */
bogdanm 0:9b334a45a8ff 294 temp = EXTI->RTSR;
bogdanm 0:9b334a45a8ff 295 temp &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 296 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
bogdanm 0:9b334a45a8ff 297 {
bogdanm 0:9b334a45a8ff 298 temp |= iocurrent;
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 EXTI->RTSR = temp;
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 temp = EXTI->FTSR;
bogdanm 0:9b334a45a8ff 303 temp &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 304 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
bogdanm 0:9b334a45a8ff 305 {
bogdanm 0:9b334a45a8ff 306 temp |= iocurrent;
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308 EXTI->FTSR = temp;
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310 }
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /**
bogdanm 0:9b334a45a8ff 315 * @brief De-initializes the GPIOx peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 316 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
bogdanm 0:9b334a45a8ff 317 * @param GPIO_Pin: specifies the port bit to be written.
bogdanm 0:9b334a45a8ff 318 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 319 * @retval None
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 uint32_t position;
bogdanm 0:9b334a45a8ff 324 uint32_t ioposition = 0x00;
bogdanm 0:9b334a45a8ff 325 uint32_t iocurrent = 0x00;
bogdanm 0:9b334a45a8ff 326 uint32_t tmp = 0x00;
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 /* Configure the port pins */
bogdanm 0:9b334a45a8ff 329 for (position = 0; position < GPIO_NUMBER; position++)
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 /* Get the IO position */
bogdanm 0:9b334a45a8ff 332 ioposition = ((uint32_t)0x01) << position;
bogdanm 0:9b334a45a8ff 333 /* Get the current IO position */
bogdanm 0:9b334a45a8ff 334 iocurrent = (GPIO_Pin) & ioposition;
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 if (iocurrent == ioposition)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 /*------------------------- GPIO Mode Configuration --------------------*/
bogdanm 0:9b334a45a8ff 339 /* Configure IO Direction in Input Floting Mode */
bogdanm 0:9b334a45a8ff 340 GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Configure the default Alternate Function in current IO */
bogdanm 0:9b334a45a8ff 343 GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /* Configure the default value for IO Speed */
bogdanm 0:9b334a45a8ff 346 GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /* Configure the default value IO Output Type */
bogdanm 0:9b334a45a8ff 349 GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
bogdanm 0:9b334a45a8ff 352 GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /*------------------------- EXTI Mode Configuration --------------------*/
bogdanm 0:9b334a45a8ff 356 /* Configure the External Interrupt or event for the current IO */
bogdanm 0:9b334a45a8ff 357 tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
bogdanm 0:9b334a45a8ff 358 SYSCFG->EXTICR[position >> 2] &= ~tmp;
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /* Clear EXTI line configuration */
bogdanm 0:9b334a45a8ff 361 EXTI->IMR &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 362 EXTI->EMR &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Clear Rising Falling edge configuration */
bogdanm 0:9b334a45a8ff 365 EXTI->RTSR &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 366 EXTI->FTSR &= ~((uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /**
bogdanm 0:9b334a45a8ff 372 * @}
bogdanm 0:9b334a45a8ff 373 */
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 /** @defgroup GPIO_Exported_Functions_Group2 Input and Output operation functions
bogdanm 0:9b334a45a8ff 376 * @brief GPIO Read and Write
bogdanm 0:9b334a45a8ff 377 *
bogdanm 0:9b334a45a8ff 378 @verbatim
bogdanm 0:9b334a45a8ff 379 ===============================================================================
bogdanm 0:9b334a45a8ff 380 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 381 ===============================================================================
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 @endverbatim
bogdanm 0:9b334a45a8ff 384 * @{
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /**
bogdanm 0:9b334a45a8ff 388 * @brief Reads the specified input port pin.
bogdanm 0:9b334a45a8ff 389 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
bogdanm 0:9b334a45a8ff 390 * @param GPIO_Pin: specifies the port bit to read.
bogdanm 0:9b334a45a8ff 391 * This parameter can be GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 392 * @retval The input port pin value.
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 GPIO_PinState bitstatus;
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Check the parameters */
bogdanm 0:9b334a45a8ff 399 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 bitstatus = GPIO_PIN_SET;
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 else
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 bitstatus = GPIO_PIN_RESET;
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409 return bitstatus;
bogdanm 0:9b334a45a8ff 410 }
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 /**
bogdanm 0:9b334a45a8ff 413 * @brief Sets or clears the selected data port bit.
bogdanm 0:9b334a45a8ff 414 *
bogdanm 0:9b334a45a8ff 415 * @note This function uses GPIOx_BSRR register to allow atomic read/modify
bogdanm 0:9b334a45a8ff 416 * accesses. In this way, there is no risk of an IRQ occurring between
bogdanm 0:9b334a45a8ff 417 * the read and the modify access.
bogdanm 0:9b334a45a8ff 418 *
bogdanm 0:9b334a45a8ff 419 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
bogdanm 0:9b334a45a8ff 420 * @param GPIO_Pin: specifies the port bit to be written.
bogdanm 0:9b334a45a8ff 421 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 422 * @param PinState: specifies the value to be written to the selected bit.
bogdanm 0:9b334a45a8ff 423 * This parameter can be one of the GPIO_PinState enum values:
bogdanm 0:9b334a45a8ff 424 * @arg GPIO_PIN_RESET: to clear the port pin
bogdanm 0:9b334a45a8ff 425 * @arg GPIO_PIN_SET: to set the port pin
bogdanm 0:9b334a45a8ff 426 * @retval None
bogdanm 0:9b334a45a8ff 427 */
bogdanm 0:9b334a45a8ff 428 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
bogdanm 0:9b334a45a8ff 429 {
bogdanm 0:9b334a45a8ff 430 /* Check the parameters */
bogdanm 0:9b334a45a8ff 431 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 432 assert_param(IS_GPIO_PIN_ACTION(PinState));
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 if (PinState != GPIO_PIN_RESET)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 GPIOx->BSRRL = GPIO_Pin;
bogdanm 0:9b334a45a8ff 437 }
bogdanm 0:9b334a45a8ff 438 else
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 GPIOx->BSRRH = GPIO_Pin ;
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /**
bogdanm 0:9b334a45a8ff 445 * @brief Toggles the specified GPIO pin
bogdanm 0:9b334a45a8ff 446 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
bogdanm 0:9b334a45a8ff 447 * @param GPIO_Pin: specifies the pins to be toggled.
bogdanm 0:9b334a45a8ff 448 * @retval None
bogdanm 0:9b334a45a8ff 449 */
bogdanm 0:9b334a45a8ff 450 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 /* Check the parameters */
bogdanm 0:9b334a45a8ff 453 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 GPIOx->ODR ^= GPIO_Pin;
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /**
bogdanm 0:9b334a45a8ff 459 * @brief Locks GPIO Pins configuration registers.
bogdanm 0:9b334a45a8ff 460 * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
bogdanm 0:9b334a45a8ff 461 * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
bogdanm 0:9b334a45a8ff 462 * @note The configuration of the locked GPIO pins can no longer be modified
bogdanm 0:9b334a45a8ff 463 * until the next reset.
bogdanm 0:9b334a45a8ff 464 * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
bogdanm 0:9b334a45a8ff 465 * @param GPIO_Pin: specifies the port bit to be locked.
bogdanm 0:9b334a45a8ff 466 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 467 * @retval None
bogdanm 0:9b334a45a8ff 468 */
bogdanm 0:9b334a45a8ff 469 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 __IO uint32_t tmp = GPIO_LCKR_LCKK;
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Check the parameters */
bogdanm 0:9b334a45a8ff 474 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Apply lock key write sequence */
bogdanm 0:9b334a45a8ff 477 tmp |= GPIO_Pin;
bogdanm 0:9b334a45a8ff 478 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 479 GPIOx->LCKR = tmp;
bogdanm 0:9b334a45a8ff 480 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 481 GPIOx->LCKR = GPIO_Pin;
bogdanm 0:9b334a45a8ff 482 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 483 GPIOx->LCKR = tmp;
bogdanm 0:9b334a45a8ff 484 /* Read LCKK bit*/
bogdanm 0:9b334a45a8ff 485 tmp = GPIOx->LCKR;
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 return HAL_OK;
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491 else
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 494 }
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /**
bogdanm 0:9b334a45a8ff 498 * @brief This function handles EXTI interrupt request.
bogdanm 0:9b334a45a8ff 499 * @param GPIO_Pin: Specifies the pins connected EXTI line
bogdanm 0:9b334a45a8ff 500 * @retval None
bogdanm 0:9b334a45a8ff 501 */
bogdanm 0:9b334a45a8ff 502 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 503 {
bogdanm 0:9b334a45a8ff 504 /* EXTI line interrupt detected */
bogdanm 0:9b334a45a8ff 505 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
bogdanm 0:9b334a45a8ff 508 HAL_GPIO_EXTI_Callback(GPIO_Pin);
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /**
bogdanm 0:9b334a45a8ff 513 * @brief EXTI line detection callbacks.
bogdanm 0:9b334a45a8ff 514 * @param GPIO_Pin: Specifies the pins connected EXTI line
bogdanm 0:9b334a45a8ff 515 * @retval None
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 520 the HAL_GPIO_EXTI_Callback could be implemented in the user file
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /**
bogdanm 0:9b334a45a8ff 525 * @}
bogdanm 0:9b334a45a8ff 526 */
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /**
bogdanm 0:9b334a45a8ff 530 * @}
bogdanm 0:9b334a45a8ff 531 */
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 #endif /* HAL_GPIO_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 534 /**
bogdanm 0:9b334a45a8ff 535 * @}
bogdanm 0:9b334a45a8ff 536 */
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /**
bogdanm 0:9b334a45a8ff 539 * @}
bogdanm 0:9b334a45a8ff 540 */
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/