en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_hal_dma.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief Header file of DMA HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F3xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F3xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f3xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup DMA DMA HAL module driver
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /**
bogdanm 0:9b334a45a8ff 63 * @brief DMA Configuration Structure definition
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 typedef struct
bogdanm 0:9b334a45a8ff 66 {
bogdanm 0:9b334a45a8ff 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 0:9b334a45a8ff 68 from memory to memory or from peripheral to memory.
bogdanm 0:9b334a45a8ff 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 0:9b334a45a8ff 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 0:9b334a45a8ff 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 0:9b334a45a8ff 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 0:9b334a45a8ff 81 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 0:9b334a45a8ff 84 This parameter can be a value of @ref DMA_mode
bogdanm 0:9b334a45a8ff 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 0:9b334a45a8ff 86 data transfer is configured on the selected Channel */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 0:9b334a45a8ff 89 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 } DMA_InitTypeDef;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
bogdanm 0:9b334a45a8ff 94 * @brief DMA Configuration enumeration values definition
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 typedef enum
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 0:9b334a45a8ff 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 } DMA_ControlTypeDef;
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @brief HAL DMA State structures definition
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106 typedef enum
bogdanm 0:9b334a45a8ff 107 {
bogdanm 0:9b334a45a8ff 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 0:9b334a45a8ff 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 0:9b334a45a8ff 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 0:9b334a45a8ff 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 0:9b334a45a8ff 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 }HAL_DMA_StateTypeDef;
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /**
bogdanm 0:9b334a45a8ff 118 * @brief HAL DMA Error Code structure definition
bogdanm 0:9b334a45a8ff 119 */
bogdanm 0:9b334a45a8ff 120 typedef enum
bogdanm 0:9b334a45a8ff 121 {
bogdanm 0:9b334a45a8ff 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 0:9b334a45a8ff 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /**
bogdanm 0:9b334a45a8ff 129 * @brief DMA handle Structure definition
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131 typedef struct __DMA_HandleTypeDef
bogdanm 0:9b334a45a8ff 132 {
bogdanm 0:9b334a45a8ff 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 void *Parent; /*!< Parent object state */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 } DMA_HandleTypeDef;
bogdanm 0:9b334a45a8ff 152 /**
bogdanm 0:9b334a45a8ff 153 * @}
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 0:9b334a45a8ff 158 * @{
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 0:9b334a45a8ff 162 * @{
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 0:9b334a45a8ff 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 0:9b334a45a8ff 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 0:9b334a45a8ff 167 /**
bogdanm 0:9b334a45a8ff 168 * @}
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 0:9b334a45a8ff 173 * @{
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 0:9b334a45a8ff 176 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 0:9b334a45a8ff 177 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 0:9b334a45a8ff 180 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 0:9b334a45a8ff 181 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 0:9b334a45a8ff 182 /**
bogdanm 0:9b334a45a8ff 183 * @}
bogdanm 0:9b334a45a8ff 184 */
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
bogdanm 0:9b334a45a8ff 187 * @{
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @}
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 0:9b334a45a8ff 195 * @{
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 0:9b334a45a8ff 198 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 0:9b334a45a8ff 201 ((STATE) == DMA_PINC_DISABLE))
bogdanm 0:9b334a45a8ff 202 /**
bogdanm 0:9b334a45a8ff 203 * @}
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 0:9b334a45a8ff 207 * @{
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 0:9b334a45a8ff 210 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 0:9b334a45a8ff 213 ((STATE) == DMA_MINC_DISABLE))
bogdanm 0:9b334a45a8ff 214 /**
bogdanm 0:9b334a45a8ff 215 * @}
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 0:9b334a45a8ff 219 * @{
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 0:9b334a45a8ff 222 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 0:9b334a45a8ff 223 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 0:9b334a45a8ff 226 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 0:9b334a45a8ff 227 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 0:9b334a45a8ff 228 /**
bogdanm 0:9b334a45a8ff 229 * @}
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 0:9b334a45a8ff 234 * @{
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 0:9b334a45a8ff 237 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 0:9b334a45a8ff 238 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 0:9b334a45a8ff 241 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 0:9b334a45a8ff 242 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @}
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /** @defgroup DMA_mode DMA mode
bogdanm 0:9b334a45a8ff 248 * @{
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 0:9b334a45a8ff 251 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 0:9b334a45a8ff 254 ((MODE) == DMA_CIRCULAR))
bogdanm 0:9b334a45a8ff 255 /**
bogdanm 0:9b334a45a8ff 256 * @}
bogdanm 0:9b334a45a8ff 257 */
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 0:9b334a45a8ff 260 * @{
bogdanm 0:9b334a45a8ff 261 */
bogdanm 0:9b334a45a8ff 262 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 0:9b334a45a8ff 263 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 0:9b334a45a8ff 264 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 0:9b334a45a8ff 265 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 0:9b334a45a8ff 268 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 0:9b334a45a8ff 269 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 0:9b334a45a8ff 270 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 0:9b334a45a8ff 271 /**
bogdanm 0:9b334a45a8ff 272 * @}
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 0:9b334a45a8ff 277 * @{
bogdanm 0:9b334a45a8ff 278 */
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 0:9b334a45a8ff 281 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 0:9b334a45a8ff 282 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @}
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 0:9b334a45a8ff 289 * @{
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 293 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 294 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 295 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 296 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 297 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 298 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 299 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 300 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 301 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 302 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 303 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 304 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 305 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 306 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 307 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 308 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 309 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 310 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 311 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 312 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 313 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 314 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 315 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 316 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 317 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 318 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 319 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /**
bogdanm 0:9b334a45a8ff 323 * @}
bogdanm 0:9b334a45a8ff 324 */
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /**
bogdanm 0:9b334a45a8ff 327 * @}
bogdanm 0:9b334a45a8ff 328 */
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Exported macros -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 331 /** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm 0:9b334a45a8ff 332 * @{
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /** @brief Reset DMA handle state
bogdanm 0:9b334a45a8ff 336 * @param __HANDLE__: DMA handle.
bogdanm 0:9b334a45a8ff 337 * @retval None
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /**
bogdanm 0:9b334a45a8ff 342 * @brief Enable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 343 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 344 * @retval None.
bogdanm 0:9b334a45a8ff 345 */
bogdanm 0:9b334a45a8ff 346 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /**
bogdanm 0:9b334a45a8ff 349 * @brief Disable the specified DMA Channel.
bogdanm 0:9b334a45a8ff 350 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 351 * @retval None.
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Interrupt & Flag management */
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /**
bogdanm 0:9b334a45a8ff 359 * @brief Enables the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 360 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 361 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 362 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 363 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 364 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 365 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 366 * @retval None
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /**
bogdanm 0:9b334a45a8ff 371 * @brief Disables the specified DMA Channel interrupts.
bogdanm 0:9b334a45a8ff 372 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 373 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 374 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 375 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 376 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 377 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 378 * @retval None
bogdanm 0:9b334a45a8ff 379 */
bogdanm 0:9b334a45a8ff 380 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 384 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 385 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 0:9b334a45a8ff 386 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 387 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 388 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 389 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 390 * @retval The state of DMA_IT (SET or RESET).
bogdanm 0:9b334a45a8ff 391 */
bogdanm 0:9b334a45a8ff 392 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /**
bogdanm 0:9b334a45a8ff 395 * @}
bogdanm 0:9b334a45a8ff 396 */
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Include DMA HAL Extended module */
bogdanm 0:9b334a45a8ff 399 #include "stm32f3xx_hal_dma_ex.h"
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 402 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 403 * @{
bogdanm 0:9b334a45a8ff 404 */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 407 * @{
bogdanm 0:9b334a45a8ff 408 */
bogdanm 0:9b334a45a8ff 409 /* Initialization and de-initialization functions *****************************/
bogdanm 0:9b334a45a8ff 410 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 411 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /**
bogdanm 0:9b334a45a8ff 414 * @}
bogdanm 0:9b334a45a8ff 415 */
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
bogdanm 0:9b334a45a8ff 418 * @{
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420 /* IO operation functions *****************************************************/
bogdanm 0:9b334a45a8ff 421 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 422 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 423 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 424 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 425 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /**
bogdanm 0:9b334a45a8ff 428 * @}
bogdanm 0:9b334a45a8ff 429 */
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 0:9b334a45a8ff 432 * @{
bogdanm 0:9b334a45a8ff 433 */
bogdanm 0:9b334a45a8ff 434 /* Peripheral State and Error functions ***************************************/
bogdanm 0:9b334a45a8ff 435 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 436 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /**
bogdanm 0:9b334a45a8ff 439 * @}
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /**
bogdanm 0:9b334a45a8ff 443 * @}
bogdanm 0:9b334a45a8ff 444 */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /**
bogdanm 0:9b334a45a8ff 447 * @}
bogdanm 0:9b334a45a8ff 448 */
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /**
bogdanm 0:9b334a45a8ff 451 * @}
bogdanm 0:9b334a45a8ff 452 */
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456 #endif
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 #endif /* __STM32F3xx_HAL_DMA_H */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/