fix LPC812 PWM
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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f3xx_hal_adc_ex.c |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.1.0 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 12-Sept-2014 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief This file provides firmware functions to manage the following |
bogdanm | 0:9b334a45a8ff | 8 | * functionalities of the Analog to Digital Convertor (ADC) |
bogdanm | 0:9b334a45a8ff | 9 | * peripheral: |
bogdanm | 0:9b334a45a8ff | 10 | * + Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 11 | * ++ Initialization and Configuration of ADC |
bogdanm | 0:9b334a45a8ff | 12 | * + Operation functions |
bogdanm | 0:9b334a45a8ff | 13 | * ++ Start, stop, get result of conversions of regular and injected |
bogdanm | 0:9b334a45a8ff | 14 | * groups, using 3 possible modes: polling, interruption or DMA. |
bogdanm | 0:9b334a45a8ff | 15 | * ++ Multimode feature (available on devices with 2 ADCs or more) |
bogdanm | 0:9b334a45a8ff | 16 | * ++ Calibration (ADC automatic self-calibration) |
bogdanm | 0:9b334a45a8ff | 17 | * + Control functions |
bogdanm | 0:9b334a45a8ff | 18 | * ++ Configure channels on regular group |
bogdanm | 0:9b334a45a8ff | 19 | * ++ Configure channels on injected group |
bogdanm | 0:9b334a45a8ff | 20 | * ++ Configure the analog watchdog |
bogdanm | 0:9b334a45a8ff | 21 | * + State functions |
bogdanm | 0:9b334a45a8ff | 22 | * ++ ADC state machine management |
bogdanm | 0:9b334a45a8ff | 23 | * ++ Interrupts and flags management |
bogdanm | 0:9b334a45a8ff | 24 | * |
bogdanm | 0:9b334a45a8ff | 25 | @verbatim |
bogdanm | 0:9b334a45a8ff | 26 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 27 | ##### ADC specific features ##### |
bogdanm | 0:9b334a45a8ff | 28 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 29 | [..] |
bogdanm | 0:9b334a45a8ff | 30 | (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on |
bogdanm | 0:9b334a45a8ff | 31 | STM32F30xxC devices). |
bogdanm | 0:9b334a45a8ff | 32 | |
bogdanm | 0:9b334a45a8ff | 33 | (#) Interrupt generation at the end of regular conversion, end of injected |
bogdanm | 0:9b334a45a8ff | 34 | conversion, and in case of analog watchdog or overrun events. |
bogdanm | 0:9b334a45a8ff | 35 | |
bogdanm | 0:9b334a45a8ff | 36 | (#) Single and continuous conversion modes. |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | (#) Scan mode for automatic conversion of channel 0 to channel 'n'. |
bogdanm | 0:9b334a45a8ff | 39 | |
bogdanm | 0:9b334a45a8ff | 40 | (#) Data alignment with in-built data coherency. |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | (#) Channel-wise programmable sampling time. |
bogdanm | 0:9b334a45a8ff | 43 | |
bogdanm | 0:9b334a45a8ff | 44 | (#) ADC conversion Regular or Injected groups. |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | (#) External trigger (timer or EXTI) with configurable polarity for both |
bogdanm | 0:9b334a45a8ff | 47 | regular and injected groups. |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | (#) DMA request generation for transfer of conversions data of regular group. |
bogdanm | 0:9b334a45a8ff | 50 | |
bogdanm | 0:9b334a45a8ff | 51 | (#) Multimode Dual mode (available on devices with 2 ADCs or more). |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | (#) Configurable DMA data storage in Multimode Dual mode (available on devices |
bogdanm | 0:9b334a45a8ff | 54 | with 2 DCs or more). |
bogdanm | 0:9b334a45a8ff | 55 | |
bogdanm | 0:9b334a45a8ff | 56 | (#) Configurable delay between conversions in Dual interleaved mode (available |
bogdanm | 0:9b334a45a8ff | 57 | on devices with 2 DCs or more). |
bogdanm | 0:9b334a45a8ff | 58 | |
bogdanm | 0:9b334a45a8ff | 59 | (#) ADC calibration |
bogdanm | 0:9b334a45a8ff | 60 | |
bogdanm | 0:9b334a45a8ff | 61 | (#) ADC channels selectable single/differential input (available only on |
bogdanm | 0:9b334a45a8ff | 62 | STM32F30xxC devices) |
bogdanm | 0:9b334a45a8ff | 63 | |
bogdanm | 0:9b334a45a8ff | 64 | (#) ADC Injected sequencer&channels configuration context queue (available |
bogdanm | 0:9b334a45a8ff | 65 | only on STM32F30xxC devices) |
bogdanm | 0:9b334a45a8ff | 66 | |
bogdanm | 0:9b334a45a8ff | 67 | (#) ADC offset on injected and regular groups (offset on regular group |
bogdanm | 0:9b334a45a8ff | 68 | available only on STM32F30xxC devices) |
bogdanm | 0:9b334a45a8ff | 69 | |
bogdanm | 0:9b334a45a8ff | 70 | (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
bogdanm | 0:9b334a45a8ff | 71 | slower speed. |
bogdanm | 0:9b334a45a8ff | 72 | |
bogdanm | 0:9b334a45a8ff | 73 | (#) ADC input range: from Vref (connected to Vssa) to Vref+ (connected to |
bogdanm | 0:9b334a45a8ff | 74 | Vdda or to an external voltage reference). |
bogdanm | 0:9b334a45a8ff | 75 | |
bogdanm | 0:9b334a45a8ff | 76 | |
bogdanm | 0:9b334a45a8ff | 77 | ##### How to use this driver ##### |
bogdanm | 0:9b334a45a8ff | 78 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 79 | [..] |
bogdanm | 0:9b334a45a8ff | 80 | |
bogdanm | 0:9b334a45a8ff | 81 | (#) Enable the ADC interface |
bogdanm | 0:9b334a45a8ff | 82 | As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured |
bogdanm | 0:9b334a45a8ff | 83 | at RCC top level: clock source and clock prescaler. |
bogdanm | 0:9b334a45a8ff | 84 | |
bogdanm | 0:9b334a45a8ff | 85 | For STM32F30x/STM32F33x devices: |
bogdanm | 0:9b334a45a8ff | 86 | Two possible clock sources: synchronous clock derived from AHB clock |
bogdanm | 0:9b334a45a8ff | 87 | or asynchronous clock derived from ADC dedicated PLL 72MHz. |
bogdanm | 0:9b334a45a8ff | 88 | - synchronous clock is configured using macro __ADCx_CLK_ENABLE() |
bogdanm | 0:9b334a45a8ff | 89 | - asynchronous clock is configured using macro __HAL_RCC_ADCx_CONFIG() |
bogdanm | 0:9b334a45a8ff | 90 | or function HAL_RCCEx_PeriphCLKConfig(). |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | For example, in case of device with a single ADC: |
bogdanm | 0:9b334a45a8ff | 93 | __ADC1_CLK_ENABLE() (mandatory) |
bogdanm | 0:9b334a45a8ff | 94 | __HAL_RCC_ADC1_CONFIG(RCC_ADC1PLLCLK_DIV1); (optional) |
bogdanm | 0:9b334a45a8ff | 95 | |
bogdanm | 0:9b334a45a8ff | 96 | For example, in case of device with several ADCs: |
bogdanm | 0:9b334a45a8ff | 97 | if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) |
bogdanm | 0:9b334a45a8ff | 98 | { |
bogdanm | 0:9b334a45a8ff | 99 | __ADC12_CLK_ENABLE() (mandatory) |
bogdanm | 0:9b334a45a8ff | 100 | __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); (optional) |
bogdanm | 0:9b334a45a8ff | 101 | } |
bogdanm | 0:9b334a45a8ff | 102 | else |
bogdanm | 0:9b334a45a8ff | 103 | { |
bogdanm | 0:9b334a45a8ff | 104 | __ADC34_CLK_ENABLE() (mandatory) |
bogdanm | 0:9b334a45a8ff | 105 | __HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); (optional) |
bogdanm | 0:9b334a45a8ff | 106 | } |
bogdanm | 0:9b334a45a8ff | 107 | |
bogdanm | 0:9b334a45a8ff | 108 | For STM32F37x devices: |
bogdanm | 0:9b334a45a8ff | 109 | Only one clock source: APB2 clock. |
bogdanm | 0:9b334a45a8ff | 110 | Example: |
bogdanm | 0:9b334a45a8ff | 111 | __HAL_RCC_ADC1_CONFIG(RCC_ADC1PCLK2_DIV2); |
bogdanm | 0:9b334a45a8ff | 112 | |
bogdanm | 0:9b334a45a8ff | 113 | (#) ADC pins configuration |
bogdanm | 0:9b334a45a8ff | 114 | (++) Enable the clock for the ADC GPIOs using the following function: |
bogdanm | 0:9b334a45a8ff | 115 | __GPIOx_CLK_ENABLE(); |
bogdanm | 0:9b334a45a8ff | 116 | (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); |
bogdanm | 0:9b334a45a8ff | 117 | |
bogdanm | 0:9b334a45a8ff | 118 | (#) Configure the ADC parameters (conversion resolution, data alignment, |
bogdanm | 0:9b334a45a8ff | 119 | continuous mode, ...) using the HAL_ADC_Init() function. |
bogdanm | 0:9b334a45a8ff | 120 | |
bogdanm | 0:9b334a45a8ff | 121 | (#) Activate the ADC peripheral using one of the start functions: |
bogdanm | 0:9b334a45a8ff | 122 | HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA() |
bogdanm | 0:9b334a45a8ff | 123 | HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or |
bogdanm | 0:9b334a45a8ff | 124 | HAL_ADC_MultiModeStart_DMA(). |
bogdanm | 0:9b334a45a8ff | 125 | |
bogdanm | 0:9b334a45a8ff | 126 | *** Channels to regular group configuration *** |
bogdanm | 0:9b334a45a8ff | 127 | ============================================ |
bogdanm | 0:9b334a45a8ff | 128 | [..] |
bogdanm | 0:9b334a45a8ff | 129 | (+) To configure the ADC regular group features, use |
bogdanm | 0:9b334a45a8ff | 130 | HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. |
bogdanm | 0:9b334a45a8ff | 131 | (+) To activate the continuous mode, use the HAL_ADC_Init() function. |
bogdanm | 0:9b334a45a8ff | 132 | (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. |
bogdanm | 0:9b334a45a8ff | 133 | |
bogdanm | 0:9b334a45a8ff | 134 | *** Multimode ADCs configuration *** |
bogdanm | 0:9b334a45a8ff | 135 | ====================================================== |
bogdanm | 0:9b334a45a8ff | 136 | [..] |
bogdanm | 0:9b334a45a8ff | 137 | (+) Multimode feature is available on devices with 2 ADCs or more. |
bogdanm | 0:9b334a45a8ff | 138 | (+) Refer to "Channels to regular group" description to |
bogdanm | 0:9b334a45a8ff | 139 | configure the ADC1 and ADC2 regular groups. |
bogdanm | 0:9b334a45a8ff | 140 | (+) Select the Multi mode ADC features (dual mode |
bogdanm | 0:9b334a45a8ff | 141 | simultaneous, interleaved, ...) and configure the DMA mode using |
bogdanm | 0:9b334a45a8ff | 142 | HAL_ADCEx_MultiModeConfigChannel() functions. |
bogdanm | 0:9b334a45a8ff | 143 | (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() |
bogdanm | 0:9b334a45a8ff | 144 | function. |
bogdanm | 0:9b334a45a8ff | 145 | |
bogdanm | 0:9b334a45a8ff | 146 | *** DMA for regular configuration *** |
bogdanm | 0:9b334a45a8ff | 147 | ============================================================= |
bogdanm | 0:9b334a45a8ff | 148 | [..] |
bogdanm | 0:9b334a45a8ff | 149 | (+) To enable the DMA mode for regular group, use the |
bogdanm | 0:9b334a45a8ff | 150 | HAL_ADC_Start_DMA() function. |
bogdanm | 0:9b334a45a8ff | 151 | (+) To enable the generation of DMA requests continuously at the end of |
bogdanm | 0:9b334a45a8ff | 152 | the last DMA transfer, use the HAL_ADC_Init() function. |
bogdanm | 0:9b334a45a8ff | 153 | |
bogdanm | 0:9b334a45a8ff | 154 | *** Channels to injected group configuration *** |
bogdanm | 0:9b334a45a8ff | 155 | ============================================= |
bogdanm | 0:9b334a45a8ff | 156 | [..] |
bogdanm | 0:9b334a45a8ff | 157 | (+) To configure the ADC Injected channels group features, use |
bogdanm | 0:9b334a45a8ff | 158 | HAL_ADCEx_InjectedConfigChannel() functions. |
bogdanm | 0:9b334a45a8ff | 159 | (+) To activate the continuous mode, use the HAL_ADC_Init() function. |
bogdanm | 0:9b334a45a8ff | 160 | (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() |
bogdanm | 0:9b334a45a8ff | 161 | function. |
bogdanm | 0:9b334a45a8ff | 162 | |
bogdanm | 0:9b334a45a8ff | 163 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 164 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 165 | * @attention |
bogdanm | 0:9b334a45a8ff | 166 | * |
bogdanm | 0:9b334a45a8ff | 167 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 168 | * |
bogdanm | 0:9b334a45a8ff | 169 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 170 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 171 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 172 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 173 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 174 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 175 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 176 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 177 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 178 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 179 | * |
bogdanm | 0:9b334a45a8ff | 180 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 181 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 182 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 183 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 184 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 185 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 186 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 187 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 188 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 189 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 190 | * |
bogdanm | 0:9b334a45a8ff | 191 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 192 | */ |
bogdanm | 0:9b334a45a8ff | 193 | |
bogdanm | 0:9b334a45a8ff | 194 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 195 | #include "stm32f3xx_hal.h" |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | /** @addtogroup STM32F3xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 198 | * @{ |
bogdanm | 0:9b334a45a8ff | 199 | */ |
bogdanm | 0:9b334a45a8ff | 200 | |
bogdanm | 0:9b334a45a8ff | 201 | /** @defgroup ADCEx ADC Extended HAL module driver |
bogdanm | 0:9b334a45a8ff | 202 | * @brief ADC Extended HAL module driver |
bogdanm | 0:9b334a45a8ff | 203 | * @{ |
bogdanm | 0:9b334a45a8ff | 204 | */ |
bogdanm | 0:9b334a45a8ff | 205 | |
bogdanm | 0:9b334a45a8ff | 206 | #ifdef HAL_ADC_MODULE_ENABLED |
bogdanm | 0:9b334a45a8ff | 207 | |
bogdanm | 0:9b334a45a8ff | 208 | /* Private typedef -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 209 | /* Private define ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 210 | /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants |
bogdanm | 0:9b334a45a8ff | 211 | * @{ |
bogdanm | 0:9b334a45a8ff | 212 | */ |
bogdanm | 0:9b334a45a8ff | 213 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 214 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 215 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 216 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 217 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
bogdanm | 0:9b334a45a8ff | 218 | /* settling time. */ |
bogdanm | 0:9b334a45a8ff | 219 | /* Values defined to be higher than worst cases: low clock frequency, */ |
bogdanm | 0:9b334a45a8ff | 220 | /* maximum prescalers. */ |
bogdanm | 0:9b334a45a8ff | 221 | /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */ |
bogdanm | 0:9b334a45a8ff | 222 | /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */ |
bogdanm | 0:9b334a45a8ff | 223 | /* resolution 12 bits. */ |
bogdanm | 0:9b334a45a8ff | 224 | /* Unit: ms */ |
bogdanm | 0:9b334a45a8ff | 225 | #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10) |
bogdanm | 0:9b334a45a8ff | 226 | #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) |
bogdanm | 0:9b334a45a8ff | 227 | #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) |
bogdanm | 0:9b334a45a8ff | 228 | #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11) |
bogdanm | 0:9b334a45a8ff | 229 | |
bogdanm | 0:9b334a45a8ff | 230 | /* Timeout to wait for current conversion on going to be completed. */ |
bogdanm | 0:9b334a45a8ff | 231 | /* Timeout fixed to worst case, for 1 channel. */ |
bogdanm | 0:9b334a45a8ff | 232 | /* - maximum sampling time (601.5 adc_clk) */ |
bogdanm | 0:9b334a45a8ff | 233 | /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ |
bogdanm | 0:9b334a45a8ff | 234 | /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */ |
bogdanm | 0:9b334a45a8ff | 235 | /* Unit: cycles of CPU clock. */ |
bogdanm | 0:9b334a45a8ff | 236 | #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928) |
bogdanm | 0:9b334a45a8ff | 237 | |
bogdanm | 0:9b334a45a8ff | 238 | /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ |
bogdanm | 0:9b334a45a8ff | 239 | /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */ |
bogdanm | 0:9b334a45a8ff | 240 | /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 72MHz to */ |
bogdanm | 0:9b334a45a8ff | 241 | /* have the minimum number of CPU cycles to fulfill this delay. */ |
bogdanm | 0:9b334a45a8ff | 242 | #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)720) |
bogdanm | 0:9b334a45a8ff | 243 | |
bogdanm | 0:9b334a45a8ff | 244 | /* Delay for temperature sensor stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 245 | /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */ |
bogdanm | 0:9b334a45a8ff | 246 | /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 72MHz to */ |
bogdanm | 0:9b334a45a8ff | 247 | /* have the minimum number of CPU cycles to fulfill this delay. */ |
bogdanm | 0:9b334a45a8ff | 248 | #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t)720) |
bogdanm | 0:9b334a45a8ff | 249 | |
bogdanm | 0:9b334a45a8ff | 250 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 251 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 252 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 253 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 254 | |
bogdanm | 0:9b334a45a8ff | 255 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 256 | /* Fixed timeout values for ADC calibration, enable settling time. */ |
bogdanm | 0:9b334a45a8ff | 257 | /* Values defined to be higher than worst cases: low clocks freq, */ |
bogdanm | 0:9b334a45a8ff | 258 | /* maximum prescalers. */ |
bogdanm | 0:9b334a45a8ff | 259 | /* ex: On STM32F303C, clock source PLL=1MHz, presc. RCC_ADC12PLLCLK_DIV256 */ |
bogdanm | 0:9b334a45a8ff | 260 | /* Unit: ms */ |
bogdanm | 0:9b334a45a8ff | 261 | #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10) |
bogdanm | 0:9b334a45a8ff | 262 | #define ADC_ENABLE_TIMEOUT ((uint32_t) 10) |
bogdanm | 0:9b334a45a8ff | 263 | |
bogdanm | 0:9b334a45a8ff | 264 | /* Delay for ADC stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 265 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
bogdanm | 0:9b334a45a8ff | 266 | /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */ |
bogdanm | 0:9b334a45a8ff | 267 | /* have the minimum number of CPU cycles to fulfill this delay. */ |
bogdanm | 0:9b334a45a8ff | 268 | #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)72) |
bogdanm | 0:9b334a45a8ff | 269 | |
bogdanm | 0:9b334a45a8ff | 270 | /* Maximum number of CPU cycles corresponding to 1 ADC cycle */ |
bogdanm | 0:9b334a45a8ff | 271 | /* Value fixed to worst case: clock prescalers slowing down ADC clock to */ |
bogdanm | 0:9b334a45a8ff | 272 | /* minimum frequency */ |
bogdanm | 0:9b334a45a8ff | 273 | /* - AHB prescaler: 16 */ |
bogdanm | 0:9b334a45a8ff | 274 | /* - ADC prescaler: 8 */ |
bogdanm | 0:9b334a45a8ff | 275 | /* Unit: cycles of CPU clock. */ |
bogdanm | 0:9b334a45a8ff | 276 | #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128) |
bogdanm | 0:9b334a45a8ff | 277 | |
bogdanm | 0:9b334a45a8ff | 278 | /* ADC conversion cycles (unit: ADC clock cycles) */ |
bogdanm | 0:9b334a45a8ff | 279 | /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ |
bogdanm | 0:9b334a45a8ff | 280 | /* resolution 12 bits) */ |
bogdanm | 0:9b334a45a8ff | 281 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14) |
bogdanm | 0:9b334a45a8ff | 282 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20) |
bogdanm | 0:9b334a45a8ff | 283 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26) |
bogdanm | 0:9b334a45a8ff | 284 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41) |
bogdanm | 0:9b334a45a8ff | 285 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54) |
bogdanm | 0:9b334a45a8ff | 286 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68) |
bogdanm | 0:9b334a45a8ff | 287 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84) |
bogdanm | 0:9b334a45a8ff | 288 | #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252) |
bogdanm | 0:9b334a45a8ff | 289 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 290 | /** |
bogdanm | 0:9b334a45a8ff | 291 | * @} |
bogdanm | 0:9b334a45a8ff | 292 | */ |
bogdanm | 0:9b334a45a8ff | 293 | |
bogdanm | 0:9b334a45a8ff | 294 | /* Private macro -------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 295 | /* Private variables ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 296 | /* Private function prototypes -----------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 297 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 298 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 299 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 300 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 301 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 302 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 303 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); |
bogdanm | 0:9b334a45a8ff | 304 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 305 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 306 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 307 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 308 | |
bogdanm | 0:9b334a45a8ff | 309 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 310 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 311 | static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 312 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 313 | |
bogdanm | 0:9b334a45a8ff | 314 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 315 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 316 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 317 | |
bogdanm | 0:9b334a45a8ff | 318 | /* Exported functions --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 319 | |
bogdanm | 0:9b334a45a8ff | 320 | /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions |
bogdanm | 0:9b334a45a8ff | 321 | * @{ |
bogdanm | 0:9b334a45a8ff | 322 | */ |
bogdanm | 0:9b334a45a8ff | 323 | |
bogdanm | 0:9b334a45a8ff | 324 | /** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 325 | * @brief Extended Initialization and Configuration functions |
bogdanm | 0:9b334a45a8ff | 326 | * |
bogdanm | 0:9b334a45a8ff | 327 | @verbatim |
bogdanm | 0:9b334a45a8ff | 328 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 329 | ##### Initialization and de-initialization functions ##### |
bogdanm | 0:9b334a45a8ff | 330 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 331 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 332 | (+) Initialize and configure the ADC. |
bogdanm | 0:9b334a45a8ff | 333 | (+) De-initialize the ADC. |
bogdanm | 0:9b334a45a8ff | 334 | |
bogdanm | 0:9b334a45a8ff | 335 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 336 | * @{ |
bogdanm | 0:9b334a45a8ff | 337 | */ |
bogdanm | 0:9b334a45a8ff | 338 | |
bogdanm | 0:9b334a45a8ff | 339 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 340 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 341 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 342 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 343 | /** |
bogdanm | 0:9b334a45a8ff | 344 | * @brief Initializes the ADC peripheral and regular group according to |
bogdanm | 0:9b334a45a8ff | 345 | * parameters specified in structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 346 | * @note As prerequisite, ADC clock must be configured at RCC top level |
bogdanm | 0:9b334a45a8ff | 347 | * depending on both possible clock sources: AHB clock or PLL clock. |
bogdanm | 0:9b334a45a8ff | 348 | * See commented example code below that can be copied and uncommented |
bogdanm | 0:9b334a45a8ff | 349 | * into HAL_ADC_MspInit(). |
bogdanm | 0:9b334a45a8ff | 350 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 351 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
bogdanm | 0:9b334a45a8ff | 352 | * coming from ADC state reset. Following calls to this function can |
bogdanm | 0:9b334a45a8ff | 353 | * be used to reconfigure some parameters of ADC_InitTypeDef |
bogdanm | 0:9b334a45a8ff | 354 | * structure on the fly, without modifying MSP configuration. If ADC |
bogdanm | 0:9b334a45a8ff | 355 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
bogdanm | 0:9b334a45a8ff | 356 | * before HAL_ADC_Init(). |
bogdanm | 0:9b334a45a8ff | 357 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 358 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 359 | * "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 360 | * @note This function configures the ADC within 2 scopes: scope of entire |
bogdanm | 0:9b334a45a8ff | 361 | * ADC and scope of regular group. For parameters details, see comments |
bogdanm | 0:9b334a45a8ff | 362 | * of structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 363 | * @note For devices with several ADCs: parameters related to common ADC |
bogdanm | 0:9b334a45a8ff | 364 | * registers (ADC clock mode) are set only if all ADCs sharing the |
bogdanm | 0:9b334a45a8ff | 365 | * same common group are disabled. |
bogdanm | 0:9b334a45a8ff | 366 | * If this is not the case, these common parameters setting are |
bogdanm | 0:9b334a45a8ff | 367 | * bypassed without error reporting: it can be the intended behaviour in |
bogdanm | 0:9b334a45a8ff | 368 | * case of update of a parameter of ADC_InitTypeDef on the fly, |
bogdanm | 0:9b334a45a8ff | 369 | * without disabling the other ADCs sharing the same common group. |
bogdanm | 0:9b334a45a8ff | 370 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 371 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 372 | */ |
bogdanm | 0:9b334a45a8ff | 373 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 374 | { |
bogdanm | 0:9b334a45a8ff | 375 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 376 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 377 | ADC_HandleTypeDef tmphadcSharingSameCommonRegister; |
bogdanm | 0:9b334a45a8ff | 378 | uint32_t tmpCFGR = 0; |
bogdanm | 0:9b334a45a8ff | 379 | uint32_t WaitLoopIndex = 0; |
bogdanm | 0:9b334a45a8ff | 380 | |
bogdanm | 0:9b334a45a8ff | 381 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 382 | if(hadc == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 383 | { |
bogdanm | 0:9b334a45a8ff | 384 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 385 | } |
bogdanm | 0:9b334a45a8ff | 386 | |
bogdanm | 0:9b334a45a8ff | 387 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 388 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 389 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
bogdanm | 0:9b334a45a8ff | 390 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
bogdanm | 0:9b334a45a8ff | 391 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
bogdanm | 0:9b334a45a8ff | 392 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
bogdanm | 0:9b334a45a8ff | 393 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
bogdanm | 0:9b334a45a8ff | 394 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 395 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 396 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
bogdanm | 0:9b334a45a8ff | 397 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
bogdanm | 0:9b334a45a8ff | 398 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
bogdanm | 0:9b334a45a8ff | 399 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
bogdanm | 0:9b334a45a8ff | 400 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
bogdanm | 0:9b334a45a8ff | 401 | assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); |
bogdanm | 0:9b334a45a8ff | 402 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); |
bogdanm | 0:9b334a45a8ff | 403 | |
bogdanm | 0:9b334a45a8ff | 404 | |
bogdanm | 0:9b334a45a8ff | 405 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
bogdanm | 0:9b334a45a8ff | 406 | /* at RCC top level depending on both possible clock sources: */ |
bogdanm | 0:9b334a45a8ff | 407 | /* PLL clock or AHB clock. */ |
bogdanm | 0:9b334a45a8ff | 408 | /* For example: */ |
bogdanm | 0:9b334a45a8ff | 409 | /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */ |
bogdanm | 0:9b334a45a8ff | 410 | /* { */ |
bogdanm | 0:9b334a45a8ff | 411 | /* __ADC12_CLK_ENABLE(); */ |
bogdanm | 0:9b334a45a8ff | 412 | /* __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); */ |
bogdanm | 0:9b334a45a8ff | 413 | /* } */ |
bogdanm | 0:9b334a45a8ff | 414 | /* else */ |
bogdanm | 0:9b334a45a8ff | 415 | /* { */ |
bogdanm | 0:9b334a45a8ff | 416 | /* __ADC34_CLK_ENABLE(); */ |
bogdanm | 0:9b334a45a8ff | 417 | /* __HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); */ |
bogdanm | 0:9b334a45a8ff | 418 | /* } */ |
bogdanm | 0:9b334a45a8ff | 419 | |
bogdanm | 0:9b334a45a8ff | 420 | |
bogdanm | 0:9b334a45a8ff | 421 | /* Actions performed only if ADC is coming from state reset: */ |
bogdanm | 0:9b334a45a8ff | 422 | /* - Initialization of ADC MSP */ |
bogdanm | 0:9b334a45a8ff | 423 | /* - ADC voltage regulator enable */ |
bogdanm | 0:9b334a45a8ff | 424 | if (hadc->State == HAL_ADC_STATE_RESET) |
bogdanm | 0:9b334a45a8ff | 425 | { |
bogdanm | 0:9b334a45a8ff | 426 | /* Init the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 427 | HAL_ADC_MspInit(hadc); |
bogdanm | 0:9b334a45a8ff | 428 | |
bogdanm | 0:9b334a45a8ff | 429 | /* Enable voltage regulator (if disabled at this step) */ |
bogdanm | 0:9b334a45a8ff | 430 | if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) |
bogdanm | 0:9b334a45a8ff | 431 | { |
bogdanm | 0:9b334a45a8ff | 432 | /* Note: The software must wait for the startup time of the ADC voltage */ |
bogdanm | 0:9b334a45a8ff | 433 | /* regulator before launching a calibration or enabling the ADC. */ |
bogdanm | 0:9b334a45a8ff | 434 | /* This temporization must be implemented by software and is */ |
bogdanm | 0:9b334a45a8ff | 435 | /* equal to 10 us in the worst case process/temperature/power */ |
bogdanm | 0:9b334a45a8ff | 436 | /* supply. */ |
bogdanm | 0:9b334a45a8ff | 437 | |
bogdanm | 0:9b334a45a8ff | 438 | /* Disable the ADC (if not already disabled) */ |
bogdanm | 0:9b334a45a8ff | 439 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 440 | |
bogdanm | 0:9b334a45a8ff | 441 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 442 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 443 | { |
bogdanm | 0:9b334a45a8ff | 444 | /* Initialize the ADC state */ |
bogdanm | 0:9b334a45a8ff | 445 | hadc->State = HAL_ADC_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 446 | |
bogdanm | 0:9b334a45a8ff | 447 | /* Set the intermediate state before moving the ADC voltage regulator */ |
bogdanm | 0:9b334a45a8ff | 448 | /* to state enable. */ |
bogdanm | 0:9b334a45a8ff | 449 | hadc->Instance->CR &= ~(ADC_CR_ADVREGEN); |
bogdanm | 0:9b334a45a8ff | 450 | /* Set ADVREGEN bits to 0x01 */ |
bogdanm | 0:9b334a45a8ff | 451 | hadc->Instance->CR |= ADC_CR_ADVREGEN_0; |
bogdanm | 0:9b334a45a8ff | 452 | |
bogdanm | 0:9b334a45a8ff | 453 | /* Delay for ADC stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 454 | /* Delay fixed to worst case: maximum CPU frequency */ |
bogdanm | 0:9b334a45a8ff | 455 | while(WaitLoopIndex < ADC_STAB_DELAY_CPU_CYCLES) |
bogdanm | 0:9b334a45a8ff | 456 | { |
bogdanm | 0:9b334a45a8ff | 457 | WaitLoopIndex++; |
bogdanm | 0:9b334a45a8ff | 458 | } |
bogdanm | 0:9b334a45a8ff | 459 | } |
bogdanm | 0:9b334a45a8ff | 460 | } |
bogdanm | 0:9b334a45a8ff | 461 | } |
bogdanm | 0:9b334a45a8ff | 462 | |
bogdanm | 0:9b334a45a8ff | 463 | /* Verification that ADC voltage regulator is correctly enabled, whatever */ |
bogdanm | 0:9b334a45a8ff | 464 | /* ADC coming from state reset or not (if any potential problem of */ |
bogdanm | 0:9b334a45a8ff | 465 | /* clocking, voltage regulator would not be enabled). */ |
bogdanm | 0:9b334a45a8ff | 466 | if ((hadc->Instance->CR & ADC_CR_ADVREGEN) != ADC_CR_ADVREGEN_0) |
bogdanm | 0:9b334a45a8ff | 467 | { |
bogdanm | 0:9b334a45a8ff | 468 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 469 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 470 | |
bogdanm | 0:9b334a45a8ff | 471 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 472 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 473 | |
bogdanm | 0:9b334a45a8ff | 474 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 475 | } |
bogdanm | 0:9b334a45a8ff | 476 | |
bogdanm | 0:9b334a45a8ff | 477 | |
bogdanm | 0:9b334a45a8ff | 478 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 479 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 480 | /* and if there is no conversion on going on regular group (ADC can be */ |
bogdanm | 0:9b334a45a8ff | 481 | /* enabled anyway, in case of call of this function to update a parameter */ |
bogdanm | 0:9b334a45a8ff | 482 | /* on the fly). */ |
bogdanm | 0:9b334a45a8ff | 483 | if ((hadc->State != HAL_ADC_STATE_ERROR) && |
bogdanm | 0:9b334a45a8ff | 484 | (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) |
bogdanm | 0:9b334a45a8ff | 485 | { |
bogdanm | 0:9b334a45a8ff | 486 | /* Initialize the ADC state */ |
bogdanm | 0:9b334a45a8ff | 487 | hadc->State = HAL_ADC_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 488 | |
bogdanm | 0:9b334a45a8ff | 489 | /* Configuration of common ADC parameters */ |
bogdanm | 0:9b334a45a8ff | 490 | |
bogdanm | 0:9b334a45a8ff | 491 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 492 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 493 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 494 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 495 | |
bogdanm | 0:9b334a45a8ff | 496 | /* Set handle of the other ADC sharing the same common register */ |
bogdanm | 0:9b334a45a8ff | 497 | __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); |
bogdanm | 0:9b334a45a8ff | 498 | |
bogdanm | 0:9b334a45a8ff | 499 | |
bogdanm | 0:9b334a45a8ff | 500 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 501 | /* Parameters that can be updated only when ADC is disabled: */ |
bogdanm | 0:9b334a45a8ff | 502 | /* - Multimode clock configuration */ |
bogdanm | 0:9b334a45a8ff | 503 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 504 | ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) || |
bogdanm | 0:9b334a45a8ff | 505 | (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) )) |
bogdanm | 0:9b334a45a8ff | 506 | { |
bogdanm | 0:9b334a45a8ff | 507 | /* Reset configuration of ADC common register CCR: */ |
bogdanm | 0:9b334a45a8ff | 508 | /* - ADC clock mode: CKMODE */ |
bogdanm | 0:9b334a45a8ff | 509 | /* Some parameters of this register are not reset, since they are set */ |
bogdanm | 0:9b334a45a8ff | 510 | /* by other functions and must be kept in case of usage of this */ |
bogdanm | 0:9b334a45a8ff | 511 | /* function on the fly (update of a parameter of ADC_InitTypeDef */ |
bogdanm | 0:9b334a45a8ff | 512 | /* without needing to reconfigure all other ADC groups/channels */ |
bogdanm | 0:9b334a45a8ff | 513 | /* parameters): */ |
bogdanm | 0:9b334a45a8ff | 514 | /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */ |
bogdanm | 0:9b334a45a8ff | 515 | /* into HAL_ADCEx_MultiModeConfigChannel() ) */ |
bogdanm | 0:9b334a45a8ff | 516 | /* - internal measurement paths: Vbat, temperature sensor, Vref */ |
bogdanm | 0:9b334a45a8ff | 517 | /* (set into HAL_ADC_ConfigChannel() or */ |
bogdanm | 0:9b334a45a8ff | 518 | /* HAL_ADCEx_InjectedConfigChannel() ) */ |
bogdanm | 0:9b334a45a8ff | 519 | tmpADC_Common->CCR &= ~(ADC_CCR_CKMODE); |
bogdanm | 0:9b334a45a8ff | 520 | |
bogdanm | 0:9b334a45a8ff | 521 | /* Configuration of common ADC clock: clock source PLL or AHB with */ |
bogdanm | 0:9b334a45a8ff | 522 | /* selectable prescaler */ |
bogdanm | 0:9b334a45a8ff | 523 | tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; |
bogdanm | 0:9b334a45a8ff | 524 | } |
bogdanm | 0:9b334a45a8ff | 525 | |
bogdanm | 0:9b334a45a8ff | 526 | /* Configuration of ADC: */ |
bogdanm | 0:9b334a45a8ff | 527 | /* - resolution */ |
bogdanm | 0:9b334a45a8ff | 528 | /* - data alignment */ |
bogdanm | 0:9b334a45a8ff | 529 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 530 | /* - external trigger polarity */ |
bogdanm | 0:9b334a45a8ff | 531 | /* - continuous conversion mode */ |
bogdanm | 0:9b334a45a8ff | 532 | /* - overrun */ |
bogdanm | 0:9b334a45a8ff | 533 | /* - discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 534 | hadc->Instance->CFGR &= ~( ADC_CFGR_DISCNUM | |
bogdanm | 0:9b334a45a8ff | 535 | ADC_CFGR_DISCEN | |
bogdanm | 0:9b334a45a8ff | 536 | ADC_CFGR_CONT | |
bogdanm | 0:9b334a45a8ff | 537 | ADC_CFGR_OVRMOD | |
bogdanm | 0:9b334a45a8ff | 538 | ADC_CFGR_EXTSEL | |
bogdanm | 0:9b334a45a8ff | 539 | ADC_CFGR_EXTEN | |
bogdanm | 0:9b334a45a8ff | 540 | ADC_CFGR_ALIGN | |
bogdanm | 0:9b334a45a8ff | 541 | ADC_CFGR_RES ); |
bogdanm | 0:9b334a45a8ff | 542 | |
bogdanm | 0:9b334a45a8ff | 543 | tmpCFGR |= ( __HAL_ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) | |
bogdanm | 0:9b334a45a8ff | 544 | __HAL_ADC_CFGR_OVERRUN(hadc->Init.Overrun) | |
bogdanm | 0:9b334a45a8ff | 545 | hadc->Init.DataAlign | |
bogdanm | 0:9b334a45a8ff | 546 | hadc->Init.Resolution ); |
bogdanm | 0:9b334a45a8ff | 547 | |
bogdanm | 0:9b334a45a8ff | 548 | /* Enable discontinuous mode only if continuous mode is disabled */ |
bogdanm | 0:9b334a45a8ff | 549 | if ((hadc->Init.DiscontinuousConvMode == ENABLE) && |
bogdanm | 0:9b334a45a8ff | 550 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 551 | { |
bogdanm | 0:9b334a45a8ff | 552 | /* Enable the selected ADC regular discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 553 | /* Set the number of channels to be converted in discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 554 | tmpCFGR |= ( ADC_CFGR_DISCEN | |
bogdanm | 0:9b334a45a8ff | 555 | __HAL_ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
bogdanm | 0:9b334a45a8ff | 556 | } |
bogdanm | 0:9b334a45a8ff | 557 | |
bogdanm | 0:9b334a45a8ff | 558 | /* Enable external trigger if trigger selection is different of software */ |
bogdanm | 0:9b334a45a8ff | 559 | /* start. */ |
bogdanm | 0:9b334a45a8ff | 560 | /* Note: This configuration keeps the hardware feature of parameter */ |
bogdanm | 0:9b334a45a8ff | 561 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
bogdanm | 0:9b334a45a8ff | 562 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 563 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 564 | { |
bogdanm | 0:9b334a45a8ff | 565 | tmpCFGR |= ( __HAL_ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | |
bogdanm | 0:9b334a45a8ff | 566 | hadc->Init.ExternalTrigConvEdge ); |
bogdanm | 0:9b334a45a8ff | 567 | } |
bogdanm | 0:9b334a45a8ff | 568 | |
bogdanm | 0:9b334a45a8ff | 569 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 570 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 571 | /* conversion on going on regular and injected groups: */ |
bogdanm | 0:9b334a45a8ff | 572 | /* - DMA continuous request */ |
bogdanm | 0:9b334a45a8ff | 573 | /* - LowPowerAutoWait feature */ |
bogdanm | 0:9b334a45a8ff | 574 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 575 | { |
bogdanm | 0:9b334a45a8ff | 576 | hadc->Instance->CFGR &= ~( ADC_CFGR_AUTDLY | |
bogdanm | 0:9b334a45a8ff | 577 | ADC_CFGR_DMACFG ); |
bogdanm | 0:9b334a45a8ff | 578 | |
bogdanm | 0:9b334a45a8ff | 579 | tmpCFGR |= ( __HAL_ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | |
bogdanm | 0:9b334a45a8ff | 580 | __HAL_ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); |
bogdanm | 0:9b334a45a8ff | 581 | } |
bogdanm | 0:9b334a45a8ff | 582 | |
bogdanm | 0:9b334a45a8ff | 583 | /* Update ADC configuration register with previous settings */ |
bogdanm | 0:9b334a45a8ff | 584 | hadc->Instance->CFGR |= tmpCFGR; |
bogdanm | 0:9b334a45a8ff | 585 | |
bogdanm | 0:9b334a45a8ff | 586 | |
bogdanm | 0:9b334a45a8ff | 587 | /* Configuration of regular group sequencer: */ |
bogdanm | 0:9b334a45a8ff | 588 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 589 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
bogdanm | 0:9b334a45a8ff | 590 | /* Parameter "NbrOfConversion" is discarded. */ |
bogdanm | 0:9b334a45a8ff | 591 | /* Note: Scan mode is not present by hardware on this device, but */ |
bogdanm | 0:9b334a45a8ff | 592 | /* emulated by software for alignment over all STM32 devices. */ |
bogdanm | 0:9b334a45a8ff | 593 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 594 | /* parameter "NbrOfConversion" */ |
bogdanm | 0:9b334a45a8ff | 595 | hadc->Instance->SQR1 &= ~(ADC_SQR1_L); |
bogdanm | 0:9b334a45a8ff | 596 | if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) |
bogdanm | 0:9b334a45a8ff | 597 | { |
bogdanm | 0:9b334a45a8ff | 598 | /* Set number of ranks in regular group sequencer */ |
bogdanm | 0:9b334a45a8ff | 599 | hadc->Instance->SQR1 |= (hadc->Init.NbrOfConversion - (uint8_t)1); |
bogdanm | 0:9b334a45a8ff | 600 | } |
bogdanm | 0:9b334a45a8ff | 601 | |
bogdanm | 0:9b334a45a8ff | 602 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 603 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 604 | |
bogdanm | 0:9b334a45a8ff | 605 | /* Initialize the ADC state */ |
bogdanm | 0:9b334a45a8ff | 606 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 607 | |
bogdanm | 0:9b334a45a8ff | 608 | } |
bogdanm | 0:9b334a45a8ff | 609 | else |
bogdanm | 0:9b334a45a8ff | 610 | { |
bogdanm | 0:9b334a45a8ff | 611 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 612 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 613 | |
bogdanm | 0:9b334a45a8ff | 614 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 615 | } |
bogdanm | 0:9b334a45a8ff | 616 | |
bogdanm | 0:9b334a45a8ff | 617 | |
bogdanm | 0:9b334a45a8ff | 618 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 619 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 620 | } |
bogdanm | 0:9b334a45a8ff | 621 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 622 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 623 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 624 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 625 | |
bogdanm | 0:9b334a45a8ff | 626 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 627 | /** |
bogdanm | 0:9b334a45a8ff | 628 | * @brief Initializes the ADC peripheral and regular group according to |
bogdanm | 0:9b334a45a8ff | 629 | * parameters specified in structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 630 | * @note As prerequisite, ADC clock must be configured at RCC top level |
bogdanm | 0:9b334a45a8ff | 631 | * (clock source APB2). |
bogdanm | 0:9b334a45a8ff | 632 | * See commented example code below that can be copied and uncommented |
bogdanm | 0:9b334a45a8ff | 633 | * into HAL_ADC_MspInit(). |
bogdanm | 0:9b334a45a8ff | 634 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 635 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
bogdanm | 0:9b334a45a8ff | 636 | * coming from ADC state reset. Following calls to this function can |
bogdanm | 0:9b334a45a8ff | 637 | * be used to reconfigure some parameters of ADC_InitTypeDef |
bogdanm | 0:9b334a45a8ff | 638 | * structure on the fly, without modifying MSP configuration. If ADC |
bogdanm | 0:9b334a45a8ff | 639 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
bogdanm | 0:9b334a45a8ff | 640 | * before HAL_ADC_Init(). |
bogdanm | 0:9b334a45a8ff | 641 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 642 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 643 | * "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 644 | * @note This function configures the ADC within 2 scopes: scope of entire |
bogdanm | 0:9b334a45a8ff | 645 | * ADC and scope of regular group. For parameters details, see comments |
bogdanm | 0:9b334a45a8ff | 646 | * of structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 647 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 648 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 649 | */ |
bogdanm | 0:9b334a45a8ff | 650 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 651 | { |
bogdanm | 0:9b334a45a8ff | 652 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 653 | |
bogdanm | 0:9b334a45a8ff | 654 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 655 | if(hadc == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 656 | { |
bogdanm | 0:9b334a45a8ff | 657 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 658 | } |
bogdanm | 0:9b334a45a8ff | 659 | |
bogdanm | 0:9b334a45a8ff | 660 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 661 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 662 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
bogdanm | 0:9b334a45a8ff | 663 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
bogdanm | 0:9b334a45a8ff | 664 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
bogdanm | 0:9b334a45a8ff | 665 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 666 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 667 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
bogdanm | 0:9b334a45a8ff | 668 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
bogdanm | 0:9b334a45a8ff | 669 | |
bogdanm | 0:9b334a45a8ff | 670 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
bogdanm | 0:9b334a45a8ff | 671 | /* at RCC top level. */ |
bogdanm | 0:9b334a45a8ff | 672 | /* For example: */ |
bogdanm | 0:9b334a45a8ff | 673 | /* __ADC1_CLK_ENABLE(); */ |
bogdanm | 0:9b334a45a8ff | 674 | |
bogdanm | 0:9b334a45a8ff | 675 | |
bogdanm | 0:9b334a45a8ff | 676 | /* Actions performed only if ADC is coming from state reset: */ |
bogdanm | 0:9b334a45a8ff | 677 | /* - Initialization of ADC MSP */ |
bogdanm | 0:9b334a45a8ff | 678 | if (hadc->State == HAL_ADC_STATE_RESET) |
bogdanm | 0:9b334a45a8ff | 679 | { |
bogdanm | 0:9b334a45a8ff | 680 | /* Init the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 681 | HAL_ADC_MspInit(hadc); |
bogdanm | 0:9b334a45a8ff | 682 | } |
bogdanm | 0:9b334a45a8ff | 683 | |
bogdanm | 0:9b334a45a8ff | 684 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 685 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 686 | /* Note: In case of ADC already enabled, precaution to not launch an */ |
bogdanm | 0:9b334a45a8ff | 687 | /* unwanted conversion while modifying register CR2 by writing 1 to */ |
bogdanm | 0:9b334a45a8ff | 688 | /* bit ADON. */ |
bogdanm | 0:9b334a45a8ff | 689 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 690 | |
bogdanm | 0:9b334a45a8ff | 691 | |
bogdanm | 0:9b334a45a8ff | 692 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 693 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 694 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 695 | { |
bogdanm | 0:9b334a45a8ff | 696 | /* Initialize the ADC state */ |
bogdanm | 0:9b334a45a8ff | 697 | hadc->State = HAL_ADC_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 698 | |
bogdanm | 0:9b334a45a8ff | 699 | /* Set ADC parameters */ |
bogdanm | 0:9b334a45a8ff | 700 | |
bogdanm | 0:9b334a45a8ff | 701 | /* Configuration of ADC: */ |
bogdanm | 0:9b334a45a8ff | 702 | /* - data alignment */ |
bogdanm | 0:9b334a45a8ff | 703 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 704 | /* - external trigger polarity (always set to 1, because needed for all */ |
bogdanm | 0:9b334a45a8ff | 705 | /* triggers: external trigger of SW start) */ |
bogdanm | 0:9b334a45a8ff | 706 | /* - continuous conversion mode */ |
bogdanm | 0:9b334a45a8ff | 707 | hadc->Instance->CR2 &= ~( ADC_CR2_ALIGN | |
bogdanm | 0:9b334a45a8ff | 708 | ADC_CR2_EXTSEL | |
bogdanm | 0:9b334a45a8ff | 709 | ADC_CR2_EXTTRIG | |
bogdanm | 0:9b334a45a8ff | 710 | ADC_CR2_CONT ); |
bogdanm | 0:9b334a45a8ff | 711 | |
bogdanm | 0:9b334a45a8ff | 712 | hadc->Instance->CR2 |= ( hadc->Init.DataAlign | |
bogdanm | 0:9b334a45a8ff | 713 | hadc->Init.ExternalTrigConv | |
bogdanm | 0:9b334a45a8ff | 714 | ADC_CR2_EXTTRIG | |
bogdanm | 0:9b334a45a8ff | 715 | __HAL_ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); |
bogdanm | 0:9b334a45a8ff | 716 | |
bogdanm | 0:9b334a45a8ff | 717 | /* Configuration of ADC: */ |
bogdanm | 0:9b334a45a8ff | 718 | /* - scan mode */ |
bogdanm | 0:9b334a45a8ff | 719 | /* - discontinuous mode disable/enable */ |
bogdanm | 0:9b334a45a8ff | 720 | /* - discontinuous mode number of conversions */ |
bogdanm | 0:9b334a45a8ff | 721 | hadc->Instance->CR1 &= ~( ADC_CR1_SCAN | |
bogdanm | 0:9b334a45a8ff | 722 | ADC_CR1_DISCEN | |
bogdanm | 0:9b334a45a8ff | 723 | ADC_CR1_DISCNUM ); |
bogdanm | 0:9b334a45a8ff | 724 | |
bogdanm | 0:9b334a45a8ff | 725 | hadc->Instance->CR1 |= ( __HAL_ADC_CR1_SCAN(hadc->Init.ScanConvMode) ); |
bogdanm | 0:9b334a45a8ff | 726 | |
bogdanm | 0:9b334a45a8ff | 727 | /* Enable discontinuous mode only if continuous mode is disabled */ |
bogdanm | 0:9b334a45a8ff | 728 | if ((hadc->Init.DiscontinuousConvMode == ENABLE) && |
bogdanm | 0:9b334a45a8ff | 729 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 730 | { |
bogdanm | 0:9b334a45a8ff | 731 | /* Enable the selected ADC regular discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 732 | hadc->Instance->CR1 |= (ADC_CR1_DISCEN); |
bogdanm | 0:9b334a45a8ff | 733 | |
bogdanm | 0:9b334a45a8ff | 734 | /* Set the number of channels to be converted in discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 735 | hadc->Instance->CR1 |= __HAL_ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); |
bogdanm | 0:9b334a45a8ff | 736 | } |
bogdanm | 0:9b334a45a8ff | 737 | |
bogdanm | 0:9b334a45a8ff | 738 | /* Configuration of regular group sequencer: */ |
bogdanm | 0:9b334a45a8ff | 739 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 740 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
bogdanm | 0:9b334a45a8ff | 741 | /* Parameter "NbrOfConversion" is discarded. */ |
bogdanm | 0:9b334a45a8ff | 742 | /* Note: Scan mode is present by hardware on this device and, if */ |
bogdanm | 0:9b334a45a8ff | 743 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
bogdanm | 0:9b334a45a8ff | 744 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
bogdanm | 0:9b334a45a8ff | 745 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 746 | /* parameter "NbrOfConversion" */ |
bogdanm | 0:9b334a45a8ff | 747 | hadc->Instance->SQR1 &= ~(ADC_SQR1_L); |
bogdanm | 0:9b334a45a8ff | 748 | if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) |
bogdanm | 0:9b334a45a8ff | 749 | { |
bogdanm | 0:9b334a45a8ff | 750 | /* Set number of ranks in regular group sequencer */ |
bogdanm | 0:9b334a45a8ff | 751 | hadc->Instance->SQR1 |= __HAL_ADC_SQR1_L(hadc->Init.NbrOfConversion); |
bogdanm | 0:9b334a45a8ff | 752 | } |
bogdanm | 0:9b334a45a8ff | 753 | |
bogdanm | 0:9b334a45a8ff | 754 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 755 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 756 | |
bogdanm | 0:9b334a45a8ff | 757 | /* Initialize the ADC state */ |
bogdanm | 0:9b334a45a8ff | 758 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 759 | } |
bogdanm | 0:9b334a45a8ff | 760 | |
bogdanm | 0:9b334a45a8ff | 761 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 762 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 763 | } |
bogdanm | 0:9b334a45a8ff | 764 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 765 | |
bogdanm | 0:9b334a45a8ff | 766 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 767 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 768 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 769 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 770 | /** |
bogdanm | 0:9b334a45a8ff | 771 | * @brief Deinitialize the ADC peripheral registers to their default reset |
bogdanm | 0:9b334a45a8ff | 772 | * values, with deinitialization of the ADC MSP. |
bogdanm | 0:9b334a45a8ff | 773 | * @note For devices with several ADCs: reset of ADC common registers is done |
bogdanm | 0:9b334a45a8ff | 774 | * only if all ADCs sharing the same common group are disabled. |
bogdanm | 0:9b334a45a8ff | 775 | * If this is not the case, reset of these common parameters reset is |
bogdanm | 0:9b334a45a8ff | 776 | * bypassed without error reporting: it can be the intended behaviour in |
bogdanm | 0:9b334a45a8ff | 777 | * case of reset of a single ADC while the other ADCs sharing the same |
bogdanm | 0:9b334a45a8ff | 778 | * common group is still running. |
bogdanm | 0:9b334a45a8ff | 779 | * @note For devices with several ADCs: Global reset of all ADCs sharing a |
bogdanm | 0:9b334a45a8ff | 780 | * common group is possible. |
bogdanm | 0:9b334a45a8ff | 781 | * As this function is intended to reset a single ADC, to not impact |
bogdanm | 0:9b334a45a8ff | 782 | * other ADCs, instructions for global reset of multiple ADCs have been |
bogdanm | 0:9b334a45a8ff | 783 | * let commented below. |
bogdanm | 0:9b334a45a8ff | 784 | * If needed, the example code can be copied and uncommented into |
bogdanm | 0:9b334a45a8ff | 785 | * function HAL_ADC_MspDeInit(). |
bogdanm | 0:9b334a45a8ff | 786 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 787 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 788 | */ |
bogdanm | 0:9b334a45a8ff | 789 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 790 | { |
bogdanm | 0:9b334a45a8ff | 791 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 792 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 793 | ADC_HandleTypeDef tmphadcSharingSameCommonRegister; |
bogdanm | 0:9b334a45a8ff | 794 | |
bogdanm | 0:9b334a45a8ff | 795 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 796 | if(hadc == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 797 | { |
bogdanm | 0:9b334a45a8ff | 798 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 799 | } |
bogdanm | 0:9b334a45a8ff | 800 | |
bogdanm | 0:9b334a45a8ff | 801 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 802 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 803 | |
bogdanm | 0:9b334a45a8ff | 804 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 805 | hadc->State = HAL_ADC_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 806 | |
bogdanm | 0:9b334a45a8ff | 807 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 808 | tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 809 | |
bogdanm | 0:9b334a45a8ff | 810 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 811 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 812 | { |
bogdanm | 0:9b334a45a8ff | 813 | /* Flush register JSQR: queue sequencer reset when injected queue */ |
bogdanm | 0:9b334a45a8ff | 814 | /* sequencer is enabled and ADC disabled */ |
bogdanm | 0:9b334a45a8ff | 815 | /* Enable injected queue sequencer after injected conversion stop */ |
bogdanm | 0:9b334a45a8ff | 816 | hadc->Instance->CFGR |= ADC_CFGR_JQM; |
bogdanm | 0:9b334a45a8ff | 817 | |
bogdanm | 0:9b334a45a8ff | 818 | /* Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 819 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 820 | |
bogdanm | 0:9b334a45a8ff | 821 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 822 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 823 | { |
bogdanm | 0:9b334a45a8ff | 824 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 825 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 826 | } |
bogdanm | 0:9b334a45a8ff | 827 | else |
bogdanm | 0:9b334a45a8ff | 828 | { |
bogdanm | 0:9b334a45a8ff | 829 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 830 | } |
bogdanm | 0:9b334a45a8ff | 831 | } |
bogdanm | 0:9b334a45a8ff | 832 | |
bogdanm | 0:9b334a45a8ff | 833 | |
bogdanm | 0:9b334a45a8ff | 834 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 835 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 836 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 837 | { |
bogdanm | 0:9b334a45a8ff | 838 | |
bogdanm | 0:9b334a45a8ff | 839 | /* ========== Reset ADC registers ========== */ |
bogdanm | 0:9b334a45a8ff | 840 | /* Reset register IER */ |
bogdanm | 0:9b334a45a8ff | 841 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | |
bogdanm | 0:9b334a45a8ff | 842 | ADC_IT_JQOVF | ADC_IT_OVR | |
bogdanm | 0:9b334a45a8ff | 843 | ADC_IT_JEOS | ADC_IT_JEOC | |
bogdanm | 0:9b334a45a8ff | 844 | ADC_IT_EOS | ADC_IT_EOC | |
bogdanm | 0:9b334a45a8ff | 845 | ADC_IT_EOSMP | ADC_IT_RDY ) ); |
bogdanm | 0:9b334a45a8ff | 846 | |
bogdanm | 0:9b334a45a8ff | 847 | /* Reset register ISR */ |
bogdanm | 0:9b334a45a8ff | 848 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | |
bogdanm | 0:9b334a45a8ff | 849 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | |
bogdanm | 0:9b334a45a8ff | 850 | ADC_FLAG_JEOS | ADC_FLAG_JEOC | |
bogdanm | 0:9b334a45a8ff | 851 | ADC_FLAG_EOS | ADC_FLAG_EOC | |
bogdanm | 0:9b334a45a8ff | 852 | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); |
bogdanm | 0:9b334a45a8ff | 853 | |
bogdanm | 0:9b334a45a8ff | 854 | /* Reset register CR */ |
bogdanm | 0:9b334a45a8ff | 855 | /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */ |
bogdanm | 0:9b334a45a8ff | 856 | /* in access mode "read-set": no direct reset applicable. */ |
bogdanm | 0:9b334a45a8ff | 857 | /* Reset Calibration mode to default setting (single ended): */ |
bogdanm | 0:9b334a45a8ff | 858 | /* Disable voltage regulator: */ |
bogdanm | 0:9b334a45a8ff | 859 | /* Note: Voltage regulator disable is conditioned to ADC state disabled: */ |
bogdanm | 0:9b334a45a8ff | 860 | /* already done above. */ |
bogdanm | 0:9b334a45a8ff | 861 | /* Note: Voltage regulator disable is intended for power saving. */ |
bogdanm | 0:9b334a45a8ff | 862 | /* Sequence to disable voltage regulator: */ |
bogdanm | 0:9b334a45a8ff | 863 | /* 1. Set the intermediate state before moving the ADC voltage regulator */ |
bogdanm | 0:9b334a45a8ff | 864 | /* to disable state. */ |
bogdanm | 0:9b334a45a8ff | 865 | hadc->Instance->CR &= ~(ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); |
bogdanm | 0:9b334a45a8ff | 866 | /* 2. Set ADVREGEN bits to 0x10 */ |
bogdanm | 0:9b334a45a8ff | 867 | hadc->Instance->CR |= ADC_CR_ADVREGEN_1; |
bogdanm | 0:9b334a45a8ff | 868 | |
bogdanm | 0:9b334a45a8ff | 869 | /* Reset register CFGR */ |
bogdanm | 0:9b334a45a8ff | 870 | hadc->Instance->CFGR &= ~(ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | |
bogdanm | 0:9b334a45a8ff | 871 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | |
bogdanm | 0:9b334a45a8ff | 872 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | |
bogdanm | 0:9b334a45a8ff | 873 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | |
bogdanm | 0:9b334a45a8ff | 874 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | |
bogdanm | 0:9b334a45a8ff | 875 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ); |
bogdanm | 0:9b334a45a8ff | 876 | |
bogdanm | 0:9b334a45a8ff | 877 | /* Reset register SMPR1 */ |
bogdanm | 0:9b334a45a8ff | 878 | hadc->Instance->SMPR1 &= ~(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | |
bogdanm | 0:9b334a45a8ff | 879 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | |
bogdanm | 0:9b334a45a8ff | 880 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 ); |
bogdanm | 0:9b334a45a8ff | 881 | |
bogdanm | 0:9b334a45a8ff | 882 | /* Reset register SMPR2 */ |
bogdanm | 0:9b334a45a8ff | 883 | hadc->Instance->SMPR2 &= ~(ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | |
bogdanm | 0:9b334a45a8ff | 884 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | |
bogdanm | 0:9b334a45a8ff | 885 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); |
bogdanm | 0:9b334a45a8ff | 886 | |
bogdanm | 0:9b334a45a8ff | 887 | /* Reset register TR1 */ |
bogdanm | 0:9b334a45a8ff | 888 | hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1); |
bogdanm | 0:9b334a45a8ff | 889 | |
bogdanm | 0:9b334a45a8ff | 890 | /* Reset register TR2 */ |
bogdanm | 0:9b334a45a8ff | 891 | hadc->Instance->TR2 &= ~(ADC_TR2_HT2 | ADC_TR2_LT2); |
bogdanm | 0:9b334a45a8ff | 892 | |
bogdanm | 0:9b334a45a8ff | 893 | /* Reset register TR3 */ |
bogdanm | 0:9b334a45a8ff | 894 | hadc->Instance->TR3 &= ~(ADC_TR3_HT3 | ADC_TR3_LT3); |
bogdanm | 0:9b334a45a8ff | 895 | |
bogdanm | 0:9b334a45a8ff | 896 | /* Reset register SQR1 */ |
bogdanm | 0:9b334a45a8ff | 897 | hadc->Instance->SQR1 &= ~(ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | |
bogdanm | 0:9b334a45a8ff | 898 | ADC_SQR1_SQ1 | ADC_SQR1_L); |
bogdanm | 0:9b334a45a8ff | 899 | |
bogdanm | 0:9b334a45a8ff | 900 | /* Reset register SQR2 */ |
bogdanm | 0:9b334a45a8ff | 901 | hadc->Instance->SQR2 &= ~(ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | |
bogdanm | 0:9b334a45a8ff | 902 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5); |
bogdanm | 0:9b334a45a8ff | 903 | |
bogdanm | 0:9b334a45a8ff | 904 | /* Reset register SQR3 */ |
bogdanm | 0:9b334a45a8ff | 905 | hadc->Instance->SQR3 &= ~(ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | |
bogdanm | 0:9b334a45a8ff | 906 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10); |
bogdanm | 0:9b334a45a8ff | 907 | |
bogdanm | 0:9b334a45a8ff | 908 | /* Reset register SQR4 */ |
bogdanm | 0:9b334a45a8ff | 909 | hadc->Instance->SQR4 &= ~(ADC_SQR4_SQ16 | ADC_SQR4_SQ15); |
bogdanm | 0:9b334a45a8ff | 910 | |
bogdanm | 0:9b334a45a8ff | 911 | /* Reset register DR */ |
bogdanm | 0:9b334a45a8ff | 912 | /* bits in access mode read only, no direct reset applicable*/ |
bogdanm | 0:9b334a45a8ff | 913 | |
bogdanm | 0:9b334a45a8ff | 914 | /* Reset register OFR1 */ |
bogdanm | 0:9b334a45a8ff | 915 | hadc->Instance->OFR1 &= ~(ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); |
bogdanm | 0:9b334a45a8ff | 916 | /* Reset register OFR2 */ |
bogdanm | 0:9b334a45a8ff | 917 | hadc->Instance->OFR2 &= ~(ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); |
bogdanm | 0:9b334a45a8ff | 918 | /* Reset register OFR3 */ |
bogdanm | 0:9b334a45a8ff | 919 | hadc->Instance->OFR3 &= ~(ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); |
bogdanm | 0:9b334a45a8ff | 920 | /* Reset register OFR4 */ |
bogdanm | 0:9b334a45a8ff | 921 | hadc->Instance->OFR4 &= ~(ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); |
bogdanm | 0:9b334a45a8ff | 922 | |
bogdanm | 0:9b334a45a8ff | 923 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
bogdanm | 0:9b334a45a8ff | 924 | /* bits in access mode read only, no direct reset applicable*/ |
bogdanm | 0:9b334a45a8ff | 925 | |
bogdanm | 0:9b334a45a8ff | 926 | /* Reset register AWD2CR */ |
bogdanm | 0:9b334a45a8ff | 927 | hadc->Instance->AWD2CR &= ~(ADC_AWD2CR_AWD2CH); |
bogdanm | 0:9b334a45a8ff | 928 | |
bogdanm | 0:9b334a45a8ff | 929 | /* Reset register AWD3CR */ |
bogdanm | 0:9b334a45a8ff | 930 | hadc->Instance->AWD3CR &= ~(ADC_AWD3CR_AWD3CH); |
bogdanm | 0:9b334a45a8ff | 931 | |
bogdanm | 0:9b334a45a8ff | 932 | /* Reset register DIFSEL */ |
bogdanm | 0:9b334a45a8ff | 933 | hadc->Instance->DIFSEL &= ~(ADC_DIFSEL_DIFSEL); |
bogdanm | 0:9b334a45a8ff | 934 | |
bogdanm | 0:9b334a45a8ff | 935 | /* Reset register CALFACT */ |
bogdanm | 0:9b334a45a8ff | 936 | hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); |
bogdanm | 0:9b334a45a8ff | 937 | |
bogdanm | 0:9b334a45a8ff | 938 | |
bogdanm | 0:9b334a45a8ff | 939 | |
bogdanm | 0:9b334a45a8ff | 940 | |
bogdanm | 0:9b334a45a8ff | 941 | |
bogdanm | 0:9b334a45a8ff | 942 | |
bogdanm | 0:9b334a45a8ff | 943 | /* ========== Reset common ADC registers ========== */ |
bogdanm | 0:9b334a45a8ff | 944 | |
bogdanm | 0:9b334a45a8ff | 945 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 946 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 947 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 948 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 949 | |
bogdanm | 0:9b334a45a8ff | 950 | /* Set handle of the other ADC sharing the same common register */ |
bogdanm | 0:9b334a45a8ff | 951 | __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); |
bogdanm | 0:9b334a45a8ff | 952 | |
bogdanm | 0:9b334a45a8ff | 953 | /* Software is allowed to change common parameters only when all ADCs of */ |
bogdanm | 0:9b334a45a8ff | 954 | /* the common group are disabled. */ |
bogdanm | 0:9b334a45a8ff | 955 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 956 | ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) || |
bogdanm | 0:9b334a45a8ff | 957 | (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) )) |
bogdanm | 0:9b334a45a8ff | 958 | { |
bogdanm | 0:9b334a45a8ff | 959 | /* Reset configuration of ADC common register CCR: |
bogdanm | 0:9b334a45a8ff | 960 | - clock mode: CKMODE |
bogdanm | 0:9b334a45a8ff | 961 | - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into |
bogdanm | 0:9b334a45a8ff | 962 | HAL_ADCEx_MultiModeConfigChannel() ) |
bogdanm | 0:9b334a45a8ff | 963 | - internal measurement paths: Vbat, temperature sensor, Vref (set into |
bogdanm | 0:9b334a45a8ff | 964 | HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) |
bogdanm | 0:9b334a45a8ff | 965 | */ |
bogdanm | 0:9b334a45a8ff | 966 | tmpADC_Common->CCR &= ~( ADC_CCR_CKMODE | |
bogdanm | 0:9b334a45a8ff | 967 | ADC_CCR_VBATEN | |
bogdanm | 0:9b334a45a8ff | 968 | ADC_CCR_TSEN | |
bogdanm | 0:9b334a45a8ff | 969 | ADC_CCR_VREFEN | |
bogdanm | 0:9b334a45a8ff | 970 | ADC_CCR_DMACFG | |
bogdanm | 0:9b334a45a8ff | 971 | ADC_CCR_DMACFG | |
bogdanm | 0:9b334a45a8ff | 972 | ADC_CCR_DELAY | |
bogdanm | 0:9b334a45a8ff | 973 | ADC_CCR_MULTI ); |
bogdanm | 0:9b334a45a8ff | 974 | |
bogdanm | 0:9b334a45a8ff | 975 | /* Other ADC common registers (CSR, CDR) are in access mode read only, |
bogdanm | 0:9b334a45a8ff | 976 | no direct reset applicable */ |
bogdanm | 0:9b334a45a8ff | 977 | } |
bogdanm | 0:9b334a45a8ff | 978 | |
bogdanm | 0:9b334a45a8ff | 979 | |
bogdanm | 0:9b334a45a8ff | 980 | /* ========== Hard reset of ADC peripheral ========== */ |
bogdanm | 0:9b334a45a8ff | 981 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
bogdanm | 0:9b334a45a8ff | 982 | /* forced to a similar state after device power-on. */ |
bogdanm | 0:9b334a45a8ff | 983 | /* Caution: */ |
bogdanm | 0:9b334a45a8ff | 984 | /* These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4 */ |
bogdanm | 0:9b334a45a8ff | 985 | /* if available (ADC2, ADC3, ADC4 availability depends on STM32 product) */ |
bogdanm | 0:9b334a45a8ff | 986 | /* As this function is intended to reset a single ADC, instructions for */ |
bogdanm | 0:9b334a45a8ff | 987 | /* global reset of multiple ADC have been let commented below. */ |
bogdanm | 0:9b334a45a8ff | 988 | /* */ |
bogdanm | 0:9b334a45a8ff | 989 | /* If global reset of common ADC is corresponding to the current */ |
bogdanm | 0:9b334a45a8ff | 990 | /* application, copy-paste and uncomment the following reset code into */ |
bogdanm | 0:9b334a45a8ff | 991 | /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)": */ |
bogdanm | 0:9b334a45a8ff | 992 | /* */ |
bogdanm | 0:9b334a45a8ff | 993 | /* ADC clock reset */ |
bogdanm | 0:9b334a45a8ff | 994 | /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */ |
bogdanm | 0:9b334a45a8ff | 995 | /* { */ |
bogdanm | 0:9b334a45a8ff | 996 | /* __ADC12_FORCE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 997 | /* __ADC12_RELEASE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 998 | /* } */ |
bogdanm | 0:9b334a45a8ff | 999 | /* else */ |
bogdanm | 0:9b334a45a8ff | 1000 | /* { */ |
bogdanm | 0:9b334a45a8ff | 1001 | /* __ADC34_FORCE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 1002 | /* __ADC34_RELEASE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 1003 | /* } */ |
bogdanm | 0:9b334a45a8ff | 1004 | /* */ |
bogdanm | 0:9b334a45a8ff | 1005 | /* ADC clock disable of both possible clock sources: AHB clock and */ |
bogdanm | 0:9b334a45a8ff | 1006 | /* PLL clock. */ |
bogdanm | 0:9b334a45a8ff | 1007 | /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */ |
bogdanm | 0:9b334a45a8ff | 1008 | /* { */ |
bogdanm | 0:9b334a45a8ff | 1009 | /* __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_OFF); */ |
bogdanm | 0:9b334a45a8ff | 1010 | /* __ADC12_CLK_DISABLE(); */ |
bogdanm | 0:9b334a45a8ff | 1011 | /* } */ |
bogdanm | 0:9b334a45a8ff | 1012 | /* else */ |
bogdanm | 0:9b334a45a8ff | 1013 | /* { */ |
bogdanm | 0:9b334a45a8ff | 1014 | /* __HAL_RCC_ADC34_CONFIG(RCC_ADC12PLLCLK_OFF); */ |
bogdanm | 0:9b334a45a8ff | 1015 | /* __ADC34_CLK_DISABLE(); */ |
bogdanm | 0:9b334a45a8ff | 1016 | /* } */ |
bogdanm | 0:9b334a45a8ff | 1017 | |
bogdanm | 0:9b334a45a8ff | 1018 | /* DeInit the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 1019 | HAL_ADC_MspDeInit(hadc); |
bogdanm | 0:9b334a45a8ff | 1020 | |
bogdanm | 0:9b334a45a8ff | 1021 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1022 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1023 | |
bogdanm | 0:9b334a45a8ff | 1024 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1025 | hadc->State = HAL_ADC_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 1026 | } |
bogdanm | 0:9b334a45a8ff | 1027 | |
bogdanm | 0:9b334a45a8ff | 1028 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1029 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1030 | |
bogdanm | 0:9b334a45a8ff | 1031 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1032 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1033 | } |
bogdanm | 0:9b334a45a8ff | 1034 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1035 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1036 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1037 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1038 | |
bogdanm | 0:9b334a45a8ff | 1039 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1040 | /** |
bogdanm | 0:9b334a45a8ff | 1041 | * @brief Deinitialize the ADC peripheral registers to its default reset values. |
bogdanm | 0:9b334a45a8ff | 1042 | * @note To not impact other ADCs, reset of common ADC registers have been |
bogdanm | 0:9b334a45a8ff | 1043 | * left commented below. |
bogdanm | 0:9b334a45a8ff | 1044 | * If needed, the example code can be copied and uncommented into |
bogdanm | 0:9b334a45a8ff | 1045 | * function HAL_ADC_MspDeInit(). |
bogdanm | 0:9b334a45a8ff | 1046 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1047 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1048 | */ |
bogdanm | 0:9b334a45a8ff | 1049 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1050 | { |
bogdanm | 0:9b334a45a8ff | 1051 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1052 | |
bogdanm | 0:9b334a45a8ff | 1053 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 1054 | if(hadc == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 1055 | { |
bogdanm | 0:9b334a45a8ff | 1056 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1057 | } |
bogdanm | 0:9b334a45a8ff | 1058 | |
bogdanm | 0:9b334a45a8ff | 1059 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1060 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1061 | |
bogdanm | 0:9b334a45a8ff | 1062 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1063 | hadc->State = HAL_ADC_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 1064 | |
bogdanm | 0:9b334a45a8ff | 1065 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 1066 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1067 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1068 | |
bogdanm | 0:9b334a45a8ff | 1069 | |
bogdanm | 0:9b334a45a8ff | 1070 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 1071 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 1072 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1073 | { |
bogdanm | 0:9b334a45a8ff | 1074 | /* ========== Reset ADC registers ========== */ |
bogdanm | 0:9b334a45a8ff | 1075 | /* Reset register SR */ |
bogdanm | 0:9b334a45a8ff | 1076 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
bogdanm | 0:9b334a45a8ff | 1077 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
bogdanm | 0:9b334a45a8ff | 1078 | |
bogdanm | 0:9b334a45a8ff | 1079 | /* Reset register CR1 */ |
bogdanm | 0:9b334a45a8ff | 1080 | hadc->Instance->CR1 &= ~(ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | |
bogdanm | 0:9b334a45a8ff | 1081 | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | |
bogdanm | 0:9b334a45a8ff | 1082 | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | |
bogdanm | 0:9b334a45a8ff | 1083 | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH); |
bogdanm | 0:9b334a45a8ff | 1084 | |
bogdanm | 0:9b334a45a8ff | 1085 | /* Reset register CR2 */ |
bogdanm | 0:9b334a45a8ff | 1086 | hadc->Instance->CR2 &= ~(ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
bogdanm | 0:9b334a45a8ff | 1087 | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | |
bogdanm | 0:9b334a45a8ff | 1088 | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | |
bogdanm | 0:9b334a45a8ff | 1089 | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | |
bogdanm | 0:9b334a45a8ff | 1090 | ADC_CR2_ADON ); |
bogdanm | 0:9b334a45a8ff | 1091 | |
bogdanm | 0:9b334a45a8ff | 1092 | /* Reset register SMPR1 */ |
bogdanm | 0:9b334a45a8ff | 1093 | hadc->Instance->SMPR1 &= ~(ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | |
bogdanm | 0:9b334a45a8ff | 1094 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | |
bogdanm | 0:9b334a45a8ff | 1095 | ADC_SMPR1_SMP11 |ADC_SMPR1_SMP10); |
bogdanm | 0:9b334a45a8ff | 1096 | |
bogdanm | 0:9b334a45a8ff | 1097 | /* Reset register SMPR2 */ |
bogdanm | 0:9b334a45a8ff | 1098 | hadc->Instance->SMPR2 &= ~(ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | |
bogdanm | 0:9b334a45a8ff | 1099 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | |
bogdanm | 0:9b334a45a8ff | 1100 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | |
bogdanm | 0:9b334a45a8ff | 1101 | ADC_SMPR2_SMP0); |
bogdanm | 0:9b334a45a8ff | 1102 | |
bogdanm | 0:9b334a45a8ff | 1103 | /* Reset register JOFR1 */ |
bogdanm | 0:9b334a45a8ff | 1104 | hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); |
bogdanm | 0:9b334a45a8ff | 1105 | /* Reset register JOFR2 */ |
bogdanm | 0:9b334a45a8ff | 1106 | hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); |
bogdanm | 0:9b334a45a8ff | 1107 | /* Reset register JOFR3 */ |
bogdanm | 0:9b334a45a8ff | 1108 | hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); |
bogdanm | 0:9b334a45a8ff | 1109 | /* Reset register JOFR4 */ |
bogdanm | 0:9b334a45a8ff | 1110 | hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); |
bogdanm | 0:9b334a45a8ff | 1111 | |
bogdanm | 0:9b334a45a8ff | 1112 | /* Reset register HTR */ |
bogdanm | 0:9b334a45a8ff | 1113 | hadc->Instance->HTR &= ~(ADC_HTR_HT); |
bogdanm | 0:9b334a45a8ff | 1114 | /* Reset register LTR */ |
bogdanm | 0:9b334a45a8ff | 1115 | hadc->Instance->LTR &= ~(ADC_LTR_LT); |
bogdanm | 0:9b334a45a8ff | 1116 | |
bogdanm | 0:9b334a45a8ff | 1117 | /* Reset register SQR1 */ |
bogdanm | 0:9b334a45a8ff | 1118 | hadc->Instance->SQR1 &= ~(ADC_SQR1_L | |
bogdanm | 0:9b334a45a8ff | 1119 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
bogdanm | 0:9b334a45a8ff | 1120 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
bogdanm | 0:9b334a45a8ff | 1121 | |
bogdanm | 0:9b334a45a8ff | 1122 | /* Reset register SQR1 */ |
bogdanm | 0:9b334a45a8ff | 1123 | hadc->Instance->SQR1 &= ~(ADC_SQR1_L | |
bogdanm | 0:9b334a45a8ff | 1124 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
bogdanm | 0:9b334a45a8ff | 1125 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
bogdanm | 0:9b334a45a8ff | 1126 | |
bogdanm | 0:9b334a45a8ff | 1127 | /* Reset register SQR2 */ |
bogdanm | 0:9b334a45a8ff | 1128 | hadc->Instance->SQR2 &= ~(ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | |
bogdanm | 0:9b334a45a8ff | 1129 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); |
bogdanm | 0:9b334a45a8ff | 1130 | |
bogdanm | 0:9b334a45a8ff | 1131 | /* Reset register SQR3 */ |
bogdanm | 0:9b334a45a8ff | 1132 | hadc->Instance->SQR3 &= ~(ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | |
bogdanm | 0:9b334a45a8ff | 1133 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); |
bogdanm | 0:9b334a45a8ff | 1134 | |
bogdanm | 0:9b334a45a8ff | 1135 | /* Reset register JSQR */ |
bogdanm | 0:9b334a45a8ff | 1136 | hadc->Instance->JSQR &= ~(ADC_JSQR_JL | |
bogdanm | 0:9b334a45a8ff | 1137 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
bogdanm | 0:9b334a45a8ff | 1138 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
bogdanm | 0:9b334a45a8ff | 1139 | |
bogdanm | 0:9b334a45a8ff | 1140 | /* Reset register JSQR */ |
bogdanm | 0:9b334a45a8ff | 1141 | hadc->Instance->JSQR &= ~(ADC_JSQR_JL | |
bogdanm | 0:9b334a45a8ff | 1142 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
bogdanm | 0:9b334a45a8ff | 1143 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
bogdanm | 0:9b334a45a8ff | 1144 | |
bogdanm | 0:9b334a45a8ff | 1145 | /* Reset register DR */ |
bogdanm | 0:9b334a45a8ff | 1146 | /* bits in access mode read only, no direct reset applicable*/ |
bogdanm | 0:9b334a45a8ff | 1147 | |
bogdanm | 0:9b334a45a8ff | 1148 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
bogdanm | 0:9b334a45a8ff | 1149 | /* bits in access mode read only, no direct reset applicable*/ |
bogdanm | 0:9b334a45a8ff | 1150 | |
bogdanm | 0:9b334a45a8ff | 1151 | /* Reset VBAT measurement path, in case of enabled before by selecting */ |
bogdanm | 0:9b334a45a8ff | 1152 | /* channel ADC_CHANNEL_VBAT. */ |
bogdanm | 0:9b334a45a8ff | 1153 | SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT); |
bogdanm | 0:9b334a45a8ff | 1154 | |
bogdanm | 0:9b334a45a8ff | 1155 | |
bogdanm | 0:9b334a45a8ff | 1156 | /* ========== Hard reset ADC peripheral ========== */ |
bogdanm | 0:9b334a45a8ff | 1157 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
bogdanm | 0:9b334a45a8ff | 1158 | /* forced to a similar state after device power-on. */ |
bogdanm | 0:9b334a45a8ff | 1159 | /* If needed, copy-paste and uncomment the following reset code into */ |
bogdanm | 0:9b334a45a8ff | 1160 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
bogdanm | 0:9b334a45a8ff | 1161 | /* */ |
bogdanm | 0:9b334a45a8ff | 1162 | /* __ADC1_FORCE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 1163 | /* __ADC1_RELEASE_RESET(); */ |
bogdanm | 0:9b334a45a8ff | 1164 | |
bogdanm | 0:9b334a45a8ff | 1165 | /* DeInit the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 1166 | HAL_ADC_MspDeInit(hadc); |
bogdanm | 0:9b334a45a8ff | 1167 | |
bogdanm | 0:9b334a45a8ff | 1168 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1169 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1170 | |
bogdanm | 0:9b334a45a8ff | 1171 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1172 | hadc->State = HAL_ADC_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 1173 | |
bogdanm | 0:9b334a45a8ff | 1174 | } |
bogdanm | 0:9b334a45a8ff | 1175 | |
bogdanm | 0:9b334a45a8ff | 1176 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1177 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1178 | |
bogdanm | 0:9b334a45a8ff | 1179 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1180 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1181 | } |
bogdanm | 0:9b334a45a8ff | 1182 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1183 | |
bogdanm | 0:9b334a45a8ff | 1184 | /** |
bogdanm | 0:9b334a45a8ff | 1185 | * @} |
bogdanm | 0:9b334a45a8ff | 1186 | */ |
bogdanm | 0:9b334a45a8ff | 1187 | |
bogdanm | 0:9b334a45a8ff | 1188 | /** @defgroup ADCEx_Exported_Functions_Group2 Extended Input and Output operation functions |
bogdanm | 0:9b334a45a8ff | 1189 | * @brief Extended IO operation functions |
bogdanm | 0:9b334a45a8ff | 1190 | * |
bogdanm | 0:9b334a45a8ff | 1191 | @verbatim |
bogdanm | 0:9b334a45a8ff | 1192 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1193 | ##### IO operation functions ##### |
bogdanm | 0:9b334a45a8ff | 1194 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1195 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 1196 | (+) Start conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 1197 | (+) Stop conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 1198 | (+) Poll for conversion complete on regular group. |
bogdanm | 0:9b334a45a8ff | 1199 | (+) Poll for conversion event. |
bogdanm | 0:9b334a45a8ff | 1200 | (+) Get result of regular channel conversion. |
bogdanm | 0:9b334a45a8ff | 1201 | (+) Start conversion of regular group and enable interruptions. |
bogdanm | 0:9b334a45a8ff | 1202 | (+) Stop conversion of regular group and disable interruptions. |
bogdanm | 0:9b334a45a8ff | 1203 | (+) Handle ADC interrupt request |
bogdanm | 0:9b334a45a8ff | 1204 | (+) Start conversion of regular group and enable DMA transfer. |
bogdanm | 0:9b334a45a8ff | 1205 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
bogdanm | 0:9b334a45a8ff | 1206 | |
bogdanm | 0:9b334a45a8ff | 1207 | (+) Start conversion of injected group. |
bogdanm | 0:9b334a45a8ff | 1208 | (+) Stop conversion of injected group. |
bogdanm | 0:9b334a45a8ff | 1209 | (+) Poll for conversion complete on injected group. |
bogdanm | 0:9b334a45a8ff | 1210 | (+) Get result of injected channel conversion. |
bogdanm | 0:9b334a45a8ff | 1211 | (+) Start conversion of injected group and enable interruptions. |
bogdanm | 0:9b334a45a8ff | 1212 | (+) Stop conversion of injected group and disable interruptions. |
bogdanm | 0:9b334a45a8ff | 1213 | |
bogdanm | 0:9b334a45a8ff | 1214 | (+) Start multimode and enable DMA transfer. |
bogdanm | 0:9b334a45a8ff | 1215 | (+) Stop multimode and disable ADC DMA transfer. |
bogdanm | 0:9b334a45a8ff | 1216 | (+) Get result of multimode conversion. |
bogdanm | 0:9b334a45a8ff | 1217 | |
bogdanm | 0:9b334a45a8ff | 1218 | (+) Perform the ADC self-calibration for single or differential ending. |
bogdanm | 0:9b334a45a8ff | 1219 | (+) Get calibration factors for single or differential ending. |
bogdanm | 0:9b334a45a8ff | 1220 | (+) Set calibration factors for single or differential ending. |
bogdanm | 0:9b334a45a8ff | 1221 | |
bogdanm | 0:9b334a45a8ff | 1222 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 1223 | * @{ |
bogdanm | 0:9b334a45a8ff | 1224 | */ |
bogdanm | 0:9b334a45a8ff | 1225 | |
bogdanm | 0:9b334a45a8ff | 1226 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1227 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1228 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1229 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1230 | /** |
bogdanm | 0:9b334a45a8ff | 1231 | * @brief Enables ADC, starts conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 1232 | * Interruptions enabled in this function: None. |
bogdanm | 0:9b334a45a8ff | 1233 | * @note: Case of multimode enabled (for devices with several ADCs): if ADC |
bogdanm | 0:9b334a45a8ff | 1234 | * is slave, ADC is enabled only (conversion is not started). If ADC |
bogdanm | 0:9b334a45a8ff | 1235 | * is master, ADC is enabled and multimode conversion is started. |
bogdanm | 0:9b334a45a8ff | 1236 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1237 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1238 | */ |
bogdanm | 0:9b334a45a8ff | 1239 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1240 | { |
bogdanm | 0:9b334a45a8ff | 1241 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1242 | |
bogdanm | 0:9b334a45a8ff | 1243 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1244 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1245 | |
bogdanm | 0:9b334a45a8ff | 1246 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1247 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1248 | |
bogdanm | 0:9b334a45a8ff | 1249 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1250 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1251 | |
bogdanm | 0:9b334a45a8ff | 1252 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1253 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1254 | { |
bogdanm | 0:9b334a45a8ff | 1255 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 1256 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 1257 | { |
bogdanm | 0:9b334a45a8ff | 1258 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1259 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1260 | } |
bogdanm | 0:9b334a45a8ff | 1261 | else |
bogdanm | 0:9b334a45a8ff | 1262 | { |
bogdanm | 0:9b334a45a8ff | 1263 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1264 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 1265 | } |
bogdanm | 0:9b334a45a8ff | 1266 | |
bogdanm | 0:9b334a45a8ff | 1267 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1268 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1269 | |
bogdanm | 0:9b334a45a8ff | 1270 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1271 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 1272 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 1273 | |
bogdanm | 0:9b334a45a8ff | 1274 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 1275 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 1276 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1277 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1278 | /* Case of multimode enabled (for devices with several ADCs): if ADC is */ |
bogdanm | 0:9b334a45a8ff | 1279 | /* slave, ADC is enabled only (conversion is not started). If ADC is */ |
bogdanm | 0:9b334a45a8ff | 1280 | /* master, ADC is enabled and conversion is started. */ |
bogdanm | 0:9b334a45a8ff | 1281 | if (__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
bogdanm | 0:9b334a45a8ff | 1282 | { |
bogdanm | 0:9b334a45a8ff | 1283 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 1284 | } |
bogdanm | 0:9b334a45a8ff | 1285 | } |
bogdanm | 0:9b334a45a8ff | 1286 | |
bogdanm | 0:9b334a45a8ff | 1287 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1288 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1289 | |
bogdanm | 0:9b334a45a8ff | 1290 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1291 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1292 | } |
bogdanm | 0:9b334a45a8ff | 1293 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1294 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1295 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1296 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1297 | |
bogdanm | 0:9b334a45a8ff | 1298 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1299 | /** |
bogdanm | 0:9b334a45a8ff | 1300 | * @brief Enables ADC, starts conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 1301 | * Interruptions enabled in this function: None. |
bogdanm | 0:9b334a45a8ff | 1302 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1303 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1304 | */ |
bogdanm | 0:9b334a45a8ff | 1305 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1306 | { |
bogdanm | 0:9b334a45a8ff | 1307 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1308 | |
bogdanm | 0:9b334a45a8ff | 1309 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1310 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1311 | |
bogdanm | 0:9b334a45a8ff | 1312 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1313 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1314 | |
bogdanm | 0:9b334a45a8ff | 1315 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1316 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1317 | |
bogdanm | 0:9b334a45a8ff | 1318 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1319 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1320 | { |
bogdanm | 0:9b334a45a8ff | 1321 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 1322 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 1323 | { |
bogdanm | 0:9b334a45a8ff | 1324 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1325 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1326 | } |
bogdanm | 0:9b334a45a8ff | 1327 | else |
bogdanm | 0:9b334a45a8ff | 1328 | { |
bogdanm | 0:9b334a45a8ff | 1329 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1330 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 1331 | } |
bogdanm | 0:9b334a45a8ff | 1332 | |
bogdanm | 0:9b334a45a8ff | 1333 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1334 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1335 | |
bogdanm | 0:9b334a45a8ff | 1336 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1337 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 1338 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 1339 | |
bogdanm | 0:9b334a45a8ff | 1340 | /* Start conversion of regular group if software start has been selected. */ |
bogdanm | 0:9b334a45a8ff | 1341 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1342 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1343 | /* Note: Alternate trigger for single conversion could be to force an */ |
bogdanm | 0:9b334a45a8ff | 1344 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
bogdanm | 0:9b334a45a8ff | 1345 | if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
bogdanm | 0:9b334a45a8ff | 1346 | { |
bogdanm | 0:9b334a45a8ff | 1347 | /* Start ADC conversion on regular group */ |
bogdanm | 0:9b334a45a8ff | 1348 | hadc->Instance->CR2 |= ADC_CR2_SWSTART; |
bogdanm | 0:9b334a45a8ff | 1349 | } |
bogdanm | 0:9b334a45a8ff | 1350 | } |
bogdanm | 0:9b334a45a8ff | 1351 | |
bogdanm | 0:9b334a45a8ff | 1352 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1353 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1354 | |
bogdanm | 0:9b334a45a8ff | 1355 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1356 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1357 | } |
bogdanm | 0:9b334a45a8ff | 1358 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1359 | |
bogdanm | 0:9b334a45a8ff | 1360 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1361 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1362 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1363 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1364 | /** |
bogdanm | 0:9b334a45a8ff | 1365 | * @brief Stop ADC conversion of regular group (and injected group in |
bogdanm | 0:9b334a45a8ff | 1366 | * case of auto_injection mode), disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 1367 | * @note: ADC peripheral disable is forcing interruption of potential |
bogdanm | 0:9b334a45a8ff | 1368 | * conversion on injected group. If injected group is under use, it |
bogdanm | 0:9b334a45a8ff | 1369 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
bogdanm | 0:9b334a45a8ff | 1370 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1371 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1372 | */ |
bogdanm | 0:9b334a45a8ff | 1373 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1374 | { |
bogdanm | 0:9b334a45a8ff | 1375 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1376 | |
bogdanm | 0:9b334a45a8ff | 1377 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1378 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1379 | |
bogdanm | 0:9b334a45a8ff | 1380 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1381 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1382 | |
bogdanm | 0:9b334a45a8ff | 1383 | /* 1. Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 1384 | tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 1385 | |
bogdanm | 0:9b334a45a8ff | 1386 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 1387 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1388 | { |
bogdanm | 0:9b334a45a8ff | 1389 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1390 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1391 | |
bogdanm | 0:9b334a45a8ff | 1392 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1393 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1394 | { |
bogdanm | 0:9b334a45a8ff | 1395 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1396 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1397 | } |
bogdanm | 0:9b334a45a8ff | 1398 | } |
bogdanm | 0:9b334a45a8ff | 1399 | |
bogdanm | 0:9b334a45a8ff | 1400 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1401 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1402 | |
bogdanm | 0:9b334a45a8ff | 1403 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1404 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1405 | } |
bogdanm | 0:9b334a45a8ff | 1406 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1407 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1408 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1409 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1410 | |
bogdanm | 0:9b334a45a8ff | 1411 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1412 | /** |
bogdanm | 0:9b334a45a8ff | 1413 | * @brief Stop ADC conversion of regular group (and injected channels in |
bogdanm | 0:9b334a45a8ff | 1414 | * case of auto_injection mode), disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 1415 | * @note: ADC peripheral disable is forcing interruption of potential |
bogdanm | 0:9b334a45a8ff | 1416 | * conversion on injected group. If injected group is under use, it |
bogdanm | 0:9b334a45a8ff | 1417 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
bogdanm | 0:9b334a45a8ff | 1418 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1419 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1420 | */ |
bogdanm | 0:9b334a45a8ff | 1421 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1422 | { |
bogdanm | 0:9b334a45a8ff | 1423 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1424 | |
bogdanm | 0:9b334a45a8ff | 1425 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1426 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1427 | |
bogdanm | 0:9b334a45a8ff | 1428 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1429 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1430 | |
bogdanm | 0:9b334a45a8ff | 1431 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 1432 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1433 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1434 | |
bogdanm | 0:9b334a45a8ff | 1435 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1436 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1437 | { |
bogdanm | 0:9b334a45a8ff | 1438 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1439 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1440 | } |
bogdanm | 0:9b334a45a8ff | 1441 | |
bogdanm | 0:9b334a45a8ff | 1442 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1443 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1444 | |
bogdanm | 0:9b334a45a8ff | 1445 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1446 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1447 | } |
bogdanm | 0:9b334a45a8ff | 1448 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1449 | |
bogdanm | 0:9b334a45a8ff | 1450 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1451 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1452 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1453 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1454 | /** |
bogdanm | 0:9b334a45a8ff | 1455 | * @brief Wait for regular group conversion to be completed. |
bogdanm | 0:9b334a45a8ff | 1456 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1457 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 1458 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1459 | */ |
bogdanm | 0:9b334a45a8ff | 1460 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1461 | { |
bogdanm | 0:9b334a45a8ff | 1462 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 1463 | uint32_t tmp_Flag_EOC; |
bogdanm | 0:9b334a45a8ff | 1464 | |
bogdanm | 0:9b334a45a8ff | 1465 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1466 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1467 | |
bogdanm | 0:9b334a45a8ff | 1468 | /* If end of conversion selected to end of sequence */ |
bogdanm | 0:9b334a45a8ff | 1469 | if (hadc->Init.EOCSelection == EOC_SEQ_CONV) |
bogdanm | 0:9b334a45a8ff | 1470 | { |
bogdanm | 0:9b334a45a8ff | 1471 | tmp_Flag_EOC = ADC_FLAG_EOS; |
bogdanm | 0:9b334a45a8ff | 1472 | } |
bogdanm | 0:9b334a45a8ff | 1473 | /* If end of conversion selected to end of each conversion */ |
bogdanm | 0:9b334a45a8ff | 1474 | else /* EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 1475 | { |
bogdanm | 0:9b334a45a8ff | 1476 | tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); |
bogdanm | 0:9b334a45a8ff | 1477 | } |
bogdanm | 0:9b334a45a8ff | 1478 | |
bogdanm | 0:9b334a45a8ff | 1479 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 1480 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1481 | |
bogdanm | 0:9b334a45a8ff | 1482 | /* Wait until End of Conversion flag is raised */ |
bogdanm | 0:9b334a45a8ff | 1483 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
bogdanm | 0:9b334a45a8ff | 1484 | { |
bogdanm | 0:9b334a45a8ff | 1485 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 1486 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1487 | { |
bogdanm | 0:9b334a45a8ff | 1488 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1489 | { |
bogdanm | 0:9b334a45a8ff | 1490 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 1491 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1492 | |
bogdanm | 0:9b334a45a8ff | 1493 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1494 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1495 | |
bogdanm | 0:9b334a45a8ff | 1496 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1497 | } |
bogdanm | 0:9b334a45a8ff | 1498 | } |
bogdanm | 0:9b334a45a8ff | 1499 | } |
bogdanm | 0:9b334a45a8ff | 1500 | |
bogdanm | 0:9b334a45a8ff | 1501 | /* Clear end of conversion flag of regular group if low power feature */ |
bogdanm | 0:9b334a45a8ff | 1502 | /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ |
bogdanm | 0:9b334a45a8ff | 1503 | /* until data register is read using function HAL_ADC_GetValue(). */ |
bogdanm | 0:9b334a45a8ff | 1504 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
bogdanm | 0:9b334a45a8ff | 1505 | { |
bogdanm | 0:9b334a45a8ff | 1506 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 1507 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
bogdanm | 0:9b334a45a8ff | 1508 | } |
bogdanm | 0:9b334a45a8ff | 1509 | |
bogdanm | 0:9b334a45a8ff | 1510 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 1511 | if(hadc->State != HAL_ADC_STATE_ERROR) |
bogdanm | 0:9b334a45a8ff | 1512 | { |
bogdanm | 0:9b334a45a8ff | 1513 | /* Update ADC state machine */ |
bogdanm | 0:9b334a45a8ff | 1514 | if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) |
bogdanm | 0:9b334a45a8ff | 1515 | { |
bogdanm | 0:9b334a45a8ff | 1516 | /* Check if a conversion is ready on injected group */ |
bogdanm | 0:9b334a45a8ff | 1517 | if(hadc->State == HAL_ADC_STATE_EOC_INJ) |
bogdanm | 0:9b334a45a8ff | 1518 | { |
bogdanm | 0:9b334a45a8ff | 1519 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1520 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1521 | } |
bogdanm | 0:9b334a45a8ff | 1522 | else |
bogdanm | 0:9b334a45a8ff | 1523 | { |
bogdanm | 0:9b334a45a8ff | 1524 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1525 | hadc->State = HAL_ADC_STATE_EOC_REG; |
bogdanm | 0:9b334a45a8ff | 1526 | } |
bogdanm | 0:9b334a45a8ff | 1527 | } |
bogdanm | 0:9b334a45a8ff | 1528 | } |
bogdanm | 0:9b334a45a8ff | 1529 | |
bogdanm | 0:9b334a45a8ff | 1530 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1531 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1532 | } |
bogdanm | 0:9b334a45a8ff | 1533 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1534 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1535 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1536 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1537 | |
bogdanm | 0:9b334a45a8ff | 1538 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1539 | /** |
bogdanm | 0:9b334a45a8ff | 1540 | * @brief Wait for regular group conversion to be completed. |
bogdanm | 0:9b334a45a8ff | 1541 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1542 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 1543 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1544 | */ |
bogdanm | 0:9b334a45a8ff | 1545 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1546 | { |
bogdanm | 0:9b334a45a8ff | 1547 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 1548 | |
bogdanm | 0:9b334a45a8ff | 1549 | /* Variables for polling in case of scan mode enabled */ |
bogdanm | 0:9b334a45a8ff | 1550 | uint32_t Conversion_Timeout_CPU_cycles_max =0; |
bogdanm | 0:9b334a45a8ff | 1551 | uint32_t Conversion_Timeout_CPU_cycles =0; |
bogdanm | 0:9b334a45a8ff | 1552 | |
bogdanm | 0:9b334a45a8ff | 1553 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1554 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1555 | |
bogdanm | 0:9b334a45a8ff | 1556 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 1557 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1558 | |
bogdanm | 0:9b334a45a8ff | 1559 | /* Polling for end of conversion: differentiation if single/sequence */ |
bogdanm | 0:9b334a45a8ff | 1560 | /* conversion. */ |
bogdanm | 0:9b334a45a8ff | 1561 | /* - If single conversion for regular group (Scan mode disabled or enabled */ |
bogdanm | 0:9b334a45a8ff | 1562 | /* with NbrOfConversion =1), flag EOC is used to determine the */ |
bogdanm | 0:9b334a45a8ff | 1563 | /* conversion completion. */ |
bogdanm | 0:9b334a45a8ff | 1564 | /* - If sequence conversion for regular group, flag EOC is set only a the */ |
bogdanm | 0:9b334a45a8ff | 1565 | /* end of the sequence. To poll for each conversion, the maximum */ |
bogdanm | 0:9b334a45a8ff | 1566 | /* conversion time is calculated from ADC conversion time (selected */ |
bogdanm | 0:9b334a45a8ff | 1567 | /* sampling time + conversion time of 12.5 ADC clock cycles) and */ |
bogdanm | 0:9b334a45a8ff | 1568 | /* APB2/ADC clock prescalers (depending on settings, conversion time */ |
bogdanm | 0:9b334a45a8ff | 1569 | /* range can be from 28 to 32256 CPU cycles). */ |
bogdanm | 0:9b334a45a8ff | 1570 | if ((HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN)) && |
bogdanm | 0:9b334a45a8ff | 1571 | ((hadc->Instance->SQR1 & ADC_SQR1_L) == RESET) ) |
bogdanm | 0:9b334a45a8ff | 1572 | { |
bogdanm | 0:9b334a45a8ff | 1573 | /* Wait until End of Conversion flag is raised */ |
bogdanm | 0:9b334a45a8ff | 1574 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
bogdanm | 0:9b334a45a8ff | 1575 | { |
bogdanm | 0:9b334a45a8ff | 1576 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 1577 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1578 | { |
bogdanm | 0:9b334a45a8ff | 1579 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1580 | { |
bogdanm | 0:9b334a45a8ff | 1581 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 1582 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1583 | |
bogdanm | 0:9b334a45a8ff | 1584 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1585 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1586 | |
bogdanm | 0:9b334a45a8ff | 1587 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1588 | } |
bogdanm | 0:9b334a45a8ff | 1589 | } |
bogdanm | 0:9b334a45a8ff | 1590 | } |
bogdanm | 0:9b334a45a8ff | 1591 | } |
bogdanm | 0:9b334a45a8ff | 1592 | else |
bogdanm | 0:9b334a45a8ff | 1593 | { |
bogdanm | 0:9b334a45a8ff | 1594 | /* Computation of CPU cycles corresponding to ADC conversion cycles */ |
bogdanm | 0:9b334a45a8ff | 1595 | /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ |
bogdanm | 0:9b334a45a8ff | 1596 | /* channels. */ |
bogdanm | 0:9b334a45a8ff | 1597 | Conversion_Timeout_CPU_cycles_max = __HAL_ADC_CLOCK_PRECSALER_RANGE() ; |
bogdanm | 0:9b334a45a8ff | 1598 | Conversion_Timeout_CPU_cycles_max *= __HAL_ADC_CONVCYCLES_MAX_RANGE(hadc); |
bogdanm | 0:9b334a45a8ff | 1599 | |
bogdanm | 0:9b334a45a8ff | 1600 | /* Maximum conversion cycles taking in account offset of 34 CPU cycles: */ |
bogdanm | 0:9b334a45a8ff | 1601 | /* number of CPU cycles for processing of conversion cycles estimation. */ |
bogdanm | 0:9b334a45a8ff | 1602 | Conversion_Timeout_CPU_cycles = 34; |
bogdanm | 0:9b334a45a8ff | 1603 | |
bogdanm | 0:9b334a45a8ff | 1604 | /* Poll with maximum conversion time */ |
bogdanm | 0:9b334a45a8ff | 1605 | while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) |
bogdanm | 0:9b334a45a8ff | 1606 | { |
bogdanm | 0:9b334a45a8ff | 1607 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 1608 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1609 | { |
bogdanm | 0:9b334a45a8ff | 1610 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1611 | { |
bogdanm | 0:9b334a45a8ff | 1612 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 1613 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1614 | |
bogdanm | 0:9b334a45a8ff | 1615 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1616 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1617 | |
bogdanm | 0:9b334a45a8ff | 1618 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1619 | } |
bogdanm | 0:9b334a45a8ff | 1620 | } |
bogdanm | 0:9b334a45a8ff | 1621 | Conversion_Timeout_CPU_cycles ++; |
bogdanm | 0:9b334a45a8ff | 1622 | } |
bogdanm | 0:9b334a45a8ff | 1623 | } |
bogdanm | 0:9b334a45a8ff | 1624 | |
bogdanm | 0:9b334a45a8ff | 1625 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 1626 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 1627 | |
bogdanm | 0:9b334a45a8ff | 1628 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 1629 | if(hadc->State != HAL_ADC_STATE_ERROR) |
bogdanm | 0:9b334a45a8ff | 1630 | { |
bogdanm | 0:9b334a45a8ff | 1631 | /* Update ADC state machine */ |
bogdanm | 0:9b334a45a8ff | 1632 | if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) |
bogdanm | 0:9b334a45a8ff | 1633 | { |
bogdanm | 0:9b334a45a8ff | 1634 | /* Check if a conversion is ready on injected group */ |
bogdanm | 0:9b334a45a8ff | 1635 | if(hadc->State == HAL_ADC_STATE_EOC_INJ) |
bogdanm | 0:9b334a45a8ff | 1636 | { |
bogdanm | 0:9b334a45a8ff | 1637 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1638 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1639 | } |
bogdanm | 0:9b334a45a8ff | 1640 | else |
bogdanm | 0:9b334a45a8ff | 1641 | { |
bogdanm | 0:9b334a45a8ff | 1642 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1643 | hadc->State = HAL_ADC_STATE_EOC_REG; |
bogdanm | 0:9b334a45a8ff | 1644 | } |
bogdanm | 0:9b334a45a8ff | 1645 | } |
bogdanm | 0:9b334a45a8ff | 1646 | } |
bogdanm | 0:9b334a45a8ff | 1647 | |
bogdanm | 0:9b334a45a8ff | 1648 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1649 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1650 | } |
bogdanm | 0:9b334a45a8ff | 1651 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1652 | |
bogdanm | 0:9b334a45a8ff | 1653 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1654 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1655 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1656 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1657 | /** |
bogdanm | 0:9b334a45a8ff | 1658 | * @brief Poll for conversion event. |
bogdanm | 0:9b334a45a8ff | 1659 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1660 | * @param EventType: the ADC event type. |
bogdanm | 0:9b334a45a8ff | 1661 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1662 | * @arg AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) |
bogdanm | 0:9b334a45a8ff | 1663 | * @arg AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices) |
bogdanm | 0:9b334a45a8ff | 1664 | * @arg AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices) |
bogdanm | 0:9b334a45a8ff | 1665 | * @arg OVR_EVENT: ADC Overrun event |
bogdanm | 0:9b334a45a8ff | 1666 | * @arg JQOVF_EVENT: ADC Injected context queue overflow event |
bogdanm | 0:9b334a45a8ff | 1667 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 1668 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1669 | */ |
bogdanm | 0:9b334a45a8ff | 1670 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1671 | { |
bogdanm | 0:9b334a45a8ff | 1672 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 1673 | |
bogdanm | 0:9b334a45a8ff | 1674 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1675 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1676 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
bogdanm | 0:9b334a45a8ff | 1677 | |
bogdanm | 0:9b334a45a8ff | 1678 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1679 | |
bogdanm | 0:9b334a45a8ff | 1680 | /* Check selected event flag */ |
bogdanm | 0:9b334a45a8ff | 1681 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
bogdanm | 0:9b334a45a8ff | 1682 | { |
bogdanm | 0:9b334a45a8ff | 1683 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 1684 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1685 | { |
bogdanm | 0:9b334a45a8ff | 1686 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1687 | { |
bogdanm | 0:9b334a45a8ff | 1688 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 1689 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1690 | |
bogdanm | 0:9b334a45a8ff | 1691 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1692 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1693 | |
bogdanm | 0:9b334a45a8ff | 1694 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1695 | } |
bogdanm | 0:9b334a45a8ff | 1696 | } |
bogdanm | 0:9b334a45a8ff | 1697 | } |
bogdanm | 0:9b334a45a8ff | 1698 | |
bogdanm | 0:9b334a45a8ff | 1699 | |
bogdanm | 0:9b334a45a8ff | 1700 | switch(EventType) |
bogdanm | 0:9b334a45a8ff | 1701 | { |
bogdanm | 0:9b334a45a8ff | 1702 | /* Analog watchdog (level out of window) event */ |
bogdanm | 0:9b334a45a8ff | 1703 | /* Note: In case of several analog watchdog enabled, if needed to know */ |
bogdanm | 0:9b334a45a8ff | 1704 | /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */ |
bogdanm | 0:9b334a45a8ff | 1705 | /* flags HAL_ADC_STATE_AWD/2/3 function. */ |
bogdanm | 0:9b334a45a8ff | 1706 | /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */ |
bogdanm | 0:9b334a45a8ff | 1707 | /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */ |
bogdanm | 0:9b334a45a8ff | 1708 | /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */ |
bogdanm | 0:9b334a45a8ff | 1709 | /* Check analog watchdog 1 flag */ |
bogdanm | 0:9b334a45a8ff | 1710 | case AWD_EVENT: |
bogdanm | 0:9b334a45a8ff | 1711 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1712 | hadc->State = HAL_ADC_STATE_AWD; |
bogdanm | 0:9b334a45a8ff | 1713 | |
bogdanm | 0:9b334a45a8ff | 1714 | /* Clear ADC analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1715 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); |
bogdanm | 0:9b334a45a8ff | 1716 | break; |
bogdanm | 0:9b334a45a8ff | 1717 | |
bogdanm | 0:9b334a45a8ff | 1718 | /* Check analog watchdog 2 flag */ |
bogdanm | 0:9b334a45a8ff | 1719 | case AWD2_EVENT: |
bogdanm | 0:9b334a45a8ff | 1720 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1721 | hadc->State = HAL_ADC_STATE_AWD2; |
bogdanm | 0:9b334a45a8ff | 1722 | |
bogdanm | 0:9b334a45a8ff | 1723 | /* Clear ADC analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1724 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); |
bogdanm | 0:9b334a45a8ff | 1725 | break; |
bogdanm | 0:9b334a45a8ff | 1726 | |
bogdanm | 0:9b334a45a8ff | 1727 | /* Check analog watchdog 3 flag */ |
bogdanm | 0:9b334a45a8ff | 1728 | case AWD3_EVENT: |
bogdanm | 0:9b334a45a8ff | 1729 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1730 | hadc->State = HAL_ADC_STATE_AWD3; |
bogdanm | 0:9b334a45a8ff | 1731 | |
bogdanm | 0:9b334a45a8ff | 1732 | /* Clear ADC analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1733 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); |
bogdanm | 0:9b334a45a8ff | 1734 | break; |
bogdanm | 0:9b334a45a8ff | 1735 | |
bogdanm | 0:9b334a45a8ff | 1736 | /* Injected context queue overflow event */ |
bogdanm | 0:9b334a45a8ff | 1737 | case JQOVF_EVENT: |
bogdanm | 0:9b334a45a8ff | 1738 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1739 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 1740 | |
bogdanm | 0:9b334a45a8ff | 1741 | /* Set ADC error code to Injected context queue overflow */ |
bogdanm | 0:9b334a45a8ff | 1742 | hadc->ErrorCode |= HAL_ADC_ERROR_JQOVF; |
bogdanm | 0:9b334a45a8ff | 1743 | |
bogdanm | 0:9b334a45a8ff | 1744 | /* Clear ADC Injected context queue overflow flag */ |
bogdanm | 0:9b334a45a8ff | 1745 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); |
bogdanm | 0:9b334a45a8ff | 1746 | break; |
bogdanm | 0:9b334a45a8ff | 1747 | |
bogdanm | 0:9b334a45a8ff | 1748 | /* Overrun event */ |
bogdanm | 0:9b334a45a8ff | 1749 | default: /* Case OVR_EVENT */ |
bogdanm | 0:9b334a45a8ff | 1750 | /* If overrun is set to overwrite previous data, overrun event is not */ |
bogdanm | 0:9b334a45a8ff | 1751 | /* considered as an error. */ |
bogdanm | 0:9b334a45a8ff | 1752 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
bogdanm | 0:9b334a45a8ff | 1753 | /* overrun ") */ |
bogdanm | 0:9b334a45a8ff | 1754 | if (hadc->Init.Overrun == OVR_DATA_PRESERVED) |
bogdanm | 0:9b334a45a8ff | 1755 | { |
bogdanm | 0:9b334a45a8ff | 1756 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1757 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 1758 | |
bogdanm | 0:9b334a45a8ff | 1759 | /* Set ADC error code to overrun */ |
bogdanm | 0:9b334a45a8ff | 1760 | hadc->ErrorCode |= HAL_ADC_ERROR_OVR; |
bogdanm | 0:9b334a45a8ff | 1761 | } |
bogdanm | 0:9b334a45a8ff | 1762 | |
bogdanm | 0:9b334a45a8ff | 1763 | /* Clear ADC Overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1764 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 1765 | break; |
bogdanm | 0:9b334a45a8ff | 1766 | } |
bogdanm | 0:9b334a45a8ff | 1767 | |
bogdanm | 0:9b334a45a8ff | 1768 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1769 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1770 | } |
bogdanm | 0:9b334a45a8ff | 1771 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1772 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1773 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1774 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1775 | |
bogdanm | 0:9b334a45a8ff | 1776 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1777 | /** |
bogdanm | 0:9b334a45a8ff | 1778 | * @brief Poll for conversion event. |
bogdanm | 0:9b334a45a8ff | 1779 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1780 | * @param EventType: the ADC event type. |
bogdanm | 0:9b334a45a8ff | 1781 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1782 | * @arg AWD_EVENT: ADC Analog watchdog event. |
bogdanm | 0:9b334a45a8ff | 1783 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 1784 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1785 | */ |
bogdanm | 0:9b334a45a8ff | 1786 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1787 | { |
bogdanm | 0:9b334a45a8ff | 1788 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 1789 | |
bogdanm | 0:9b334a45a8ff | 1790 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1791 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1792 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
bogdanm | 0:9b334a45a8ff | 1793 | |
bogdanm | 0:9b334a45a8ff | 1794 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1795 | |
bogdanm | 0:9b334a45a8ff | 1796 | /* Check selected event flag */ |
bogdanm | 0:9b334a45a8ff | 1797 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
bogdanm | 0:9b334a45a8ff | 1798 | { |
bogdanm | 0:9b334a45a8ff | 1799 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 1800 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1801 | { |
bogdanm | 0:9b334a45a8ff | 1802 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1803 | { |
bogdanm | 0:9b334a45a8ff | 1804 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 1805 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1806 | |
bogdanm | 0:9b334a45a8ff | 1807 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1808 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1809 | |
bogdanm | 0:9b334a45a8ff | 1810 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1811 | } |
bogdanm | 0:9b334a45a8ff | 1812 | } |
bogdanm | 0:9b334a45a8ff | 1813 | } |
bogdanm | 0:9b334a45a8ff | 1814 | |
bogdanm | 0:9b334a45a8ff | 1815 | /* Analog watchdog (level out of window) event */ |
bogdanm | 0:9b334a45a8ff | 1816 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1817 | hadc->State = HAL_ADC_STATE_AWD; |
bogdanm | 0:9b334a45a8ff | 1818 | |
bogdanm | 0:9b334a45a8ff | 1819 | /* Clear ADC analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1820 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
bogdanm | 0:9b334a45a8ff | 1821 | |
bogdanm | 0:9b334a45a8ff | 1822 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1823 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1824 | } |
bogdanm | 0:9b334a45a8ff | 1825 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1826 | |
bogdanm | 0:9b334a45a8ff | 1827 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1828 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1829 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1830 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1831 | /** |
bogdanm | 0:9b334a45a8ff | 1832 | * @brief Enables ADC, starts conversion of regular group with interruption. |
bogdanm | 0:9b334a45a8ff | 1833 | * Interruptions enabled in this function: EOC (end of conversion), |
bogdanm | 0:9b334a45a8ff | 1834 | * overrun (if available). |
bogdanm | 0:9b334a45a8ff | 1835 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 1836 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 1837 | * function must be called for ADC slave first, then ADC master. |
bogdanm | 0:9b334a45a8ff | 1838 | * For ADC slave, ADC is enabled only (conversion is not started). |
bogdanm | 0:9b334a45a8ff | 1839 | * For ADC master, ADC is enabled and multimode conversion is started. |
bogdanm | 0:9b334a45a8ff | 1840 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1841 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1842 | */ |
bogdanm | 0:9b334a45a8ff | 1843 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1844 | { |
bogdanm | 0:9b334a45a8ff | 1845 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1846 | |
bogdanm | 0:9b334a45a8ff | 1847 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1848 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1849 | |
bogdanm | 0:9b334a45a8ff | 1850 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1851 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1852 | |
bogdanm | 0:9b334a45a8ff | 1853 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1854 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1855 | |
bogdanm | 0:9b334a45a8ff | 1856 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1857 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1858 | { |
bogdanm | 0:9b334a45a8ff | 1859 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 1860 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 1861 | { |
bogdanm | 0:9b334a45a8ff | 1862 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1863 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1864 | } |
bogdanm | 0:9b334a45a8ff | 1865 | else |
bogdanm | 0:9b334a45a8ff | 1866 | { |
bogdanm | 0:9b334a45a8ff | 1867 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1868 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 1869 | } |
bogdanm | 0:9b334a45a8ff | 1870 | |
bogdanm | 0:9b334a45a8ff | 1871 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1872 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1873 | |
bogdanm | 0:9b334a45a8ff | 1874 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1875 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 1876 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 1877 | |
bogdanm | 0:9b334a45a8ff | 1878 | /* Enable ADC end of conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 1879 | /* Enable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 1880 | switch(hadc->Init.EOCSelection) |
bogdanm | 0:9b334a45a8ff | 1881 | { |
bogdanm | 0:9b334a45a8ff | 1882 | case EOC_SEQ_CONV: |
bogdanm | 0:9b334a45a8ff | 1883 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
bogdanm | 0:9b334a45a8ff | 1884 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 1885 | break; |
bogdanm | 0:9b334a45a8ff | 1886 | /* case EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 1887 | default: |
bogdanm | 0:9b334a45a8ff | 1888 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 1889 | break; |
bogdanm | 0:9b334a45a8ff | 1890 | } |
bogdanm | 0:9b334a45a8ff | 1891 | |
bogdanm | 0:9b334a45a8ff | 1892 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 1893 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 1894 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1895 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1896 | /* Case of multimode enabled (for devices with several ADCs): if ADC is */ |
bogdanm | 0:9b334a45a8ff | 1897 | /* slave, ADC is enabled only (conversion is not started). If ADC is */ |
bogdanm | 0:9b334a45a8ff | 1898 | /* master, ADC is enabled and conversion is started. */ |
bogdanm | 0:9b334a45a8ff | 1899 | if (__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
bogdanm | 0:9b334a45a8ff | 1900 | { |
bogdanm | 0:9b334a45a8ff | 1901 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 1902 | } |
bogdanm | 0:9b334a45a8ff | 1903 | } |
bogdanm | 0:9b334a45a8ff | 1904 | |
bogdanm | 0:9b334a45a8ff | 1905 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1906 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1907 | |
bogdanm | 0:9b334a45a8ff | 1908 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1909 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1910 | } |
bogdanm | 0:9b334a45a8ff | 1911 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 1912 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 1913 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 1914 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 1915 | |
bogdanm | 0:9b334a45a8ff | 1916 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 1917 | /** |
bogdanm | 0:9b334a45a8ff | 1918 | * @brief Enables ADC, starts conversion of regular group with interruption. |
bogdanm | 0:9b334a45a8ff | 1919 | * Interruptions enabled in this function: EOC (end of conversion), |
bogdanm | 0:9b334a45a8ff | 1920 | * overrun (if available). |
bogdanm | 0:9b334a45a8ff | 1921 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 1922 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1923 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1924 | */ |
bogdanm | 0:9b334a45a8ff | 1925 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1926 | { |
bogdanm | 0:9b334a45a8ff | 1927 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1928 | |
bogdanm | 0:9b334a45a8ff | 1929 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1930 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1931 | |
bogdanm | 0:9b334a45a8ff | 1932 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1933 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1934 | |
bogdanm | 0:9b334a45a8ff | 1935 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1936 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1937 | |
bogdanm | 0:9b334a45a8ff | 1938 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1939 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 1940 | { |
bogdanm | 0:9b334a45a8ff | 1941 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 1942 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 1943 | { |
bogdanm | 0:9b334a45a8ff | 1944 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1945 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 1946 | } |
bogdanm | 0:9b334a45a8ff | 1947 | else |
bogdanm | 0:9b334a45a8ff | 1948 | { |
bogdanm | 0:9b334a45a8ff | 1949 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 1950 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 1951 | } |
bogdanm | 0:9b334a45a8ff | 1952 | |
bogdanm | 0:9b334a45a8ff | 1953 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 1954 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1955 | |
bogdanm | 0:9b334a45a8ff | 1956 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1957 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 1958 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 1959 | |
bogdanm | 0:9b334a45a8ff | 1960 | /* Enable end of conversion interrupt for regular group */ |
bogdanm | 0:9b334a45a8ff | 1961 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); |
bogdanm | 0:9b334a45a8ff | 1962 | |
bogdanm | 0:9b334a45a8ff | 1963 | /* Start conversion of regular group if software start has been selected. */ |
bogdanm | 0:9b334a45a8ff | 1964 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1965 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1966 | if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
bogdanm | 0:9b334a45a8ff | 1967 | { |
bogdanm | 0:9b334a45a8ff | 1968 | /* Start ADC conversion on regular group */ |
bogdanm | 0:9b334a45a8ff | 1969 | hadc->Instance->CR2 |= ADC_CR2_SWSTART; |
bogdanm | 0:9b334a45a8ff | 1970 | } |
bogdanm | 0:9b334a45a8ff | 1971 | } |
bogdanm | 0:9b334a45a8ff | 1972 | |
bogdanm | 0:9b334a45a8ff | 1973 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1974 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1975 | |
bogdanm | 0:9b334a45a8ff | 1976 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1977 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 1978 | } |
bogdanm | 0:9b334a45a8ff | 1979 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 1980 | |
bogdanm | 0:9b334a45a8ff | 1981 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 1982 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 1983 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 1984 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 1985 | /** |
bogdanm | 0:9b334a45a8ff | 1986 | * @brief Stop ADC conversion of regular group (and injected group in |
bogdanm | 0:9b334a45a8ff | 1987 | * case of auto_injection mode), disable interruption of |
bogdanm | 0:9b334a45a8ff | 1988 | * end-of-conversion, disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 1989 | * @note: ADC peripheral disable is forcing interruption of potential |
bogdanm | 0:9b334a45a8ff | 1990 | * conversion on injected group. If injected group is under use, it |
bogdanm | 0:9b334a45a8ff | 1991 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
bogdanm | 0:9b334a45a8ff | 1992 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1993 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1994 | */ |
bogdanm | 0:9b334a45a8ff | 1995 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1996 | { |
bogdanm | 0:9b334a45a8ff | 1997 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1998 | |
bogdanm | 0:9b334a45a8ff | 1999 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2000 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2001 | |
bogdanm | 0:9b334a45a8ff | 2002 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2003 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2004 | |
bogdanm | 0:9b334a45a8ff | 2005 | /* 1. Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 2006 | tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 2007 | |
bogdanm | 0:9b334a45a8ff | 2008 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 2009 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2010 | { |
bogdanm | 0:9b334a45a8ff | 2011 | /* Disable ADC end of conversion interrupt for regular group */ |
bogdanm | 0:9b334a45a8ff | 2012 | /* Disable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 2013 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 2014 | |
bogdanm | 0:9b334a45a8ff | 2015 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2016 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2017 | |
bogdanm | 0:9b334a45a8ff | 2018 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2019 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2020 | { |
bogdanm | 0:9b334a45a8ff | 2021 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2022 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 2023 | } |
bogdanm | 0:9b334a45a8ff | 2024 | } |
bogdanm | 0:9b334a45a8ff | 2025 | |
bogdanm | 0:9b334a45a8ff | 2026 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2027 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2028 | |
bogdanm | 0:9b334a45a8ff | 2029 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2030 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2031 | } |
bogdanm | 0:9b334a45a8ff | 2032 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2033 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2034 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2035 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2036 | |
bogdanm | 0:9b334a45a8ff | 2037 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2038 | /** |
bogdanm | 0:9b334a45a8ff | 2039 | * @brief Stop ADC conversion of regular group (and injected group in |
bogdanm | 0:9b334a45a8ff | 2040 | * case of auto_injection mode), disable interrution of |
bogdanm | 0:9b334a45a8ff | 2041 | * end-of-conversion, disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 2042 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2043 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2044 | */ |
bogdanm | 0:9b334a45a8ff | 2045 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2046 | { |
bogdanm | 0:9b334a45a8ff | 2047 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2048 | |
bogdanm | 0:9b334a45a8ff | 2049 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2050 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2051 | |
bogdanm | 0:9b334a45a8ff | 2052 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2053 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2054 | |
bogdanm | 0:9b334a45a8ff | 2055 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 2056 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2057 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2058 | |
bogdanm | 0:9b334a45a8ff | 2059 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2060 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2061 | { |
bogdanm | 0:9b334a45a8ff | 2062 | /* Disable ADC end of conversion interrupt for regular group */ |
bogdanm | 0:9b334a45a8ff | 2063 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
bogdanm | 0:9b334a45a8ff | 2064 | |
bogdanm | 0:9b334a45a8ff | 2065 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2066 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 2067 | } |
bogdanm | 0:9b334a45a8ff | 2068 | |
bogdanm | 0:9b334a45a8ff | 2069 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2070 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2071 | |
bogdanm | 0:9b334a45a8ff | 2072 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2073 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2074 | } |
bogdanm | 0:9b334a45a8ff | 2075 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2076 | |
bogdanm | 0:9b334a45a8ff | 2077 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2078 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2079 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2080 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2081 | /** |
bogdanm | 0:9b334a45a8ff | 2082 | * @brief Enables ADC, starts conversion of regular group and transfers result |
bogdanm | 0:9b334a45a8ff | 2083 | * through DMA. |
bogdanm | 0:9b334a45a8ff | 2084 | * Interruptions enabled in this function: |
bogdanm | 0:9b334a45a8ff | 2085 | * overrun (if available), DMA half transfer, DMA transfer complete. |
bogdanm | 0:9b334a45a8ff | 2086 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 2087 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 2088 | * function is for single-ADC mode only. For multimode, use the |
bogdanm | 0:9b334a45a8ff | 2089 | * dedicated MultimodeStart function. |
bogdanm | 0:9b334a45a8ff | 2090 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2091 | * @param pData: The destination Buffer address. |
bogdanm | 0:9b334a45a8ff | 2092 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
bogdanm | 0:9b334a45a8ff | 2093 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2094 | */ |
bogdanm | 0:9b334a45a8ff | 2095 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
bogdanm | 0:9b334a45a8ff | 2096 | { |
bogdanm | 0:9b334a45a8ff | 2097 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2098 | |
bogdanm | 0:9b334a45a8ff | 2099 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2100 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2101 | |
bogdanm | 0:9b334a45a8ff | 2102 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2103 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2104 | |
bogdanm | 0:9b334a45a8ff | 2105 | /* Verification if multimode is disabled (for devices with several ADC) */ |
bogdanm | 0:9b334a45a8ff | 2106 | /* If multimode is enabled, dedicated function multimode conversion */ |
bogdanm | 0:9b334a45a8ff | 2107 | /* start DMA must be used. */ |
bogdanm | 0:9b334a45a8ff | 2108 | if(__HAL_ADC_COMMON_CCR_MULTI(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 2109 | { |
bogdanm | 0:9b334a45a8ff | 2110 | |
bogdanm | 0:9b334a45a8ff | 2111 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2112 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 2113 | |
bogdanm | 0:9b334a45a8ff | 2114 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 2115 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2116 | { |
bogdanm | 0:9b334a45a8ff | 2117 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 2118 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 2119 | { |
bogdanm | 0:9b334a45a8ff | 2120 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2121 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2122 | } |
bogdanm | 0:9b334a45a8ff | 2123 | else |
bogdanm | 0:9b334a45a8ff | 2124 | { |
bogdanm | 0:9b334a45a8ff | 2125 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2126 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 2127 | } |
bogdanm | 0:9b334a45a8ff | 2128 | |
bogdanm | 0:9b334a45a8ff | 2129 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 2130 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 2131 | |
bogdanm | 0:9b334a45a8ff | 2132 | |
bogdanm | 0:9b334a45a8ff | 2133 | /* Set the DMA transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 2134 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
bogdanm | 0:9b334a45a8ff | 2135 | |
bogdanm | 0:9b334a45a8ff | 2136 | /* Set the DMA half transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 2137 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
bogdanm | 0:9b334a45a8ff | 2138 | |
bogdanm | 0:9b334a45a8ff | 2139 | /* Set the DMA error callback */ |
bogdanm | 0:9b334a45a8ff | 2140 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
bogdanm | 0:9b334a45a8ff | 2141 | |
bogdanm | 0:9b334a45a8ff | 2142 | |
bogdanm | 0:9b334a45a8ff | 2143 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
bogdanm | 0:9b334a45a8ff | 2144 | /* start (in case of SW start): */ |
bogdanm | 0:9b334a45a8ff | 2145 | |
bogdanm | 0:9b334a45a8ff | 2146 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 2147 | /* (To ensure of no unknown state from potential previous ADC */ |
bogdanm | 0:9b334a45a8ff | 2148 | /* operations) */ |
bogdanm | 0:9b334a45a8ff | 2149 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 2150 | |
bogdanm | 0:9b334a45a8ff | 2151 | /* Enable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 2152 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 2153 | |
bogdanm | 0:9b334a45a8ff | 2154 | /* Enable ADC DMA mode */ |
bogdanm | 0:9b334a45a8ff | 2155 | hadc->Instance->CFGR |= ADC_CFGR_DMAEN; |
bogdanm | 0:9b334a45a8ff | 2156 | |
bogdanm | 0:9b334a45a8ff | 2157 | /* Start the DMA channel */ |
bogdanm | 0:9b334a45a8ff | 2158 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
bogdanm | 0:9b334a45a8ff | 2159 | |
bogdanm | 0:9b334a45a8ff | 2160 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 2161 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 2162 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 2163 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 2164 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 2165 | |
bogdanm | 0:9b334a45a8ff | 2166 | } |
bogdanm | 0:9b334a45a8ff | 2167 | } |
bogdanm | 0:9b334a45a8ff | 2168 | else |
bogdanm | 0:9b334a45a8ff | 2169 | { |
bogdanm | 0:9b334a45a8ff | 2170 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2171 | } |
bogdanm | 0:9b334a45a8ff | 2172 | |
bogdanm | 0:9b334a45a8ff | 2173 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2174 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2175 | |
bogdanm | 0:9b334a45a8ff | 2176 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2177 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2178 | } |
bogdanm | 0:9b334a45a8ff | 2179 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2180 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2181 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2182 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2183 | |
bogdanm | 0:9b334a45a8ff | 2184 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2185 | /** |
bogdanm | 0:9b334a45a8ff | 2186 | * @brief Enables ADC, starts conversion of regular group and transfers result |
bogdanm | 0:9b334a45a8ff | 2187 | * through DMA. |
bogdanm | 0:9b334a45a8ff | 2188 | * Interruptions enabled in this function: |
bogdanm | 0:9b334a45a8ff | 2189 | * overrun (if available), DMA half transfer, DMA transfer complete. |
bogdanm | 0:9b334a45a8ff | 2190 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 2191 | * @note For devices with several ADCs: This function is for single-ADC mode |
bogdanm | 0:9b334a45a8ff | 2192 | * only. For multimode, use the dedicated MultimodeStart function. |
bogdanm | 0:9b334a45a8ff | 2193 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2194 | * @param pData: The destination Buffer address. |
bogdanm | 0:9b334a45a8ff | 2195 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
bogdanm | 0:9b334a45a8ff | 2196 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2197 | */ |
bogdanm | 0:9b334a45a8ff | 2198 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
bogdanm | 0:9b334a45a8ff | 2199 | { |
bogdanm | 0:9b334a45a8ff | 2200 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2201 | |
bogdanm | 0:9b334a45a8ff | 2202 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2203 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2204 | |
bogdanm | 0:9b334a45a8ff | 2205 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2206 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2207 | |
bogdanm | 0:9b334a45a8ff | 2208 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2209 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 2210 | |
bogdanm | 0:9b334a45a8ff | 2211 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 2212 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2213 | { |
bogdanm | 0:9b334a45a8ff | 2214 | /* State machine update: Check if an injected conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 2215 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 2216 | { |
bogdanm | 0:9b334a45a8ff | 2217 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2218 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2219 | } |
bogdanm | 0:9b334a45a8ff | 2220 | else |
bogdanm | 0:9b334a45a8ff | 2221 | { |
bogdanm | 0:9b334a45a8ff | 2222 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2223 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 2224 | } |
bogdanm | 0:9b334a45a8ff | 2225 | |
bogdanm | 0:9b334a45a8ff | 2226 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 2227 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 2228 | |
bogdanm | 0:9b334a45a8ff | 2229 | |
bogdanm | 0:9b334a45a8ff | 2230 | /* Set the DMA transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 2231 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
bogdanm | 0:9b334a45a8ff | 2232 | |
bogdanm | 0:9b334a45a8ff | 2233 | /* Set the DMA half transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 2234 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
bogdanm | 0:9b334a45a8ff | 2235 | |
bogdanm | 0:9b334a45a8ff | 2236 | /* Set the DMA error callback */ |
bogdanm | 0:9b334a45a8ff | 2237 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
bogdanm | 0:9b334a45a8ff | 2238 | |
bogdanm | 0:9b334a45a8ff | 2239 | |
bogdanm | 0:9b334a45a8ff | 2240 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
bogdanm | 0:9b334a45a8ff | 2241 | /* start (in case of SW start): */ |
bogdanm | 0:9b334a45a8ff | 2242 | |
bogdanm | 0:9b334a45a8ff | 2243 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 2244 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 2245 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 2246 | |
bogdanm | 0:9b334a45a8ff | 2247 | /* Enable ADC DMA mode */ |
bogdanm | 0:9b334a45a8ff | 2248 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
bogdanm | 0:9b334a45a8ff | 2249 | |
bogdanm | 0:9b334a45a8ff | 2250 | /* Start the DMA channel */ |
bogdanm | 0:9b334a45a8ff | 2251 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
bogdanm | 0:9b334a45a8ff | 2252 | |
bogdanm | 0:9b334a45a8ff | 2253 | /* Start conversion of regular group if software start has been selected. */ |
bogdanm | 0:9b334a45a8ff | 2254 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 2255 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 2256 | /* Note: Alternate trigger for single conversion could be to force an */ |
bogdanm | 0:9b334a45a8ff | 2257 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
bogdanm | 0:9b334a45a8ff | 2258 | if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
bogdanm | 0:9b334a45a8ff | 2259 | { |
bogdanm | 0:9b334a45a8ff | 2260 | /* Start ADC conversion on regular group */ |
bogdanm | 0:9b334a45a8ff | 2261 | hadc->Instance->CR2 |= ADC_CR2_SWSTART; |
bogdanm | 0:9b334a45a8ff | 2262 | } |
bogdanm | 0:9b334a45a8ff | 2263 | } |
bogdanm | 0:9b334a45a8ff | 2264 | |
bogdanm | 0:9b334a45a8ff | 2265 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2266 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2267 | |
bogdanm | 0:9b334a45a8ff | 2268 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2269 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2270 | } |
bogdanm | 0:9b334a45a8ff | 2271 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2272 | |
bogdanm | 0:9b334a45a8ff | 2273 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2274 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2275 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2276 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2277 | /** |
bogdanm | 0:9b334a45a8ff | 2278 | * @brief Stop ADC conversion of regular group (and injected channels in |
bogdanm | 0:9b334a45a8ff | 2279 | * case of auto_injection mode), disable ADC DMA transfer, disable |
bogdanm | 0:9b334a45a8ff | 2280 | * ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 2281 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 2282 | * @note: ADC peripheral disable is forcing interruption of potential |
bogdanm | 0:9b334a45a8ff | 2283 | * conversion on injected group. If injected group is under use, it |
bogdanm | 0:9b334a45a8ff | 2284 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
bogdanm | 0:9b334a45a8ff | 2285 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 2286 | * function is for single-ADC mode only. For multimode, use the |
bogdanm | 0:9b334a45a8ff | 2287 | * dedicated MultimodeStop function. |
bogdanm | 0:9b334a45a8ff | 2288 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2289 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 2290 | */ |
bogdanm | 0:9b334a45a8ff | 2291 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2292 | { |
bogdanm | 0:9b334a45a8ff | 2293 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2294 | |
bogdanm | 0:9b334a45a8ff | 2295 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2296 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2297 | |
bogdanm | 0:9b334a45a8ff | 2298 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2299 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2300 | |
bogdanm | 0:9b334a45a8ff | 2301 | /* 1. Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 2302 | tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 2303 | |
bogdanm | 0:9b334a45a8ff | 2304 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 2305 | if (tmpHALStatus == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 2306 | { |
bogdanm | 0:9b334a45a8ff | 2307 | /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ |
bogdanm | 0:9b334a45a8ff | 2308 | hadc->Instance->CFGR &= ~ADC_CFGR_DMAEN; |
bogdanm | 0:9b334a45a8ff | 2309 | |
bogdanm | 0:9b334a45a8ff | 2310 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
bogdanm | 0:9b334a45a8ff | 2311 | /* while DMA transfer is on going) */ |
bogdanm | 0:9b334a45a8ff | 2312 | tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); |
bogdanm | 0:9b334a45a8ff | 2313 | |
bogdanm | 0:9b334a45a8ff | 2314 | /* Check if DMA channel effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2315 | if (tmpHALStatus != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 2316 | { |
bogdanm | 0:9b334a45a8ff | 2317 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2318 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2319 | } |
bogdanm | 0:9b334a45a8ff | 2320 | |
bogdanm | 0:9b334a45a8ff | 2321 | /* Disable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 2322 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 2323 | |
bogdanm | 0:9b334a45a8ff | 2324 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2325 | /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */ |
bogdanm | 0:9b334a45a8ff | 2326 | /* memory a potential failing status. */ |
bogdanm | 0:9b334a45a8ff | 2327 | if (tmpHALStatus == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 2328 | { |
bogdanm | 0:9b334a45a8ff | 2329 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2330 | } |
bogdanm | 0:9b334a45a8ff | 2331 | else |
bogdanm | 0:9b334a45a8ff | 2332 | { |
bogdanm | 0:9b334a45a8ff | 2333 | ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2334 | } |
bogdanm | 0:9b334a45a8ff | 2335 | |
bogdanm | 0:9b334a45a8ff | 2336 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2337 | if (tmpHALStatus == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 2338 | { |
bogdanm | 0:9b334a45a8ff | 2339 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2340 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 2341 | } |
bogdanm | 0:9b334a45a8ff | 2342 | |
bogdanm | 0:9b334a45a8ff | 2343 | } |
bogdanm | 0:9b334a45a8ff | 2344 | |
bogdanm | 0:9b334a45a8ff | 2345 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2346 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2347 | |
bogdanm | 0:9b334a45a8ff | 2348 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2349 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2350 | } |
bogdanm | 0:9b334a45a8ff | 2351 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2352 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2353 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2354 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2355 | |
bogdanm | 0:9b334a45a8ff | 2356 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2357 | /** |
bogdanm | 0:9b334a45a8ff | 2358 | * @brief Stop ADC conversion of regular group (and injected group in |
bogdanm | 0:9b334a45a8ff | 2359 | * case of auto_injection mode), disable ADC DMA transfer, disable |
bogdanm | 0:9b334a45a8ff | 2360 | * ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 2361 | * @note: ADC peripheral disable is forcing interruption of potential |
bogdanm | 0:9b334a45a8ff | 2362 | * conversion on injected group. If injected group is under use, it |
bogdanm | 0:9b334a45a8ff | 2363 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
bogdanm | 0:9b334a45a8ff | 2364 | * @note For devices with several ADCs: This function is for single-ADC mode |
bogdanm | 0:9b334a45a8ff | 2365 | * only. For multimode, use the dedicated MultimodeStop function. |
bogdanm | 0:9b334a45a8ff | 2366 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2367 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 2368 | */ |
bogdanm | 0:9b334a45a8ff | 2369 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2370 | { |
bogdanm | 0:9b334a45a8ff | 2371 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2372 | |
bogdanm | 0:9b334a45a8ff | 2373 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2374 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2375 | |
bogdanm | 0:9b334a45a8ff | 2376 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2377 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2378 | |
bogdanm | 0:9b334a45a8ff | 2379 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 2380 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2381 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2382 | |
bogdanm | 0:9b334a45a8ff | 2383 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2384 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2385 | { |
bogdanm | 0:9b334a45a8ff | 2386 | /* Disable ADC DMA mode */ |
bogdanm | 0:9b334a45a8ff | 2387 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
bogdanm | 0:9b334a45a8ff | 2388 | |
bogdanm | 0:9b334a45a8ff | 2389 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
bogdanm | 0:9b334a45a8ff | 2390 | /* while DMA transfer is on going) */ |
bogdanm | 0:9b334a45a8ff | 2391 | tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); |
bogdanm | 0:9b334a45a8ff | 2392 | |
bogdanm | 0:9b334a45a8ff | 2393 | /* Check if DMA channel effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2394 | if (tmpHALStatus == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 2395 | { |
bogdanm | 0:9b334a45a8ff | 2396 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2397 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 2398 | } |
bogdanm | 0:9b334a45a8ff | 2399 | else |
bogdanm | 0:9b334a45a8ff | 2400 | { |
bogdanm | 0:9b334a45a8ff | 2401 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2402 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2403 | } |
bogdanm | 0:9b334a45a8ff | 2404 | } |
bogdanm | 0:9b334a45a8ff | 2405 | |
bogdanm | 0:9b334a45a8ff | 2406 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2407 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2408 | |
bogdanm | 0:9b334a45a8ff | 2409 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2410 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2411 | } |
bogdanm | 0:9b334a45a8ff | 2412 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2413 | |
bogdanm | 0:9b334a45a8ff | 2414 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2415 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2416 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2417 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2418 | /** |
bogdanm | 0:9b334a45a8ff | 2419 | * @brief Get ADC regular group conversion result. |
bogdanm | 0:9b334a45a8ff | 2420 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2421 | * @retval Converted value |
bogdanm | 0:9b334a45a8ff | 2422 | */ |
bogdanm | 0:9b334a45a8ff | 2423 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2424 | { |
bogdanm | 0:9b334a45a8ff | 2425 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2426 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2427 | |
bogdanm | 0:9b334a45a8ff | 2428 | /* Note: EOC flag is automatically cleared by hardware when reading */ |
bogdanm | 0:9b334a45a8ff | 2429 | /* register DR. Additionally, clear flag EOS by software. */ |
bogdanm | 0:9b334a45a8ff | 2430 | |
bogdanm | 0:9b334a45a8ff | 2431 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 2432 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); |
bogdanm | 0:9b334a45a8ff | 2433 | |
bogdanm | 0:9b334a45a8ff | 2434 | /* Return ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 2435 | return hadc->Instance->DR; |
bogdanm | 0:9b334a45a8ff | 2436 | } |
bogdanm | 0:9b334a45a8ff | 2437 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2438 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2439 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2440 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2441 | |
bogdanm | 0:9b334a45a8ff | 2442 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2443 | /** |
bogdanm | 0:9b334a45a8ff | 2444 | * @brief Get ADC regular group conversion result. |
bogdanm | 0:9b334a45a8ff | 2445 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2446 | * @retval Converted value |
bogdanm | 0:9b334a45a8ff | 2447 | */ |
bogdanm | 0:9b334a45a8ff | 2448 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2449 | { |
bogdanm | 0:9b334a45a8ff | 2450 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2451 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2452 | |
bogdanm | 0:9b334a45a8ff | 2453 | /* Note: EOC flag is not cleared here by software because automatically */ |
bogdanm | 0:9b334a45a8ff | 2454 | /* cleared by hardware when reading register DR. */ |
bogdanm | 0:9b334a45a8ff | 2455 | |
bogdanm | 0:9b334a45a8ff | 2456 | /* Return ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 2457 | return hadc->Instance->DR; |
bogdanm | 0:9b334a45a8ff | 2458 | } |
bogdanm | 0:9b334a45a8ff | 2459 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2460 | |
bogdanm | 0:9b334a45a8ff | 2461 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2462 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2463 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2464 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2465 | /** |
bogdanm | 0:9b334a45a8ff | 2466 | * @brief Handles ADC interrupt request. |
bogdanm | 0:9b334a45a8ff | 2467 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2468 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2469 | */ |
bogdanm | 0:9b334a45a8ff | 2470 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2471 | { |
bogdanm | 0:9b334a45a8ff | 2472 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2473 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2474 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 2475 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
bogdanm | 0:9b334a45a8ff | 2476 | |
bogdanm | 0:9b334a45a8ff | 2477 | /* ========== Check End of Conversion flag for regular group ========== */ |
bogdanm | 0:9b334a45a8ff | 2478 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || |
bogdanm | 0:9b334a45a8ff | 2479 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) |
bogdanm | 0:9b334a45a8ff | 2480 | { |
bogdanm | 0:9b334a45a8ff | 2481 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 2482 | if(hadc->State != HAL_ADC_STATE_ERROR) |
bogdanm | 0:9b334a45a8ff | 2483 | { |
bogdanm | 0:9b334a45a8ff | 2484 | /* Check if an injected conversion is ready */ |
bogdanm | 0:9b334a45a8ff | 2485 | if(hadc->State == HAL_ADC_STATE_EOC_INJ) |
bogdanm | 0:9b334a45a8ff | 2486 | { |
bogdanm | 0:9b334a45a8ff | 2487 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2488 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2489 | } |
bogdanm | 0:9b334a45a8ff | 2490 | else |
bogdanm | 0:9b334a45a8ff | 2491 | { |
bogdanm | 0:9b334a45a8ff | 2492 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2493 | hadc->State = HAL_ADC_STATE_EOC_REG; |
bogdanm | 0:9b334a45a8ff | 2494 | } |
bogdanm | 0:9b334a45a8ff | 2495 | } |
bogdanm | 0:9b334a45a8ff | 2496 | |
bogdanm | 0:9b334a45a8ff | 2497 | /* Disable interruption if no further conversion upcoming by regular */ |
bogdanm | 0:9b334a45a8ff | 2498 | /* external trigger or by continuous mode, */ |
bogdanm | 0:9b334a45a8ff | 2499 | /* and if scan sequence if completed. */ |
bogdanm | 0:9b334a45a8ff | 2500 | if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 2501 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 2502 | { |
bogdanm | 0:9b334a45a8ff | 2503 | /* If End of Sequence is reached, disable interrupts */ |
bogdanm | 0:9b334a45a8ff | 2504 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
bogdanm | 0:9b334a45a8ff | 2505 | { |
bogdanm | 0:9b334a45a8ff | 2506 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
bogdanm | 0:9b334a45a8ff | 2507 | /* ADSTART==0 (no conversion on going) */ |
bogdanm | 0:9b334a45a8ff | 2508 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 2509 | { |
bogdanm | 0:9b334a45a8ff | 2510 | /* Disable ADC end of sequence conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 2511 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
bogdanm | 0:9b334a45a8ff | 2512 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
bogdanm | 0:9b334a45a8ff | 2513 | /* by overrun IRQ process below. */ |
bogdanm | 0:9b334a45a8ff | 2514 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
bogdanm | 0:9b334a45a8ff | 2515 | } |
bogdanm | 0:9b334a45a8ff | 2516 | else |
bogdanm | 0:9b334a45a8ff | 2517 | { |
bogdanm | 0:9b334a45a8ff | 2518 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 2519 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2520 | |
bogdanm | 0:9b334a45a8ff | 2521 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 2522 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 2523 | } |
bogdanm | 0:9b334a45a8ff | 2524 | } |
bogdanm | 0:9b334a45a8ff | 2525 | } |
bogdanm | 0:9b334a45a8ff | 2526 | |
bogdanm | 0:9b334a45a8ff | 2527 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 2528 | /* Note: into callback, to determine if conversion has been triggered */ |
bogdanm | 0:9b334a45a8ff | 2529 | /* from EOC or EOS, possibility to use: */ |
bogdanm | 0:9b334a45a8ff | 2530 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ |
bogdanm | 0:9b334a45a8ff | 2531 | HAL_ADC_ConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2532 | |
bogdanm | 0:9b334a45a8ff | 2533 | |
bogdanm | 0:9b334a45a8ff | 2534 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 2535 | /* Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */ |
bogdanm | 0:9b334a45a8ff | 2536 | /* flags clear induces the release of the preserved data. */ |
bogdanm | 0:9b334a45a8ff | 2537 | /* Therefore, if the preserved data value is needed, it must be */ |
bogdanm | 0:9b334a45a8ff | 2538 | /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ |
bogdanm | 0:9b334a45a8ff | 2539 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); |
bogdanm | 0:9b334a45a8ff | 2540 | } |
bogdanm | 0:9b334a45a8ff | 2541 | |
bogdanm | 0:9b334a45a8ff | 2542 | |
bogdanm | 0:9b334a45a8ff | 2543 | /* ========== Check End of Conversion flag for injected group ========== */ |
bogdanm | 0:9b334a45a8ff | 2544 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) || |
bogdanm | 0:9b334a45a8ff | 2545 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) ) |
bogdanm | 0:9b334a45a8ff | 2546 | { |
bogdanm | 0:9b334a45a8ff | 2547 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 2548 | if(hadc->State != HAL_ADC_STATE_ERROR) |
bogdanm | 0:9b334a45a8ff | 2549 | { |
bogdanm | 0:9b334a45a8ff | 2550 | /* Check if a regular conversion is ready */ |
bogdanm | 0:9b334a45a8ff | 2551 | if(hadc->State == HAL_ADC_STATE_EOC_REG) |
bogdanm | 0:9b334a45a8ff | 2552 | { |
bogdanm | 0:9b334a45a8ff | 2553 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2554 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2555 | } |
bogdanm | 0:9b334a45a8ff | 2556 | else |
bogdanm | 0:9b334a45a8ff | 2557 | { |
bogdanm | 0:9b334a45a8ff | 2558 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2559 | hadc->State = HAL_ADC_STATE_EOC_INJ; |
bogdanm | 0:9b334a45a8ff | 2560 | } |
bogdanm | 0:9b334a45a8ff | 2561 | } |
bogdanm | 0:9b334a45a8ff | 2562 | |
bogdanm | 0:9b334a45a8ff | 2563 | /* Disable interruption if no further conversion upcoming by injected */ |
bogdanm | 0:9b334a45a8ff | 2564 | /* external trigger or by automatic injected conversion with regular */ |
bogdanm | 0:9b334a45a8ff | 2565 | /* group having no further conversion upcoming (same conditions as */ |
bogdanm | 0:9b334a45a8ff | 2566 | /* regular group interruption disabling above), */ |
bogdanm | 0:9b334a45a8ff | 2567 | /* and if injected scan sequence is completed. */ |
bogdanm | 0:9b334a45a8ff | 2568 | if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) || |
bogdanm | 0:9b334a45a8ff | 2569 | (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) && |
bogdanm | 0:9b334a45a8ff | 2570 | (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 2571 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
bogdanm | 0:9b334a45a8ff | 2572 | { |
bogdanm | 0:9b334a45a8ff | 2573 | /* If End of Sequence is reached, disable interrupts */ |
bogdanm | 0:9b334a45a8ff | 2574 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) |
bogdanm | 0:9b334a45a8ff | 2575 | { |
bogdanm | 0:9b334a45a8ff | 2576 | /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ |
bogdanm | 0:9b334a45a8ff | 2577 | /* JADSTART==0 (no conversion on going) */ |
bogdanm | 0:9b334a45a8ff | 2578 | if (__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 2579 | { |
bogdanm | 0:9b334a45a8ff | 2580 | /* Disable ADC end of sequence conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 2581 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); |
bogdanm | 0:9b334a45a8ff | 2582 | } |
bogdanm | 0:9b334a45a8ff | 2583 | else |
bogdanm | 0:9b334a45a8ff | 2584 | { |
bogdanm | 0:9b334a45a8ff | 2585 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 2586 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2587 | |
bogdanm | 0:9b334a45a8ff | 2588 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 2589 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 2590 | } |
bogdanm | 0:9b334a45a8ff | 2591 | } |
bogdanm | 0:9b334a45a8ff | 2592 | } |
bogdanm | 0:9b334a45a8ff | 2593 | |
bogdanm | 0:9b334a45a8ff | 2594 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 2595 | /* Note: into callback, to determine if conversion has been triggered */ |
bogdanm | 0:9b334a45a8ff | 2596 | /* from JEOC or JEOS, possibility to use: */ |
bogdanm | 0:9b334a45a8ff | 2597 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */ |
bogdanm | 0:9b334a45a8ff | 2598 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2599 | |
bogdanm | 0:9b334a45a8ff | 2600 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 2601 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); |
bogdanm | 0:9b334a45a8ff | 2602 | } |
bogdanm | 0:9b334a45a8ff | 2603 | |
bogdanm | 0:9b334a45a8ff | 2604 | |
bogdanm | 0:9b334a45a8ff | 2605 | /* ========== Check Analog watchdog flags ========== */ |
bogdanm | 0:9b334a45a8ff | 2606 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1)) || |
bogdanm | 0:9b334a45a8ff | 2607 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2)) || |
bogdanm | 0:9b334a45a8ff | 2608 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3)) ) |
bogdanm | 0:9b334a45a8ff | 2609 | { |
bogdanm | 0:9b334a45a8ff | 2610 | |
bogdanm | 0:9b334a45a8ff | 2611 | if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) != RESET) |
bogdanm | 0:9b334a45a8ff | 2612 | { |
bogdanm | 0:9b334a45a8ff | 2613 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2614 | hadc->State = HAL_ADC_STATE_AWD; |
bogdanm | 0:9b334a45a8ff | 2615 | |
bogdanm | 0:9b334a45a8ff | 2616 | /* Clear ADC Analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 2617 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); |
bogdanm | 0:9b334a45a8ff | 2618 | } |
bogdanm | 0:9b334a45a8ff | 2619 | else if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) != RESET) |
bogdanm | 0:9b334a45a8ff | 2620 | { |
bogdanm | 0:9b334a45a8ff | 2621 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2622 | hadc->State = HAL_ADC_STATE_AWD2; |
bogdanm | 0:9b334a45a8ff | 2623 | |
bogdanm | 0:9b334a45a8ff | 2624 | /* Clear ADC Analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 2625 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); |
bogdanm | 0:9b334a45a8ff | 2626 | } |
bogdanm | 0:9b334a45a8ff | 2627 | else if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) != RESET) |
bogdanm | 0:9b334a45a8ff | 2628 | { |
bogdanm | 0:9b334a45a8ff | 2629 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2630 | hadc->State = HAL_ADC_STATE_AWD3; |
bogdanm | 0:9b334a45a8ff | 2631 | |
bogdanm | 0:9b334a45a8ff | 2632 | /* Clear ADC Analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 2633 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); |
bogdanm | 0:9b334a45a8ff | 2634 | } |
bogdanm | 0:9b334a45a8ff | 2635 | else |
bogdanm | 0:9b334a45a8ff | 2636 | { |
bogdanm | 0:9b334a45a8ff | 2637 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 2638 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2639 | } |
bogdanm | 0:9b334a45a8ff | 2640 | |
bogdanm | 0:9b334a45a8ff | 2641 | /* Level out of window callback */ |
bogdanm | 0:9b334a45a8ff | 2642 | /* Note: In case of several analog watchdog enabled, if needed to know */ |
bogdanm | 0:9b334a45a8ff | 2643 | /* which one triggered and on which ADCx, either: */ |
bogdanm | 0:9b334a45a8ff | 2644 | /* Test Analog Watchdog flags ADC_FLAG_AWD1/2/3 into function */ |
bogdanm | 0:9b334a45a8ff | 2645 | /* HAL_ADC_LevelOutOfWindowCallback(). */ |
bogdanm | 0:9b334a45a8ff | 2646 | /* For example: "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD1) != RESET)" */ |
bogdanm | 0:9b334a45a8ff | 2647 | /* "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD2) != RESET)" */ |
bogdanm | 0:9b334a45a8ff | 2648 | /* "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD3) != RESET)" */ |
bogdanm | 0:9b334a45a8ff | 2649 | /* Test ADC state of Analog Watchdog flags HAL_ADC_STATE_AWD/2/3 into */ |
bogdanm | 0:9b334a45a8ff | 2650 | /* HAL_ADC_LevelOutOfWindowCallback(). */ |
bogdanm | 0:9b334a45a8ff | 2651 | /* For example: "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD) " */ |
bogdanm | 0:9b334a45a8ff | 2652 | /* "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD2)" */ |
bogdanm | 0:9b334a45a8ff | 2653 | /* "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD3)" */ |
bogdanm | 0:9b334a45a8ff | 2654 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2655 | } |
bogdanm | 0:9b334a45a8ff | 2656 | |
bogdanm | 0:9b334a45a8ff | 2657 | |
bogdanm | 0:9b334a45a8ff | 2658 | /* ========== Check Overrun flag ========== */ |
bogdanm | 0:9b334a45a8ff | 2659 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
bogdanm | 0:9b334a45a8ff | 2660 | { |
bogdanm | 0:9b334a45a8ff | 2661 | /* If overrun is set to overwrite previous data (default setting), */ |
bogdanm | 0:9b334a45a8ff | 2662 | /* overrun event is not considered as an error. */ |
bogdanm | 0:9b334a45a8ff | 2663 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
bogdanm | 0:9b334a45a8ff | 2664 | /* overrun ") */ |
bogdanm | 0:9b334a45a8ff | 2665 | /* Exception for usage with DMA overrun event always considered as an */ |
bogdanm | 0:9b334a45a8ff | 2666 | /* error. */ |
bogdanm | 0:9b334a45a8ff | 2667 | if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) || |
bogdanm | 0:9b334a45a8ff | 2668 | HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN) ) |
bogdanm | 0:9b334a45a8ff | 2669 | { |
bogdanm | 0:9b334a45a8ff | 2670 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 2671 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2672 | |
bogdanm | 0:9b334a45a8ff | 2673 | /* Set ADC error code to overrun */ |
bogdanm | 0:9b334a45a8ff | 2674 | hadc->ErrorCode |= HAL_ADC_ERROR_OVR; |
bogdanm | 0:9b334a45a8ff | 2675 | |
bogdanm | 0:9b334a45a8ff | 2676 | /* Error callback */ |
bogdanm | 0:9b334a45a8ff | 2677 | HAL_ADC_ErrorCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2678 | } |
bogdanm | 0:9b334a45a8ff | 2679 | |
bogdanm | 0:9b334a45a8ff | 2680 | /* Clear the Overrun flag */ |
bogdanm | 0:9b334a45a8ff | 2681 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 2682 | |
bogdanm | 0:9b334a45a8ff | 2683 | } |
bogdanm | 0:9b334a45a8ff | 2684 | |
bogdanm | 0:9b334a45a8ff | 2685 | |
bogdanm | 0:9b334a45a8ff | 2686 | /* ========== Check Injected context queue overflow flag ========== */ |
bogdanm | 0:9b334a45a8ff | 2687 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF)) |
bogdanm | 0:9b334a45a8ff | 2688 | { |
bogdanm | 0:9b334a45a8ff | 2689 | /* Change ADC state to overrun state */ |
bogdanm | 0:9b334a45a8ff | 2690 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2691 | |
bogdanm | 0:9b334a45a8ff | 2692 | /* Set ADC error code to Injected context queue overflow */ |
bogdanm | 0:9b334a45a8ff | 2693 | hadc->ErrorCode |= HAL_ADC_ERROR_JQOVF; |
bogdanm | 0:9b334a45a8ff | 2694 | |
bogdanm | 0:9b334a45a8ff | 2695 | /* Clear the Injected context queue overflow flag */ |
bogdanm | 0:9b334a45a8ff | 2696 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); |
bogdanm | 0:9b334a45a8ff | 2697 | |
bogdanm | 0:9b334a45a8ff | 2698 | /* Error callback */ |
bogdanm | 0:9b334a45a8ff | 2699 | HAL_ADCEx_InjectedQueueOverflowCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2700 | } |
bogdanm | 0:9b334a45a8ff | 2701 | |
bogdanm | 0:9b334a45a8ff | 2702 | } |
bogdanm | 0:9b334a45a8ff | 2703 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2704 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2705 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2706 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2707 | |
bogdanm | 0:9b334a45a8ff | 2708 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2709 | /** |
bogdanm | 0:9b334a45a8ff | 2710 | * @brief Handles ADC interrupt request |
bogdanm | 0:9b334a45a8ff | 2711 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2712 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2713 | */ |
bogdanm | 0:9b334a45a8ff | 2714 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2715 | { |
bogdanm | 0:9b334a45a8ff | 2716 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2717 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2718 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 2719 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
bogdanm | 0:9b334a45a8ff | 2720 | |
bogdanm | 0:9b334a45a8ff | 2721 | |
bogdanm | 0:9b334a45a8ff | 2722 | /* ========== Check End of Conversion flag for regular group ========== */ |
bogdanm | 0:9b334a45a8ff | 2723 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) |
bogdanm | 0:9b334a45a8ff | 2724 | { |
bogdanm | 0:9b334a45a8ff | 2725 | /* Check if an injected conversion is ready */ |
bogdanm | 0:9b334a45a8ff | 2726 | if(hadc->State == HAL_ADC_STATE_EOC_INJ) |
bogdanm | 0:9b334a45a8ff | 2727 | { |
bogdanm | 0:9b334a45a8ff | 2728 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2729 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2730 | } |
bogdanm | 0:9b334a45a8ff | 2731 | else |
bogdanm | 0:9b334a45a8ff | 2732 | { |
bogdanm | 0:9b334a45a8ff | 2733 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2734 | hadc->State = HAL_ADC_STATE_EOC_REG; |
bogdanm | 0:9b334a45a8ff | 2735 | } |
bogdanm | 0:9b334a45a8ff | 2736 | |
bogdanm | 0:9b334a45a8ff | 2737 | /* Disable interruption if no further conversion upcoming regular */ |
bogdanm | 0:9b334a45a8ff | 2738 | /* external trigger or by continuous mode */ |
bogdanm | 0:9b334a45a8ff | 2739 | if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 2740 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 2741 | { |
bogdanm | 0:9b334a45a8ff | 2742 | /* Disable ADC end of single conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 2743 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
bogdanm | 0:9b334a45a8ff | 2744 | } |
bogdanm | 0:9b334a45a8ff | 2745 | |
bogdanm | 0:9b334a45a8ff | 2746 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 2747 | HAL_ADC_ConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2748 | |
bogdanm | 0:9b334a45a8ff | 2749 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 2750 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 2751 | } |
bogdanm | 0:9b334a45a8ff | 2752 | |
bogdanm | 0:9b334a45a8ff | 2753 | |
bogdanm | 0:9b334a45a8ff | 2754 | /* ========== Check End of Conversion flag for injected group ========== */ |
bogdanm | 0:9b334a45a8ff | 2755 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) |
bogdanm | 0:9b334a45a8ff | 2756 | { |
bogdanm | 0:9b334a45a8ff | 2757 | /* Check if a regular conversion is ready */ |
bogdanm | 0:9b334a45a8ff | 2758 | if(hadc->State == HAL_ADC_STATE_EOC_REG) |
bogdanm | 0:9b334a45a8ff | 2759 | { |
bogdanm | 0:9b334a45a8ff | 2760 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2761 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 2762 | } |
bogdanm | 0:9b334a45a8ff | 2763 | else |
bogdanm | 0:9b334a45a8ff | 2764 | { |
bogdanm | 0:9b334a45a8ff | 2765 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2766 | hadc->State = HAL_ADC_STATE_EOC_INJ; |
bogdanm | 0:9b334a45a8ff | 2767 | } |
bogdanm | 0:9b334a45a8ff | 2768 | |
bogdanm | 0:9b334a45a8ff | 2769 | /* Disable interruption if no further conversion upcoming injected */ |
bogdanm | 0:9b334a45a8ff | 2770 | /* external trigger or by automatic injected conversion with regular */ |
bogdanm | 0:9b334a45a8ff | 2771 | /* group having no further conversion upcoming (same conditions as */ |
bogdanm | 0:9b334a45a8ff | 2772 | /* regular group interruption disabling above). */ |
bogdanm | 0:9b334a45a8ff | 2773 | if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) || |
bogdanm | 0:9b334a45a8ff | 2774 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
bogdanm | 0:9b334a45a8ff | 2775 | (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 2776 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
bogdanm | 0:9b334a45a8ff | 2777 | { |
bogdanm | 0:9b334a45a8ff | 2778 | /* Disable ADC end of single conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 2779 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
bogdanm | 0:9b334a45a8ff | 2780 | } |
bogdanm | 0:9b334a45a8ff | 2781 | |
bogdanm | 0:9b334a45a8ff | 2782 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 2783 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2784 | |
bogdanm | 0:9b334a45a8ff | 2785 | /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */ |
bogdanm | 0:9b334a45a8ff | 2786 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC)); |
bogdanm | 0:9b334a45a8ff | 2787 | } |
bogdanm | 0:9b334a45a8ff | 2788 | |
bogdanm | 0:9b334a45a8ff | 2789 | |
bogdanm | 0:9b334a45a8ff | 2790 | /* ========== Check Analog watchdog flags ========== */ |
bogdanm | 0:9b334a45a8ff | 2791 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
bogdanm | 0:9b334a45a8ff | 2792 | { |
bogdanm | 0:9b334a45a8ff | 2793 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2794 | hadc->State = HAL_ADC_STATE_AWD; |
bogdanm | 0:9b334a45a8ff | 2795 | |
bogdanm | 0:9b334a45a8ff | 2796 | /* Clear the ADCx's Analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 2797 | __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); |
bogdanm | 0:9b334a45a8ff | 2798 | |
bogdanm | 0:9b334a45a8ff | 2799 | /* Level out of window callback */ |
bogdanm | 0:9b334a45a8ff | 2800 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2801 | } |
bogdanm | 0:9b334a45a8ff | 2802 | |
bogdanm | 0:9b334a45a8ff | 2803 | } |
bogdanm | 0:9b334a45a8ff | 2804 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2805 | |
bogdanm | 0:9b334a45a8ff | 2806 | |
bogdanm | 0:9b334a45a8ff | 2807 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2808 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2809 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2810 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2811 | /** |
bogdanm | 0:9b334a45a8ff | 2812 | * @brief Perform an ADC automatic self-calibration |
bogdanm | 0:9b334a45a8ff | 2813 | * Calibration prerequisite: ADC must be disabled (execute this |
bogdanm | 0:9b334a45a8ff | 2814 | * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). |
bogdanm | 0:9b334a45a8ff | 2815 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2816 | * @param SingleDiff: Selection of single-ended or differential input |
bogdanm | 0:9b334a45a8ff | 2817 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 2818 | * @arg ADC_SINGLE_ENDED: Channel in mode input single ended |
bogdanm | 0:9b334a45a8ff | 2819 | * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended |
bogdanm | 0:9b334a45a8ff | 2820 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 2821 | */ |
bogdanm | 0:9b334a45a8ff | 2822 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) |
bogdanm | 0:9b334a45a8ff | 2823 | { |
bogdanm | 0:9b334a45a8ff | 2824 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2825 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 2826 | |
bogdanm | 0:9b334a45a8ff | 2827 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2828 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2829 | assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); |
bogdanm | 0:9b334a45a8ff | 2830 | |
bogdanm | 0:9b334a45a8ff | 2831 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2832 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2833 | |
bogdanm | 0:9b334a45a8ff | 2834 | /* Calibration prerequisite: ADC must be disabled. */ |
bogdanm | 0:9b334a45a8ff | 2835 | |
bogdanm | 0:9b334a45a8ff | 2836 | /* Disable the ADC (if not already disabled) */ |
bogdanm | 0:9b334a45a8ff | 2837 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2838 | |
bogdanm | 0:9b334a45a8ff | 2839 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2840 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2841 | { |
bogdanm | 0:9b334a45a8ff | 2842 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 2843 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 2844 | |
bogdanm | 0:9b334a45a8ff | 2845 | /* Select calibration mode single ended or differential ended */ |
bogdanm | 0:9b334a45a8ff | 2846 | hadc->Instance->CR &= (~ADC_CR_ADCALDIF); |
bogdanm | 0:9b334a45a8ff | 2847 | if (SingleDiff == ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 2848 | { |
bogdanm | 0:9b334a45a8ff | 2849 | hadc->Instance->CR |= ADC_CR_ADCALDIF; |
bogdanm | 0:9b334a45a8ff | 2850 | } |
bogdanm | 0:9b334a45a8ff | 2851 | |
bogdanm | 0:9b334a45a8ff | 2852 | /* Start ADC calibration */ |
bogdanm | 0:9b334a45a8ff | 2853 | hadc->Instance->CR |= ADC_CR_ADCAL; |
bogdanm | 0:9b334a45a8ff | 2854 | |
bogdanm | 0:9b334a45a8ff | 2855 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 2856 | |
bogdanm | 0:9b334a45a8ff | 2857 | /* Wait for calibration completion */ |
bogdanm | 0:9b334a45a8ff | 2858 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) |
bogdanm | 0:9b334a45a8ff | 2859 | { |
bogdanm | 0:9b334a45a8ff | 2860 | if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 2861 | { |
bogdanm | 0:9b334a45a8ff | 2862 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2863 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2864 | |
bogdanm | 0:9b334a45a8ff | 2865 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2866 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2867 | |
bogdanm | 0:9b334a45a8ff | 2868 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2869 | } |
bogdanm | 0:9b334a45a8ff | 2870 | } |
bogdanm | 0:9b334a45a8ff | 2871 | } |
bogdanm | 0:9b334a45a8ff | 2872 | else |
bogdanm | 0:9b334a45a8ff | 2873 | { |
bogdanm | 0:9b334a45a8ff | 2874 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2875 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2876 | } |
bogdanm | 0:9b334a45a8ff | 2877 | |
bogdanm | 0:9b334a45a8ff | 2878 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2879 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2880 | |
bogdanm | 0:9b334a45a8ff | 2881 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2882 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2883 | } |
bogdanm | 0:9b334a45a8ff | 2884 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 2885 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 2886 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 2887 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 2888 | |
bogdanm | 0:9b334a45a8ff | 2889 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 2890 | /** |
bogdanm | 0:9b334a45a8ff | 2891 | * @brief Perform an ADC automatic self-calibration |
bogdanm | 0:9b334a45a8ff | 2892 | * Calibration prerequisite: ADC must be disabled (execute this |
bogdanm | 0:9b334a45a8ff | 2893 | * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). |
bogdanm | 0:9b334a45a8ff | 2894 | * During calibration process, ADC is enabled. ADC is let enabled at |
bogdanm | 0:9b334a45a8ff | 2895 | * the completion of this function. |
bogdanm | 0:9b334a45a8ff | 2896 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2897 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 2898 | */ |
bogdanm | 0:9b334a45a8ff | 2899 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 2900 | { |
bogdanm | 0:9b334a45a8ff | 2901 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2902 | uint32_t WaitLoopIndex = 0; |
bogdanm | 0:9b334a45a8ff | 2903 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 2904 | |
bogdanm | 0:9b334a45a8ff | 2905 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 2906 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 2907 | |
bogdanm | 0:9b334a45a8ff | 2908 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 2909 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2910 | |
bogdanm | 0:9b334a45a8ff | 2911 | /* 1. Calibration prerequisite: */ |
bogdanm | 0:9b334a45a8ff | 2912 | /* - ADC must be disabled for at least two ADC clock cycles in disable */ |
bogdanm | 0:9b334a45a8ff | 2913 | /* mode before ADC enable */ |
bogdanm | 0:9b334a45a8ff | 2914 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 2915 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2916 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 2917 | |
bogdanm | 0:9b334a45a8ff | 2918 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 2919 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 2920 | { |
bogdanm | 0:9b334a45a8ff | 2921 | |
bogdanm | 0:9b334a45a8ff | 2922 | /* Wait two ADC clock cycles */ |
bogdanm | 0:9b334a45a8ff | 2923 | while(WaitLoopIndex < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2) |
bogdanm | 0:9b334a45a8ff | 2924 | { |
bogdanm | 0:9b334a45a8ff | 2925 | WaitLoopIndex++; |
bogdanm | 0:9b334a45a8ff | 2926 | } |
bogdanm | 0:9b334a45a8ff | 2927 | |
bogdanm | 0:9b334a45a8ff | 2928 | /* 2. Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 2929 | ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 2930 | |
bogdanm | 0:9b334a45a8ff | 2931 | |
bogdanm | 0:9b334a45a8ff | 2932 | /* 3. Resets ADC calibration registers */ |
bogdanm | 0:9b334a45a8ff | 2933 | hadc->Instance->CR2 |= ADC_CR2_RSTCAL; |
bogdanm | 0:9b334a45a8ff | 2934 | |
bogdanm | 0:9b334a45a8ff | 2935 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 2936 | |
bogdanm | 0:9b334a45a8ff | 2937 | /* Wait for calibration reset completion */ |
bogdanm | 0:9b334a45a8ff | 2938 | while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) |
bogdanm | 0:9b334a45a8ff | 2939 | { |
bogdanm | 0:9b334a45a8ff | 2940 | if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 2941 | { |
bogdanm | 0:9b334a45a8ff | 2942 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2943 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2944 | |
bogdanm | 0:9b334a45a8ff | 2945 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2946 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2947 | |
bogdanm | 0:9b334a45a8ff | 2948 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2949 | } |
bogdanm | 0:9b334a45a8ff | 2950 | } |
bogdanm | 0:9b334a45a8ff | 2951 | |
bogdanm | 0:9b334a45a8ff | 2952 | |
bogdanm | 0:9b334a45a8ff | 2953 | /* 4. Start ADC calibration */ |
bogdanm | 0:9b334a45a8ff | 2954 | hadc->Instance->CR2 |= ADC_CR2_CAL; |
bogdanm | 0:9b334a45a8ff | 2955 | |
bogdanm | 0:9b334a45a8ff | 2956 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 2957 | |
bogdanm | 0:9b334a45a8ff | 2958 | /* Wait for calibration completion */ |
bogdanm | 0:9b334a45a8ff | 2959 | while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) |
bogdanm | 0:9b334a45a8ff | 2960 | { |
bogdanm | 0:9b334a45a8ff | 2961 | if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 2962 | { |
bogdanm | 0:9b334a45a8ff | 2963 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2964 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 2965 | |
bogdanm | 0:9b334a45a8ff | 2966 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2967 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2968 | |
bogdanm | 0:9b334a45a8ff | 2969 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2970 | } |
bogdanm | 0:9b334a45a8ff | 2971 | } |
bogdanm | 0:9b334a45a8ff | 2972 | |
bogdanm | 0:9b334a45a8ff | 2973 | } |
bogdanm | 0:9b334a45a8ff | 2974 | |
bogdanm | 0:9b334a45a8ff | 2975 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 2976 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 2977 | |
bogdanm | 0:9b334a45a8ff | 2978 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 2979 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 2980 | } |
bogdanm | 0:9b334a45a8ff | 2981 | |
bogdanm | 0:9b334a45a8ff | 2982 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 2983 | |
bogdanm | 0:9b334a45a8ff | 2984 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 2985 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 2986 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 2987 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 2988 | /** |
bogdanm | 0:9b334a45a8ff | 2989 | * @brief Get the calibration factor from automatic conversion result |
bogdanm | 0:9b334a45a8ff | 2990 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 2991 | * @param SingleDiff: Selection of single-ended or differential input |
bogdanm | 0:9b334a45a8ff | 2992 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 2993 | * @arg ADC_SINGLE_ENDED: Channel in mode input single ended |
bogdanm | 0:9b334a45a8ff | 2994 | * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended |
bogdanm | 0:9b334a45a8ff | 2995 | * @retval Converted value |
bogdanm | 0:9b334a45a8ff | 2996 | */ |
bogdanm | 0:9b334a45a8ff | 2997 | uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) |
bogdanm | 0:9b334a45a8ff | 2998 | { |
bogdanm | 0:9b334a45a8ff | 2999 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3000 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3001 | assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); |
bogdanm | 0:9b334a45a8ff | 3002 | |
bogdanm | 0:9b334a45a8ff | 3003 | /* Return the selected ADC calibration value */ |
bogdanm | 0:9b334a45a8ff | 3004 | if (SingleDiff == ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 3005 | { |
bogdanm | 0:9b334a45a8ff | 3006 | return __HAL_ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); |
bogdanm | 0:9b334a45a8ff | 3007 | } |
bogdanm | 0:9b334a45a8ff | 3008 | else |
bogdanm | 0:9b334a45a8ff | 3009 | { |
bogdanm | 0:9b334a45a8ff | 3010 | return ((hadc->Instance->CALFACT) & 0x0000007F); |
bogdanm | 0:9b334a45a8ff | 3011 | } |
bogdanm | 0:9b334a45a8ff | 3012 | } |
bogdanm | 0:9b334a45a8ff | 3013 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3014 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3015 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3016 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3017 | |
bogdanm | 0:9b334a45a8ff | 3018 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3019 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3020 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3021 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3022 | /** |
bogdanm | 0:9b334a45a8ff | 3023 | * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going. |
bogdanm | 0:9b334a45a8ff | 3024 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3025 | * @param SingleDiff: Selection of single-ended or differential input |
bogdanm | 0:9b334a45a8ff | 3026 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 3027 | * @arg ADC_SINGLE_ENDED: Channel in mode input single ended |
bogdanm | 0:9b334a45a8ff | 3028 | * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended |
bogdanm | 0:9b334a45a8ff | 3029 | * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum) |
bogdanm | 0:9b334a45a8ff | 3030 | * @retval HAL state |
bogdanm | 0:9b334a45a8ff | 3031 | */ |
bogdanm | 0:9b334a45a8ff | 3032 | HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) |
bogdanm | 0:9b334a45a8ff | 3033 | { |
bogdanm | 0:9b334a45a8ff | 3034 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3035 | |
bogdanm | 0:9b334a45a8ff | 3036 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3037 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3038 | assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); |
bogdanm | 0:9b334a45a8ff | 3039 | assert_param(IS_ADC_CALFACT(CalibrationFactor)); |
bogdanm | 0:9b334a45a8ff | 3040 | |
bogdanm | 0:9b334a45a8ff | 3041 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3042 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3043 | |
bogdanm | 0:9b334a45a8ff | 3044 | /* Verification of hardware constraints before modifying the calibration */ |
bogdanm | 0:9b334a45a8ff | 3045 | /* factors register: ADC must be enabled, no conversion on going. */ |
bogdanm | 0:9b334a45a8ff | 3046 | if ( (__HAL_ADC_IS_ENABLED(hadc) != RESET) && |
bogdanm | 0:9b334a45a8ff | 3047 | (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) ) |
bogdanm | 0:9b334a45a8ff | 3048 | { |
bogdanm | 0:9b334a45a8ff | 3049 | /* Set the selected ADC calibration value */ |
bogdanm | 0:9b334a45a8ff | 3050 | if (SingleDiff == ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 3051 | { |
bogdanm | 0:9b334a45a8ff | 3052 | hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT_D; |
bogdanm | 0:9b334a45a8ff | 3053 | hadc->Instance->CALFACT |= __HAL_ADC_CALFACT_DIFF_SET(CalibrationFactor); |
bogdanm | 0:9b334a45a8ff | 3054 | } |
bogdanm | 0:9b334a45a8ff | 3055 | else |
bogdanm | 0:9b334a45a8ff | 3056 | { |
bogdanm | 0:9b334a45a8ff | 3057 | hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT_S; |
bogdanm | 0:9b334a45a8ff | 3058 | hadc->Instance->CALFACT |= CalibrationFactor; |
bogdanm | 0:9b334a45a8ff | 3059 | } |
bogdanm | 0:9b334a45a8ff | 3060 | } |
bogdanm | 0:9b334a45a8ff | 3061 | else |
bogdanm | 0:9b334a45a8ff | 3062 | { |
bogdanm | 0:9b334a45a8ff | 3063 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 3064 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 3065 | |
bogdanm | 0:9b334a45a8ff | 3066 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 3067 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3068 | } |
bogdanm | 0:9b334a45a8ff | 3069 | |
bogdanm | 0:9b334a45a8ff | 3070 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3071 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3072 | |
bogdanm | 0:9b334a45a8ff | 3073 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3074 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3075 | } |
bogdanm | 0:9b334a45a8ff | 3076 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3077 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3078 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3079 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3080 | |
bogdanm | 0:9b334a45a8ff | 3081 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3082 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3083 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3084 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3085 | /** |
bogdanm | 0:9b334a45a8ff | 3086 | * @brief Enables ADC, starts conversion of injected group. |
bogdanm | 0:9b334a45a8ff | 3087 | * Interruptions enabled in this function: None. |
bogdanm | 0:9b334a45a8ff | 3088 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 3089 | * function must be called for ADC slave first, then ADC master. |
bogdanm | 0:9b334a45a8ff | 3090 | * For ADC slave, ADC is enabled only (conversion is not started). |
bogdanm | 0:9b334a45a8ff | 3091 | * For ADC master, ADC is enabled and multimode conversion is started. |
bogdanm | 0:9b334a45a8ff | 3092 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3093 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 3094 | */ |
bogdanm | 0:9b334a45a8ff | 3095 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3096 | { |
bogdanm | 0:9b334a45a8ff | 3097 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3098 | |
bogdanm | 0:9b334a45a8ff | 3099 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3100 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3101 | |
bogdanm | 0:9b334a45a8ff | 3102 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3103 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3104 | |
bogdanm | 0:9b334a45a8ff | 3105 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3106 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 3107 | |
bogdanm | 0:9b334a45a8ff | 3108 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 3109 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3110 | { |
bogdanm | 0:9b334a45a8ff | 3111 | /* Check if a regular conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 3112 | if(hadc->State == HAL_ADC_STATE_BUSY_REG) |
bogdanm | 0:9b334a45a8ff | 3113 | { |
bogdanm | 0:9b334a45a8ff | 3114 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3115 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3116 | } |
bogdanm | 0:9b334a45a8ff | 3117 | else |
bogdanm | 0:9b334a45a8ff | 3118 | { |
bogdanm | 0:9b334a45a8ff | 3119 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3120 | hadc->State = HAL_ADC_STATE_BUSY_INJ; |
bogdanm | 0:9b334a45a8ff | 3121 | } |
bogdanm | 0:9b334a45a8ff | 3122 | |
bogdanm | 0:9b334a45a8ff | 3123 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 3124 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 3125 | |
bogdanm | 0:9b334a45a8ff | 3126 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 3127 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 3128 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); |
bogdanm | 0:9b334a45a8ff | 3129 | |
bogdanm | 0:9b334a45a8ff | 3130 | /* Enable conversion of injected group, if automatic injected conversion */ |
bogdanm | 0:9b334a45a8ff | 3131 | /* is disabled. */ |
bogdanm | 0:9b334a45a8ff | 3132 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 3133 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 3134 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 3135 | /* Case of multimode enabled (for devices with several ADCs): if ADC is */ |
bogdanm | 0:9b334a45a8ff | 3136 | /* slave, ADC is enabled only (conversion is not started). If ADC is */ |
bogdanm | 0:9b334a45a8ff | 3137 | /* master, ADC is enabled and conversion is started. */ |
bogdanm | 0:9b334a45a8ff | 3138 | if ( |
bogdanm | 0:9b334a45a8ff | 3139 | HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) && |
bogdanm | 0:9b334a45a8ff | 3140 | __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
bogdanm | 0:9b334a45a8ff | 3141 | { |
bogdanm | 0:9b334a45a8ff | 3142 | hadc->Instance->CR |= ADC_CR_JADSTART; |
bogdanm | 0:9b334a45a8ff | 3143 | } |
bogdanm | 0:9b334a45a8ff | 3144 | } |
bogdanm | 0:9b334a45a8ff | 3145 | |
bogdanm | 0:9b334a45a8ff | 3146 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3147 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3148 | |
bogdanm | 0:9b334a45a8ff | 3149 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3150 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3151 | } |
bogdanm | 0:9b334a45a8ff | 3152 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3153 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3154 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3155 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3156 | |
bogdanm | 0:9b334a45a8ff | 3157 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 3158 | /** |
bogdanm | 0:9b334a45a8ff | 3159 | * @brief Enables ADC, starts conversion of injected group. |
bogdanm | 0:9b334a45a8ff | 3160 | * Interruptions enabled in this function: None. |
bogdanm | 0:9b334a45a8ff | 3161 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3162 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 3163 | */ |
bogdanm | 0:9b334a45a8ff | 3164 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3165 | { |
bogdanm | 0:9b334a45a8ff | 3166 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3167 | |
bogdanm | 0:9b334a45a8ff | 3168 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3169 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3170 | |
bogdanm | 0:9b334a45a8ff | 3171 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3172 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3173 | |
bogdanm | 0:9b334a45a8ff | 3174 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3175 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 3176 | |
bogdanm | 0:9b334a45a8ff | 3177 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 3178 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3179 | { |
bogdanm | 0:9b334a45a8ff | 3180 | /* Check if a regular conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 3181 | if(hadc->State == HAL_ADC_STATE_BUSY_REG) |
bogdanm | 0:9b334a45a8ff | 3182 | { |
bogdanm | 0:9b334a45a8ff | 3183 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3184 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3185 | } |
bogdanm | 0:9b334a45a8ff | 3186 | else |
bogdanm | 0:9b334a45a8ff | 3187 | { |
bogdanm | 0:9b334a45a8ff | 3188 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3189 | hadc->State = HAL_ADC_STATE_BUSY_INJ; |
bogdanm | 0:9b334a45a8ff | 3190 | } |
bogdanm | 0:9b334a45a8ff | 3191 | |
bogdanm | 0:9b334a45a8ff | 3192 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 3193 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 3194 | |
bogdanm | 0:9b334a45a8ff | 3195 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 3196 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 3197 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); |
bogdanm | 0:9b334a45a8ff | 3198 | |
bogdanm | 0:9b334a45a8ff | 3199 | /* Start conversion of injected group if software start has been selected */ |
bogdanm | 0:9b334a45a8ff | 3200 | /* and if automatic injected conversion is disabled. */ |
bogdanm | 0:9b334a45a8ff | 3201 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 3202 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 3203 | /* If automatic injected conversion is enabled, conversion will start */ |
bogdanm | 0:9b334a45a8ff | 3204 | /* after next regular group conversion. */ |
bogdanm | 0:9b334a45a8ff | 3205 | if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
bogdanm | 0:9b334a45a8ff | 3206 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
bogdanm | 0:9b334a45a8ff | 3207 | { |
bogdanm | 0:9b334a45a8ff | 3208 | /* Enable ADC software conversion for injected channels */ |
bogdanm | 0:9b334a45a8ff | 3209 | hadc->Instance->CR2 |= ADC_CR2_JSWSTART; |
bogdanm | 0:9b334a45a8ff | 3210 | } |
bogdanm | 0:9b334a45a8ff | 3211 | } |
bogdanm | 0:9b334a45a8ff | 3212 | |
bogdanm | 0:9b334a45a8ff | 3213 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3214 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3215 | |
bogdanm | 0:9b334a45a8ff | 3216 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3217 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3218 | } |
bogdanm | 0:9b334a45a8ff | 3219 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 3220 | |
bogdanm | 0:9b334a45a8ff | 3221 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3222 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3223 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3224 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3225 | /** |
bogdanm | 0:9b334a45a8ff | 3226 | * @brief Stop conversion of injected channels. Disable ADC peripheral if |
bogdanm | 0:9b334a45a8ff | 3227 | * no regular conversion is on going. |
bogdanm | 0:9b334a45a8ff | 3228 | * @note If ADC must be disabled with this function and if regular conversion |
bogdanm | 0:9b334a45a8ff | 3229 | * is on going, function HAL_ADC_Stop must be used preliminarily. |
bogdanm | 0:9b334a45a8ff | 3230 | * @note In case of auto-injection mode, HAL_ADC_Stop must be used. |
bogdanm | 0:9b334a45a8ff | 3231 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 3232 | * function must be called for ADC master first, then ADC slave. |
bogdanm | 0:9b334a45a8ff | 3233 | * For ADC master, conversion is stopped and ADC is disabled. |
bogdanm | 0:9b334a45a8ff | 3234 | * For ADC slave, ADC is disabled only (conversion stop of ADC master |
bogdanm | 0:9b334a45a8ff | 3235 | * has already stopped conversion of ADC slave). |
bogdanm | 0:9b334a45a8ff | 3236 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3237 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3238 | */ |
bogdanm | 0:9b334a45a8ff | 3239 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3240 | { |
bogdanm | 0:9b334a45a8ff | 3241 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3242 | |
bogdanm | 0:9b334a45a8ff | 3243 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3244 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3245 | |
bogdanm | 0:9b334a45a8ff | 3246 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3247 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3248 | |
bogdanm | 0:9b334a45a8ff | 3249 | /* 1. Stop potential conversion on going on injected group only. */ |
bogdanm | 0:9b334a45a8ff | 3250 | tmpHALStatus = ADC_ConversionStop(hadc, INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 3251 | |
bogdanm | 0:9b334a45a8ff | 3252 | /* Disable ADC peripheral if injected conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 3253 | /* and if no conversion on the other group (regular group) is intended to */ |
bogdanm | 0:9b334a45a8ff | 3254 | /* continue. */ |
bogdanm | 0:9b334a45a8ff | 3255 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3256 | { |
bogdanm | 0:9b334a45a8ff | 3257 | if((__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 3258 | (hadc->State != HAL_ADC_STATE_BUSY_REG) && |
bogdanm | 0:9b334a45a8ff | 3259 | (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) ) |
bogdanm | 0:9b334a45a8ff | 3260 | { |
bogdanm | 0:9b334a45a8ff | 3261 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3262 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 3263 | |
bogdanm | 0:9b334a45a8ff | 3264 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 3265 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3266 | { |
bogdanm | 0:9b334a45a8ff | 3267 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3268 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 3269 | } |
bogdanm | 0:9b334a45a8ff | 3270 | } |
bogdanm | 0:9b334a45a8ff | 3271 | /* Conversion on injected group is stopped, but ADC not disabled since */ |
bogdanm | 0:9b334a45a8ff | 3272 | /* conversion on regular group is still running. */ |
bogdanm | 0:9b334a45a8ff | 3273 | else |
bogdanm | 0:9b334a45a8ff | 3274 | { |
bogdanm | 0:9b334a45a8ff | 3275 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 3276 | } |
bogdanm | 0:9b334a45a8ff | 3277 | } |
bogdanm | 0:9b334a45a8ff | 3278 | |
bogdanm | 0:9b334a45a8ff | 3279 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3280 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3281 | |
bogdanm | 0:9b334a45a8ff | 3282 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3283 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3284 | } |
bogdanm | 0:9b334a45a8ff | 3285 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3286 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3287 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3288 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3289 | |
bogdanm | 0:9b334a45a8ff | 3290 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 3291 | /** |
bogdanm | 0:9b334a45a8ff | 3292 | * @brief Stop conversion of injected channels. Disable ADC peripheral if |
bogdanm | 0:9b334a45a8ff | 3293 | * no regular conversion is on going. |
bogdanm | 0:9b334a45a8ff | 3294 | * @note If ADC must be disabled with this function and if regular conversion |
bogdanm | 0:9b334a45a8ff | 3295 | * is on going, function HAL_ADC_Stop must be used preliminarily. |
bogdanm | 0:9b334a45a8ff | 3296 | * @note In case of auto-injection mode, HAL_ADC_Stop must be used. |
bogdanm | 0:9b334a45a8ff | 3297 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3298 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3299 | */ |
bogdanm | 0:9b334a45a8ff | 3300 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3301 | { |
bogdanm | 0:9b334a45a8ff | 3302 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3303 | |
bogdanm | 0:9b334a45a8ff | 3304 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3305 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3306 | |
bogdanm | 0:9b334a45a8ff | 3307 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3308 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3309 | |
bogdanm | 0:9b334a45a8ff | 3310 | /* Stop potential conversion and disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3311 | /* Conditioned to: */ |
bogdanm | 0:9b334a45a8ff | 3312 | /* - No conversion on the other group (regular group) is intended to */ |
bogdanm | 0:9b334a45a8ff | 3313 | /* continue (injected and regular groups stop conversion and ADC disable */ |
bogdanm | 0:9b334a45a8ff | 3314 | /* are common) */ |
bogdanm | 0:9b334a45a8ff | 3315 | /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ |
bogdanm | 0:9b334a45a8ff | 3316 | if((hadc->State != HAL_ADC_STATE_BUSY_REG) && |
bogdanm | 0:9b334a45a8ff | 3317 | (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && |
bogdanm | 0:9b334a45a8ff | 3318 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
bogdanm | 0:9b334a45a8ff | 3319 | { |
bogdanm | 0:9b334a45a8ff | 3320 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 3321 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3322 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 3323 | |
bogdanm | 0:9b334a45a8ff | 3324 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 3325 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3326 | { |
bogdanm | 0:9b334a45a8ff | 3327 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3328 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 3329 | } |
bogdanm | 0:9b334a45a8ff | 3330 | } |
bogdanm | 0:9b334a45a8ff | 3331 | else |
bogdanm | 0:9b334a45a8ff | 3332 | { |
bogdanm | 0:9b334a45a8ff | 3333 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 3334 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 3335 | |
bogdanm | 0:9b334a45a8ff | 3336 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3337 | } |
bogdanm | 0:9b334a45a8ff | 3338 | |
bogdanm | 0:9b334a45a8ff | 3339 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3340 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3341 | |
bogdanm | 0:9b334a45a8ff | 3342 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3343 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3344 | } |
bogdanm | 0:9b334a45a8ff | 3345 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 3346 | |
bogdanm | 0:9b334a45a8ff | 3347 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3348 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3349 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3350 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3351 | /** |
bogdanm | 0:9b334a45a8ff | 3352 | * @brief Wait for injected group conversion to be completed. |
bogdanm | 0:9b334a45a8ff | 3353 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3354 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 3355 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 3356 | */ |
bogdanm | 0:9b334a45a8ff | 3357 | HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 3358 | { |
bogdanm | 0:9b334a45a8ff | 3359 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 3360 | uint32_t tmp_Flag_EOC; |
bogdanm | 0:9b334a45a8ff | 3361 | |
bogdanm | 0:9b334a45a8ff | 3362 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3363 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3364 | |
bogdanm | 0:9b334a45a8ff | 3365 | /* If end of conversion selected to end of sequence */ |
bogdanm | 0:9b334a45a8ff | 3366 | if (hadc->Init.EOCSelection == EOC_SEQ_CONV) |
bogdanm | 0:9b334a45a8ff | 3367 | { |
bogdanm | 0:9b334a45a8ff | 3368 | tmp_Flag_EOC = ADC_FLAG_JEOS; |
bogdanm | 0:9b334a45a8ff | 3369 | } |
bogdanm | 0:9b334a45a8ff | 3370 | /* If end of conversion selected to end of each conversion */ |
bogdanm | 0:9b334a45a8ff | 3371 | else /* EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 3372 | { |
bogdanm | 0:9b334a45a8ff | 3373 | tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS); |
bogdanm | 0:9b334a45a8ff | 3374 | } |
bogdanm | 0:9b334a45a8ff | 3375 | |
bogdanm | 0:9b334a45a8ff | 3376 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 3377 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 3378 | |
bogdanm | 0:9b334a45a8ff | 3379 | /* Wait until End of Conversion flag is raised */ |
bogdanm | 0:9b334a45a8ff | 3380 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
bogdanm | 0:9b334a45a8ff | 3381 | { |
bogdanm | 0:9b334a45a8ff | 3382 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 3383 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 3384 | { |
bogdanm | 0:9b334a45a8ff | 3385 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 3386 | { |
bogdanm | 0:9b334a45a8ff | 3387 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 3388 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 3389 | |
bogdanm | 0:9b334a45a8ff | 3390 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3391 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3392 | |
bogdanm | 0:9b334a45a8ff | 3393 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3394 | } |
bogdanm | 0:9b334a45a8ff | 3395 | } |
bogdanm | 0:9b334a45a8ff | 3396 | } |
bogdanm | 0:9b334a45a8ff | 3397 | |
bogdanm | 0:9b334a45a8ff | 3398 | /* Clear end of conversion flag of injected group if low power feature */ |
bogdanm | 0:9b334a45a8ff | 3399 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
bogdanm | 0:9b334a45a8ff | 3400 | /* register is read using function HAL_ADC_GetValue(). */ |
bogdanm | 0:9b334a45a8ff | 3401 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
bogdanm | 0:9b334a45a8ff | 3402 | { |
bogdanm | 0:9b334a45a8ff | 3403 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 3404 | __HAL_ADC_CLEAR_FLAG(hadc,(ADC_FLAG_JEOC | ADC_FLAG_JEOS)); |
bogdanm | 0:9b334a45a8ff | 3405 | } |
bogdanm | 0:9b334a45a8ff | 3406 | |
bogdanm | 0:9b334a45a8ff | 3407 | |
bogdanm | 0:9b334a45a8ff | 3408 | /* Update ADC state machine */ |
bogdanm | 0:9b334a45a8ff | 3409 | if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) |
bogdanm | 0:9b334a45a8ff | 3410 | { |
bogdanm | 0:9b334a45a8ff | 3411 | /* Check if a conversion is ready on regular group */ |
bogdanm | 0:9b334a45a8ff | 3412 | if(hadc->State == HAL_ADC_STATE_EOC_REG) |
bogdanm | 0:9b334a45a8ff | 3413 | { |
bogdanm | 0:9b334a45a8ff | 3414 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3415 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3416 | } |
bogdanm | 0:9b334a45a8ff | 3417 | else |
bogdanm | 0:9b334a45a8ff | 3418 | { |
bogdanm | 0:9b334a45a8ff | 3419 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3420 | hadc->State = HAL_ADC_STATE_EOC_INJ; |
bogdanm | 0:9b334a45a8ff | 3421 | } |
bogdanm | 0:9b334a45a8ff | 3422 | } |
bogdanm | 0:9b334a45a8ff | 3423 | |
bogdanm | 0:9b334a45a8ff | 3424 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 3425 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3426 | } |
bogdanm | 0:9b334a45a8ff | 3427 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3428 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3429 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3430 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3431 | |
bogdanm | 0:9b334a45a8ff | 3432 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 3433 | /** |
bogdanm | 0:9b334a45a8ff | 3434 | * @brief Wait for injected group conversion to be completed. |
bogdanm | 0:9b334a45a8ff | 3435 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3436 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 3437 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 3438 | */ |
bogdanm | 0:9b334a45a8ff | 3439 | HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 3440 | { |
bogdanm | 0:9b334a45a8ff | 3441 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 3442 | |
bogdanm | 0:9b334a45a8ff | 3443 | /* Variables for polling in case of scan mode enabled */ |
bogdanm | 0:9b334a45a8ff | 3444 | uint32_t Conversion_Timeout_CPU_cycles_max =0; |
bogdanm | 0:9b334a45a8ff | 3445 | uint32_t Conversion_Timeout_CPU_cycles =0; |
bogdanm | 0:9b334a45a8ff | 3446 | |
bogdanm | 0:9b334a45a8ff | 3447 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3448 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3449 | |
bogdanm | 0:9b334a45a8ff | 3450 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 3451 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 3452 | |
bogdanm | 0:9b334a45a8ff | 3453 | /* Polling for end of conversion: differentiation if single/sequence */ |
bogdanm | 0:9b334a45a8ff | 3454 | /* conversion. */ |
bogdanm | 0:9b334a45a8ff | 3455 | /* For injected group, flag JEOC is set only at the end of the sequence, */ |
bogdanm | 0:9b334a45a8ff | 3456 | /* not for each conversion within the sequence. */ |
bogdanm | 0:9b334a45a8ff | 3457 | /* - If single conversion for injected group (scan mode disabled or */ |
bogdanm | 0:9b334a45a8ff | 3458 | /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */ |
bogdanm | 0:9b334a45a8ff | 3459 | /* conversion completion. */ |
bogdanm | 0:9b334a45a8ff | 3460 | /* - If sequence conversion for injected group (scan mode enabled and */ |
bogdanm | 0:9b334a45a8ff | 3461 | /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ |
bogdanm | 0:9b334a45a8ff | 3462 | /* sequence. */ |
bogdanm | 0:9b334a45a8ff | 3463 | /* To poll for each conversion, the maximum conversion time is computed */ |
bogdanm | 0:9b334a45a8ff | 3464 | /* from ADC conversion time (selected sampling time + conversion time of */ |
bogdanm | 0:9b334a45a8ff | 3465 | /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ |
bogdanm | 0:9b334a45a8ff | 3466 | /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ |
bogdanm | 0:9b334a45a8ff | 3467 | if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) |
bogdanm | 0:9b334a45a8ff | 3468 | { |
bogdanm | 0:9b334a45a8ff | 3469 | /* Wait until End of Conversion flag is raised */ |
bogdanm | 0:9b334a45a8ff | 3470 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) |
bogdanm | 0:9b334a45a8ff | 3471 | { |
bogdanm | 0:9b334a45a8ff | 3472 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 3473 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 3474 | { |
bogdanm | 0:9b334a45a8ff | 3475 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 3476 | { |
bogdanm | 0:9b334a45a8ff | 3477 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 3478 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 3479 | |
bogdanm | 0:9b334a45a8ff | 3480 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3481 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3482 | |
bogdanm | 0:9b334a45a8ff | 3483 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3484 | } |
bogdanm | 0:9b334a45a8ff | 3485 | } |
bogdanm | 0:9b334a45a8ff | 3486 | } |
bogdanm | 0:9b334a45a8ff | 3487 | } |
bogdanm | 0:9b334a45a8ff | 3488 | else |
bogdanm | 0:9b334a45a8ff | 3489 | { |
bogdanm | 0:9b334a45a8ff | 3490 | /* Calculation of CPU cycles corresponding to ADC conversion cycles. */ |
bogdanm | 0:9b334a45a8ff | 3491 | /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ |
bogdanm | 0:9b334a45a8ff | 3492 | /* channels. */ |
bogdanm | 0:9b334a45a8ff | 3493 | Conversion_Timeout_CPU_cycles_max = __HAL_ADC_CLOCK_PRECSALER_RANGE() ; |
bogdanm | 0:9b334a45a8ff | 3494 | Conversion_Timeout_CPU_cycles_max *= __HAL_ADC_CONVCYCLES_MAX_RANGE(hadc); |
bogdanm | 0:9b334a45a8ff | 3495 | |
bogdanm | 0:9b334a45a8ff | 3496 | /* Maximum conversion cycles taking in account offset of 34 CPU cycles: */ |
bogdanm | 0:9b334a45a8ff | 3497 | /* number of CPU cycles for processing of conversion cycles estimation. */ |
bogdanm | 0:9b334a45a8ff | 3498 | Conversion_Timeout_CPU_cycles = 34; |
bogdanm | 0:9b334a45a8ff | 3499 | |
bogdanm | 0:9b334a45a8ff | 3500 | /* Poll with maximum conversion time */ |
bogdanm | 0:9b334a45a8ff | 3501 | while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) |
bogdanm | 0:9b334a45a8ff | 3502 | { |
bogdanm | 0:9b334a45a8ff | 3503 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 3504 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 3505 | { |
bogdanm | 0:9b334a45a8ff | 3506 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 3507 | { |
bogdanm | 0:9b334a45a8ff | 3508 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 3509 | hadc->State = HAL_ADC_STATE_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 3510 | |
bogdanm | 0:9b334a45a8ff | 3511 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3512 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3513 | |
bogdanm | 0:9b334a45a8ff | 3514 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3515 | } |
bogdanm | 0:9b334a45a8ff | 3516 | } |
bogdanm | 0:9b334a45a8ff | 3517 | Conversion_Timeout_CPU_cycles ++; |
bogdanm | 0:9b334a45a8ff | 3518 | } |
bogdanm | 0:9b334a45a8ff | 3519 | } |
bogdanm | 0:9b334a45a8ff | 3520 | |
bogdanm | 0:9b334a45a8ff | 3521 | |
bogdanm | 0:9b334a45a8ff | 3522 | /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */ |
bogdanm | 0:9b334a45a8ff | 3523 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); |
bogdanm | 0:9b334a45a8ff | 3524 | |
bogdanm | 0:9b334a45a8ff | 3525 | /* Check if a regular conversion is ready */ |
bogdanm | 0:9b334a45a8ff | 3526 | if(hadc->State == HAL_ADC_STATE_EOC_REG) |
bogdanm | 0:9b334a45a8ff | 3527 | { |
bogdanm | 0:9b334a45a8ff | 3528 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3529 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3530 | } |
bogdanm | 0:9b334a45a8ff | 3531 | else |
bogdanm | 0:9b334a45a8ff | 3532 | { |
bogdanm | 0:9b334a45a8ff | 3533 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3534 | hadc->State = HAL_ADC_STATE_EOC_INJ; |
bogdanm | 0:9b334a45a8ff | 3535 | } |
bogdanm | 0:9b334a45a8ff | 3536 | |
bogdanm | 0:9b334a45a8ff | 3537 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 3538 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3539 | } |
bogdanm | 0:9b334a45a8ff | 3540 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 3541 | |
bogdanm | 0:9b334a45a8ff | 3542 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3543 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3544 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3545 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3546 | /** |
bogdanm | 0:9b334a45a8ff | 3547 | * @brief Enables ADC, starts conversion of injected group with interruption. |
bogdanm | 0:9b334a45a8ff | 3548 | * Interruptions enabled in this function: JEOC (end of conversion). |
bogdanm | 0:9b334a45a8ff | 3549 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 3550 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 3551 | * function must be called for ADC slave first, then ADC master. |
bogdanm | 0:9b334a45a8ff | 3552 | * For ADC slave, ADC is enabled only (conversion is not started). |
bogdanm | 0:9b334a45a8ff | 3553 | * For ADC master, ADC is enabled and multimode conversion is started. |
bogdanm | 0:9b334a45a8ff | 3554 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3555 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 3556 | */ |
bogdanm | 0:9b334a45a8ff | 3557 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3558 | { |
bogdanm | 0:9b334a45a8ff | 3559 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3560 | |
bogdanm | 0:9b334a45a8ff | 3561 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3562 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3563 | |
bogdanm | 0:9b334a45a8ff | 3564 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3565 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3566 | |
bogdanm | 0:9b334a45a8ff | 3567 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3568 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 3569 | |
bogdanm | 0:9b334a45a8ff | 3570 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 3571 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3572 | { |
bogdanm | 0:9b334a45a8ff | 3573 | /* Check if a regular conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 3574 | if(hadc->State == HAL_ADC_STATE_BUSY_REG) |
bogdanm | 0:9b334a45a8ff | 3575 | { |
bogdanm | 0:9b334a45a8ff | 3576 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3577 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3578 | } |
bogdanm | 0:9b334a45a8ff | 3579 | else |
bogdanm | 0:9b334a45a8ff | 3580 | { |
bogdanm | 0:9b334a45a8ff | 3581 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3582 | hadc->State = HAL_ADC_STATE_BUSY_INJ; |
bogdanm | 0:9b334a45a8ff | 3583 | } |
bogdanm | 0:9b334a45a8ff | 3584 | |
bogdanm | 0:9b334a45a8ff | 3585 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 3586 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 3587 | |
bogdanm | 0:9b334a45a8ff | 3588 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 3589 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 3590 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); |
bogdanm | 0:9b334a45a8ff | 3591 | |
bogdanm | 0:9b334a45a8ff | 3592 | /* Enable ADC Injected context queue overflow interrupt if this feature */ |
bogdanm | 0:9b334a45a8ff | 3593 | /* is enabled. */ |
bogdanm | 0:9b334a45a8ff | 3594 | if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) |
bogdanm | 0:9b334a45a8ff | 3595 | { |
bogdanm | 0:9b334a45a8ff | 3596 | __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); |
bogdanm | 0:9b334a45a8ff | 3597 | } |
bogdanm | 0:9b334a45a8ff | 3598 | |
bogdanm | 0:9b334a45a8ff | 3599 | /* Enable ADC end of conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 3600 | switch(hadc->Init.EOCSelection) |
bogdanm | 0:9b334a45a8ff | 3601 | { |
bogdanm | 0:9b334a45a8ff | 3602 | case EOC_SEQ_CONV: |
bogdanm | 0:9b334a45a8ff | 3603 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
bogdanm | 0:9b334a45a8ff | 3604 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); |
bogdanm | 0:9b334a45a8ff | 3605 | break; |
bogdanm | 0:9b334a45a8ff | 3606 | /* case EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 3607 | default: |
bogdanm | 0:9b334a45a8ff | 3608 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); |
bogdanm | 0:9b334a45a8ff | 3609 | break; |
bogdanm | 0:9b334a45a8ff | 3610 | } |
bogdanm | 0:9b334a45a8ff | 3611 | |
bogdanm | 0:9b334a45a8ff | 3612 | /* Enable conversion of injected group, if automatic injected conversion */ |
bogdanm | 0:9b334a45a8ff | 3613 | /* is disabled. */ |
bogdanm | 0:9b334a45a8ff | 3614 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 3615 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 3616 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 3617 | /* Case of multimode enabled (for devices with several ADCs): if ADC is */ |
bogdanm | 0:9b334a45a8ff | 3618 | /* slave, ADC is enabled only (conversion is not started). If ADC is */ |
bogdanm | 0:9b334a45a8ff | 3619 | /* master, ADC is enabled and conversion is started. */ |
bogdanm | 0:9b334a45a8ff | 3620 | if ( |
bogdanm | 0:9b334a45a8ff | 3621 | HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) && |
bogdanm | 0:9b334a45a8ff | 3622 | __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
bogdanm | 0:9b334a45a8ff | 3623 | { |
bogdanm | 0:9b334a45a8ff | 3624 | hadc->Instance->CR |= ADC_CR_JADSTART; |
bogdanm | 0:9b334a45a8ff | 3625 | } |
bogdanm | 0:9b334a45a8ff | 3626 | } |
bogdanm | 0:9b334a45a8ff | 3627 | |
bogdanm | 0:9b334a45a8ff | 3628 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3629 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3630 | |
bogdanm | 0:9b334a45a8ff | 3631 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3632 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3633 | } |
bogdanm | 0:9b334a45a8ff | 3634 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3635 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3636 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3637 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3638 | |
bogdanm | 0:9b334a45a8ff | 3639 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 3640 | /** |
bogdanm | 0:9b334a45a8ff | 3641 | * @brief Enables ADC, starts conversion of injected group with interruption. |
bogdanm | 0:9b334a45a8ff | 3642 | * Interruptions enabled in this function: JEOC (end of conversion), |
bogdanm | 0:9b334a45a8ff | 3643 | * overrun (if available). |
bogdanm | 0:9b334a45a8ff | 3644 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 3645 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3646 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 3647 | */ |
bogdanm | 0:9b334a45a8ff | 3648 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3649 | { |
bogdanm | 0:9b334a45a8ff | 3650 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3651 | |
bogdanm | 0:9b334a45a8ff | 3652 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3653 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3654 | |
bogdanm | 0:9b334a45a8ff | 3655 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3656 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3657 | |
bogdanm | 0:9b334a45a8ff | 3658 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3659 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 3660 | |
bogdanm | 0:9b334a45a8ff | 3661 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 3662 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3663 | { |
bogdanm | 0:9b334a45a8ff | 3664 | /* Check if a regular conversion is ongoing */ |
bogdanm | 0:9b334a45a8ff | 3665 | if(hadc->State == HAL_ADC_STATE_BUSY_REG) |
bogdanm | 0:9b334a45a8ff | 3666 | { |
bogdanm | 0:9b334a45a8ff | 3667 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3668 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3669 | } |
bogdanm | 0:9b334a45a8ff | 3670 | else |
bogdanm | 0:9b334a45a8ff | 3671 | { |
bogdanm | 0:9b334a45a8ff | 3672 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3673 | hadc->State = HAL_ADC_STATE_BUSY_INJ; |
bogdanm | 0:9b334a45a8ff | 3674 | } |
bogdanm | 0:9b334a45a8ff | 3675 | |
bogdanm | 0:9b334a45a8ff | 3676 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 3677 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 3678 | |
bogdanm | 0:9b334a45a8ff | 3679 | /* Clear injected group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 3680 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 3681 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); |
bogdanm | 0:9b334a45a8ff | 3682 | |
bogdanm | 0:9b334a45a8ff | 3683 | /* Enable end of conversion interrupt for injected channels */ |
bogdanm | 0:9b334a45a8ff | 3684 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); |
bogdanm | 0:9b334a45a8ff | 3685 | |
bogdanm | 0:9b334a45a8ff | 3686 | /* Start conversion of injected group if software start has been selected */ |
bogdanm | 0:9b334a45a8ff | 3687 | /* and if automatic injected conversion is disabled. */ |
bogdanm | 0:9b334a45a8ff | 3688 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 3689 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 3690 | /* If automatic injected conversion is enabled, conversion will start */ |
bogdanm | 0:9b334a45a8ff | 3691 | /* after next regular group conversion. */ |
bogdanm | 0:9b334a45a8ff | 3692 | if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
bogdanm | 0:9b334a45a8ff | 3693 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
bogdanm | 0:9b334a45a8ff | 3694 | { |
bogdanm | 0:9b334a45a8ff | 3695 | /* Enable ADC software conversion for injected channels */ |
bogdanm | 0:9b334a45a8ff | 3696 | hadc->Instance->CR2 |= ADC_CR2_JSWSTART; |
bogdanm | 0:9b334a45a8ff | 3697 | } |
bogdanm | 0:9b334a45a8ff | 3698 | } |
bogdanm | 0:9b334a45a8ff | 3699 | |
bogdanm | 0:9b334a45a8ff | 3700 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3701 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3702 | |
bogdanm | 0:9b334a45a8ff | 3703 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3704 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3705 | } |
bogdanm | 0:9b334a45a8ff | 3706 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 3707 | |
bogdanm | 0:9b334a45a8ff | 3708 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3709 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3710 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 3711 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 3712 | /** |
bogdanm | 0:9b334a45a8ff | 3713 | * @brief Stop conversion of injected channels, disable interruption of |
bogdanm | 0:9b334a45a8ff | 3714 | * end-of-conversion. Disable ADC peripheral if no regular conversion |
bogdanm | 0:9b334a45a8ff | 3715 | * is on going. |
bogdanm | 0:9b334a45a8ff | 3716 | * @note If ADC must be disabled with this function and if regular conversion |
bogdanm | 0:9b334a45a8ff | 3717 | * is on going, function HAL_ADC_Stop must be used preliminarily. |
bogdanm | 0:9b334a45a8ff | 3718 | * @note: Case of multimode enabled (for devices with several ADCs): This |
bogdanm | 0:9b334a45a8ff | 3719 | * function must be called for ADC master first, then ADC slave. |
bogdanm | 0:9b334a45a8ff | 3720 | * For ADC master, conversion is stopped and ADC is disabled. |
bogdanm | 0:9b334a45a8ff | 3721 | * For ADC slave, ADC is disabled only (conversion stop of ADC master |
bogdanm | 0:9b334a45a8ff | 3722 | * has already stopped conversion of ADC slave). |
bogdanm | 0:9b334a45a8ff | 3723 | * @note In case of auto-injection mode, HAL_ADC_Stop must be used. |
bogdanm | 0:9b334a45a8ff | 3724 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3725 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3726 | */ |
bogdanm | 0:9b334a45a8ff | 3727 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3728 | { |
bogdanm | 0:9b334a45a8ff | 3729 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3730 | |
bogdanm | 0:9b334a45a8ff | 3731 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3732 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3733 | |
bogdanm | 0:9b334a45a8ff | 3734 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3735 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3736 | |
bogdanm | 0:9b334a45a8ff | 3737 | /* 1. Stop potential conversion on going on injected group only. */ |
bogdanm | 0:9b334a45a8ff | 3738 | tmpHALStatus = ADC_ConversionStop(hadc, INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 3739 | |
bogdanm | 0:9b334a45a8ff | 3740 | /* Disable ADC peripheral if injected conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 3741 | /* and if no conversion on the other group (regular group) is intended to */ |
bogdanm | 0:9b334a45a8ff | 3742 | /* continue. */ |
bogdanm | 0:9b334a45a8ff | 3743 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3744 | { |
bogdanm | 0:9b334a45a8ff | 3745 | /* Disable ADC end of conversion interrupt for injected channels */ |
bogdanm | 0:9b334a45a8ff | 3746 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS)); |
bogdanm | 0:9b334a45a8ff | 3747 | |
bogdanm | 0:9b334a45a8ff | 3748 | if((__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 3749 | (hadc->State != HAL_ADC_STATE_BUSY_REG) && |
bogdanm | 0:9b334a45a8ff | 3750 | (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) ) |
bogdanm | 0:9b334a45a8ff | 3751 | { |
bogdanm | 0:9b334a45a8ff | 3752 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3753 | tmpHALStatus = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 3754 | |
bogdanm | 0:9b334a45a8ff | 3755 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 3756 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3757 | { |
bogdanm | 0:9b334a45a8ff | 3758 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3759 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 3760 | } |
bogdanm | 0:9b334a45a8ff | 3761 | } |
bogdanm | 0:9b334a45a8ff | 3762 | /* Conversion on injected group is stopped, but ADC not disabled since */ |
bogdanm | 0:9b334a45a8ff | 3763 | /* conversion on regular group is still running. */ |
bogdanm | 0:9b334a45a8ff | 3764 | else |
bogdanm | 0:9b334a45a8ff | 3765 | { |
bogdanm | 0:9b334a45a8ff | 3766 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 3767 | } |
bogdanm | 0:9b334a45a8ff | 3768 | } |
bogdanm | 0:9b334a45a8ff | 3769 | |
bogdanm | 0:9b334a45a8ff | 3770 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3771 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3772 | |
bogdanm | 0:9b334a45a8ff | 3773 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3774 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3775 | } |
bogdanm | 0:9b334a45a8ff | 3776 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 3777 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 3778 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 3779 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 3780 | |
bogdanm | 0:9b334a45a8ff | 3781 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 3782 | /** |
bogdanm | 0:9b334a45a8ff | 3783 | * @brief Stop conversion of injected channels, disable interruption of |
bogdanm | 0:9b334a45a8ff | 3784 | * end-of-conversion. Disable ADC peripheral if no regular conversion |
bogdanm | 0:9b334a45a8ff | 3785 | * is on going. |
bogdanm | 0:9b334a45a8ff | 3786 | * @note If ADC must be disabled with this function and if regular conversion |
bogdanm | 0:9b334a45a8ff | 3787 | * is on going, function HAL_ADC_Stop must be used preliminarily. |
bogdanm | 0:9b334a45a8ff | 3788 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 3789 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3790 | */ |
bogdanm | 0:9b334a45a8ff | 3791 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3792 | { |
bogdanm | 0:9b334a45a8ff | 3793 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3794 | |
bogdanm | 0:9b334a45a8ff | 3795 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3796 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3797 | |
bogdanm | 0:9b334a45a8ff | 3798 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3799 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3800 | |
bogdanm | 0:9b334a45a8ff | 3801 | /* Stop potential conversion and disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3802 | /* Conditioned to: */ |
bogdanm | 0:9b334a45a8ff | 3803 | /* - No conversion on the other group (regular group) is intended to */ |
bogdanm | 0:9b334a45a8ff | 3804 | /* continue (injected and regular groups stop conversion and ADC disable */ |
bogdanm | 0:9b334a45a8ff | 3805 | /* are common) */ |
bogdanm | 0:9b334a45a8ff | 3806 | /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ |
bogdanm | 0:9b334a45a8ff | 3807 | if((hadc->State != HAL_ADC_STATE_BUSY_REG) && |
bogdanm | 0:9b334a45a8ff | 3808 | (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && |
bogdanm | 0:9b334a45a8ff | 3809 | HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) |
bogdanm | 0:9b334a45a8ff | 3810 | { |
bogdanm | 0:9b334a45a8ff | 3811 | /* Stop potential conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 3812 | /* Disable ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 3813 | tmpHALStatus = ADC_ConversionStop_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 3814 | |
bogdanm | 0:9b334a45a8ff | 3815 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 3816 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3817 | { |
bogdanm | 0:9b334a45a8ff | 3818 | /* Disable ADC end of conversion interrupt for injected channels */ |
bogdanm | 0:9b334a45a8ff | 3819 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
bogdanm | 0:9b334a45a8ff | 3820 | |
bogdanm | 0:9b334a45a8ff | 3821 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3822 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 3823 | } |
bogdanm | 0:9b334a45a8ff | 3824 | } |
bogdanm | 0:9b334a45a8ff | 3825 | else |
bogdanm | 0:9b334a45a8ff | 3826 | { |
bogdanm | 0:9b334a45a8ff | 3827 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 3828 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 3829 | |
bogdanm | 0:9b334a45a8ff | 3830 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3831 | } |
bogdanm | 0:9b334a45a8ff | 3832 | |
bogdanm | 0:9b334a45a8ff | 3833 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3834 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3835 | |
bogdanm | 0:9b334a45a8ff | 3836 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3837 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3838 | } |
bogdanm | 0:9b334a45a8ff | 3839 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 3840 | |
bogdanm | 0:9b334a45a8ff | 3841 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 3842 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 3843 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
bogdanm | 0:9b334a45a8ff | 3844 | /** |
bogdanm | 0:9b334a45a8ff | 3845 | * @brief Enables ADC, starts conversion of regular group and transfers result |
bogdanm | 0:9b334a45a8ff | 3846 | * through DMA. |
bogdanm | 0:9b334a45a8ff | 3847 | * Multimode must have been previously configured using |
bogdanm | 0:9b334a45a8ff | 3848 | * HAL_ADCEx_MultiModeConfigChannel() function. |
bogdanm | 0:9b334a45a8ff | 3849 | * Interruptions enabled in this function: |
bogdanm | 0:9b334a45a8ff | 3850 | * overrun, DMA half transfer, DMA transfer complete. |
bogdanm | 0:9b334a45a8ff | 3851 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 3852 | * @note: ADC slave can be enabled preliminarily using single-mode |
bogdanm | 0:9b334a45a8ff | 3853 | * HAL_ADC_Start() function. |
bogdanm | 0:9b334a45a8ff | 3854 | * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) |
bogdanm | 0:9b334a45a8ff | 3855 | * @param pData: The destination Buffer address. |
bogdanm | 0:9b334a45a8ff | 3856 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
bogdanm | 0:9b334a45a8ff | 3857 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3858 | */ |
bogdanm | 0:9b334a45a8ff | 3859 | HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
bogdanm | 0:9b334a45a8ff | 3860 | { |
bogdanm | 0:9b334a45a8ff | 3861 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3862 | ADC_HandleTypeDef tmphadcSlave; |
bogdanm | 0:9b334a45a8ff | 3863 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 3864 | |
bogdanm | 0:9b334a45a8ff | 3865 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3866 | assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3867 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 3868 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
bogdanm | 0:9b334a45a8ff | 3869 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
bogdanm | 0:9b334a45a8ff | 3870 | |
bogdanm | 0:9b334a45a8ff | 3871 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3872 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3873 | |
bogdanm | 0:9b334a45a8ff | 3874 | /* Set a temporary handle of the ADC slave associated to the ADC master */ |
bogdanm | 0:9b334a45a8ff | 3875 | /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */ |
bogdanm | 0:9b334a45a8ff | 3876 | __HAL_ADC_MULTI_SLAVE(hadc, &tmphadcSlave); |
bogdanm | 0:9b334a45a8ff | 3877 | |
bogdanm | 0:9b334a45a8ff | 3878 | if (tmphadcSlave.Instance == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 3879 | { |
bogdanm | 0:9b334a45a8ff | 3880 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 3881 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 3882 | |
bogdanm | 0:9b334a45a8ff | 3883 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3884 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3885 | |
bogdanm | 0:9b334a45a8ff | 3886 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 3887 | } |
bogdanm | 0:9b334a45a8ff | 3888 | |
bogdanm | 0:9b334a45a8ff | 3889 | |
bogdanm | 0:9b334a45a8ff | 3890 | /* Enable the ADC peripherals: master and slave (in case if not already */ |
bogdanm | 0:9b334a45a8ff | 3891 | /* enabled previously) */ |
bogdanm | 0:9b334a45a8ff | 3892 | tmpHALStatus = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 3893 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3894 | { |
bogdanm | 0:9b334a45a8ff | 3895 | tmpHALStatus = ADC_Enable(&tmphadcSlave); |
bogdanm | 0:9b334a45a8ff | 3896 | } |
bogdanm | 0:9b334a45a8ff | 3897 | |
bogdanm | 0:9b334a45a8ff | 3898 | /* Start conversion all ADCs of multimode are effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 3899 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3900 | { |
bogdanm | 0:9b334a45a8ff | 3901 | /* State machine update (ADC master): Check if an injected conversion is */ |
bogdanm | 0:9b334a45a8ff | 3902 | /* ongoing. */ |
bogdanm | 0:9b334a45a8ff | 3903 | if(hadc->State == HAL_ADC_STATE_BUSY_INJ) |
bogdanm | 0:9b334a45a8ff | 3904 | { |
bogdanm | 0:9b334a45a8ff | 3905 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3906 | hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 3907 | } |
bogdanm | 0:9b334a45a8ff | 3908 | else |
bogdanm | 0:9b334a45a8ff | 3909 | { |
bogdanm | 0:9b334a45a8ff | 3910 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 3911 | hadc->State = HAL_ADC_STATE_BUSY_REG; |
bogdanm | 0:9b334a45a8ff | 3912 | } |
bogdanm | 0:9b334a45a8ff | 3913 | |
bogdanm | 0:9b334a45a8ff | 3914 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 3915 | __HAL_ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 3916 | |
bogdanm | 0:9b334a45a8ff | 3917 | |
bogdanm | 0:9b334a45a8ff | 3918 | /* Set the DMA transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 3919 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
bogdanm | 0:9b334a45a8ff | 3920 | |
bogdanm | 0:9b334a45a8ff | 3921 | /* Set the DMA half transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 3922 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
bogdanm | 0:9b334a45a8ff | 3923 | |
bogdanm | 0:9b334a45a8ff | 3924 | /* Set the DMA error callback */ |
bogdanm | 0:9b334a45a8ff | 3925 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; |
bogdanm | 0:9b334a45a8ff | 3926 | |
bogdanm | 0:9b334a45a8ff | 3927 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 3928 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 3929 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 3930 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 3931 | |
bogdanm | 0:9b334a45a8ff | 3932 | |
bogdanm | 0:9b334a45a8ff | 3933 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
bogdanm | 0:9b334a45a8ff | 3934 | /* start (in case of SW start): */ |
bogdanm | 0:9b334a45a8ff | 3935 | |
bogdanm | 0:9b334a45a8ff | 3936 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 3937 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
bogdanm | 0:9b334a45a8ff | 3938 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 3939 | |
bogdanm | 0:9b334a45a8ff | 3940 | /* Enable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 3941 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 3942 | |
bogdanm | 0:9b334a45a8ff | 3943 | /* Start the DMA channel */ |
bogdanm | 0:9b334a45a8ff | 3944 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); |
bogdanm | 0:9b334a45a8ff | 3945 | |
bogdanm | 0:9b334a45a8ff | 3946 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 3947 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 3948 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 3949 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 3950 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 3951 | |
bogdanm | 0:9b334a45a8ff | 3952 | } |
bogdanm | 0:9b334a45a8ff | 3953 | |
bogdanm | 0:9b334a45a8ff | 3954 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 3955 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3956 | |
bogdanm | 0:9b334a45a8ff | 3957 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 3958 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 3959 | } |
bogdanm | 0:9b334a45a8ff | 3960 | |
bogdanm | 0:9b334a45a8ff | 3961 | /** |
bogdanm | 0:9b334a45a8ff | 3962 | * @brief Stop ADC conversion of regular group (and injected channels in |
bogdanm | 0:9b334a45a8ff | 3963 | * case of auto_injection mode), disable ADC DMA transfer, disable |
bogdanm | 0:9b334a45a8ff | 3964 | * ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 3965 | * @note Multimode is kept enabled after this function. To disable multimode |
bogdanm | 0:9b334a45a8ff | 3966 | * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be |
bogdanm | 0:9b334a45a8ff | 3967 | * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). |
bogdanm | 0:9b334a45a8ff | 3968 | * @note In case of DMA configured in circular mode, function |
bogdanm | 0:9b334a45a8ff | 3969 | * HAL_ADC_Stop_DMA must be called after this function with handle of |
bogdanm | 0:9b334a45a8ff | 3970 | * ADC slave, to properly disable the DMA channel. |
bogdanm | 0:9b334a45a8ff | 3971 | * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) |
bogdanm | 0:9b334a45a8ff | 3972 | * @retval None |
bogdanm | 0:9b334a45a8ff | 3973 | */ |
bogdanm | 0:9b334a45a8ff | 3974 | HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 3975 | { |
bogdanm | 0:9b334a45a8ff | 3976 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 3977 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 3978 | ADC_HandleTypeDef tmphadcSlave; |
bogdanm | 0:9b334a45a8ff | 3979 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 3980 | |
bogdanm | 0:9b334a45a8ff | 3981 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 3982 | assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 3983 | |
bogdanm | 0:9b334a45a8ff | 3984 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 3985 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 3986 | |
bogdanm | 0:9b334a45a8ff | 3987 | |
bogdanm | 0:9b334a45a8ff | 3988 | /* 1. Stop potential multimode conversion on going, on regular and injected groups */ |
bogdanm | 0:9b334a45a8ff | 3989 | tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP); |
bogdanm | 0:9b334a45a8ff | 3990 | |
bogdanm | 0:9b334a45a8ff | 3991 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 3992 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 3993 | { |
bogdanm | 0:9b334a45a8ff | 3994 | /* Set a temporary handle of the ADC slave associated to the ADC master */ |
bogdanm | 0:9b334a45a8ff | 3995 | /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */ |
bogdanm | 0:9b334a45a8ff | 3996 | __HAL_ADC_MULTI_SLAVE(hadc, &tmphadcSlave); |
bogdanm | 0:9b334a45a8ff | 3997 | |
bogdanm | 0:9b334a45a8ff | 3998 | if (tmphadcSlave.Instance == HAL_NULL) |
bogdanm | 0:9b334a45a8ff | 3999 | { |
bogdanm | 0:9b334a45a8ff | 4000 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4001 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4002 | |
bogdanm | 0:9b334a45a8ff | 4003 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4004 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4005 | |
bogdanm | 0:9b334a45a8ff | 4006 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4007 | } |
bogdanm | 0:9b334a45a8ff | 4008 | |
bogdanm | 0:9b334a45a8ff | 4009 | /* Procedure to disable the ADC peripheral: wait for conversions */ |
bogdanm | 0:9b334a45a8ff | 4010 | /* effectively stopped (ADC master and ADC slave), then disable ADC */ |
bogdanm | 0:9b334a45a8ff | 4011 | |
bogdanm | 0:9b334a45a8ff | 4012 | /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ |
bogdanm | 0:9b334a45a8ff | 4013 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 4014 | |
bogdanm | 0:9b334a45a8ff | 4015 | while(__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || |
bogdanm | 0:9b334a45a8ff | 4016 | __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) |
bogdanm | 0:9b334a45a8ff | 4017 | { |
bogdanm | 0:9b334a45a8ff | 4018 | if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 4019 | { |
bogdanm | 0:9b334a45a8ff | 4020 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4021 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4022 | |
bogdanm | 0:9b334a45a8ff | 4023 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4024 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4025 | |
bogdanm | 0:9b334a45a8ff | 4026 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4027 | } |
bogdanm | 0:9b334a45a8ff | 4028 | } |
bogdanm | 0:9b334a45a8ff | 4029 | |
bogdanm | 0:9b334a45a8ff | 4030 | |
bogdanm | 0:9b334a45a8ff | 4031 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 4032 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 4033 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 4034 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 4035 | |
bogdanm | 0:9b334a45a8ff | 4036 | /* Reset configuration of ADC DMA continuous request for dual mode */ |
bogdanm | 0:9b334a45a8ff | 4037 | tmpADC_Common->CCR &= ~ADC_CCR_DMACFG; |
bogdanm | 0:9b334a45a8ff | 4038 | |
bogdanm | 0:9b334a45a8ff | 4039 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
bogdanm | 0:9b334a45a8ff | 4040 | /* while DMA transfer is on going) */ |
bogdanm | 0:9b334a45a8ff | 4041 | /* Note: DMA channel of ADC slave should stopped after this function with */ |
bogdanm | 0:9b334a45a8ff | 4042 | /* function HAL_ADC_Stop_DMA. */ |
bogdanm | 0:9b334a45a8ff | 4043 | tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); |
bogdanm | 0:9b334a45a8ff | 4044 | |
bogdanm | 0:9b334a45a8ff | 4045 | /* Check if DMA channel effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 4046 | if (tmpHALStatus != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 4047 | { |
bogdanm | 0:9b334a45a8ff | 4048 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4049 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4050 | } |
bogdanm | 0:9b334a45a8ff | 4051 | |
bogdanm | 0:9b334a45a8ff | 4052 | /* Disable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 4053 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 4054 | |
bogdanm | 0:9b334a45a8ff | 4055 | |
bogdanm | 0:9b334a45a8ff | 4056 | |
bogdanm | 0:9b334a45a8ff | 4057 | /* 2. Disable the ADC peripherals: master and slave */ |
bogdanm | 0:9b334a45a8ff | 4058 | /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */ |
bogdanm | 0:9b334a45a8ff | 4059 | /* memory a potential failing status. */ |
bogdanm | 0:9b334a45a8ff | 4060 | if (tmpHALStatus != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 4061 | { |
bogdanm | 0:9b334a45a8ff | 4062 | /* Check if ADC are effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 4063 | if ((ADC_Disable(hadc) != HAL_ERROR) && |
bogdanm | 0:9b334a45a8ff | 4064 | (ADC_Disable(&tmphadcSlave) != HAL_ERROR) ) |
bogdanm | 0:9b334a45a8ff | 4065 | { |
bogdanm | 0:9b334a45a8ff | 4066 | tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 4067 | |
bogdanm | 0:9b334a45a8ff | 4068 | /* Change ADC state (ADC master) */ |
bogdanm | 0:9b334a45a8ff | 4069 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 4070 | } |
bogdanm | 0:9b334a45a8ff | 4071 | } |
bogdanm | 0:9b334a45a8ff | 4072 | else |
bogdanm | 0:9b334a45a8ff | 4073 | { |
bogdanm | 0:9b334a45a8ff | 4074 | ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 4075 | ADC_Disable(&tmphadcSlave); |
bogdanm | 0:9b334a45a8ff | 4076 | } |
bogdanm | 0:9b334a45a8ff | 4077 | |
bogdanm | 0:9b334a45a8ff | 4078 | } |
bogdanm | 0:9b334a45a8ff | 4079 | |
bogdanm | 0:9b334a45a8ff | 4080 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4081 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4082 | |
bogdanm | 0:9b334a45a8ff | 4083 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 4084 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 4085 | } |
bogdanm | 0:9b334a45a8ff | 4086 | |
bogdanm | 0:9b334a45a8ff | 4087 | /** |
bogdanm | 0:9b334a45a8ff | 4088 | * @brief Returns the last ADC Master&Slave regular conversions results data |
bogdanm | 0:9b334a45a8ff | 4089 | * in the selected multi mode. |
bogdanm | 0:9b334a45a8ff | 4090 | * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) |
bogdanm | 0:9b334a45a8ff | 4091 | * @retval The converted data value. |
bogdanm | 0:9b334a45a8ff | 4092 | */ |
bogdanm | 0:9b334a45a8ff | 4093 | uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 4094 | { |
bogdanm | 0:9b334a45a8ff | 4095 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 4096 | |
bogdanm | 0:9b334a45a8ff | 4097 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4098 | assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4099 | |
bogdanm | 0:9b334a45a8ff | 4100 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 4101 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 4102 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 4103 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 4104 | |
bogdanm | 0:9b334a45a8ff | 4105 | /* Return the multi mode conversion value */ |
bogdanm | 0:9b334a45a8ff | 4106 | return tmpADC_Common->CDR; |
bogdanm | 0:9b334a45a8ff | 4107 | } |
bogdanm | 0:9b334a45a8ff | 4108 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 4109 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 4110 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
bogdanm | 0:9b334a45a8ff | 4111 | |
bogdanm | 0:9b334a45a8ff | 4112 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 4113 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 4114 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 4115 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 4116 | /** |
bogdanm | 0:9b334a45a8ff | 4117 | * @brief Get ADC injected group conversion result. |
bogdanm | 0:9b334a45a8ff | 4118 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4119 | * @param InjectedRank: the converted ADC injected rank. |
bogdanm | 0:9b334a45a8ff | 4120 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 4121 | * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected |
bogdanm | 0:9b334a45a8ff | 4122 | * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected |
bogdanm | 0:9b334a45a8ff | 4123 | * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected |
bogdanm | 0:9b334a45a8ff | 4124 | * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected |
bogdanm | 0:9b334a45a8ff | 4125 | * @retval None |
bogdanm | 0:9b334a45a8ff | 4126 | */ |
bogdanm | 0:9b334a45a8ff | 4127 | uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) |
bogdanm | 0:9b334a45a8ff | 4128 | { |
bogdanm | 0:9b334a45a8ff | 4129 | uint32_t tmp_jdr = 0; |
bogdanm | 0:9b334a45a8ff | 4130 | |
bogdanm | 0:9b334a45a8ff | 4131 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4132 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4133 | assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); |
bogdanm | 0:9b334a45a8ff | 4134 | |
bogdanm | 0:9b334a45a8ff | 4135 | /* Clear injected group conversion flag to have similar behaviour as */ |
bogdanm | 0:9b334a45a8ff | 4136 | /* regular group: reading data register also clears end of conversion flag, */ |
bogdanm | 0:9b334a45a8ff | 4137 | /* and in case of usage of ADC feature "LowPowerAutoWait". */ |
bogdanm | 0:9b334a45a8ff | 4138 | __HAL_ADC_CLEAR_FLAG(hadc,(ADC_FLAG_JEOC | ADC_FLAG_JEOS)); |
bogdanm | 0:9b334a45a8ff | 4139 | |
bogdanm | 0:9b334a45a8ff | 4140 | /* Get ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 4141 | switch(InjectedRank) |
bogdanm | 0:9b334a45a8ff | 4142 | { |
bogdanm | 0:9b334a45a8ff | 4143 | case ADC_INJECTED_RANK_4: |
bogdanm | 0:9b334a45a8ff | 4144 | tmp_jdr = hadc->Instance->JDR4; |
bogdanm | 0:9b334a45a8ff | 4145 | break; |
bogdanm | 0:9b334a45a8ff | 4146 | case ADC_INJECTED_RANK_3: |
bogdanm | 0:9b334a45a8ff | 4147 | tmp_jdr = hadc->Instance->JDR3; |
bogdanm | 0:9b334a45a8ff | 4148 | break; |
bogdanm | 0:9b334a45a8ff | 4149 | case ADC_INJECTED_RANK_2: |
bogdanm | 0:9b334a45a8ff | 4150 | tmp_jdr = hadc->Instance->JDR2; |
bogdanm | 0:9b334a45a8ff | 4151 | break; |
bogdanm | 0:9b334a45a8ff | 4152 | case ADC_INJECTED_RANK_1: |
bogdanm | 0:9b334a45a8ff | 4153 | default: |
bogdanm | 0:9b334a45a8ff | 4154 | tmp_jdr = hadc->Instance->JDR1; |
bogdanm | 0:9b334a45a8ff | 4155 | break; |
bogdanm | 0:9b334a45a8ff | 4156 | } |
bogdanm | 0:9b334a45a8ff | 4157 | |
bogdanm | 0:9b334a45a8ff | 4158 | /* Return ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 4159 | return tmp_jdr; |
bogdanm | 0:9b334a45a8ff | 4160 | } |
bogdanm | 0:9b334a45a8ff | 4161 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 4162 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 4163 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 4164 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 4165 | |
bogdanm | 0:9b334a45a8ff | 4166 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 4167 | /** |
bogdanm | 0:9b334a45a8ff | 4168 | * @brief Get ADC injected group conversion result. |
bogdanm | 0:9b334a45a8ff | 4169 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4170 | * @param InjectedRank: the converted ADC injected rank. |
bogdanm | 0:9b334a45a8ff | 4171 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 4172 | * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected |
bogdanm | 0:9b334a45a8ff | 4173 | * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected |
bogdanm | 0:9b334a45a8ff | 4174 | * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected |
bogdanm | 0:9b334a45a8ff | 4175 | * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected |
bogdanm | 0:9b334a45a8ff | 4176 | * @retval None |
bogdanm | 0:9b334a45a8ff | 4177 | */ |
bogdanm | 0:9b334a45a8ff | 4178 | uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) |
bogdanm | 0:9b334a45a8ff | 4179 | { |
bogdanm | 0:9b334a45a8ff | 4180 | uint32_t tmp_jdr = 0; |
bogdanm | 0:9b334a45a8ff | 4181 | |
bogdanm | 0:9b334a45a8ff | 4182 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4183 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4184 | assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); |
bogdanm | 0:9b334a45a8ff | 4185 | |
bogdanm | 0:9b334a45a8ff | 4186 | /* Clear injected group conversion flag to have similar behaviour as */ |
bogdanm | 0:9b334a45a8ff | 4187 | /* regular group: reading data register also clears end of conversion flag. */ |
bogdanm | 0:9b334a45a8ff | 4188 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); |
bogdanm | 0:9b334a45a8ff | 4189 | |
bogdanm | 0:9b334a45a8ff | 4190 | /* Get ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 4191 | switch(InjectedRank) |
bogdanm | 0:9b334a45a8ff | 4192 | { |
bogdanm | 0:9b334a45a8ff | 4193 | case ADC_INJECTED_RANK_4: |
bogdanm | 0:9b334a45a8ff | 4194 | tmp_jdr = hadc->Instance->JDR4; |
bogdanm | 0:9b334a45a8ff | 4195 | break; |
bogdanm | 0:9b334a45a8ff | 4196 | case ADC_INJECTED_RANK_3: |
bogdanm | 0:9b334a45a8ff | 4197 | tmp_jdr = hadc->Instance->JDR3; |
bogdanm | 0:9b334a45a8ff | 4198 | break; |
bogdanm | 0:9b334a45a8ff | 4199 | case ADC_INJECTED_RANK_2: |
bogdanm | 0:9b334a45a8ff | 4200 | tmp_jdr = hadc->Instance->JDR2; |
bogdanm | 0:9b334a45a8ff | 4201 | break; |
bogdanm | 0:9b334a45a8ff | 4202 | case ADC_INJECTED_RANK_1: |
bogdanm | 0:9b334a45a8ff | 4203 | default: |
bogdanm | 0:9b334a45a8ff | 4204 | tmp_jdr = hadc->Instance->JDR1; |
bogdanm | 0:9b334a45a8ff | 4205 | break; |
bogdanm | 0:9b334a45a8ff | 4206 | } |
bogdanm | 0:9b334a45a8ff | 4207 | |
bogdanm | 0:9b334a45a8ff | 4208 | /* Return ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 4209 | return tmp_jdr; |
bogdanm | 0:9b334a45a8ff | 4210 | } |
bogdanm | 0:9b334a45a8ff | 4211 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 4212 | |
bogdanm | 0:9b334a45a8ff | 4213 | /** |
bogdanm | 0:9b334a45a8ff | 4214 | * @brief Injected conversion complete callback in non blocking mode |
bogdanm | 0:9b334a45a8ff | 4215 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4216 | * @retval None |
bogdanm | 0:9b334a45a8ff | 4217 | */ |
bogdanm | 0:9b334a45a8ff | 4218 | __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 4219 | { |
bogdanm | 0:9b334a45a8ff | 4220 | /* NOTE : This function Should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 4221 | the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 4222 | */ |
bogdanm | 0:9b334a45a8ff | 4223 | } |
bogdanm | 0:9b334a45a8ff | 4224 | |
bogdanm | 0:9b334a45a8ff | 4225 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 4226 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 4227 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 4228 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 4229 | /** |
bogdanm | 0:9b334a45a8ff | 4230 | * @brief Injected context queue overflow flag callback. |
bogdanm | 0:9b334a45a8ff | 4231 | * @note: This callback is called if injected context queue is enabled |
bogdanm | 0:9b334a45a8ff | 4232 | (parameter "QueueInjectedContext" in injected channel configuration) |
bogdanm | 0:9b334a45a8ff | 4233 | and if a new injected context is set when queue is full (maximum 2 |
bogdanm | 0:9b334a45a8ff | 4234 | contexts). |
bogdanm | 0:9b334a45a8ff | 4235 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4236 | * @retval None |
bogdanm | 0:9b334a45a8ff | 4237 | */ |
bogdanm | 0:9b334a45a8ff | 4238 | __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 4239 | { |
bogdanm | 0:9b334a45a8ff | 4240 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 4241 | function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented |
bogdanm | 0:9b334a45a8ff | 4242 | in the user file. |
bogdanm | 0:9b334a45a8ff | 4243 | */ |
bogdanm | 0:9b334a45a8ff | 4244 | } |
bogdanm | 0:9b334a45a8ff | 4245 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 4246 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 4247 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 4248 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 4249 | |
bogdanm | 0:9b334a45a8ff | 4250 | /** |
bogdanm | 0:9b334a45a8ff | 4251 | * @} |
bogdanm | 0:9b334a45a8ff | 4252 | */ |
bogdanm | 0:9b334a45a8ff | 4253 | |
bogdanm | 0:9b334a45a8ff | 4254 | /** @defgroup ADCEx_Exported_Functions_Group3 Extended Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 4255 | * @brief Extended Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 4256 | * |
bogdanm | 0:9b334a45a8ff | 4257 | @verbatim |
bogdanm | 0:9b334a45a8ff | 4258 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 4259 | ##### Peripheral Control functions ##### |
bogdanm | 0:9b334a45a8ff | 4260 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 4261 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 4262 | (+) Configure channels on regular group |
bogdanm | 0:9b334a45a8ff | 4263 | (+) Configure channels on injected group |
bogdanm | 0:9b334a45a8ff | 4264 | (+) Configure multimode |
bogdanm | 0:9b334a45a8ff | 4265 | (+) Configure the analog watchdog |
bogdanm | 0:9b334a45a8ff | 4266 | |
bogdanm | 0:9b334a45a8ff | 4267 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 4268 | * @{ |
bogdanm | 0:9b334a45a8ff | 4269 | */ |
bogdanm | 0:9b334a45a8ff | 4270 | |
bogdanm | 0:9b334a45a8ff | 4271 | |
bogdanm | 0:9b334a45a8ff | 4272 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 4273 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 4274 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 4275 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 4276 | /** |
bogdanm | 0:9b334a45a8ff | 4277 | * @brief Configures the the selected channel to be linked to the regular |
bogdanm | 0:9b334a45a8ff | 4278 | * group. |
bogdanm | 0:9b334a45a8ff | 4279 | * @note In case of usage of internal measurement channels: |
bogdanm | 0:9b334a45a8ff | 4280 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4281 | * The recommended sampling time is at least: |
bogdanm | 0:9b334a45a8ff | 4282 | * - For devices STM32F37x: 17.1us for temperature sensor |
bogdanm | 0:9b334a45a8ff | 4283 | * - For the other STM32F3 devices: 2.2us for each of channels |
bogdanm | 0:9b334a45a8ff | 4284 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4285 | * These internal paths can be be disabled using function |
bogdanm | 0:9b334a45a8ff | 4286 | * HAL_ADC_DeInit(). |
bogdanm | 0:9b334a45a8ff | 4287 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 4288 | * This function initializes channel into regular group, following |
bogdanm | 0:9b334a45a8ff | 4289 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 4290 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 4291 | * the ADC. |
bogdanm | 0:9b334a45a8ff | 4292 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 4293 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 4294 | * "ADC_ChannelConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 4295 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4296 | * @param sConfig: Structure ADC channel for regular group. |
bogdanm | 0:9b334a45a8ff | 4297 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 4298 | */ |
bogdanm | 0:9b334a45a8ff | 4299 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
bogdanm | 0:9b334a45a8ff | 4300 | { |
bogdanm | 0:9b334a45a8ff | 4301 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 4302 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 4303 | ADC_HandleTypeDef tmphadcSharingSameCommonRegister; |
bogdanm | 0:9b334a45a8ff | 4304 | uint32_t tmpOffsetShifted; |
bogdanm | 0:9b334a45a8ff | 4305 | uint32_t WaitLoopIndex = 0; |
bogdanm | 0:9b334a45a8ff | 4306 | |
bogdanm | 0:9b334a45a8ff | 4307 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4308 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4309 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
bogdanm | 0:9b334a45a8ff | 4310 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
bogdanm | 0:9b334a45a8ff | 4311 | assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); |
bogdanm | 0:9b334a45a8ff | 4312 | assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); |
bogdanm | 0:9b334a45a8ff | 4313 | assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), sConfig->Offset)); |
bogdanm | 0:9b334a45a8ff | 4314 | |
bogdanm | 0:9b334a45a8ff | 4315 | |
bogdanm | 0:9b334a45a8ff | 4316 | /* Verification of channel number: Channels 1 to 14 are available in */ |
bogdanm | 0:9b334a45a8ff | 4317 | /* differential mode. Channels 15, 16, 17, 18 can be used only in */ |
bogdanm | 0:9b334a45a8ff | 4318 | /* single-ended mode. */ |
bogdanm | 0:9b334a45a8ff | 4319 | if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 4320 | { |
bogdanm | 0:9b334a45a8ff | 4321 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 4322 | } |
bogdanm | 0:9b334a45a8ff | 4323 | else |
bogdanm | 0:9b334a45a8ff | 4324 | { |
bogdanm | 0:9b334a45a8ff | 4325 | assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 4326 | } |
bogdanm | 0:9b334a45a8ff | 4327 | |
bogdanm | 0:9b334a45a8ff | 4328 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 4329 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4330 | |
bogdanm | 0:9b334a45a8ff | 4331 | |
bogdanm | 0:9b334a45a8ff | 4332 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 4333 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 4334 | /* conversion on going on regular group: */ |
bogdanm | 0:9b334a45a8ff | 4335 | /* - Channel number */ |
bogdanm | 0:9b334a45a8ff | 4336 | /* - Channel rank */ |
bogdanm | 0:9b334a45a8ff | 4337 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 4338 | { |
bogdanm | 0:9b334a45a8ff | 4339 | /* Regular sequence configuration */ |
bogdanm | 0:9b334a45a8ff | 4340 | /* For Rank 1 to 4 */ |
bogdanm | 0:9b334a45a8ff | 4341 | if (sConfig->Rank < 5) |
bogdanm | 0:9b334a45a8ff | 4342 | { |
bogdanm | 0:9b334a45a8ff | 4343 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4344 | hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4345 | |
bogdanm | 0:9b334a45a8ff | 4346 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4347 | hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4348 | } |
bogdanm | 0:9b334a45a8ff | 4349 | /* For Rank 5 to 9 */ |
bogdanm | 0:9b334a45a8ff | 4350 | else if (sConfig->Rank < 10) |
bogdanm | 0:9b334a45a8ff | 4351 | { |
bogdanm | 0:9b334a45a8ff | 4352 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4353 | hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4354 | |
bogdanm | 0:9b334a45a8ff | 4355 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4356 | hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4357 | } |
bogdanm | 0:9b334a45a8ff | 4358 | /* For Rank 10 to 14 */ |
bogdanm | 0:9b334a45a8ff | 4359 | else if (sConfig->Rank < 15) |
bogdanm | 0:9b334a45a8ff | 4360 | { |
bogdanm | 0:9b334a45a8ff | 4361 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4362 | hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4363 | |
bogdanm | 0:9b334a45a8ff | 4364 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4365 | hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4366 | } |
bogdanm | 0:9b334a45a8ff | 4367 | /* For Rank 15 to 16 */ |
bogdanm | 0:9b334a45a8ff | 4368 | else |
bogdanm | 0:9b334a45a8ff | 4369 | { |
bogdanm | 0:9b334a45a8ff | 4370 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4371 | hadc->Instance->SQR4 &= ~__HAL_ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4372 | |
bogdanm | 0:9b334a45a8ff | 4373 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4374 | hadc->Instance->SQR4 |= __HAL_ADC_SQR4_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4375 | } |
bogdanm | 0:9b334a45a8ff | 4376 | |
bogdanm | 0:9b334a45a8ff | 4377 | |
bogdanm | 0:9b334a45a8ff | 4378 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 4379 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 4380 | /* conversion on going on regular group: */ |
bogdanm | 0:9b334a45a8ff | 4381 | /* - Channel sampling time */ |
bogdanm | 0:9b334a45a8ff | 4382 | /* - Channel offset */ |
bogdanm | 0:9b334a45a8ff | 4383 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 4384 | { |
bogdanm | 0:9b334a45a8ff | 4385 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 4386 | /* For channels 10 to 18 */ |
bogdanm | 0:9b334a45a8ff | 4387 | if (sConfig->Channel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 4388 | { |
bogdanm | 0:9b334a45a8ff | 4389 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4390 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4391 | |
bogdanm | 0:9b334a45a8ff | 4392 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4393 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4394 | } |
bogdanm | 0:9b334a45a8ff | 4395 | else /* For channels 0 to 9 */ |
bogdanm | 0:9b334a45a8ff | 4396 | { |
bogdanm | 0:9b334a45a8ff | 4397 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4398 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4399 | |
bogdanm | 0:9b334a45a8ff | 4400 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4401 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4402 | } |
bogdanm | 0:9b334a45a8ff | 4403 | |
bogdanm | 0:9b334a45a8ff | 4404 | |
bogdanm | 0:9b334a45a8ff | 4405 | /* Configure the offset: offset enable/disable, channel, offset value */ |
bogdanm | 0:9b334a45a8ff | 4406 | |
bogdanm | 0:9b334a45a8ff | 4407 | /* Shift the offset in function of the selected ADC resolution. */ |
bogdanm | 0:9b334a45a8ff | 4408 | /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
bogdanm | 0:9b334a45a8ff | 4409 | tmpOffsetShifted = __HAL_ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); |
bogdanm | 0:9b334a45a8ff | 4410 | |
bogdanm | 0:9b334a45a8ff | 4411 | switch (sConfig->OffsetNumber) |
bogdanm | 0:9b334a45a8ff | 4412 | { |
bogdanm | 0:9b334a45a8ff | 4413 | case ADC_OFFSET_1: |
bogdanm | 0:9b334a45a8ff | 4414 | /* Configure offset register 1: */ |
bogdanm | 0:9b334a45a8ff | 4415 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 4416 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 4417 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 4418 | hadc->Instance->OFR1 &= ~( ADC_OFR1_OFFSET1_CH | |
bogdanm | 0:9b334a45a8ff | 4419 | ADC_OFR1_OFFSET1 ); |
bogdanm | 0:9b334a45a8ff | 4420 | hadc->Instance->OFR1 |= ( ADC_OFR1_OFFSET1_EN | |
bogdanm | 0:9b334a45a8ff | 4421 | __HAL_ADC_OFR_CHANNEL(sConfig->Channel) | |
bogdanm | 0:9b334a45a8ff | 4422 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 4423 | break; |
bogdanm | 0:9b334a45a8ff | 4424 | |
bogdanm | 0:9b334a45a8ff | 4425 | case ADC_OFFSET_2: |
bogdanm | 0:9b334a45a8ff | 4426 | /* Configure offset register 2: */ |
bogdanm | 0:9b334a45a8ff | 4427 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 4428 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 4429 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 4430 | hadc->Instance->OFR2 &= ~( ADC_OFR2_OFFSET2_CH | |
bogdanm | 0:9b334a45a8ff | 4431 | ADC_OFR2_OFFSET2 ); |
bogdanm | 0:9b334a45a8ff | 4432 | hadc->Instance->OFR2 |= ( ADC_OFR2_OFFSET2_EN | |
bogdanm | 0:9b334a45a8ff | 4433 | __HAL_ADC_OFR_CHANNEL(sConfig->Channel) | |
bogdanm | 0:9b334a45a8ff | 4434 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 4435 | break; |
bogdanm | 0:9b334a45a8ff | 4436 | |
bogdanm | 0:9b334a45a8ff | 4437 | case ADC_OFFSET_3: |
bogdanm | 0:9b334a45a8ff | 4438 | /* Configure offset register 3: */ |
bogdanm | 0:9b334a45a8ff | 4439 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 4440 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 4441 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 4442 | hadc->Instance->OFR3 &= ~( ADC_OFR3_OFFSET3_CH | |
bogdanm | 0:9b334a45a8ff | 4443 | ADC_OFR3_OFFSET3 ); |
bogdanm | 0:9b334a45a8ff | 4444 | hadc->Instance->OFR3 |= ( ADC_OFR3_OFFSET3_EN | |
bogdanm | 0:9b334a45a8ff | 4445 | __HAL_ADC_OFR_CHANNEL(sConfig->Channel) | |
bogdanm | 0:9b334a45a8ff | 4446 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 4447 | break; |
bogdanm | 0:9b334a45a8ff | 4448 | |
bogdanm | 0:9b334a45a8ff | 4449 | case ADC_OFFSET_4: |
bogdanm | 0:9b334a45a8ff | 4450 | /* Configure offset register 1: */ |
bogdanm | 0:9b334a45a8ff | 4451 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 4452 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 4453 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 4454 | hadc->Instance->OFR4 &= ~( ADC_OFR4_OFFSET4_CH | |
bogdanm | 0:9b334a45a8ff | 4455 | ADC_OFR4_OFFSET4 ); |
bogdanm | 0:9b334a45a8ff | 4456 | hadc->Instance->OFR4 |= ( ADC_OFR4_OFFSET4_EN | |
bogdanm | 0:9b334a45a8ff | 4457 | __HAL_ADC_OFR_CHANNEL(sConfig->Channel) | |
bogdanm | 0:9b334a45a8ff | 4458 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 4459 | break; |
bogdanm | 0:9b334a45a8ff | 4460 | |
bogdanm | 0:9b334a45a8ff | 4461 | /* Case ADC_OFFSET_NONE */ |
bogdanm | 0:9b334a45a8ff | 4462 | default : |
bogdanm | 0:9b334a45a8ff | 4463 | /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */ |
bogdanm | 0:9b334a45a8ff | 4464 | if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 4465 | { |
bogdanm | 0:9b334a45a8ff | 4466 | /* Disable offset OFR1*/ |
bogdanm | 0:9b334a45a8ff | 4467 | hadc->Instance->OFR1 &= ~ADC_OFR1_OFFSET1_EN; |
bogdanm | 0:9b334a45a8ff | 4468 | } |
bogdanm | 0:9b334a45a8ff | 4469 | if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 4470 | { |
bogdanm | 0:9b334a45a8ff | 4471 | /* Disable offset OFR2*/ |
bogdanm | 0:9b334a45a8ff | 4472 | hadc->Instance->OFR2 &= ~ADC_OFR2_OFFSET2_EN; |
bogdanm | 0:9b334a45a8ff | 4473 | } |
bogdanm | 0:9b334a45a8ff | 4474 | if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 4475 | { |
bogdanm | 0:9b334a45a8ff | 4476 | /* Disable offset OFR3*/ |
bogdanm | 0:9b334a45a8ff | 4477 | hadc->Instance->OFR3 &= ~ADC_OFR3_OFFSET3_EN; |
bogdanm | 0:9b334a45a8ff | 4478 | } |
bogdanm | 0:9b334a45a8ff | 4479 | if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 4480 | { |
bogdanm | 0:9b334a45a8ff | 4481 | /* Disable offset OFR4*/ |
bogdanm | 0:9b334a45a8ff | 4482 | hadc->Instance->OFR4 &= ~ADC_OFR4_OFFSET4_EN; |
bogdanm | 0:9b334a45a8ff | 4483 | } |
bogdanm | 0:9b334a45a8ff | 4484 | break; |
bogdanm | 0:9b334a45a8ff | 4485 | } |
bogdanm | 0:9b334a45a8ff | 4486 | |
bogdanm | 0:9b334a45a8ff | 4487 | } |
bogdanm | 0:9b334a45a8ff | 4488 | |
bogdanm | 0:9b334a45a8ff | 4489 | |
bogdanm | 0:9b334a45a8ff | 4490 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 4491 | /* Parameters that can be updated only when ADC is disabled: */ |
bogdanm | 0:9b334a45a8ff | 4492 | /* - Single or differential mode */ |
bogdanm | 0:9b334a45a8ff | 4493 | /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ |
bogdanm | 0:9b334a45a8ff | 4494 | if (__HAL_ADC_IS_ENABLED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 4495 | { |
bogdanm | 0:9b334a45a8ff | 4496 | /* Configuration of differential mode */ |
bogdanm | 0:9b334a45a8ff | 4497 | if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 4498 | { |
bogdanm | 0:9b334a45a8ff | 4499 | /* Disable differential mode (default mode: single-ended) */ |
bogdanm | 0:9b334a45a8ff | 4500 | hadc->Instance->DIFSEL &= ~(__HAL_ADC_DIFSEL_CHANNEL(sConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 4501 | } |
bogdanm | 0:9b334a45a8ff | 4502 | else |
bogdanm | 0:9b334a45a8ff | 4503 | { |
bogdanm | 0:9b334a45a8ff | 4504 | /* Enable differential mode */ |
bogdanm | 0:9b334a45a8ff | 4505 | hadc->Instance->DIFSEL |= __HAL_ADC_DIFSEL_CHANNEL(sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4506 | |
bogdanm | 0:9b334a45a8ff | 4507 | /* Sampling time configuration of channel ADC_IN+1 (negative input) */ |
bogdanm | 0:9b334a45a8ff | 4508 | /* For channels 10 to 18 */ |
bogdanm | 0:9b334a45a8ff | 4509 | if (sConfig->Channel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 4510 | { |
bogdanm | 0:9b334a45a8ff | 4511 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4512 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, (sConfig->Channel +1)); |
bogdanm | 0:9b334a45a8ff | 4513 | |
bogdanm | 0:9b334a45a8ff | 4514 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4515 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, (sConfig->Channel +1)); |
bogdanm | 0:9b334a45a8ff | 4516 | } |
bogdanm | 0:9b334a45a8ff | 4517 | else /* For channels 0 to 9 */ |
bogdanm | 0:9b334a45a8ff | 4518 | { |
bogdanm | 0:9b334a45a8ff | 4519 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4520 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, (sConfig->Channel +1)); |
bogdanm | 0:9b334a45a8ff | 4521 | |
bogdanm | 0:9b334a45a8ff | 4522 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4523 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, (sConfig->Channel +1)); |
bogdanm | 0:9b334a45a8ff | 4524 | } |
bogdanm | 0:9b334a45a8ff | 4525 | } |
bogdanm | 0:9b334a45a8ff | 4526 | |
bogdanm | 0:9b334a45a8ff | 4527 | |
bogdanm | 0:9b334a45a8ff | 4528 | /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ |
bogdanm | 0:9b334a45a8ff | 4529 | /* internal measurement paths enable: If internal channel selected, */ |
bogdanm | 0:9b334a45a8ff | 4530 | /* enable dedicated internal buffers and path. */ |
bogdanm | 0:9b334a45a8ff | 4531 | /* Note: these internal measurement paths can be disabled using */ |
bogdanm | 0:9b334a45a8ff | 4532 | /* HAL_ADC_DeInit(). */ |
bogdanm | 0:9b334a45a8ff | 4533 | |
bogdanm | 0:9b334a45a8ff | 4534 | /* Configuration of common ADC parameters */ |
bogdanm | 0:9b334a45a8ff | 4535 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 4536 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 4537 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 4538 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 4539 | |
bogdanm | 0:9b334a45a8ff | 4540 | /* If the requested internal measurement path has already been enabled, */ |
bogdanm | 0:9b334a45a8ff | 4541 | /* bypass the configuration processing. */ |
bogdanm | 0:9b334a45a8ff | 4542 | if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && |
bogdanm | 0:9b334a45a8ff | 4543 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || |
bogdanm | 0:9b334a45a8ff | 4544 | ( (sConfig->Channel == ADC_CHANNEL_VBAT) && |
bogdanm | 0:9b334a45a8ff | 4545 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || |
bogdanm | 0:9b334a45a8ff | 4546 | ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && |
bogdanm | 0:9b334a45a8ff | 4547 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) |
bogdanm | 0:9b334a45a8ff | 4548 | ) |
bogdanm | 0:9b334a45a8ff | 4549 | { |
bogdanm | 0:9b334a45a8ff | 4550 | /* Configuration of common ADC parameters (continuation) */ |
bogdanm | 0:9b334a45a8ff | 4551 | /* Set handle of the other ADC sharing the same common register */ |
bogdanm | 0:9b334a45a8ff | 4552 | __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); |
bogdanm | 0:9b334a45a8ff | 4553 | |
bogdanm | 0:9b334a45a8ff | 4554 | /* Software is allowed to change common parameters only when all ADCs */ |
bogdanm | 0:9b334a45a8ff | 4555 | /* of the common group are disabled. */ |
bogdanm | 0:9b334a45a8ff | 4556 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 4557 | ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) || |
bogdanm | 0:9b334a45a8ff | 4558 | (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) )) |
bogdanm | 0:9b334a45a8ff | 4559 | { |
bogdanm | 0:9b334a45a8ff | 4560 | /* If Channel_16 is selected, enable Temp. sensor measurement path */ |
bogdanm | 0:9b334a45a8ff | 4561 | /* Note: Temp. sensor internal channels available on ADC1 only */ |
bogdanm | 0:9b334a45a8ff | 4562 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) |
bogdanm | 0:9b334a45a8ff | 4563 | { |
bogdanm | 0:9b334a45a8ff | 4564 | tmpADC_Common->CCR |= ADC_CCR_TSEN; |
bogdanm | 0:9b334a45a8ff | 4565 | |
bogdanm | 0:9b334a45a8ff | 4566 | /* Delay for temperature sensor stabilization time */ |
bogdanm | 0:9b334a45a8ff | 4567 | while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES) |
bogdanm | 0:9b334a45a8ff | 4568 | { |
bogdanm | 0:9b334a45a8ff | 4569 | WaitLoopIndex++; |
bogdanm | 0:9b334a45a8ff | 4570 | } |
bogdanm | 0:9b334a45a8ff | 4571 | } |
bogdanm | 0:9b334a45a8ff | 4572 | /* If Channel_17 is selected, enable VBAT measurement path */ |
bogdanm | 0:9b334a45a8ff | 4573 | /* Note: VBAT internal channels available on ADC1 only */ |
bogdanm | 0:9b334a45a8ff | 4574 | else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) |
bogdanm | 0:9b334a45a8ff | 4575 | { |
bogdanm | 0:9b334a45a8ff | 4576 | tmpADC_Common->CCR |= ADC_CCR_VBATEN; |
bogdanm | 0:9b334a45a8ff | 4577 | } |
bogdanm | 0:9b334a45a8ff | 4578 | /* If Channel_18 is selected, enable VREFINT measurement path */ |
bogdanm | 0:9b334a45a8ff | 4579 | /* Note: VrefInt internal channels available on all ADCs, but only */ |
bogdanm | 0:9b334a45a8ff | 4580 | /* one ADC is allowed to be connected to VrefInt at the same */ |
bogdanm | 0:9b334a45a8ff | 4581 | /* time. */ |
bogdanm | 0:9b334a45a8ff | 4582 | else if (sConfig->Channel == ADC_CHANNEL_VREFINT) |
bogdanm | 0:9b334a45a8ff | 4583 | { |
bogdanm | 0:9b334a45a8ff | 4584 | tmpADC_Common->CCR |= ADC_CCR_VREFEN; |
bogdanm | 0:9b334a45a8ff | 4585 | } |
bogdanm | 0:9b334a45a8ff | 4586 | } |
bogdanm | 0:9b334a45a8ff | 4587 | /* If the requested internal measurement path has already been */ |
bogdanm | 0:9b334a45a8ff | 4588 | /* enabled and other ADC of the common group are enabled, internal */ |
bogdanm | 0:9b334a45a8ff | 4589 | /* measurement paths cannot be enabled. */ |
bogdanm | 0:9b334a45a8ff | 4590 | else |
bogdanm | 0:9b334a45a8ff | 4591 | { |
bogdanm | 0:9b334a45a8ff | 4592 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4593 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4594 | |
bogdanm | 0:9b334a45a8ff | 4595 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4596 | } |
bogdanm | 0:9b334a45a8ff | 4597 | } |
bogdanm | 0:9b334a45a8ff | 4598 | |
bogdanm | 0:9b334a45a8ff | 4599 | } |
bogdanm | 0:9b334a45a8ff | 4600 | |
bogdanm | 0:9b334a45a8ff | 4601 | } |
bogdanm | 0:9b334a45a8ff | 4602 | /* If a conversion is on going on regular group, no update on regular */ |
bogdanm | 0:9b334a45a8ff | 4603 | /* channel could be done on neither of the channel configuration structure */ |
bogdanm | 0:9b334a45a8ff | 4604 | /* parameters. */ |
bogdanm | 0:9b334a45a8ff | 4605 | else |
bogdanm | 0:9b334a45a8ff | 4606 | { |
bogdanm | 0:9b334a45a8ff | 4607 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4608 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4609 | |
bogdanm | 0:9b334a45a8ff | 4610 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4611 | } |
bogdanm | 0:9b334a45a8ff | 4612 | |
bogdanm | 0:9b334a45a8ff | 4613 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4614 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4615 | |
bogdanm | 0:9b334a45a8ff | 4616 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 4617 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 4618 | } |
bogdanm | 0:9b334a45a8ff | 4619 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 4620 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 4621 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 4622 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 4623 | |
bogdanm | 0:9b334a45a8ff | 4624 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 4625 | /** |
bogdanm | 0:9b334a45a8ff | 4626 | * @brief Configures the the selected channel to be linked to the regular |
bogdanm | 0:9b334a45a8ff | 4627 | * group. |
bogdanm | 0:9b334a45a8ff | 4628 | * @note In case of usage of internal measurement channels: |
bogdanm | 0:9b334a45a8ff | 4629 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4630 | * The recommended sampling time is at least: |
bogdanm | 0:9b334a45a8ff | 4631 | * - For devices STM32F37x: 17.1us for temperature sensor |
bogdanm | 0:9b334a45a8ff | 4632 | * - For the other STM32F3 devices: 2.2us for each of channels |
bogdanm | 0:9b334a45a8ff | 4633 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4634 | * These internal paths can be be disabled using function |
bogdanm | 0:9b334a45a8ff | 4635 | * HAL_ADC_DeInit(). |
bogdanm | 0:9b334a45a8ff | 4636 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 4637 | * This function initializes channel into regular group, following |
bogdanm | 0:9b334a45a8ff | 4638 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 4639 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 4640 | * the ADC. |
bogdanm | 0:9b334a45a8ff | 4641 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 4642 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 4643 | * "ADC_ChannelConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 4644 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4645 | * @param sConfig: Structure of ADC channel for regular group. |
bogdanm | 0:9b334a45a8ff | 4646 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 4647 | */ |
bogdanm | 0:9b334a45a8ff | 4648 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
bogdanm | 0:9b334a45a8ff | 4649 | { |
bogdanm | 0:9b334a45a8ff | 4650 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 4651 | |
bogdanm | 0:9b334a45a8ff | 4652 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4653 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4654 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 4655 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
bogdanm | 0:9b334a45a8ff | 4656 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
bogdanm | 0:9b334a45a8ff | 4657 | |
bogdanm | 0:9b334a45a8ff | 4658 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 4659 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4660 | |
bogdanm | 0:9b334a45a8ff | 4661 | |
bogdanm | 0:9b334a45a8ff | 4662 | /* Regular sequence configuration */ |
bogdanm | 0:9b334a45a8ff | 4663 | /* For Rank 1 to 6 */ |
bogdanm | 0:9b334a45a8ff | 4664 | if (sConfig->Rank < 7) |
bogdanm | 0:9b334a45a8ff | 4665 | { |
bogdanm | 0:9b334a45a8ff | 4666 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4667 | hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4668 | |
bogdanm | 0:9b334a45a8ff | 4669 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4670 | hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4671 | } |
bogdanm | 0:9b334a45a8ff | 4672 | /* For Rank 7 to 12 */ |
bogdanm | 0:9b334a45a8ff | 4673 | else if (sConfig->Rank < 13) |
bogdanm | 0:9b334a45a8ff | 4674 | { |
bogdanm | 0:9b334a45a8ff | 4675 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4676 | hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4677 | |
bogdanm | 0:9b334a45a8ff | 4678 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4679 | hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4680 | } |
bogdanm | 0:9b334a45a8ff | 4681 | /* For Rank 13 to 16 */ |
bogdanm | 0:9b334a45a8ff | 4682 | else |
bogdanm | 0:9b334a45a8ff | 4683 | { |
bogdanm | 0:9b334a45a8ff | 4684 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4685 | hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4686 | |
bogdanm | 0:9b334a45a8ff | 4687 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4688 | hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); |
bogdanm | 0:9b334a45a8ff | 4689 | } |
bogdanm | 0:9b334a45a8ff | 4690 | |
bogdanm | 0:9b334a45a8ff | 4691 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 4692 | /* For channels 10 to 18 */ |
bogdanm | 0:9b334a45a8ff | 4693 | if (sConfig->Channel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 4694 | { |
bogdanm | 0:9b334a45a8ff | 4695 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4696 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4697 | |
bogdanm | 0:9b334a45a8ff | 4698 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4699 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4700 | } |
bogdanm | 0:9b334a45a8ff | 4701 | else /* For channels 0 to 9 */ |
bogdanm | 0:9b334a45a8ff | 4702 | { |
bogdanm | 0:9b334a45a8ff | 4703 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 4704 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4705 | |
bogdanm | 0:9b334a45a8ff | 4706 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 4707 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 4708 | } |
bogdanm | 0:9b334a45a8ff | 4709 | |
bogdanm | 0:9b334a45a8ff | 4710 | /* if ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor / VREFINT measurement path */ |
bogdanm | 0:9b334a45a8ff | 4711 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)) |
bogdanm | 0:9b334a45a8ff | 4712 | { |
bogdanm | 0:9b334a45a8ff | 4713 | hadc->Instance->CR2 |= ADC_CR2_TSVREFE; |
bogdanm | 0:9b334a45a8ff | 4714 | } |
bogdanm | 0:9b334a45a8ff | 4715 | |
bogdanm | 0:9b334a45a8ff | 4716 | /* if ADC1 Channel_17 is selected, enable VBAT measurement path */ |
bogdanm | 0:9b334a45a8ff | 4717 | else if (sConfig->Channel == ADC_CHANNEL_VBAT) |
bogdanm | 0:9b334a45a8ff | 4718 | { |
bogdanm | 0:9b334a45a8ff | 4719 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; |
bogdanm | 0:9b334a45a8ff | 4720 | } |
bogdanm | 0:9b334a45a8ff | 4721 | |
bogdanm | 0:9b334a45a8ff | 4722 | |
bogdanm | 0:9b334a45a8ff | 4723 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4724 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4725 | |
bogdanm | 0:9b334a45a8ff | 4726 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 4727 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 4728 | } |
bogdanm | 0:9b334a45a8ff | 4729 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 4730 | |
bogdanm | 0:9b334a45a8ff | 4731 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 4732 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 4733 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 4734 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 4735 | /** |
bogdanm | 0:9b334a45a8ff | 4736 | * @brief Configures the ADC injected group and the selected channel to be |
bogdanm | 0:9b334a45a8ff | 4737 | * linked to the injected group. |
bogdanm | 0:9b334a45a8ff | 4738 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 4739 | * This function initializes injected group, following calls to this |
bogdanm | 0:9b334a45a8ff | 4740 | * function can be used to reconfigure some parameters of structure |
bogdanm | 0:9b334a45a8ff | 4741 | * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. |
bogdanm | 0:9b334a45a8ff | 4742 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 4743 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 4744 | * "ADC_InjectionConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 4745 | * @note In case of usage of internal measurement channels: |
bogdanm | 0:9b334a45a8ff | 4746 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4747 | * The recommended sampling time is at least: |
bogdanm | 0:9b334a45a8ff | 4748 | * - For devices STM32F37x: 17.1us for temperature sensor |
bogdanm | 0:9b334a45a8ff | 4749 | * - For the other STM32F3 devices: 2.2us for each of channels |
bogdanm | 0:9b334a45a8ff | 4750 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 4751 | * These internal paths can be be disabled using function |
bogdanm | 0:9b334a45a8ff | 4752 | * HAL_ADC_DeInit(). |
bogdanm | 0:9b334a45a8ff | 4753 | * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can |
bogdanm | 0:9b334a45a8ff | 4754 | * be used. |
bogdanm | 0:9b334a45a8ff | 4755 | * @note Caution: For Injected Context Queue use: a context must be fully |
bogdanm | 0:9b334a45a8ff | 4756 | * defined before start of injected conversion: all channels configured |
bogdanm | 0:9b334a45a8ff | 4757 | * consecutively for the same ADC instance. Therefore, Number of calls of |
bogdanm | 0:9b334a45a8ff | 4758 | * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter |
bogdanm | 0:9b334a45a8ff | 4759 | * InjectedNbrOfConversion for each context. |
bogdanm | 0:9b334a45a8ff | 4760 | * - Example 1: If 1 context intended to be used (or not use of this feature: |
bogdanm | 0:9b334a45a8ff | 4761 | * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks |
bogdanm | 0:9b334a45a8ff | 4762 | * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be |
bogdanm | 0:9b334a45a8ff | 4763 | * called once for each channel (3 times) before launching a conversion. |
bogdanm | 0:9b334a45a8ff | 4764 | * This function must not be called to configure the 4th injected channel: |
bogdanm | 0:9b334a45a8ff | 4765 | * it would start a new context into context queue. |
bogdanm | 0:9b334a45a8ff | 4766 | * - Example 2: If 2 contexts intended to be used and usage of the 3 first |
bogdanm | 0:9b334a45a8ff | 4767 | * injected ranks (InjectedNbrOfConversion=3), |
bogdanm | 0:9b334a45a8ff | 4768 | * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and |
bogdanm | 0:9b334a45a8ff | 4769 | * for each context (3 channels x 2 contexts = 6 calls). Conversion can |
bogdanm | 0:9b334a45a8ff | 4770 | * start once the 1st context is set. The 2nd context can be set on the fly. |
bogdanm | 0:9b334a45a8ff | 4771 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 4772 | * @param sConfigInjected: Structure of ADC injected group and ADC channel for |
bogdanm | 0:9b334a45a8ff | 4773 | * injected group. |
bogdanm | 0:9b334a45a8ff | 4774 | * @retval None |
bogdanm | 0:9b334a45a8ff | 4775 | */ |
bogdanm | 0:9b334a45a8ff | 4776 | HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) |
bogdanm | 0:9b334a45a8ff | 4777 | { |
bogdanm | 0:9b334a45a8ff | 4778 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 4779 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 4780 | ADC_HandleTypeDef tmphadcSharingSameCommonRegister; |
bogdanm | 0:9b334a45a8ff | 4781 | uint32_t tmpOffsetShifted; |
bogdanm | 0:9b334a45a8ff | 4782 | uint32_t WaitLoopIndex = 0; |
bogdanm | 0:9b334a45a8ff | 4783 | |
bogdanm | 0:9b334a45a8ff | 4784 | /* Injected context queue feature: temporary JSQR variables defined in */ |
bogdanm | 0:9b334a45a8ff | 4785 | /* static to be passed over calls of this function */ |
bogdanm | 0:9b334a45a8ff | 4786 | static uint32_t tmp_JSQR_ContextQueueBeingBuilt_ADCInstance = 0; |
bogdanm | 0:9b334a45a8ff | 4787 | static uint32_t tmp_JSQR_ContextQueueBeingBuilt_Channel_Count = 0; |
bogdanm | 0:9b334a45a8ff | 4788 | static uint32_t tmp_JSQR_ContextQueueBeingBuilt; |
bogdanm | 0:9b334a45a8ff | 4789 | |
bogdanm | 0:9b334a45a8ff | 4790 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 4791 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 4792 | assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); |
bogdanm | 0:9b334a45a8ff | 4793 | assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); |
bogdanm | 0:9b334a45a8ff | 4794 | assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); |
bogdanm | 0:9b334a45a8ff | 4795 | assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); |
bogdanm | 0:9b334a45a8ff | 4796 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 4797 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); |
bogdanm | 0:9b334a45a8ff | 4798 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); |
bogdanm | 0:9b334a45a8ff | 4799 | assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); |
bogdanm | 0:9b334a45a8ff | 4800 | assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); |
bogdanm | 0:9b334a45a8ff | 4801 | assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); |
bogdanm | 0:9b334a45a8ff | 4802 | assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); |
bogdanm | 0:9b334a45a8ff | 4803 | |
bogdanm | 0:9b334a45a8ff | 4804 | /* Verification of channel number: Channels 1 to 14 are available in */ |
bogdanm | 0:9b334a45a8ff | 4805 | /* differential mode. Channels 15, 16, 17, 18 can be used only in */ |
bogdanm | 0:9b334a45a8ff | 4806 | /* single-ended mode. */ |
bogdanm | 0:9b334a45a8ff | 4807 | if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 4808 | { |
bogdanm | 0:9b334a45a8ff | 4809 | assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); |
bogdanm | 0:9b334a45a8ff | 4810 | } |
bogdanm | 0:9b334a45a8ff | 4811 | else |
bogdanm | 0:9b334a45a8ff | 4812 | { |
bogdanm | 0:9b334a45a8ff | 4813 | assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel)); |
bogdanm | 0:9b334a45a8ff | 4814 | } |
bogdanm | 0:9b334a45a8ff | 4815 | |
bogdanm | 0:9b334a45a8ff | 4816 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 4817 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4818 | |
bogdanm | 0:9b334a45a8ff | 4819 | |
bogdanm | 0:9b334a45a8ff | 4820 | /* Configuration of Injected group sequencer. */ |
bogdanm | 0:9b334a45a8ff | 4821 | /* Hardware constraint: Must fully define injected context register JSQR */ |
bogdanm | 0:9b334a45a8ff | 4822 | /* before make it entering into injected sequencer queue. */ |
bogdanm | 0:9b334a45a8ff | 4823 | /* */ |
bogdanm | 0:9b334a45a8ff | 4824 | /* - if scan mode is disabled: */ |
bogdanm | 0:9b334a45a8ff | 4825 | /* * Injected channels sequence length is set to 0x00: 1 channel */ |
bogdanm | 0:9b334a45a8ff | 4826 | /* converted (channel on injected rank 1) */ |
bogdanm | 0:9b334a45a8ff | 4827 | /* Parameter "InjectedNbrOfConversion" is discarded. */ |
bogdanm | 0:9b334a45a8ff | 4828 | /* * Injected context register JSQR setting is simple: register is fully */ |
bogdanm | 0:9b334a45a8ff | 4829 | /* defined on one call of this function (for injected rank 1) and can */ |
bogdanm | 0:9b334a45a8ff | 4830 | /* be entered into queue directly. */ |
bogdanm | 0:9b334a45a8ff | 4831 | /* - if scan mode is enabled: */ |
bogdanm | 0:9b334a45a8ff | 4832 | /* * Injected channels sequence length is set to parameter */ |
bogdanm | 0:9b334a45a8ff | 4833 | /* "InjectedNbrOfConversion". */ |
bogdanm | 0:9b334a45a8ff | 4834 | /* * Injected context register JSQR setting more complex: register is */ |
bogdanm | 0:9b334a45a8ff | 4835 | /* fully defined over successive calls of this function, for each */ |
bogdanm | 0:9b334a45a8ff | 4836 | /* injected channel rank. It is entered into queue only when all */ |
bogdanm | 0:9b334a45a8ff | 4837 | /* injected ranks have been set. */ |
bogdanm | 0:9b334a45a8ff | 4838 | /* Note: Scan mode is not present by hardware on this device, but used */ |
bogdanm | 0:9b334a45a8ff | 4839 | /* by software for alignment over all STM32 devices. */ |
bogdanm | 0:9b334a45a8ff | 4840 | |
bogdanm | 0:9b334a45a8ff | 4841 | if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || |
bogdanm | 0:9b334a45a8ff | 4842 | (sConfigInjected->InjectedNbrOfConversion == 1) ) |
bogdanm | 0:9b334a45a8ff | 4843 | { |
bogdanm | 0:9b334a45a8ff | 4844 | /* Configuration of context register JSQR: */ |
bogdanm | 0:9b334a45a8ff | 4845 | /* - number of ranks in injected group sequencer: fixed to 1st rank */ |
bogdanm | 0:9b334a45a8ff | 4846 | /* (scan mode disabled, only rank 1 used) */ |
bogdanm | 0:9b334a45a8ff | 4847 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 4848 | /* - external trigger polarity */ |
bogdanm | 0:9b334a45a8ff | 4849 | /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */ |
bogdanm | 0:9b334a45a8ff | 4850 | |
bogdanm | 0:9b334a45a8ff | 4851 | if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) |
bogdanm | 0:9b334a45a8ff | 4852 | { |
bogdanm | 0:9b334a45a8ff | 4853 | tmp_JSQR_ContextQueueBeingBuilt = 0; |
bogdanm | 0:9b334a45a8ff | 4854 | |
bogdanm | 0:9b334a45a8ff | 4855 | /* Enable external trigger if trigger selection is different of */ |
bogdanm | 0:9b334a45a8ff | 4856 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 4857 | /* Note: This configuration keeps the hardware feature of parameter */ |
bogdanm | 0:9b334a45a8ff | 4858 | /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ |
bogdanm | 0:9b334a45a8ff | 4859 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 4860 | if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 4861 | { |
bogdanm | 0:9b334a45a8ff | 4862 | tmp_JSQR_ContextQueueBeingBuilt |= ( __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | |
bogdanm | 0:9b334a45a8ff | 4863 | __HAL_ADC_JSQR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) | |
bogdanm | 0:9b334a45a8ff | 4864 | sConfigInjected->ExternalTrigInjecConvEdge ); |
bogdanm | 0:9b334a45a8ff | 4865 | } |
bogdanm | 0:9b334a45a8ff | 4866 | else |
bogdanm | 0:9b334a45a8ff | 4867 | { |
bogdanm | 0:9b334a45a8ff | 4868 | tmp_JSQR_ContextQueueBeingBuilt |= ( __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); |
bogdanm | 0:9b334a45a8ff | 4869 | } |
bogdanm | 0:9b334a45a8ff | 4870 | |
bogdanm | 0:9b334a45a8ff | 4871 | hadc->Instance->JSQR = tmp_JSQR_ContextQueueBeingBuilt; |
bogdanm | 0:9b334a45a8ff | 4872 | |
bogdanm | 0:9b334a45a8ff | 4873 | } |
bogdanm | 0:9b334a45a8ff | 4874 | /* If another injected rank than rank1 was intended to be set, and could */ |
bogdanm | 0:9b334a45a8ff | 4875 | /* not due to ScanConvMode disabled, error is reported. */ |
bogdanm | 0:9b334a45a8ff | 4876 | else |
bogdanm | 0:9b334a45a8ff | 4877 | { |
bogdanm | 0:9b334a45a8ff | 4878 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4879 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4880 | |
bogdanm | 0:9b334a45a8ff | 4881 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4882 | } |
bogdanm | 0:9b334a45a8ff | 4883 | |
bogdanm | 0:9b334a45a8ff | 4884 | } |
bogdanm | 0:9b334a45a8ff | 4885 | else |
bogdanm | 0:9b334a45a8ff | 4886 | { |
bogdanm | 0:9b334a45a8ff | 4887 | /* Case of scan mode enabled, several channels to set into injected group */ |
bogdanm | 0:9b334a45a8ff | 4888 | /* sequencer. */ |
bogdanm | 0:9b334a45a8ff | 4889 | /* Procedure to define injected context register JSQR over successive */ |
bogdanm | 0:9b334a45a8ff | 4890 | /* calls of this function, for each injected channel rank: */ |
bogdanm | 0:9b334a45a8ff | 4891 | |
bogdanm | 0:9b334a45a8ff | 4892 | /* 1. Start new context and set parameters related to all injected */ |
bogdanm | 0:9b334a45a8ff | 4893 | /* channels: injected sequence length and trigger */ |
bogdanm | 0:9b334a45a8ff | 4894 | if (tmp_JSQR_ContextQueueBeingBuilt_Channel_Count == 0) |
bogdanm | 0:9b334a45a8ff | 4895 | { |
bogdanm | 0:9b334a45a8ff | 4896 | /* Memorize ADC instance on the context being built */ |
bogdanm | 0:9b334a45a8ff | 4897 | tmp_JSQR_ContextQueueBeingBuilt_ADCInstance = (uint32_t)hadc->Instance; |
bogdanm | 0:9b334a45a8ff | 4898 | /* Initialize number of channels that will be configured on the context */ |
bogdanm | 0:9b334a45a8ff | 4899 | /* being built */ |
bogdanm | 0:9b334a45a8ff | 4900 | tmp_JSQR_ContextQueueBeingBuilt_Channel_Count = sConfigInjected->InjectedNbrOfConversion; |
bogdanm | 0:9b334a45a8ff | 4901 | /* Initialize value that will be set into register JSQR */ |
bogdanm | 0:9b334a45a8ff | 4902 | tmp_JSQR_ContextQueueBeingBuilt = (uint32_t)0x00000000; |
bogdanm | 0:9b334a45a8ff | 4903 | |
bogdanm | 0:9b334a45a8ff | 4904 | /* Configuration of context register JSQR: */ |
bogdanm | 0:9b334a45a8ff | 4905 | /* - number of ranks in injected group sequencer */ |
bogdanm | 0:9b334a45a8ff | 4906 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 4907 | /* - external trigger polarity */ |
bogdanm | 0:9b334a45a8ff | 4908 | tmp_JSQR_ContextQueueBeingBuilt = 0; |
bogdanm | 0:9b334a45a8ff | 4909 | |
bogdanm | 0:9b334a45a8ff | 4910 | /* Enable external trigger if trigger selection is different of */ |
bogdanm | 0:9b334a45a8ff | 4911 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 4912 | /* Note: This configuration keeps the hardware feature of parameter */ |
bogdanm | 0:9b334a45a8ff | 4913 | /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ |
bogdanm | 0:9b334a45a8ff | 4914 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 4915 | if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 4916 | { |
bogdanm | 0:9b334a45a8ff | 4917 | tmp_JSQR_ContextQueueBeingBuilt |= ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) | |
bogdanm | 0:9b334a45a8ff | 4918 | __HAL_ADC_JSQR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) | |
bogdanm | 0:9b334a45a8ff | 4919 | sConfigInjected->ExternalTrigInjecConvEdge ); |
bogdanm | 0:9b334a45a8ff | 4920 | } |
bogdanm | 0:9b334a45a8ff | 4921 | else |
bogdanm | 0:9b334a45a8ff | 4922 | { |
bogdanm | 0:9b334a45a8ff | 4923 | tmp_JSQR_ContextQueueBeingBuilt |= ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) ); |
bogdanm | 0:9b334a45a8ff | 4924 | } |
bogdanm | 0:9b334a45a8ff | 4925 | |
bogdanm | 0:9b334a45a8ff | 4926 | } |
bogdanm | 0:9b334a45a8ff | 4927 | |
bogdanm | 0:9b334a45a8ff | 4928 | /* Verification that context being built is still targeting the same ADC */ |
bogdanm | 0:9b334a45a8ff | 4929 | /* instance. If ADC instance mixing during context being built, ADC state */ |
bogdanm | 0:9b334a45a8ff | 4930 | /* changed to error */ |
bogdanm | 0:9b334a45a8ff | 4931 | if ((uint32_t)hadc->Instance == tmp_JSQR_ContextQueueBeingBuilt_ADCInstance) |
bogdanm | 0:9b334a45a8ff | 4932 | { |
bogdanm | 0:9b334a45a8ff | 4933 | /* 2. Continue setting of context under definition with parameter */ |
bogdanm | 0:9b334a45a8ff | 4934 | /* related to each channel: channel rank sequence */ |
bogdanm | 0:9b334a45a8ff | 4935 | /* Clear the old JSQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4936 | tmp_JSQR_ContextQueueBeingBuilt &= ~__HAL_ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); |
bogdanm | 0:9b334a45a8ff | 4937 | |
bogdanm | 0:9b334a45a8ff | 4938 | /* Set the JSQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 4939 | tmp_JSQR_ContextQueueBeingBuilt |= __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); |
bogdanm | 0:9b334a45a8ff | 4940 | |
bogdanm | 0:9b334a45a8ff | 4941 | /* Decrease channel count after setting into temporary JSQR variable */ |
bogdanm | 0:9b334a45a8ff | 4942 | tmp_JSQR_ContextQueueBeingBuilt_Channel_Count --; |
bogdanm | 0:9b334a45a8ff | 4943 | |
bogdanm | 0:9b334a45a8ff | 4944 | /* 3. End of context setting: If last channel set, then write context */ |
bogdanm | 0:9b334a45a8ff | 4945 | /* into register JSQR and make it enter into queue */ |
bogdanm | 0:9b334a45a8ff | 4946 | if (tmp_JSQR_ContextQueueBeingBuilt_Channel_Count == 0) |
bogdanm | 0:9b334a45a8ff | 4947 | { |
bogdanm | 0:9b334a45a8ff | 4948 | hadc->Instance->JSQR = tmp_JSQR_ContextQueueBeingBuilt; |
bogdanm | 0:9b334a45a8ff | 4949 | |
bogdanm | 0:9b334a45a8ff | 4950 | /* Reset context channels count for next context configuration */ |
bogdanm | 0:9b334a45a8ff | 4951 | tmp_JSQR_ContextQueueBeingBuilt_Channel_Count =0; |
bogdanm | 0:9b334a45a8ff | 4952 | } |
bogdanm | 0:9b334a45a8ff | 4953 | } |
bogdanm | 0:9b334a45a8ff | 4954 | else |
bogdanm | 0:9b334a45a8ff | 4955 | { |
bogdanm | 0:9b334a45a8ff | 4956 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4957 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4958 | |
bogdanm | 0:9b334a45a8ff | 4959 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 4960 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 4961 | |
bogdanm | 0:9b334a45a8ff | 4962 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4963 | } |
bogdanm | 0:9b334a45a8ff | 4964 | } |
bogdanm | 0:9b334a45a8ff | 4965 | |
bogdanm | 0:9b334a45a8ff | 4966 | |
bogdanm | 0:9b334a45a8ff | 4967 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 4968 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 4969 | /* conversion on going on injected group: */ |
bogdanm | 0:9b334a45a8ff | 4970 | /* - Injected context queue: Queue disable (active context is kept) or */ |
bogdanm | 0:9b334a45a8ff | 4971 | /* enable (context decremented, up to 2 contexts queued) */ |
bogdanm | 0:9b334a45a8ff | 4972 | /* - Injected discontinuous mode: can be enabled only if auto-injected */ |
bogdanm | 0:9b334a45a8ff | 4973 | /* mode is disabled. */ |
bogdanm | 0:9b334a45a8ff | 4974 | if (__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 4975 | { |
bogdanm | 0:9b334a45a8ff | 4976 | hadc->Instance->CFGR &= ~(ADC_CFGR_JQM | |
bogdanm | 0:9b334a45a8ff | 4977 | ADC_CFGR_JDISCEN ); |
bogdanm | 0:9b334a45a8ff | 4978 | |
bogdanm | 0:9b334a45a8ff | 4979 | /* If auto-injected mode is disabled: no constraint */ |
bogdanm | 0:9b334a45a8ff | 4980 | if (sConfigInjected->AutoInjectedConv == DISABLE) |
bogdanm | 0:9b334a45a8ff | 4981 | { |
bogdanm | 0:9b334a45a8ff | 4982 | hadc->Instance->CFGR |= (__HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | |
bogdanm | 0:9b334a45a8ff | 4983 | __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); |
bogdanm | 0:9b334a45a8ff | 4984 | } |
bogdanm | 0:9b334a45a8ff | 4985 | /* If auto-injected mode is enabled: Injected discontinuous setting is */ |
bogdanm | 0:9b334a45a8ff | 4986 | /* discarded. */ |
bogdanm | 0:9b334a45a8ff | 4987 | else |
bogdanm | 0:9b334a45a8ff | 4988 | { |
bogdanm | 0:9b334a45a8ff | 4989 | hadc->Instance->CFGR |= __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext); |
bogdanm | 0:9b334a45a8ff | 4990 | |
bogdanm | 0:9b334a45a8ff | 4991 | /* If injected discontinuous mode was intended to be set and could not */ |
bogdanm | 0:9b334a45a8ff | 4992 | /* due to auto-injected enabled, error is reported. */ |
bogdanm | 0:9b334a45a8ff | 4993 | if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 4994 | { |
bogdanm | 0:9b334a45a8ff | 4995 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 4996 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 4997 | |
bogdanm | 0:9b334a45a8ff | 4998 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 4999 | } |
bogdanm | 0:9b334a45a8ff | 5000 | } |
bogdanm | 0:9b334a45a8ff | 5001 | |
bogdanm | 0:9b334a45a8ff | 5002 | } |
bogdanm | 0:9b334a45a8ff | 5003 | |
bogdanm | 0:9b334a45a8ff | 5004 | |
bogdanm | 0:9b334a45a8ff | 5005 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 5006 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 5007 | /* conversion on going on regular and injected groups: */ |
bogdanm | 0:9b334a45a8ff | 5008 | /* - Automatic injected conversion: can be enabled if injected group */ |
bogdanm | 0:9b334a45a8ff | 5009 | /* external triggers are disabled. */ |
bogdanm | 0:9b334a45a8ff | 5010 | /* - Channel sampling time */ |
bogdanm | 0:9b334a45a8ff | 5011 | /* - Channel offset */ |
bogdanm | 0:9b334a45a8ff | 5012 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 5013 | { |
bogdanm | 0:9b334a45a8ff | 5014 | /* Configure Automatic injected conversion */ |
bogdanm | 0:9b334a45a8ff | 5015 | hadc->Instance->CFGR &= ~(ADC_CFGR_JAUTO); |
bogdanm | 0:9b334a45a8ff | 5016 | |
bogdanm | 0:9b334a45a8ff | 5017 | /* If injected group external triggers are disabled (set to injected */ |
bogdanm | 0:9b334a45a8ff | 5018 | /* software start): no constraint */ |
bogdanm | 0:9b334a45a8ff | 5019 | if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 5020 | { |
bogdanm | 0:9b334a45a8ff | 5021 | hadc->Instance->CFGR |= __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv); |
bogdanm | 0:9b334a45a8ff | 5022 | } |
bogdanm | 0:9b334a45a8ff | 5023 | /* If Automatic injected conversion was intended to be set and could not */ |
bogdanm | 0:9b334a45a8ff | 5024 | /* due to injected group external triggers enabled, error is reported. */ |
bogdanm | 0:9b334a45a8ff | 5025 | else |
bogdanm | 0:9b334a45a8ff | 5026 | { |
bogdanm | 0:9b334a45a8ff | 5027 | if (sConfigInjected->AutoInjectedConv == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5028 | { |
bogdanm | 0:9b334a45a8ff | 5029 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5030 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5031 | |
bogdanm | 0:9b334a45a8ff | 5032 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5033 | } |
bogdanm | 0:9b334a45a8ff | 5034 | } |
bogdanm | 0:9b334a45a8ff | 5035 | |
bogdanm | 0:9b334a45a8ff | 5036 | |
bogdanm | 0:9b334a45a8ff | 5037 | /* Sampling time configuration of the selected channel */ |
bogdanm | 0:9b334a45a8ff | 5038 | /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ |
bogdanm | 0:9b334a45a8ff | 5039 | if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 5040 | { |
bogdanm | 0:9b334a45a8ff | 5041 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5042 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5043 | |
bogdanm | 0:9b334a45a8ff | 5044 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5045 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5046 | } |
bogdanm | 0:9b334a45a8ff | 5047 | else /* ADC_Channel include in ADC_Channel_[0..9] */ |
bogdanm | 0:9b334a45a8ff | 5048 | { |
bogdanm | 0:9b334a45a8ff | 5049 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5050 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5051 | |
bogdanm | 0:9b334a45a8ff | 5052 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5053 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5054 | } |
bogdanm | 0:9b334a45a8ff | 5055 | |
bogdanm | 0:9b334a45a8ff | 5056 | /* Configure the offset: offset enable/disable, channel, offset value */ |
bogdanm | 0:9b334a45a8ff | 5057 | |
bogdanm | 0:9b334a45a8ff | 5058 | /* Shift the offset in function of the selected ADC resolution. */ |
bogdanm | 0:9b334a45a8ff | 5059 | /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
bogdanm | 0:9b334a45a8ff | 5060 | tmpOffsetShifted = __HAL_ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); |
bogdanm | 0:9b334a45a8ff | 5061 | |
bogdanm | 0:9b334a45a8ff | 5062 | switch (sConfigInjected->InjectedOffsetNumber) |
bogdanm | 0:9b334a45a8ff | 5063 | { |
bogdanm | 0:9b334a45a8ff | 5064 | case ADC_OFFSET_1: |
bogdanm | 0:9b334a45a8ff | 5065 | /* Configure offset register 1: */ |
bogdanm | 0:9b334a45a8ff | 5066 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 5067 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 5068 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 5069 | hadc->Instance->OFR1 &= ~( ADC_OFR1_OFFSET1_CH | |
bogdanm | 0:9b334a45a8ff | 5070 | ADC_OFR1_OFFSET1 ); |
bogdanm | 0:9b334a45a8ff | 5071 | hadc->Instance->OFR1 |= ( ADC_OFR1_OFFSET1_EN | |
bogdanm | 0:9b334a45a8ff | 5072 | __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | |
bogdanm | 0:9b334a45a8ff | 5073 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 5074 | break; |
bogdanm | 0:9b334a45a8ff | 5075 | |
bogdanm | 0:9b334a45a8ff | 5076 | case ADC_OFFSET_2: |
bogdanm | 0:9b334a45a8ff | 5077 | /* Configure offset register 2: */ |
bogdanm | 0:9b334a45a8ff | 5078 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 5079 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 5080 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 5081 | hadc->Instance->OFR2 &= ~( ADC_OFR2_OFFSET2_CH | |
bogdanm | 0:9b334a45a8ff | 5082 | ADC_OFR2_OFFSET2 ); |
bogdanm | 0:9b334a45a8ff | 5083 | hadc->Instance->OFR2 |= ( ADC_OFR2_OFFSET2_EN | |
bogdanm | 0:9b334a45a8ff | 5084 | __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | |
bogdanm | 0:9b334a45a8ff | 5085 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 5086 | break; |
bogdanm | 0:9b334a45a8ff | 5087 | |
bogdanm | 0:9b334a45a8ff | 5088 | case ADC_OFFSET_3: |
bogdanm | 0:9b334a45a8ff | 5089 | /* Configure offset register 3: */ |
bogdanm | 0:9b334a45a8ff | 5090 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 5091 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 5092 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 5093 | hadc->Instance->OFR3 &= ~( ADC_OFR3_OFFSET3_CH | |
bogdanm | 0:9b334a45a8ff | 5094 | ADC_OFR3_OFFSET3 ); |
bogdanm | 0:9b334a45a8ff | 5095 | hadc->Instance->OFR3 |= ( ADC_OFR3_OFFSET3_EN | |
bogdanm | 0:9b334a45a8ff | 5096 | __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | |
bogdanm | 0:9b334a45a8ff | 5097 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 5098 | break; |
bogdanm | 0:9b334a45a8ff | 5099 | |
bogdanm | 0:9b334a45a8ff | 5100 | case ADC_OFFSET_4: |
bogdanm | 0:9b334a45a8ff | 5101 | /* Configure offset register 1: */ |
bogdanm | 0:9b334a45a8ff | 5102 | /* - Enable offset */ |
bogdanm | 0:9b334a45a8ff | 5103 | /* - Set channel number */ |
bogdanm | 0:9b334a45a8ff | 5104 | /* - Set offset value */ |
bogdanm | 0:9b334a45a8ff | 5105 | hadc->Instance->OFR4 &= ~( ADC_OFR4_OFFSET4_CH | |
bogdanm | 0:9b334a45a8ff | 5106 | ADC_OFR4_OFFSET4 ); |
bogdanm | 0:9b334a45a8ff | 5107 | hadc->Instance->OFR4 |= ( ADC_OFR4_OFFSET4_EN | |
bogdanm | 0:9b334a45a8ff | 5108 | __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | |
bogdanm | 0:9b334a45a8ff | 5109 | tmpOffsetShifted ); |
bogdanm | 0:9b334a45a8ff | 5110 | break; |
bogdanm | 0:9b334a45a8ff | 5111 | |
bogdanm | 0:9b334a45a8ff | 5112 | /* Case ADC_OFFSET_NONE */ |
bogdanm | 0:9b334a45a8ff | 5113 | default : |
bogdanm | 0:9b334a45a8ff | 5114 | /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */ |
bogdanm | 0:9b334a45a8ff | 5115 | if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) |
bogdanm | 0:9b334a45a8ff | 5116 | { |
bogdanm | 0:9b334a45a8ff | 5117 | /* Disable offset OFR1*/ |
bogdanm | 0:9b334a45a8ff | 5118 | hadc->Instance->OFR1 &= ~ADC_OFR1_OFFSET1_EN; |
bogdanm | 0:9b334a45a8ff | 5119 | } |
bogdanm | 0:9b334a45a8ff | 5120 | if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) |
bogdanm | 0:9b334a45a8ff | 5121 | { |
bogdanm | 0:9b334a45a8ff | 5122 | /* Disable offset OFR2*/ |
bogdanm | 0:9b334a45a8ff | 5123 | hadc->Instance->OFR2 &= ~ADC_OFR2_OFFSET2_EN; |
bogdanm | 0:9b334a45a8ff | 5124 | } |
bogdanm | 0:9b334a45a8ff | 5125 | if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) |
bogdanm | 0:9b334a45a8ff | 5126 | { |
bogdanm | 0:9b334a45a8ff | 5127 | /* Disable offset OFR3*/ |
bogdanm | 0:9b334a45a8ff | 5128 | hadc->Instance->OFR3 &= ~ADC_OFR3_OFFSET3_EN; |
bogdanm | 0:9b334a45a8ff | 5129 | } |
bogdanm | 0:9b334a45a8ff | 5130 | if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) |
bogdanm | 0:9b334a45a8ff | 5131 | { |
bogdanm | 0:9b334a45a8ff | 5132 | /* Disable offset OFR4*/ |
bogdanm | 0:9b334a45a8ff | 5133 | hadc->Instance->OFR4 &= ~ADC_OFR4_OFFSET4_EN; |
bogdanm | 0:9b334a45a8ff | 5134 | } |
bogdanm | 0:9b334a45a8ff | 5135 | break; |
bogdanm | 0:9b334a45a8ff | 5136 | } |
bogdanm | 0:9b334a45a8ff | 5137 | |
bogdanm | 0:9b334a45a8ff | 5138 | } |
bogdanm | 0:9b334a45a8ff | 5139 | |
bogdanm | 0:9b334a45a8ff | 5140 | |
bogdanm | 0:9b334a45a8ff | 5141 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 5142 | /* Parameters that can be updated only when ADC is disabled: */ |
bogdanm | 0:9b334a45a8ff | 5143 | /* - Single or differential mode */ |
bogdanm | 0:9b334a45a8ff | 5144 | /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ |
bogdanm | 0:9b334a45a8ff | 5145 | if (__HAL_ADC_IS_ENABLED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 5146 | { |
bogdanm | 0:9b334a45a8ff | 5147 | /* Configuration of differential mode */ |
bogdanm | 0:9b334a45a8ff | 5148 | if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) |
bogdanm | 0:9b334a45a8ff | 5149 | { |
bogdanm | 0:9b334a45a8ff | 5150 | /* Disable differential mode (default mode: single-ended) */ |
bogdanm | 0:9b334a45a8ff | 5151 | hadc->Instance->DIFSEL &= ~(__HAL_ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); |
bogdanm | 0:9b334a45a8ff | 5152 | } |
bogdanm | 0:9b334a45a8ff | 5153 | else |
bogdanm | 0:9b334a45a8ff | 5154 | { |
bogdanm | 0:9b334a45a8ff | 5155 | /* Enable differential mode */ |
bogdanm | 0:9b334a45a8ff | 5156 | hadc->Instance->DIFSEL |= __HAL_ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5157 | |
bogdanm | 0:9b334a45a8ff | 5158 | /* Sampling time configuration of channel ADC_IN+1 (negative input) */ |
bogdanm | 0:9b334a45a8ff | 5159 | /* For channels 10 to 18 */ |
bogdanm | 0:9b334a45a8ff | 5160 | if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 5161 | { |
bogdanm | 0:9b334a45a8ff | 5162 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5163 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, (sConfigInjected->InjectedChannel +1)); |
bogdanm | 0:9b334a45a8ff | 5164 | |
bogdanm | 0:9b334a45a8ff | 5165 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5166 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, (sConfigInjected->InjectedChannel +1)); |
bogdanm | 0:9b334a45a8ff | 5167 | } |
bogdanm | 0:9b334a45a8ff | 5168 | else /* For channels 0 to 9 */ |
bogdanm | 0:9b334a45a8ff | 5169 | { |
bogdanm | 0:9b334a45a8ff | 5170 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5171 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, (sConfigInjected->InjectedChannel +1)); |
bogdanm | 0:9b334a45a8ff | 5172 | |
bogdanm | 0:9b334a45a8ff | 5173 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5174 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, (sConfigInjected->InjectedChannel +1)); |
bogdanm | 0:9b334a45a8ff | 5175 | } |
bogdanm | 0:9b334a45a8ff | 5176 | } |
bogdanm | 0:9b334a45a8ff | 5177 | |
bogdanm | 0:9b334a45a8ff | 5178 | |
bogdanm | 0:9b334a45a8ff | 5179 | /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ |
bogdanm | 0:9b334a45a8ff | 5180 | /* internal measurement paths enable: If internal channel selected, */ |
bogdanm | 0:9b334a45a8ff | 5181 | /* enable dedicated internal buffers and path. */ |
bogdanm | 0:9b334a45a8ff | 5182 | /* Note: these internal measurement paths can be disabled using */ |
bogdanm | 0:9b334a45a8ff | 5183 | /* HAL_ADC_deInit(). */ |
bogdanm | 0:9b334a45a8ff | 5184 | |
bogdanm | 0:9b334a45a8ff | 5185 | /* Configuration of common ADC parameters */ |
bogdanm | 0:9b334a45a8ff | 5186 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 5187 | /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 5188 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 5189 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 5190 | |
bogdanm | 0:9b334a45a8ff | 5191 | /* If the requested internal measurement path has already been enabled, */ |
bogdanm | 0:9b334a45a8ff | 5192 | /* bypass the configuration processing. */ |
bogdanm | 0:9b334a45a8ff | 5193 | if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && |
bogdanm | 0:9b334a45a8ff | 5194 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || |
bogdanm | 0:9b334a45a8ff | 5195 | ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && |
bogdanm | 0:9b334a45a8ff | 5196 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || |
bogdanm | 0:9b334a45a8ff | 5197 | ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && |
bogdanm | 0:9b334a45a8ff | 5198 | (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) |
bogdanm | 0:9b334a45a8ff | 5199 | ) |
bogdanm | 0:9b334a45a8ff | 5200 | { |
bogdanm | 0:9b334a45a8ff | 5201 | /* Configuration of common ADC parameters (continuation) */ |
bogdanm | 0:9b334a45a8ff | 5202 | /* Set handle of the other ADC sharing the same common register */ |
bogdanm | 0:9b334a45a8ff | 5203 | __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); |
bogdanm | 0:9b334a45a8ff | 5204 | |
bogdanm | 0:9b334a45a8ff | 5205 | /* Software is allowed to change common parameters only when all ADCs */ |
bogdanm | 0:9b334a45a8ff | 5206 | /* of the common group are disabled. */ |
bogdanm | 0:9b334a45a8ff | 5207 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 5208 | ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) || |
bogdanm | 0:9b334a45a8ff | 5209 | (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) )) |
bogdanm | 0:9b334a45a8ff | 5210 | { |
bogdanm | 0:9b334a45a8ff | 5211 | /* If Channel_16 is selected, enable Temp. sensor measurement path */ |
bogdanm | 0:9b334a45a8ff | 5212 | /* Note: Temp. sensor internal channels available on ADC1 only */ |
bogdanm | 0:9b334a45a8ff | 5213 | if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) |
bogdanm | 0:9b334a45a8ff | 5214 | { |
bogdanm | 0:9b334a45a8ff | 5215 | tmpADC_Common->CCR |= ADC_CCR_TSEN; |
bogdanm | 0:9b334a45a8ff | 5216 | |
bogdanm | 0:9b334a45a8ff | 5217 | /* Delay for temperature sensor stabilization time */ |
bogdanm | 0:9b334a45a8ff | 5218 | while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES) |
bogdanm | 0:9b334a45a8ff | 5219 | { |
bogdanm | 0:9b334a45a8ff | 5220 | WaitLoopIndex++; |
bogdanm | 0:9b334a45a8ff | 5221 | } |
bogdanm | 0:9b334a45a8ff | 5222 | } |
bogdanm | 0:9b334a45a8ff | 5223 | /* If Channel_17 is selected, enable VBAT measurement path */ |
bogdanm | 0:9b334a45a8ff | 5224 | /* Note: VBAT internal channels available on ADC1 only */ |
bogdanm | 0:9b334a45a8ff | 5225 | else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) |
bogdanm | 0:9b334a45a8ff | 5226 | { |
bogdanm | 0:9b334a45a8ff | 5227 | tmpADC_Common->CCR |= ADC_CCR_VBATEN; |
bogdanm | 0:9b334a45a8ff | 5228 | } |
bogdanm | 0:9b334a45a8ff | 5229 | /* If Channel_18 is selected, enable VREFINT measurement path */ |
bogdanm | 0:9b334a45a8ff | 5230 | /* Note: VrefInt internal channels available on all ADCs, but only */ |
bogdanm | 0:9b334a45a8ff | 5231 | /* one ADC is allowed to be connected to VrefInt at the same */ |
bogdanm | 0:9b334a45a8ff | 5232 | /* time. */ |
bogdanm | 0:9b334a45a8ff | 5233 | else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) |
bogdanm | 0:9b334a45a8ff | 5234 | { |
bogdanm | 0:9b334a45a8ff | 5235 | tmpADC_Common->CCR |= ADC_CCR_VREFEN; |
bogdanm | 0:9b334a45a8ff | 5236 | } |
bogdanm | 0:9b334a45a8ff | 5237 | } |
bogdanm | 0:9b334a45a8ff | 5238 | /* If the requested internal measurement path has already been enabled */ |
bogdanm | 0:9b334a45a8ff | 5239 | /* and other ADC of the common group are enabled, internal */ |
bogdanm | 0:9b334a45a8ff | 5240 | /* measurement paths cannot be enabled. */ |
bogdanm | 0:9b334a45a8ff | 5241 | else |
bogdanm | 0:9b334a45a8ff | 5242 | { |
bogdanm | 0:9b334a45a8ff | 5243 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5244 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5245 | |
bogdanm | 0:9b334a45a8ff | 5246 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5247 | } |
bogdanm | 0:9b334a45a8ff | 5248 | } |
bogdanm | 0:9b334a45a8ff | 5249 | |
bogdanm | 0:9b334a45a8ff | 5250 | } |
bogdanm | 0:9b334a45a8ff | 5251 | |
bogdanm | 0:9b334a45a8ff | 5252 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 5253 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5254 | |
bogdanm | 0:9b334a45a8ff | 5255 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 5256 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 5257 | } |
bogdanm | 0:9b334a45a8ff | 5258 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 5259 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 5260 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 5261 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 5262 | |
bogdanm | 0:9b334a45a8ff | 5263 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 5264 | /** |
bogdanm | 0:9b334a45a8ff | 5265 | * @brief Configures the ADC injected group and the selected channel to be |
bogdanm | 0:9b334a45a8ff | 5266 | * linked to the injected group. |
bogdanm | 0:9b334a45a8ff | 5267 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 5268 | * This function initializes injected group, following calls to this |
bogdanm | 0:9b334a45a8ff | 5269 | * function can be used to reconfigure some parameters of structure |
bogdanm | 0:9b334a45a8ff | 5270 | * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. |
bogdanm | 0:9b334a45a8ff | 5271 | * The setting of these parameters is conditioned to ADC state: |
bogdanm | 0:9b334a45a8ff | 5272 | * this function must be called when ADC is not under conversion. |
bogdanm | 0:9b334a45a8ff | 5273 | * @note In case of usage of internal measurement channels: |
bogdanm | 0:9b334a45a8ff | 5274 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 5275 | * The recommended sampling time is at least: |
bogdanm | 0:9b334a45a8ff | 5276 | * - For devices STM32F37x: 17.1us for temperature sensor |
bogdanm | 0:9b334a45a8ff | 5277 | * - For the other STM32F3 devices: 2.2us for each of channels |
bogdanm | 0:9b334a45a8ff | 5278 | * Vbat/VrefInt/TempSensor. |
bogdanm | 0:9b334a45a8ff | 5279 | * These internal paths can be be disabled using function |
bogdanm | 0:9b334a45a8ff | 5280 | * HAL_ADC_DeInit(). |
bogdanm | 0:9b334a45a8ff | 5281 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5282 | * @param sConfigInjected: Structure of ADC injected group and ADC channel for |
bogdanm | 0:9b334a45a8ff | 5283 | * injected group. |
bogdanm | 0:9b334a45a8ff | 5284 | * @retval None |
bogdanm | 0:9b334a45a8ff | 5285 | */ |
bogdanm | 0:9b334a45a8ff | 5286 | HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) |
bogdanm | 0:9b334a45a8ff | 5287 | { |
bogdanm | 0:9b334a45a8ff | 5288 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 5289 | |
bogdanm | 0:9b334a45a8ff | 5290 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 5291 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 5292 | assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); |
bogdanm | 0:9b334a45a8ff | 5293 | assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); |
bogdanm | 0:9b334a45a8ff | 5294 | assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); |
bogdanm | 0:9b334a45a8ff | 5295 | assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); |
bogdanm | 0:9b334a45a8ff | 5296 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 5297 | assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); |
bogdanm | 0:9b334a45a8ff | 5298 | assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); |
bogdanm | 0:9b334a45a8ff | 5299 | assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); |
bogdanm | 0:9b334a45a8ff | 5300 | |
bogdanm | 0:9b334a45a8ff | 5301 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 5302 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5303 | |
bogdanm | 0:9b334a45a8ff | 5304 | |
bogdanm | 0:9b334a45a8ff | 5305 | /* Configuration of injected group sequencer: */ |
bogdanm | 0:9b334a45a8ff | 5306 | /* - if scan mode is disabled, injected channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 5307 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
bogdanm | 0:9b334a45a8ff | 5308 | /* Parameter "InjectedNbrOfConversion" is discarded. */ |
bogdanm | 0:9b334a45a8ff | 5309 | /* Note: Scan mode is present by hardware on this device and, if */ |
bogdanm | 0:9b334a45a8ff | 5310 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
bogdanm | 0:9b334a45a8ff | 5311 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
bogdanm | 0:9b334a45a8ff | 5312 | /* - if scan mode is enabled, injected channels sequence length is set to */ |
bogdanm | 0:9b334a45a8ff | 5313 | /* parameter ""InjectedNbrOfConversion". */ |
bogdanm | 0:9b334a45a8ff | 5314 | if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) |
bogdanm | 0:9b334a45a8ff | 5315 | { |
bogdanm | 0:9b334a45a8ff | 5316 | if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) |
bogdanm | 0:9b334a45a8ff | 5317 | { |
bogdanm | 0:9b334a45a8ff | 5318 | /* Clear the old SQx bits for all injected ranks */ |
bogdanm | 0:9b334a45a8ff | 5319 | hadc->Instance->JSQR &= ~ (ADC_JSQR_JL | |
bogdanm | 0:9b334a45a8ff | 5320 | ADC_JSQR_JSQ4 | |
bogdanm | 0:9b334a45a8ff | 5321 | ADC_JSQR_JSQ3 | |
bogdanm | 0:9b334a45a8ff | 5322 | ADC_JSQR_JSQ2 | |
bogdanm | 0:9b334a45a8ff | 5323 | ADC_JSQR_JSQ1 ); |
bogdanm | 0:9b334a45a8ff | 5324 | |
bogdanm | 0:9b334a45a8ff | 5325 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 5326 | hadc->Instance->JSQR |= __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, |
bogdanm | 0:9b334a45a8ff | 5327 | ADC_INJECTED_RANK_1, |
bogdanm | 0:9b334a45a8ff | 5328 | 0x01); |
bogdanm | 0:9b334a45a8ff | 5329 | } |
bogdanm | 0:9b334a45a8ff | 5330 | /* If another injected rank than rank1 was intended to be set, and could */ |
bogdanm | 0:9b334a45a8ff | 5331 | /* not due to ScanConvMode disabled, error is reported. */ |
bogdanm | 0:9b334a45a8ff | 5332 | else |
bogdanm | 0:9b334a45a8ff | 5333 | { |
bogdanm | 0:9b334a45a8ff | 5334 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5335 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5336 | |
bogdanm | 0:9b334a45a8ff | 5337 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5338 | } |
bogdanm | 0:9b334a45a8ff | 5339 | } |
bogdanm | 0:9b334a45a8ff | 5340 | else |
bogdanm | 0:9b334a45a8ff | 5341 | { |
bogdanm | 0:9b334a45a8ff | 5342 | /* Clear the old SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 5343 | hadc->Instance->JSQR &= ~ (ADC_JSQR_JL | |
bogdanm | 0:9b334a45a8ff | 5344 | __HAL_ADC_JSQR_RK(ADC_JSQR_JSQ1, |
bogdanm | 0:9b334a45a8ff | 5345 | sConfigInjected->InjectedRank, |
bogdanm | 0:9b334a45a8ff | 5346 | sConfigInjected->InjectedNbrOfConversion) ); |
bogdanm | 0:9b334a45a8ff | 5347 | |
bogdanm | 0:9b334a45a8ff | 5348 | /* Since injected channels rank conv. order depends on total number of */ |
bogdanm | 0:9b334a45a8ff | 5349 | /* injected conversions, selected rank must be below or equal to total */ |
bogdanm | 0:9b334a45a8ff | 5350 | /* number of injected conversions to be updated. */ |
bogdanm | 0:9b334a45a8ff | 5351 | if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) |
bogdanm | 0:9b334a45a8ff | 5352 | { |
bogdanm | 0:9b334a45a8ff | 5353 | /* Set the SQx bits for the selected rank */ |
bogdanm | 0:9b334a45a8ff | 5354 | hadc->Instance->JSQR |= (__HAL_ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) | |
bogdanm | 0:9b334a45a8ff | 5355 | __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, |
bogdanm | 0:9b334a45a8ff | 5356 | sConfigInjected->InjectedRank, |
bogdanm | 0:9b334a45a8ff | 5357 | sConfigInjected->InjectedNbrOfConversion) ); |
bogdanm | 0:9b334a45a8ff | 5358 | } |
bogdanm | 0:9b334a45a8ff | 5359 | } |
bogdanm | 0:9b334a45a8ff | 5360 | |
bogdanm | 0:9b334a45a8ff | 5361 | |
bogdanm | 0:9b334a45a8ff | 5362 | /* Configuration of injected group: external trigger */ |
bogdanm | 0:9b334a45a8ff | 5363 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 5364 | /* - external trigger polarity */ |
bogdanm | 0:9b334a45a8ff | 5365 | /* If Automatic injected conversion disabled: always set to 1, */ |
bogdanm | 0:9b334a45a8ff | 5366 | /* because needed for all triggers: external trigger of SW start) */ |
bogdanm | 0:9b334a45a8ff | 5367 | /* Hardware constraint: ADC must be disabled */ |
bogdanm | 0:9b334a45a8ff | 5368 | /* Note: In case of ADC already enabled, caution to not launch an unwanted */ |
bogdanm | 0:9b334a45a8ff | 5369 | /* conversion while modifying register CR2 by writing 1 to bit ADON */ |
bogdanm | 0:9b334a45a8ff | 5370 | /* These settings are modified only if required parameters are different as */ |
bogdanm | 0:9b334a45a8ff | 5371 | /* current setting */ |
bogdanm | 0:9b334a45a8ff | 5372 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 5373 | ((hadc->Instance->CR2 & ADC_CR2_JEXTSEL) != sConfigInjected->ExternalTrigInjecConv) ) |
bogdanm | 0:9b334a45a8ff | 5374 | { |
bogdanm | 0:9b334a45a8ff | 5375 | hadc->Instance->CR2 &= ~( ADC_CR2_JEXTSEL | |
bogdanm | 0:9b334a45a8ff | 5376 | ADC_CR2_JEXTTRIG | |
bogdanm | 0:9b334a45a8ff | 5377 | ADC_CR2_ADON ); |
bogdanm | 0:9b334a45a8ff | 5378 | |
bogdanm | 0:9b334a45a8ff | 5379 | /* If automatic injected conversion is intended to be enabled and */ |
bogdanm | 0:9b334a45a8ff | 5380 | /* conditions are fulfilled (injected group external triggers are */ |
bogdanm | 0:9b334a45a8ff | 5381 | /* disabled), then keep injected external trigger JEXTTRIG cleared */ |
bogdanm | 0:9b334a45a8ff | 5382 | if (!((sConfigInjected->AutoInjectedConv == ENABLE) && |
bogdanm | 0:9b334a45a8ff | 5383 | (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START))) |
bogdanm | 0:9b334a45a8ff | 5384 | { |
bogdanm | 0:9b334a45a8ff | 5385 | hadc->Instance->CR2 |= ( sConfigInjected->ExternalTrigInjecConv | |
bogdanm | 0:9b334a45a8ff | 5386 | ADC_CR2_JEXTTRIG ); |
bogdanm | 0:9b334a45a8ff | 5387 | } |
bogdanm | 0:9b334a45a8ff | 5388 | else |
bogdanm | 0:9b334a45a8ff | 5389 | { |
bogdanm | 0:9b334a45a8ff | 5390 | hadc->Instance->CR2 |= ( sConfigInjected->ExternalTrigInjecConv ); |
bogdanm | 0:9b334a45a8ff | 5391 | } |
bogdanm | 0:9b334a45a8ff | 5392 | } |
bogdanm | 0:9b334a45a8ff | 5393 | |
bogdanm | 0:9b334a45a8ff | 5394 | |
bogdanm | 0:9b334a45a8ff | 5395 | /* Configuration of injected group */ |
bogdanm | 0:9b334a45a8ff | 5396 | /* - Automatic injected conversion */ |
bogdanm | 0:9b334a45a8ff | 5397 | /* - Injected discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 5398 | hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | |
bogdanm | 0:9b334a45a8ff | 5399 | ADC_CR1_JDISCEN ); |
bogdanm | 0:9b334a45a8ff | 5400 | |
bogdanm | 0:9b334a45a8ff | 5401 | /* Automatic injected conversion can be enabled if injected group */ |
bogdanm | 0:9b334a45a8ff | 5402 | /* external triggers are disabled. */ |
bogdanm | 0:9b334a45a8ff | 5403 | if (sConfigInjected->AutoInjectedConv == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5404 | { |
bogdanm | 0:9b334a45a8ff | 5405 | if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 5406 | { |
bogdanm | 0:9b334a45a8ff | 5407 | hadc->Instance->CR1 |= ADC_CR1_JAUTO; |
bogdanm | 0:9b334a45a8ff | 5408 | } |
bogdanm | 0:9b334a45a8ff | 5409 | else |
bogdanm | 0:9b334a45a8ff | 5410 | { |
bogdanm | 0:9b334a45a8ff | 5411 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5412 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5413 | |
bogdanm | 0:9b334a45a8ff | 5414 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5415 | } |
bogdanm | 0:9b334a45a8ff | 5416 | } |
bogdanm | 0:9b334a45a8ff | 5417 | |
bogdanm | 0:9b334a45a8ff | 5418 | /* Injected discontinuous can be enabled only if auto-injected mode is */ |
bogdanm | 0:9b334a45a8ff | 5419 | /* disabled. */ |
bogdanm | 0:9b334a45a8ff | 5420 | if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5421 | { |
bogdanm | 0:9b334a45a8ff | 5422 | if (sConfigInjected->AutoInjectedConv == DISABLE) |
bogdanm | 0:9b334a45a8ff | 5423 | { |
bogdanm | 0:9b334a45a8ff | 5424 | hadc->Instance->CR1 |= ADC_CR1_JDISCEN; |
bogdanm | 0:9b334a45a8ff | 5425 | } |
bogdanm | 0:9b334a45a8ff | 5426 | else |
bogdanm | 0:9b334a45a8ff | 5427 | { |
bogdanm | 0:9b334a45a8ff | 5428 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5429 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5430 | |
bogdanm | 0:9b334a45a8ff | 5431 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5432 | } |
bogdanm | 0:9b334a45a8ff | 5433 | } |
bogdanm | 0:9b334a45a8ff | 5434 | |
bogdanm | 0:9b334a45a8ff | 5435 | |
bogdanm | 0:9b334a45a8ff | 5436 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 5437 | /* For channels 10 to 18 */ |
bogdanm | 0:9b334a45a8ff | 5438 | if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10) |
bogdanm | 0:9b334a45a8ff | 5439 | { |
bogdanm | 0:9b334a45a8ff | 5440 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5441 | hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5442 | |
bogdanm | 0:9b334a45a8ff | 5443 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5444 | hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5445 | } |
bogdanm | 0:9b334a45a8ff | 5446 | else /* For channels 0 to 9 */ |
bogdanm | 0:9b334a45a8ff | 5447 | { |
bogdanm | 0:9b334a45a8ff | 5448 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 5449 | hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5450 | |
bogdanm | 0:9b334a45a8ff | 5451 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 5452 | hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); |
bogdanm | 0:9b334a45a8ff | 5453 | } |
bogdanm | 0:9b334a45a8ff | 5454 | |
bogdanm | 0:9b334a45a8ff | 5455 | /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ |
bogdanm | 0:9b334a45a8ff | 5456 | switch(sConfigInjected->InjectedRank) |
bogdanm | 0:9b334a45a8ff | 5457 | { |
bogdanm | 0:9b334a45a8ff | 5458 | case 1: |
bogdanm | 0:9b334a45a8ff | 5459 | /* Set injected channel 1 offset */ |
bogdanm | 0:9b334a45a8ff | 5460 | hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); |
bogdanm | 0:9b334a45a8ff | 5461 | hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; |
bogdanm | 0:9b334a45a8ff | 5462 | break; |
bogdanm | 0:9b334a45a8ff | 5463 | case 2: |
bogdanm | 0:9b334a45a8ff | 5464 | /* Set injected channel 2 offset */ |
bogdanm | 0:9b334a45a8ff | 5465 | hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); |
bogdanm | 0:9b334a45a8ff | 5466 | hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; |
bogdanm | 0:9b334a45a8ff | 5467 | break; |
bogdanm | 0:9b334a45a8ff | 5468 | case 3: |
bogdanm | 0:9b334a45a8ff | 5469 | /* Set injected channel 3 offset */ |
bogdanm | 0:9b334a45a8ff | 5470 | hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); |
bogdanm | 0:9b334a45a8ff | 5471 | hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; |
bogdanm | 0:9b334a45a8ff | 5472 | break; |
bogdanm | 0:9b334a45a8ff | 5473 | default: |
bogdanm | 0:9b334a45a8ff | 5474 | /* Set injected channel 4 offset */ |
bogdanm | 0:9b334a45a8ff | 5475 | hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); |
bogdanm | 0:9b334a45a8ff | 5476 | hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; |
bogdanm | 0:9b334a45a8ff | 5477 | break; |
bogdanm | 0:9b334a45a8ff | 5478 | } |
bogdanm | 0:9b334a45a8ff | 5479 | |
bogdanm | 0:9b334a45a8ff | 5480 | /* if ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor / VREFINT measurement path */ |
bogdanm | 0:9b334a45a8ff | 5481 | if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)) |
bogdanm | 0:9b334a45a8ff | 5482 | { |
bogdanm | 0:9b334a45a8ff | 5483 | hadc->Instance->CR2 |= ADC_CR2_TSVREFE; |
bogdanm | 0:9b334a45a8ff | 5484 | } |
bogdanm | 0:9b334a45a8ff | 5485 | /* if ADC1 Channel_17 is selected, enable VBAT measurement path */ |
bogdanm | 0:9b334a45a8ff | 5486 | else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) |
bogdanm | 0:9b334a45a8ff | 5487 | { |
bogdanm | 0:9b334a45a8ff | 5488 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; |
bogdanm | 0:9b334a45a8ff | 5489 | } |
bogdanm | 0:9b334a45a8ff | 5490 | |
bogdanm | 0:9b334a45a8ff | 5491 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 5492 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5493 | |
bogdanm | 0:9b334a45a8ff | 5494 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 5495 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 5496 | } |
bogdanm | 0:9b334a45a8ff | 5497 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 5498 | |
bogdanm | 0:9b334a45a8ff | 5499 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 5500 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 5501 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 5502 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 5503 | /** |
bogdanm | 0:9b334a45a8ff | 5504 | * @brief Configures the analog watchdog. |
bogdanm | 0:9b334a45a8ff | 5505 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 5506 | * This function initializes the selected analog watchdog, following |
bogdanm | 0:9b334a45a8ff | 5507 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 5508 | * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 5509 | * the ADC. |
bogdanm | 0:9b334a45a8ff | 5510 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 5511 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 5512 | * "ADC_AnalogWDGConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 5513 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5514 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
bogdanm | 0:9b334a45a8ff | 5515 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 5516 | */ |
bogdanm | 0:9b334a45a8ff | 5517 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
bogdanm | 0:9b334a45a8ff | 5518 | { |
bogdanm | 0:9b334a45a8ff | 5519 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 5520 | |
bogdanm | 0:9b334a45a8ff | 5521 | uint32_t tmpAWDHighThresholdShifted; |
bogdanm | 0:9b334a45a8ff | 5522 | uint32_t tmpAWDLowThresholdShifted; |
bogdanm | 0:9b334a45a8ff | 5523 | |
bogdanm | 0:9b334a45a8ff | 5524 | uint32_t tmpADCFlagAWD2orAWD3; |
bogdanm | 0:9b334a45a8ff | 5525 | uint32_t tmpADCITAWD2orAWD3; |
bogdanm | 0:9b334a45a8ff | 5526 | |
bogdanm | 0:9b334a45a8ff | 5527 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 5528 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 5529 | assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); |
bogdanm | 0:9b334a45a8ff | 5530 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
bogdanm | 0:9b334a45a8ff | 5531 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 5532 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
bogdanm | 0:9b334a45a8ff | 5533 | |
bogdanm | 0:9b334a45a8ff | 5534 | /* Verify if threshold is within the selected ADC resolution */ |
bogdanm | 0:9b334a45a8ff | 5535 | assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); |
bogdanm | 0:9b334a45a8ff | 5536 | assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); |
bogdanm | 0:9b334a45a8ff | 5537 | |
bogdanm | 0:9b334a45a8ff | 5538 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 5539 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5540 | |
bogdanm | 0:9b334a45a8ff | 5541 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 5542 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 5543 | /* conversion on going on regular and injected groups: */ |
bogdanm | 0:9b334a45a8ff | 5544 | /* - Analog watchdog channels */ |
bogdanm | 0:9b334a45a8ff | 5545 | /* - Analog watchdog thresholds */ |
bogdanm | 0:9b334a45a8ff | 5546 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 5547 | { |
bogdanm | 0:9b334a45a8ff | 5548 | |
bogdanm | 0:9b334a45a8ff | 5549 | /* Analog watchdogs configuration */ |
bogdanm | 0:9b334a45a8ff | 5550 | if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) |
bogdanm | 0:9b334a45a8ff | 5551 | { |
bogdanm | 0:9b334a45a8ff | 5552 | /* Configuration of analog watchdog: */ |
bogdanm | 0:9b334a45a8ff | 5553 | /* - Set the analog watchdog enable mode: regular and/or injected */ |
bogdanm | 0:9b334a45a8ff | 5554 | /* groups, one or overall group of channels. */ |
bogdanm | 0:9b334a45a8ff | 5555 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
bogdanm | 0:9b334a45a8ff | 5556 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
bogdanm | 0:9b334a45a8ff | 5557 | hadc->Instance->CFGR &= ~( ADC_CFGR_AWD1SGL | |
bogdanm | 0:9b334a45a8ff | 5558 | ADC_CFGR_JAWD1EN | |
bogdanm | 0:9b334a45a8ff | 5559 | ADC_CFGR_AWD1EN | |
bogdanm | 0:9b334a45a8ff | 5560 | ADC_CFGR_AWD1CH ); |
bogdanm | 0:9b334a45a8ff | 5561 | |
bogdanm | 0:9b334a45a8ff | 5562 | hadc->Instance->CFGR |= ( AnalogWDGConfig->WatchdogMode | |
bogdanm | 0:9b334a45a8ff | 5563 | __HAL_ADC_CFGR_AWD1CH(AnalogWDGConfig->Channel) ); |
bogdanm | 0:9b334a45a8ff | 5564 | |
bogdanm | 0:9b334a45a8ff | 5565 | /* Shift the offset in function of the selected ADC resolution: */ |
bogdanm | 0:9b334a45a8ff | 5566 | /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ |
bogdanm | 0:9b334a45a8ff | 5567 | /* are set to 0 */ |
bogdanm | 0:9b334a45a8ff | 5568 | tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
bogdanm | 0:9b334a45a8ff | 5569 | tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
bogdanm | 0:9b334a45a8ff | 5570 | |
bogdanm | 0:9b334a45a8ff | 5571 | /* Set the high and low thresholds */ |
bogdanm | 0:9b334a45a8ff | 5572 | hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1); |
bogdanm | 0:9b334a45a8ff | 5573 | hadc->Instance->TR1 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
bogdanm | 0:9b334a45a8ff | 5574 | tmpAWDLowThresholdShifted ); |
bogdanm | 0:9b334a45a8ff | 5575 | |
bogdanm | 0:9b334a45a8ff | 5576 | /* Clear the ADC Analog watchdog flag (in case of let enabled by */ |
bogdanm | 0:9b334a45a8ff | 5577 | /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ |
bogdanm | 0:9b334a45a8ff | 5578 | /* or HAL_ADC_PollForEvent(). */ |
bogdanm | 0:9b334a45a8ff | 5579 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1); |
bogdanm | 0:9b334a45a8ff | 5580 | |
bogdanm | 0:9b334a45a8ff | 5581 | /* Configure ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5582 | if(AnalogWDGConfig->ITMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5583 | { |
bogdanm | 0:9b334a45a8ff | 5584 | /* Enable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5585 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1); |
bogdanm | 0:9b334a45a8ff | 5586 | } |
bogdanm | 0:9b334a45a8ff | 5587 | else |
bogdanm | 0:9b334a45a8ff | 5588 | { |
bogdanm | 0:9b334a45a8ff | 5589 | /* Disable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5590 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1); |
bogdanm | 0:9b334a45a8ff | 5591 | } |
bogdanm | 0:9b334a45a8ff | 5592 | |
bogdanm | 0:9b334a45a8ff | 5593 | } |
bogdanm | 0:9b334a45a8ff | 5594 | /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ |
bogdanm | 0:9b334a45a8ff | 5595 | else |
bogdanm | 0:9b334a45a8ff | 5596 | { |
bogdanm | 0:9b334a45a8ff | 5597 | /* Shift the threshold in function of the selected ADC resolution */ |
bogdanm | 0:9b334a45a8ff | 5598 | /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ |
bogdanm | 0:9b334a45a8ff | 5599 | tmpAWDHighThresholdShifted = __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
bogdanm | 0:9b334a45a8ff | 5600 | tmpAWDLowThresholdShifted = __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
bogdanm | 0:9b334a45a8ff | 5601 | |
bogdanm | 0:9b334a45a8ff | 5602 | if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) |
bogdanm | 0:9b334a45a8ff | 5603 | { |
bogdanm | 0:9b334a45a8ff | 5604 | /* Set the Analog watchdog channel or group of channels. This also */ |
bogdanm | 0:9b334a45a8ff | 5605 | /* enables the watchdog. */ |
bogdanm | 0:9b334a45a8ff | 5606 | /* Note: Conditionnal register reset, because several channels can be */ |
bogdanm | 0:9b334a45a8ff | 5607 | /* set by successive calls of this function. */ |
bogdanm | 0:9b334a45a8ff | 5608 | if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) |
bogdanm | 0:9b334a45a8ff | 5609 | { |
bogdanm | 0:9b334a45a8ff | 5610 | hadc->Instance->AWD2CR |= __HAL_ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 5611 | } |
bogdanm | 0:9b334a45a8ff | 5612 | else |
bogdanm | 0:9b334a45a8ff | 5613 | { |
bogdanm | 0:9b334a45a8ff | 5614 | hadc->Instance->AWD2CR &= ~ADC_AWD2CR_AWD2CH; |
bogdanm | 0:9b334a45a8ff | 5615 | } |
bogdanm | 0:9b334a45a8ff | 5616 | |
bogdanm | 0:9b334a45a8ff | 5617 | /* Set the high and low thresholds */ |
bogdanm | 0:9b334a45a8ff | 5618 | hadc->Instance->TR2 &= ~(ADC_TR2_HT2 | ADC_TR2_LT2); |
bogdanm | 0:9b334a45a8ff | 5619 | hadc->Instance->TR2 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
bogdanm | 0:9b334a45a8ff | 5620 | tmpAWDLowThresholdShifted ); |
bogdanm | 0:9b334a45a8ff | 5621 | |
bogdanm | 0:9b334a45a8ff | 5622 | /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ |
bogdanm | 0:9b334a45a8ff | 5623 | /* settings. */ |
bogdanm | 0:9b334a45a8ff | 5624 | tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2; |
bogdanm | 0:9b334a45a8ff | 5625 | tmpADCITAWD2orAWD3 = ADC_IT_AWD2; |
bogdanm | 0:9b334a45a8ff | 5626 | } |
bogdanm | 0:9b334a45a8ff | 5627 | /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ |
bogdanm | 0:9b334a45a8ff | 5628 | else |
bogdanm | 0:9b334a45a8ff | 5629 | { |
bogdanm | 0:9b334a45a8ff | 5630 | /* Set the Analog watchdog channel or group of channels. This also */ |
bogdanm | 0:9b334a45a8ff | 5631 | /* enables the watchdog. */ |
bogdanm | 0:9b334a45a8ff | 5632 | /* Note: Conditionnal register reset, because several channels can be */ |
bogdanm | 0:9b334a45a8ff | 5633 | /* set by successive calls of this function. */ |
bogdanm | 0:9b334a45a8ff | 5634 | if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) |
bogdanm | 0:9b334a45a8ff | 5635 | { |
bogdanm | 0:9b334a45a8ff | 5636 | hadc->Instance->AWD3CR |= __HAL_ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 5637 | } |
bogdanm | 0:9b334a45a8ff | 5638 | else |
bogdanm | 0:9b334a45a8ff | 5639 | { |
bogdanm | 0:9b334a45a8ff | 5640 | hadc->Instance->AWD3CR &= ~ADC_AWD3CR_AWD3CH; |
bogdanm | 0:9b334a45a8ff | 5641 | } |
bogdanm | 0:9b334a45a8ff | 5642 | |
bogdanm | 0:9b334a45a8ff | 5643 | /* Set the high and low thresholds */ |
bogdanm | 0:9b334a45a8ff | 5644 | hadc->Instance->TR3 &= ~(ADC_TR3_HT3 | ADC_TR3_LT3); |
bogdanm | 0:9b334a45a8ff | 5645 | hadc->Instance->TR3 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
bogdanm | 0:9b334a45a8ff | 5646 | tmpAWDLowThresholdShifted ); |
bogdanm | 0:9b334a45a8ff | 5647 | |
bogdanm | 0:9b334a45a8ff | 5648 | /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ |
bogdanm | 0:9b334a45a8ff | 5649 | /* settings. */ |
bogdanm | 0:9b334a45a8ff | 5650 | tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3; |
bogdanm | 0:9b334a45a8ff | 5651 | tmpADCITAWD2orAWD3 = ADC_IT_AWD3; |
bogdanm | 0:9b334a45a8ff | 5652 | } |
bogdanm | 0:9b334a45a8ff | 5653 | |
bogdanm | 0:9b334a45a8ff | 5654 | /* Clear the ADC Analog watchdog flag (in case of let enabled by */ |
bogdanm | 0:9b334a45a8ff | 5655 | /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ |
bogdanm | 0:9b334a45a8ff | 5656 | /* or HAL_ADC_PollForEvent(). */ |
bogdanm | 0:9b334a45a8ff | 5657 | __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3); |
bogdanm | 0:9b334a45a8ff | 5658 | |
bogdanm | 0:9b334a45a8ff | 5659 | /* Configure ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5660 | if(AnalogWDGConfig->ITMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5661 | { |
bogdanm | 0:9b334a45a8ff | 5662 | __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3); |
bogdanm | 0:9b334a45a8ff | 5663 | } |
bogdanm | 0:9b334a45a8ff | 5664 | else |
bogdanm | 0:9b334a45a8ff | 5665 | { |
bogdanm | 0:9b334a45a8ff | 5666 | __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3); |
bogdanm | 0:9b334a45a8ff | 5667 | } |
bogdanm | 0:9b334a45a8ff | 5668 | } |
bogdanm | 0:9b334a45a8ff | 5669 | |
bogdanm | 0:9b334a45a8ff | 5670 | } |
bogdanm | 0:9b334a45a8ff | 5671 | /* If a conversion is on going on regular or injected groups, no update */ |
bogdanm | 0:9b334a45a8ff | 5672 | /* could be done on neither of the AWD configuration structure parameters. */ |
bogdanm | 0:9b334a45a8ff | 5673 | else |
bogdanm | 0:9b334a45a8ff | 5674 | { |
bogdanm | 0:9b334a45a8ff | 5675 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5676 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5677 | |
bogdanm | 0:9b334a45a8ff | 5678 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5679 | } |
bogdanm | 0:9b334a45a8ff | 5680 | |
bogdanm | 0:9b334a45a8ff | 5681 | |
bogdanm | 0:9b334a45a8ff | 5682 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 5683 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5684 | |
bogdanm | 0:9b334a45a8ff | 5685 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 5686 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 5687 | } |
bogdanm | 0:9b334a45a8ff | 5688 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 5689 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 5690 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 5691 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 5692 | |
bogdanm | 0:9b334a45a8ff | 5693 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 5694 | /** |
bogdanm | 0:9b334a45a8ff | 5695 | * @brief Configures the analog watchdog. |
bogdanm | 0:9b334a45a8ff | 5696 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5697 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
bogdanm | 0:9b334a45a8ff | 5698 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 5699 | */ |
bogdanm | 0:9b334a45a8ff | 5700 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
bogdanm | 0:9b334a45a8ff | 5701 | { |
bogdanm | 0:9b334a45a8ff | 5702 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 5703 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 5704 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
bogdanm | 0:9b334a45a8ff | 5705 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 5706 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
bogdanm | 0:9b334a45a8ff | 5707 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); |
bogdanm | 0:9b334a45a8ff | 5708 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); |
bogdanm | 0:9b334a45a8ff | 5709 | |
bogdanm | 0:9b334a45a8ff | 5710 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 5711 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5712 | |
bogdanm | 0:9b334a45a8ff | 5713 | /* Analog watchdog configuration */ |
bogdanm | 0:9b334a45a8ff | 5714 | |
bogdanm | 0:9b334a45a8ff | 5715 | /* Configure ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5716 | if(AnalogWDGConfig->ITMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 5717 | { |
bogdanm | 0:9b334a45a8ff | 5718 | /* Enable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5719 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
bogdanm | 0:9b334a45a8ff | 5720 | } |
bogdanm | 0:9b334a45a8ff | 5721 | else |
bogdanm | 0:9b334a45a8ff | 5722 | { |
bogdanm | 0:9b334a45a8ff | 5723 | /* Disable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 5724 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
bogdanm | 0:9b334a45a8ff | 5725 | } |
bogdanm | 0:9b334a45a8ff | 5726 | |
bogdanm | 0:9b334a45a8ff | 5727 | /* Configuration of analog watchdog: */ |
bogdanm | 0:9b334a45a8ff | 5728 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
bogdanm | 0:9b334a45a8ff | 5729 | /* one or all channels. */ |
bogdanm | 0:9b334a45a8ff | 5730 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
bogdanm | 0:9b334a45a8ff | 5731 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
bogdanm | 0:9b334a45a8ff | 5732 | hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | |
bogdanm | 0:9b334a45a8ff | 5733 | ADC_CR1_JAWDEN | |
bogdanm | 0:9b334a45a8ff | 5734 | ADC_CR1_AWDEN | |
bogdanm | 0:9b334a45a8ff | 5735 | ADC_CR1_AWDCH ); |
bogdanm | 0:9b334a45a8ff | 5736 | |
bogdanm | 0:9b334a45a8ff | 5737 | hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | |
bogdanm | 0:9b334a45a8ff | 5738 | AnalogWDGConfig->Channel ); |
bogdanm | 0:9b334a45a8ff | 5739 | |
bogdanm | 0:9b334a45a8ff | 5740 | /* Set the high threshold */ |
bogdanm | 0:9b334a45a8ff | 5741 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
bogdanm | 0:9b334a45a8ff | 5742 | |
bogdanm | 0:9b334a45a8ff | 5743 | /* Set the low threshold */ |
bogdanm | 0:9b334a45a8ff | 5744 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
bogdanm | 0:9b334a45a8ff | 5745 | |
bogdanm | 0:9b334a45a8ff | 5746 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 5747 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5748 | |
bogdanm | 0:9b334a45a8ff | 5749 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 5750 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 5751 | } |
bogdanm | 0:9b334a45a8ff | 5752 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 5753 | |
bogdanm | 0:9b334a45a8ff | 5754 | |
bogdanm | 0:9b334a45a8ff | 5755 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 5756 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 5757 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
bogdanm | 0:9b334a45a8ff | 5758 | /** |
bogdanm | 0:9b334a45a8ff | 5759 | * @brief Enable ADC multimode and configure multimode parameters |
bogdanm | 0:9b334a45a8ff | 5760 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 5761 | * This function initializes multimode parameters, following |
bogdanm | 0:9b334a45a8ff | 5762 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 5763 | * of structure "ADC_MultiModeTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 5764 | * the ADCs (both ADCs of the common group). |
bogdanm | 0:9b334a45a8ff | 5765 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 5766 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 5767 | * "ADC_MultiModeTypeDef". |
bogdanm | 0:9b334a45a8ff | 5768 | * @note To change back configuration from multimode to single mode, ADC must |
bogdanm | 0:9b334a45a8ff | 5769 | * be reset (using function HAL_ADC_Init() ). |
bogdanm | 0:9b334a45a8ff | 5770 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5771 | * @param multimode : Structure of ADC multimode configuration |
bogdanm | 0:9b334a45a8ff | 5772 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 5773 | */ |
bogdanm | 0:9b334a45a8ff | 5774 | HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) |
bogdanm | 0:9b334a45a8ff | 5775 | { |
bogdanm | 0:9b334a45a8ff | 5776 | HAL_StatusTypeDef tmpHALStatus = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 5777 | ADC_Common_TypeDef *tmpADC_Common; |
bogdanm | 0:9b334a45a8ff | 5778 | ADC_HandleTypeDef tmphadcSharingSameCommonRegister; |
bogdanm | 0:9b334a45a8ff | 5779 | |
bogdanm | 0:9b334a45a8ff | 5780 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 5781 | assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 5782 | assert_param(IS_ADC_MODE(multimode->Mode)); |
bogdanm | 0:9b334a45a8ff | 5783 | assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); |
bogdanm | 0:9b334a45a8ff | 5784 | assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); |
bogdanm | 0:9b334a45a8ff | 5785 | |
bogdanm | 0:9b334a45a8ff | 5786 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 5787 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5788 | |
bogdanm | 0:9b334a45a8ff | 5789 | |
bogdanm | 0:9b334a45a8ff | 5790 | /* Set handle of the other ADC sharing the same common register */ |
bogdanm | 0:9b334a45a8ff | 5791 | __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); |
bogdanm | 0:9b334a45a8ff | 5792 | |
bogdanm | 0:9b334a45a8ff | 5793 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 5794 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 5795 | /* conversion on going on regular group: */ |
bogdanm | 0:9b334a45a8ff | 5796 | /* - Multimode DMA configuration */ |
bogdanm | 0:9b334a45a8ff | 5797 | /* - Multimode DMA mode */ |
bogdanm | 0:9b334a45a8ff | 5798 | /* Parameters that can be updated only when ADC is disabled: */ |
bogdanm | 0:9b334a45a8ff | 5799 | /* - Multimode mode selection */ |
bogdanm | 0:9b334a45a8ff | 5800 | /* - Multimode delay */ |
bogdanm | 0:9b334a45a8ff | 5801 | /* To optimize code, all multimode settings can be set when both ADCs of */ |
bogdanm | 0:9b334a45a8ff | 5802 | /* the common group are in state: disabled. */ |
bogdanm | 0:9b334a45a8ff | 5803 | if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) && |
bogdanm | 0:9b334a45a8ff | 5804 | (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) ) |
bogdanm | 0:9b334a45a8ff | 5805 | { |
bogdanm | 0:9b334a45a8ff | 5806 | |
bogdanm | 0:9b334a45a8ff | 5807 | /* Pointer to the common control register to which is belonging hadc */ |
bogdanm | 0:9b334a45a8ff | 5808 | /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ |
bogdanm | 0:9b334a45a8ff | 5809 | /* control registers) */ |
bogdanm | 0:9b334a45a8ff | 5810 | tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc); |
bogdanm | 0:9b334a45a8ff | 5811 | |
bogdanm | 0:9b334a45a8ff | 5812 | /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ |
bogdanm | 0:9b334a45a8ff | 5813 | /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ |
bogdanm | 0:9b334a45a8ff | 5814 | /* - set the selected multimode */ |
bogdanm | 0:9b334a45a8ff | 5815 | /* - DMA access mode */ |
bogdanm | 0:9b334a45a8ff | 5816 | /* - Set delay between two sampling phases */ |
bogdanm | 0:9b334a45a8ff | 5817 | /* Note: Delay range depends on selected resolution: */ |
bogdanm | 0:9b334a45a8ff | 5818 | /* from 1 to 12 clock cycles for 12 bits */ |
bogdanm | 0:9b334a45a8ff | 5819 | /* from 1 to 10 clock cycles for 10 bits, */ |
bogdanm | 0:9b334a45a8ff | 5820 | /* from 1 to 8 clock cycles for 8 bits */ |
bogdanm | 0:9b334a45a8ff | 5821 | /* from 1 to 6 clock cycles for 6 bits */ |
bogdanm | 0:9b334a45a8ff | 5822 | /* If a higher delay is selected, it will be clamped to maximum delay */ |
bogdanm | 0:9b334a45a8ff | 5823 | /* range */ |
bogdanm | 0:9b334a45a8ff | 5824 | tmpADC_Common->CCR &= ~( ADC_CCR_MULTI | |
bogdanm | 0:9b334a45a8ff | 5825 | ADC_CCR_MDMA | |
bogdanm | 0:9b334a45a8ff | 5826 | ADC_CCR_DELAY | |
bogdanm | 0:9b334a45a8ff | 5827 | ADC_CCR_DMACFG ); |
bogdanm | 0:9b334a45a8ff | 5828 | |
bogdanm | 0:9b334a45a8ff | 5829 | tmpADC_Common->CCR |= ( multimode->Mode | |
bogdanm | 0:9b334a45a8ff | 5830 | multimode->DMAAccessMode | |
bogdanm | 0:9b334a45a8ff | 5831 | multimode->TwoSamplingDelay | |
bogdanm | 0:9b334a45a8ff | 5832 | __HAL_ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); |
bogdanm | 0:9b334a45a8ff | 5833 | } |
bogdanm | 0:9b334a45a8ff | 5834 | /* If one of the ADC sharing the same common group is enabled, no update */ |
bogdanm | 0:9b334a45a8ff | 5835 | /* could be done on neither of the multimode structure parameters. */ |
bogdanm | 0:9b334a45a8ff | 5836 | else |
bogdanm | 0:9b334a45a8ff | 5837 | { |
bogdanm | 0:9b334a45a8ff | 5838 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5839 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5840 | |
bogdanm | 0:9b334a45a8ff | 5841 | tmpHALStatus = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5842 | } |
bogdanm | 0:9b334a45a8ff | 5843 | |
bogdanm | 0:9b334a45a8ff | 5844 | |
bogdanm | 0:9b334a45a8ff | 5845 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 5846 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 5847 | |
bogdanm | 0:9b334a45a8ff | 5848 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 5849 | return tmpHALStatus; |
bogdanm | 0:9b334a45a8ff | 5850 | } |
bogdanm | 0:9b334a45a8ff | 5851 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 5852 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 5853 | /* STM32F303x8 || STM32F328xx || STM32F334x8 */ |
bogdanm | 0:9b334a45a8ff | 5854 | |
bogdanm | 0:9b334a45a8ff | 5855 | /** |
bogdanm | 0:9b334a45a8ff | 5856 | * @} |
bogdanm | 0:9b334a45a8ff | 5857 | */ |
bogdanm | 0:9b334a45a8ff | 5858 | |
bogdanm | 0:9b334a45a8ff | 5859 | /** |
bogdanm | 0:9b334a45a8ff | 5860 | * @} |
bogdanm | 0:9b334a45a8ff | 5861 | */ |
bogdanm | 0:9b334a45a8ff | 5862 | |
bogdanm | 0:9b334a45a8ff | 5863 | /** @defgroup ADCEx_Private_Functions ADC Extended Private Functions |
bogdanm | 0:9b334a45a8ff | 5864 | * @{ |
bogdanm | 0:9b334a45a8ff | 5865 | */ |
bogdanm | 0:9b334a45a8ff | 5866 | /** |
bogdanm | 0:9b334a45a8ff | 5867 | * @brief DMA transfer complete callback. |
bogdanm | 0:9b334a45a8ff | 5868 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 5869 | * @retval None |
bogdanm | 0:9b334a45a8ff | 5870 | */ |
bogdanm | 0:9b334a45a8ff | 5871 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 5872 | { |
bogdanm | 0:9b334a45a8ff | 5873 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 5874 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 5875 | |
bogdanm | 0:9b334a45a8ff | 5876 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 5877 | if(hadc->State != HAL_ADC_STATE_ERROR) |
bogdanm | 0:9b334a45a8ff | 5878 | { |
bogdanm | 0:9b334a45a8ff | 5879 | /* Update ADC state machine */ |
bogdanm | 0:9b334a45a8ff | 5880 | if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) |
bogdanm | 0:9b334a45a8ff | 5881 | { |
bogdanm | 0:9b334a45a8ff | 5882 | /* Check if a conversion is ready on injected group */ |
bogdanm | 0:9b334a45a8ff | 5883 | if(hadc->State == HAL_ADC_STATE_EOC_INJ) |
bogdanm | 0:9b334a45a8ff | 5884 | { |
bogdanm | 0:9b334a45a8ff | 5885 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 5886 | hadc->State = HAL_ADC_STATE_EOC_INJ_REG; |
bogdanm | 0:9b334a45a8ff | 5887 | } |
bogdanm | 0:9b334a45a8ff | 5888 | else |
bogdanm | 0:9b334a45a8ff | 5889 | { |
bogdanm | 0:9b334a45a8ff | 5890 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 5891 | hadc->State = HAL_ADC_STATE_EOC_REG; |
bogdanm | 0:9b334a45a8ff | 5892 | } |
bogdanm | 0:9b334a45a8ff | 5893 | } |
bogdanm | 0:9b334a45a8ff | 5894 | } |
bogdanm | 0:9b334a45a8ff | 5895 | |
bogdanm | 0:9b334a45a8ff | 5896 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 5897 | HAL_ADC_ConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 5898 | } |
bogdanm | 0:9b334a45a8ff | 5899 | |
bogdanm | 0:9b334a45a8ff | 5900 | /** |
bogdanm | 0:9b334a45a8ff | 5901 | * @brief DMA half transfer complete callback. |
bogdanm | 0:9b334a45a8ff | 5902 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 5903 | * @retval None |
bogdanm | 0:9b334a45a8ff | 5904 | */ |
bogdanm | 0:9b334a45a8ff | 5905 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 5906 | { |
bogdanm | 0:9b334a45a8ff | 5907 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 5908 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 5909 | |
bogdanm | 0:9b334a45a8ff | 5910 | /* Half conversion callback */ |
bogdanm | 0:9b334a45a8ff | 5911 | HAL_ADC_ConvHalfCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 5912 | } |
bogdanm | 0:9b334a45a8ff | 5913 | |
bogdanm | 0:9b334a45a8ff | 5914 | /** |
bogdanm | 0:9b334a45a8ff | 5915 | * @brief DMA error callback |
bogdanm | 0:9b334a45a8ff | 5916 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 5917 | * @retval None |
bogdanm | 0:9b334a45a8ff | 5918 | */ |
bogdanm | 0:9b334a45a8ff | 5919 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 5920 | { |
bogdanm | 0:9b334a45a8ff | 5921 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 5922 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 5923 | |
bogdanm | 0:9b334a45a8ff | 5924 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 5925 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5926 | |
bogdanm | 0:9b334a45a8ff | 5927 | /* Set ADC error code to DMA error */ |
bogdanm | 0:9b334a45a8ff | 5928 | hadc->ErrorCode |= HAL_ADC_ERROR_DMA; |
bogdanm | 0:9b334a45a8ff | 5929 | |
bogdanm | 0:9b334a45a8ff | 5930 | /* Error callback */ |
bogdanm | 0:9b334a45a8ff | 5931 | HAL_ADC_ErrorCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 5932 | } |
bogdanm | 0:9b334a45a8ff | 5933 | |
bogdanm | 0:9b334a45a8ff | 5934 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 5935 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 5936 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
bogdanm | 0:9b334a45a8ff | 5937 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
bogdanm | 0:9b334a45a8ff | 5938 | /** |
bogdanm | 0:9b334a45a8ff | 5939 | * @brief Enable the selected ADC. |
bogdanm | 0:9b334a45a8ff | 5940 | * @note Prerequisite condition to use this function: ADC must be disabled |
bogdanm | 0:9b334a45a8ff | 5941 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
bogdanm | 0:9b334a45a8ff | 5942 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5943 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 5944 | */ |
bogdanm | 0:9b334a45a8ff | 5945 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 5946 | { |
bogdanm | 0:9b334a45a8ff | 5947 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 5948 | |
bogdanm | 0:9b334a45a8ff | 5949 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
bogdanm | 0:9b334a45a8ff | 5950 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
bogdanm | 0:9b334a45a8ff | 5951 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
bogdanm | 0:9b334a45a8ff | 5952 | /* causes: ADC clock not running, ...). */ |
bogdanm | 0:9b334a45a8ff | 5953 | if (__HAL_ADC_IS_ENABLED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 5954 | { |
bogdanm | 0:9b334a45a8ff | 5955 | /* Check if conditions to enable the ADC are fulfilled */ |
bogdanm | 0:9b334a45a8ff | 5956 | if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 5957 | { |
bogdanm | 0:9b334a45a8ff | 5958 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5959 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5960 | |
bogdanm | 0:9b334a45a8ff | 5961 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 5962 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 5963 | |
bogdanm | 0:9b334a45a8ff | 5964 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5965 | } |
bogdanm | 0:9b334a45a8ff | 5966 | |
bogdanm | 0:9b334a45a8ff | 5967 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 5968 | __HAL_ADC_ENABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 5969 | |
bogdanm | 0:9b334a45a8ff | 5970 | /* Wait for ADC effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 5971 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 5972 | |
bogdanm | 0:9b334a45a8ff | 5973 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) |
bogdanm | 0:9b334a45a8ff | 5974 | { |
bogdanm | 0:9b334a45a8ff | 5975 | if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 5976 | { |
bogdanm | 0:9b334a45a8ff | 5977 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 5978 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 5979 | |
bogdanm | 0:9b334a45a8ff | 5980 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 5981 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 5982 | |
bogdanm | 0:9b334a45a8ff | 5983 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 5984 | } |
bogdanm | 0:9b334a45a8ff | 5985 | } |
bogdanm | 0:9b334a45a8ff | 5986 | } |
bogdanm | 0:9b334a45a8ff | 5987 | |
bogdanm | 0:9b334a45a8ff | 5988 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 5989 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 5990 | } |
bogdanm | 0:9b334a45a8ff | 5991 | |
bogdanm | 0:9b334a45a8ff | 5992 | /** |
bogdanm | 0:9b334a45a8ff | 5993 | * @brief Disable the selected ADC. |
bogdanm | 0:9b334a45a8ff | 5994 | * @note Prerequisite condition to use this function: ADC conversions must be |
bogdanm | 0:9b334a45a8ff | 5995 | * stopped. |
bogdanm | 0:9b334a45a8ff | 5996 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 5997 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 5998 | */ |
bogdanm | 0:9b334a45a8ff | 5999 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 6000 | { |
bogdanm | 0:9b334a45a8ff | 6001 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 6002 | |
bogdanm | 0:9b334a45a8ff | 6003 | /* Verification if ADC is not already disabled: */ |
bogdanm | 0:9b334a45a8ff | 6004 | /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ |
bogdanm | 0:9b334a45a8ff | 6005 | /* disabled. */ |
bogdanm | 0:9b334a45a8ff | 6006 | if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) |
bogdanm | 0:9b334a45a8ff | 6007 | { |
bogdanm | 0:9b334a45a8ff | 6008 | /* Check if conditions to disable the ADC are fulfilled */ |
bogdanm | 0:9b334a45a8ff | 6009 | if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) |
bogdanm | 0:9b334a45a8ff | 6010 | { |
bogdanm | 0:9b334a45a8ff | 6011 | /* Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 6012 | __HAL_ADC_DISABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 6013 | } |
bogdanm | 0:9b334a45a8ff | 6014 | else |
bogdanm | 0:9b334a45a8ff | 6015 | { |
bogdanm | 0:9b334a45a8ff | 6016 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6017 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6018 | |
bogdanm | 0:9b334a45a8ff | 6019 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6020 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6021 | |
bogdanm | 0:9b334a45a8ff | 6022 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6023 | } |
bogdanm | 0:9b334a45a8ff | 6024 | |
bogdanm | 0:9b334a45a8ff | 6025 | /* Wait for ADC effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 6026 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 6027 | |
bogdanm | 0:9b334a45a8ff | 6028 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) |
bogdanm | 0:9b334a45a8ff | 6029 | { |
bogdanm | 0:9b334a45a8ff | 6030 | if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 6031 | { |
bogdanm | 0:9b334a45a8ff | 6032 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6033 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6034 | |
bogdanm | 0:9b334a45a8ff | 6035 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6036 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6037 | |
bogdanm | 0:9b334a45a8ff | 6038 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6039 | } |
bogdanm | 0:9b334a45a8ff | 6040 | } |
bogdanm | 0:9b334a45a8ff | 6041 | } |
bogdanm | 0:9b334a45a8ff | 6042 | |
bogdanm | 0:9b334a45a8ff | 6043 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 6044 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 6045 | } |
bogdanm | 0:9b334a45a8ff | 6046 | |
bogdanm | 0:9b334a45a8ff | 6047 | |
bogdanm | 0:9b334a45a8ff | 6048 | /** |
bogdanm | 0:9b334a45a8ff | 6049 | * @brief Stop ADC conversion. |
bogdanm | 0:9b334a45a8ff | 6050 | * @note Prerequisite condition to use this function: ADC conversions must be |
bogdanm | 0:9b334a45a8ff | 6051 | * stopped to disable the ADC. |
bogdanm | 0:9b334a45a8ff | 6052 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 6053 | * @param ConversionGroup: ADC group regular and/or injected. |
bogdanm | 0:9b334a45a8ff | 6054 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 6055 | * @arg REGULAR_GROUP: ADC regular conversion type. |
bogdanm | 0:9b334a45a8ff | 6056 | * @arg INJECTED_GROUP: ADC injected conversion type. |
bogdanm | 0:9b334a45a8ff | 6057 | * @arg REGULAR_INJECTED_GROUP: ADC regular and injected conversion type. |
bogdanm | 0:9b334a45a8ff | 6058 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 6059 | */ |
bogdanm | 0:9b334a45a8ff | 6060 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) |
bogdanm | 0:9b334a45a8ff | 6061 | { |
bogdanm | 0:9b334a45a8ff | 6062 | uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0; |
bogdanm | 0:9b334a45a8ff | 6063 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 6064 | uint32_t Conversion_Timeout_CPU_cycles = 0; |
bogdanm | 0:9b334a45a8ff | 6065 | |
bogdanm | 0:9b334a45a8ff | 6066 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 6067 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 6068 | assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); |
bogdanm | 0:9b334a45a8ff | 6069 | |
bogdanm | 0:9b334a45a8ff | 6070 | /* Verification if ADC is not already stopped (on regular and injected */ |
bogdanm | 0:9b334a45a8ff | 6071 | /* groups) to bypass this function if not needed. */ |
bogdanm | 0:9b334a45a8ff | 6072 | if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) |
bogdanm | 0:9b334a45a8ff | 6073 | { |
bogdanm | 0:9b334a45a8ff | 6074 | /* Particular case of continuous auto-injection mode combined with */ |
bogdanm | 0:9b334a45a8ff | 6075 | /* auto-delay mode. */ |
bogdanm | 0:9b334a45a8ff | 6076 | /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ |
bogdanm | 0:9b334a45a8ff | 6077 | /* injected group stop ADC_CR_JADSTP). */ |
bogdanm | 0:9b334a45a8ff | 6078 | /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ |
bogdanm | 0:9b334a45a8ff | 6079 | /* (see reference manual). */ |
bogdanm | 0:9b334a45a8ff | 6080 | if ((HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CFGR_JAUTO)) |
bogdanm | 0:9b334a45a8ff | 6081 | && (hadc->Init.ContinuousConvMode==ENABLE) |
bogdanm | 0:9b334a45a8ff | 6082 | && (hadc->Init.LowPowerAutoWait==ENABLE)) |
bogdanm | 0:9b334a45a8ff | 6083 | { |
bogdanm | 0:9b334a45a8ff | 6084 | /* Use stop of regular group */ |
bogdanm | 0:9b334a45a8ff | 6085 | ConversionGroup = REGULAR_GROUP; |
bogdanm | 0:9b334a45a8ff | 6086 | |
bogdanm | 0:9b334a45a8ff | 6087 | /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ |
bogdanm | 0:9b334a45a8ff | 6088 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) |
bogdanm | 0:9b334a45a8ff | 6089 | { |
bogdanm | 0:9b334a45a8ff | 6090 | if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4)) |
bogdanm | 0:9b334a45a8ff | 6091 | { |
bogdanm | 0:9b334a45a8ff | 6092 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6093 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6094 | |
bogdanm | 0:9b334a45a8ff | 6095 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6096 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6097 | |
bogdanm | 0:9b334a45a8ff | 6098 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6099 | } |
bogdanm | 0:9b334a45a8ff | 6100 | Conversion_Timeout_CPU_cycles ++; |
bogdanm | 0:9b334a45a8ff | 6101 | } |
bogdanm | 0:9b334a45a8ff | 6102 | |
bogdanm | 0:9b334a45a8ff | 6103 | /* Clear JEOS */ |
bogdanm | 0:9b334a45a8ff | 6104 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); |
bogdanm | 0:9b334a45a8ff | 6105 | } |
bogdanm | 0:9b334a45a8ff | 6106 | |
bogdanm | 0:9b334a45a8ff | 6107 | /* Stop potential conversion on going on regular group */ |
bogdanm | 0:9b334a45a8ff | 6108 | if (ConversionGroup != INJECTED_GROUP) |
bogdanm | 0:9b334a45a8ff | 6109 | { |
bogdanm | 0:9b334a45a8ff | 6110 | /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ |
bogdanm | 0:9b334a45a8ff | 6111 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && |
bogdanm | 0:9b334a45a8ff | 6112 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
bogdanm | 0:9b334a45a8ff | 6113 | { |
bogdanm | 0:9b334a45a8ff | 6114 | /* Stop conversions on regular group */ |
bogdanm | 0:9b334a45a8ff | 6115 | hadc->Instance->CR |= ADC_CR_ADSTP; |
bogdanm | 0:9b334a45a8ff | 6116 | } |
bogdanm | 0:9b334a45a8ff | 6117 | } |
bogdanm | 0:9b334a45a8ff | 6118 | |
bogdanm | 0:9b334a45a8ff | 6119 | /* Stop potential conversion on going on injected group */ |
bogdanm | 0:9b334a45a8ff | 6120 | if (ConversionGroup != REGULAR_GROUP) |
bogdanm | 0:9b334a45a8ff | 6121 | { |
bogdanm | 0:9b334a45a8ff | 6122 | /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ |
bogdanm | 0:9b334a45a8ff | 6123 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && |
bogdanm | 0:9b334a45a8ff | 6124 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
bogdanm | 0:9b334a45a8ff | 6125 | { |
bogdanm | 0:9b334a45a8ff | 6126 | /* Stop conversions on injected group */ |
bogdanm | 0:9b334a45a8ff | 6127 | hadc->Instance->CR |= ADC_CR_JADSTP; |
bogdanm | 0:9b334a45a8ff | 6128 | } |
bogdanm | 0:9b334a45a8ff | 6129 | } |
bogdanm | 0:9b334a45a8ff | 6130 | |
bogdanm | 0:9b334a45a8ff | 6131 | /* Selection of start and stop bits in function of regular or injected group */ |
bogdanm | 0:9b334a45a8ff | 6132 | switch(ConversionGroup) |
bogdanm | 0:9b334a45a8ff | 6133 | { |
bogdanm | 0:9b334a45a8ff | 6134 | case REGULAR_INJECTED_GROUP: |
bogdanm | 0:9b334a45a8ff | 6135 | tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); |
bogdanm | 0:9b334a45a8ff | 6136 | break; |
bogdanm | 0:9b334a45a8ff | 6137 | case INJECTED_GROUP: |
bogdanm | 0:9b334a45a8ff | 6138 | tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; |
bogdanm | 0:9b334a45a8ff | 6139 | break; |
bogdanm | 0:9b334a45a8ff | 6140 | /* Case REGULAR_GROUP */ |
bogdanm | 0:9b334a45a8ff | 6141 | default: |
bogdanm | 0:9b334a45a8ff | 6142 | tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 6143 | break; |
bogdanm | 0:9b334a45a8ff | 6144 | } |
bogdanm | 0:9b334a45a8ff | 6145 | |
bogdanm | 0:9b334a45a8ff | 6146 | /* Wait for conversion effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 6147 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 6148 | |
bogdanm | 0:9b334a45a8ff | 6149 | while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET) |
bogdanm | 0:9b334a45a8ff | 6150 | { |
bogdanm | 0:9b334a45a8ff | 6151 | if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 6152 | { |
bogdanm | 0:9b334a45a8ff | 6153 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6154 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6155 | |
bogdanm | 0:9b334a45a8ff | 6156 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6157 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6158 | |
bogdanm | 0:9b334a45a8ff | 6159 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6160 | } |
bogdanm | 0:9b334a45a8ff | 6161 | } |
bogdanm | 0:9b334a45a8ff | 6162 | |
bogdanm | 0:9b334a45a8ff | 6163 | } |
bogdanm | 0:9b334a45a8ff | 6164 | |
bogdanm | 0:9b334a45a8ff | 6165 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 6166 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 6167 | } |
bogdanm | 0:9b334a45a8ff | 6168 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 6169 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 6170 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
bogdanm | 0:9b334a45a8ff | 6171 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
bogdanm | 0:9b334a45a8ff | 6172 | |
bogdanm | 0:9b334a45a8ff | 6173 | #if defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 6174 | /** |
bogdanm | 0:9b334a45a8ff | 6175 | * @brief Enable the selected ADC. |
bogdanm | 0:9b334a45a8ff | 6176 | * @note Prerequisite condition to use this function: ADC must be disabled |
bogdanm | 0:9b334a45a8ff | 6177 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
bogdanm | 0:9b334a45a8ff | 6178 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 6179 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 6180 | */ |
bogdanm | 0:9b334a45a8ff | 6181 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 6182 | { |
bogdanm | 0:9b334a45a8ff | 6183 | uint32_t WaitLoopIndex = 0; |
bogdanm | 0:9b334a45a8ff | 6184 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 6185 | |
bogdanm | 0:9b334a45a8ff | 6186 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
bogdanm | 0:9b334a45a8ff | 6187 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
bogdanm | 0:9b334a45a8ff | 6188 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
bogdanm | 0:9b334a45a8ff | 6189 | /* causes: ADC clock not running, ...). */ |
bogdanm | 0:9b334a45a8ff | 6190 | if (__HAL_ADC_IS_ENABLED(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 6191 | { |
bogdanm | 0:9b334a45a8ff | 6192 | /* Enable the Peripheral */ |
bogdanm | 0:9b334a45a8ff | 6193 | __HAL_ADC_ENABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 6194 | |
bogdanm | 0:9b334a45a8ff | 6195 | /* Delay for ADC stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 6196 | /* Delay fixed to worst case: maximum CPU frequency */ |
bogdanm | 0:9b334a45a8ff | 6197 | while(WaitLoopIndex < ADC_STAB_DELAY_CPU_CYCLES) |
bogdanm | 0:9b334a45a8ff | 6198 | { |
bogdanm | 0:9b334a45a8ff | 6199 | WaitLoopIndex++; |
bogdanm | 0:9b334a45a8ff | 6200 | } |
bogdanm | 0:9b334a45a8ff | 6201 | |
bogdanm | 0:9b334a45a8ff | 6202 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 6203 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 6204 | |
bogdanm | 0:9b334a45a8ff | 6205 | /* Wait for ADC effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 6206 | while(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) |
bogdanm | 0:9b334a45a8ff | 6207 | { |
bogdanm | 0:9b334a45a8ff | 6208 | if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 6209 | { |
bogdanm | 0:9b334a45a8ff | 6210 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6211 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6212 | |
bogdanm | 0:9b334a45a8ff | 6213 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6214 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6215 | |
bogdanm | 0:9b334a45a8ff | 6216 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 6217 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 6218 | |
bogdanm | 0:9b334a45a8ff | 6219 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6220 | } |
bogdanm | 0:9b334a45a8ff | 6221 | } |
bogdanm | 0:9b334a45a8ff | 6222 | } |
bogdanm | 0:9b334a45a8ff | 6223 | |
bogdanm | 0:9b334a45a8ff | 6224 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 6225 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 6226 | } |
bogdanm | 0:9b334a45a8ff | 6227 | |
bogdanm | 0:9b334a45a8ff | 6228 | /** |
bogdanm | 0:9b334a45a8ff | 6229 | * @brief Stop ADC conversion and disable the selected ADC |
bogdanm | 0:9b334a45a8ff | 6230 | * @note Prerequisite condition to use this function: ADC conversions must be |
bogdanm | 0:9b334a45a8ff | 6231 | * stopped to disable the ADC. |
bogdanm | 0:9b334a45a8ff | 6232 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 6233 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 6234 | */ |
bogdanm | 0:9b334a45a8ff | 6235 | static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 6236 | { |
bogdanm | 0:9b334a45a8ff | 6237 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 6238 | |
bogdanm | 0:9b334a45a8ff | 6239 | /* Verification if ADC is not already disabled: */ |
bogdanm | 0:9b334a45a8ff | 6240 | if (__HAL_ADC_IS_ENABLED(hadc) != RESET) |
bogdanm | 0:9b334a45a8ff | 6241 | { |
bogdanm | 0:9b334a45a8ff | 6242 | /* Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 6243 | __HAL_ADC_DISABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 6244 | |
bogdanm | 0:9b334a45a8ff | 6245 | /* Get timeout */ |
bogdanm | 0:9b334a45a8ff | 6246 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 6247 | |
bogdanm | 0:9b334a45a8ff | 6248 | /* Wait for ADC effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 6249 | while(__HAL_ADC_IS_ENABLED(hadc) != RESET) |
bogdanm | 0:9b334a45a8ff | 6250 | { |
bogdanm | 0:9b334a45a8ff | 6251 | if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 6252 | { |
bogdanm | 0:9b334a45a8ff | 6253 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 6254 | hadc->State = HAL_ADC_STATE_ERROR; |
bogdanm | 0:9b334a45a8ff | 6255 | |
bogdanm | 0:9b334a45a8ff | 6256 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 6257 | hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; |
bogdanm | 0:9b334a45a8ff | 6258 | |
bogdanm | 0:9b334a45a8ff | 6259 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 6260 | } |
bogdanm | 0:9b334a45a8ff | 6261 | } |
bogdanm | 0:9b334a45a8ff | 6262 | } |
bogdanm | 0:9b334a45a8ff | 6263 | |
bogdanm | 0:9b334a45a8ff | 6264 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 6265 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 6266 | } |
bogdanm | 0:9b334a45a8ff | 6267 | #endif /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 6268 | /** |
bogdanm | 0:9b334a45a8ff | 6269 | * @} |
bogdanm | 0:9b334a45a8ff | 6270 | */ |
bogdanm | 0:9b334a45a8ff | 6271 | |
bogdanm | 0:9b334a45a8ff | 6272 | #endif /* HAL_ADC_MODULE_ENABLED */ |
bogdanm | 0:9b334a45a8ff | 6273 | /** |
bogdanm | 0:9b334a45a8ff | 6274 | * @} |
bogdanm | 0:9b334a45a8ff | 6275 | */ |
bogdanm | 0:9b334a45a8ff | 6276 | |
bogdanm | 0:9b334a45a8ff | 6277 | /** |
bogdanm | 0:9b334a45a8ff | 6278 | * @} |
bogdanm | 0:9b334a45a8ff | 6279 | */ |
bogdanm | 0:9b334a45a8ff | 6280 | |
bogdanm | 0:9b334a45a8ff | 6281 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |