en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/stm32f334x8.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f334x8.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS STM32F334x4/STM32F334x6/STM32F334x8 Devices Peripheral Access Layer Header File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file contains:
bogdanm 0:9b334a45a8ff 10 * - Data structures and the address mapping for all peripherals
bogdanm 0:9b334a45a8ff 11 * - Peripheral's registers declarations and bits definition
bogdanm 0:9b334a45a8ff 12 * - Macros to access peripheral’s registers hardware
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 ******************************************************************************
bogdanm 0:9b334a45a8ff 15 * @attention
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 20 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 25 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 27 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 28 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 ******************************************************************************
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /** @addtogroup CMSIS_Device
bogdanm 0:9b334a45a8ff 45 * @{
bogdanm 0:9b334a45a8ff 46 */
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /** @addtogroup stm32f334x8
bogdanm 0:9b334a45a8ff 49 * @{
bogdanm 0:9b334a45a8ff 50 */
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 #ifndef __STM32F334x8_H
bogdanm 0:9b334a45a8ff 53 #define __STM32F334x8_H
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 56 extern "C" {
bogdanm 0:9b334a45a8ff 57 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /**
bogdanm 0:9b334a45a8ff 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 0:9b334a45a8ff 67 #define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */
bogdanm 0:9b334a45a8ff 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */
bogdanm 0:9b334a45a8ff 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 70 #define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /**
bogdanm 0:9b334a45a8ff 73 * @}
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 0:9b334a45a8ff 77 * @{
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /**
bogdanm 0:9b334a45a8ff 81 * @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device
bogdanm 0:9b334a45a8ff 82 * in @ref Library_configuration_section
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84 typedef enum
bogdanm 0:9b334a45a8ff 85 {
bogdanm 0:9b334a45a8ff 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 0:9b334a45a8ff 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 0:9b334a45a8ff 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 0:9b334a45a8ff 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 0:9b334a45a8ff 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 0:9b334a45a8ff 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 0:9b334a45a8ff 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 0:9b334a45a8ff 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 0:9b334a45a8ff 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
bogdanm 0:9b334a45a8ff 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
bogdanm 0:9b334a45a8ff 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 0:9b334a45a8ff 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 0:9b334a45a8ff 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 0:9b334a45a8ff 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 0:9b334a45a8ff 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
bogdanm 0:9b334a45a8ff 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 0:9b334a45a8ff 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 0:9b334a45a8ff 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
bogdanm 0:9b334a45a8ff 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
bogdanm 0:9b334a45a8ff 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
bogdanm 0:9b334a45a8ff 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
bogdanm 0:9b334a45a8ff 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
bogdanm 0:9b334a45a8ff 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
bogdanm 0:9b334a45a8ff 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
bogdanm 0:9b334a45a8ff 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
bogdanm 0:9b334a45a8ff 115 CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
bogdanm 0:9b334a45a8ff 116 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
bogdanm 0:9b334a45a8ff 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
bogdanm 0:9b334a45a8ff 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
bogdanm 0:9b334a45a8ff 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 0:9b334a45a8ff 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
bogdanm 0:9b334a45a8ff 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
bogdanm 0:9b334a45a8ff 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
bogdanm 0:9b334a45a8ff 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 0:9b334a45a8ff 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 0:9b334a45a8ff 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 0:9b334a45a8ff 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
bogdanm 0:9b334a45a8ff 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 0:9b334a45a8ff 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 0:9b334a45a8ff 129 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
bogdanm 0:9b334a45a8ff 130 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
bogdanm 0:9b334a45a8ff 131 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
bogdanm 0:9b334a45a8ff 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 0:9b334a45a8ff 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
bogdanm 0:9b334a45a8ff 134 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
bogdanm 0:9b334a45a8ff 135 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
bogdanm 0:9b334a45a8ff 136 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
bogdanm 0:9b334a45a8ff 137 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
bogdanm 0:9b334a45a8ff 138 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
bogdanm 0:9b334a45a8ff 139 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
bogdanm 0:9b334a45a8ff 140 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
bogdanm 0:9b334a45a8ff 141 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
bogdanm 0:9b334a45a8ff 142 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
bogdanm 0:9b334a45a8ff 143 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
bogdanm 0:9b334a45a8ff 144 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
bogdanm 0:9b334a45a8ff 145 FPU_IRQn = 81 /*!< Floating point Interrupt */
bogdanm 0:9b334a45a8ff 146 } IRQn_Type;
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @}
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 0:9b334a45a8ff 153 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
bogdanm 0:9b334a45a8ff 154 #include <stdint.h>
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /** @addtogroup Peripheral_registers_structures
bogdanm 0:9b334a45a8ff 157 * @{
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /**
bogdanm 0:9b334a45a8ff 161 * @brief Analog to Digital Converter
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 typedef struct
bogdanm 0:9b334a45a8ff 165 {
bogdanm 0:9b334a45a8ff 166 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 167 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 168 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 169 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 170 uint32_t RESERVED0; /*!< Reserved, 0x010 */
bogdanm 0:9b334a45a8ff 171 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 172 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 173 uint32_t RESERVED1; /*!< Reserved, 0x01C */
bogdanm 0:9b334a45a8ff 174 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 175 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 176 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 177 uint32_t RESERVED2; /*!< Reserved, 0x02C */
bogdanm 0:9b334a45a8ff 178 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 179 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 180 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 181 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 182 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 183 uint32_t RESERVED3; /*!< Reserved, 0x044 */
bogdanm 0:9b334a45a8ff 184 uint32_t RESERVED4; /*!< Reserved, 0x048 */
bogdanm 0:9b334a45a8ff 185 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 186 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
bogdanm 0:9b334a45a8ff 187 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 188 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 189 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 190 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 191 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
bogdanm 0:9b334a45a8ff 192 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
bogdanm 0:9b334a45a8ff 195 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 196 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
bogdanm 0:9b334a45a8ff 197 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
bogdanm 0:9b334a45a8ff 198 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
bogdanm 0:9b334a45a8ff 199 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
bogdanm 0:9b334a45a8ff 200 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 } ADC_TypeDef;
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 typedef struct
bogdanm 0:9b334a45a8ff 207 {
bogdanm 0:9b334a45a8ff 208 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
bogdanm 0:9b334a45a8ff 209 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
bogdanm 0:9b334a45a8ff 210 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 0:9b334a45a8ff 212 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
bogdanm 0:9b334a45a8ff 213 } ADC_Common_TypeDef;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /**
bogdanm 0:9b334a45a8ff 216 * @brief Controller Area Network TxMailBox
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218 typedef struct
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 0:9b334a45a8ff 221 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 222 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 0:9b334a45a8ff 223 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 0:9b334a45a8ff 224 } CAN_TxMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /**
bogdanm 0:9b334a45a8ff 227 * @brief Controller Area Network FIFOMailBox
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229 typedef struct
bogdanm 0:9b334a45a8ff 230 {
bogdanm 0:9b334a45a8ff 231 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 0:9b334a45a8ff 232 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 233 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 0:9b334a45a8ff 234 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 0:9b334a45a8ff 235 } CAN_FIFOMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /**
bogdanm 0:9b334a45a8ff 238 * @brief Controller Area Network FilterRegister
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 typedef struct
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 243 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 244 } CAN_FilterRegister_TypeDef;
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /**
bogdanm 0:9b334a45a8ff 247 * @brief Controller Area Network
bogdanm 0:9b334a45a8ff 248 */
bogdanm 0:9b334a45a8ff 249 typedef struct
bogdanm 0:9b334a45a8ff 250 {
bogdanm 0:9b334a45a8ff 251 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 252 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 253 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 254 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 255 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 256 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 257 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 258 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 259 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 0:9b334a45a8ff 260 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 0:9b334a45a8ff 261 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 0:9b334a45a8ff 262 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 0:9b334a45a8ff 263 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 0:9b334a45a8ff 264 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 0:9b334a45a8ff 265 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 0:9b334a45a8ff 266 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 0:9b334a45a8ff 267 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 0:9b334a45a8ff 268 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 0:9b334a45a8ff 269 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 0:9b334a45a8ff 270 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 0:9b334a45a8ff 271 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 0:9b334a45a8ff 272 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 0:9b334a45a8ff 273 } CAN_TypeDef;
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /**
bogdanm 0:9b334a45a8ff 276 * @brief Analog Comparators
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 typedef struct
bogdanm 0:9b334a45a8ff 280 {
bogdanm 0:9b334a45a8ff 281 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 282 } COMP_TypeDef;
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @brief CRC calculation unit
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 typedef struct
bogdanm 0:9b334a45a8ff 289 {
bogdanm 0:9b334a45a8ff 290 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 291 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 292 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 0:9b334a45a8ff 293 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 294 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 295 uint32_t RESERVED2; /*!< Reserved, 0x0C */
bogdanm 0:9b334a45a8ff 296 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 297 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 298 } CRC_TypeDef;
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /**
bogdanm 0:9b334a45a8ff 301 * @brief Digital to Analog Converter
bogdanm 0:9b334a45a8ff 302 */
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 typedef struct
bogdanm 0:9b334a45a8ff 305 {
bogdanm 0:9b334a45a8ff 306 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 307 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 308 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 309 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 310 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 311 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 312 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 313 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 314 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 315 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 316 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 317 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 318 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 319 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 320 } DAC_TypeDef;
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /**
bogdanm 0:9b334a45a8ff 323 * @brief Debug MCU
bogdanm 0:9b334a45a8ff 324 */
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 typedef struct
bogdanm 0:9b334a45a8ff 327 {
bogdanm 0:9b334a45a8ff 328 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 329 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 330 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 331 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 332 }DBGMCU_TypeDef;
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /**
bogdanm 0:9b334a45a8ff 335 * @brief DMA Controller
bogdanm 0:9b334a45a8ff 336 */
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 typedef struct
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 0:9b334a45a8ff 341 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 0:9b334a45a8ff 342 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 0:9b334a45a8ff 343 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 0:9b334a45a8ff 344 } DMA_Channel_TypeDef;
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 typedef struct
bogdanm 0:9b334a45a8ff 347 {
bogdanm 0:9b334a45a8ff 348 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 349 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 350 } DMA_TypeDef;
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @brief External Interrupt/Event Controller
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 typedef struct
bogdanm 0:9b334a45a8ff 357 {
bogdanm 0:9b334a45a8ff 358 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 359 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 360 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 361 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 362 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 363 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 364 uint32_t RESERVED1; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 365 uint32_t RESERVED2; /*!< Reserved, 0x1C */
bogdanm 0:9b334a45a8ff 366 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 367 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 368 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 369 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 370 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 371 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 372 }EXTI_TypeDef;
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /**
bogdanm 0:9b334a45a8ff 375 * @brief FLASH Registers
bogdanm 0:9b334a45a8ff 376 */
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 typedef struct
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 381 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 382 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 383 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 385 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 386 uint32_t RESERVED; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 387 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 388 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 } FLASH_TypeDef;
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /**
bogdanm 0:9b334a45a8ff 393 * @brief Option Bytes Registers
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395 typedef struct
bogdanm 0:9b334a45a8ff 396 {
bogdanm 0:9b334a45a8ff 397 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 398 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
bogdanm 0:9b334a45a8ff 399 uint16_t RESERVED0; /*!< Reserved, 0x04 */
bogdanm 0:9b334a45a8ff 400 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 401 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 402 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 403 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 404 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
bogdanm 0:9b334a45a8ff 405 } OB_TypeDef;
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /**
bogdanm 0:9b334a45a8ff 408 * @brief General Purpose I/O
bogdanm 0:9b334a45a8ff 409 */
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 typedef struct
bogdanm 0:9b334a45a8ff 412 {
bogdanm 0:9b334a45a8ff 413 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 414 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 415 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 416 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 417 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 418 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 419 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 420 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
bogdanm 0:9b334a45a8ff 421 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 422 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 0:9b334a45a8ff 423 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 424 }GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 /**
bogdanm 0:9b334a45a8ff 427 * @brief Operational Amplifier (OPAMP)
bogdanm 0:9b334a45a8ff 428 */
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 typedef struct
bogdanm 0:9b334a45a8ff 431 {
bogdanm 0:9b334a45a8ff 432 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 433 } OPAMP_TypeDef;
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /**
bogdanm 0:9b334a45a8ff 436 * @brief High resolution Timer (HRTIM)
bogdanm 0:9b334a45a8ff 437 */
bogdanm 0:9b334a45a8ff 438 /* HRTIM master registers definition */
bogdanm 0:9b334a45a8ff 439 typedef struct
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 442 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 443 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 444 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 445 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 446 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 447 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 448 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 449 uint32_t RESERVED0; /*!< Reserved, 0x20 */
bogdanm 0:9b334a45a8ff 450 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 451 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 452 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 453 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
bogdanm 0:9b334a45a8ff 454 }HRTIM_Master_TypeDef;
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* HRTIM Timer A to E registers definition */
bogdanm 0:9b334a45a8ff 457 typedef struct
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 462 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 463 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 464 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 465 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 466 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 467 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 468 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 469 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 470 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 471 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 472 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 473 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 474 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 475 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 476 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 477 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 478 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 479 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 480 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 481 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 482 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 483 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 484 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 485 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 486 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
bogdanm 0:9b334a45a8ff 487 }HRTIM_Timerx_TypeDef;
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* HRTIM common register definition */
bogdanm 0:9b334a45a8ff 490 typedef struct
bogdanm 0:9b334a45a8ff 491 {
bogdanm 0:9b334a45a8ff 492 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 493 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 494 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 495 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 496 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 497 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 498 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 499 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 500 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 501 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 502 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 503 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 504 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 505 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 506 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 507 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 508 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 509 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 510 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 511 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 512 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 513 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 514 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 515 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 516 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 517 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 518 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 519 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 520 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
bogdanm 0:9b334a45a8ff 521 }HRTIM_Common_TypeDef;
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* HRTIM register definition */
bogdanm 0:9b334a45a8ff 524 typedef struct {
bogdanm 0:9b334a45a8ff 525 HRTIM_Master_TypeDef sMasterRegs;
bogdanm 0:9b334a45a8ff 526 HRTIM_Timerx_TypeDef sTimerxRegs[5];
bogdanm 0:9b334a45a8ff 527 uint32_t RESERVED0[32];
bogdanm 0:9b334a45a8ff 528 HRTIM_Common_TypeDef sCommonRegs;
bogdanm 0:9b334a45a8ff 529 }HRTIM_TypeDef;
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /**
bogdanm 0:9b334a45a8ff 532 * @brief System configuration controller
bogdanm 0:9b334a45a8ff 533 */
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 typedef struct
bogdanm 0:9b334a45a8ff 536 {
bogdanm 0:9b334a45a8ff 537 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 538 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 539 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
bogdanm 0:9b334a45a8ff 540 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 541 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 0:9b334a45a8ff 542 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
bogdanm 0:9b334a45a8ff 543 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
bogdanm 0:9b334a45a8ff 544 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
bogdanm 0:9b334a45a8ff 545 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
bogdanm 0:9b334a45a8ff 546 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
bogdanm 0:9b334a45a8ff 547 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
bogdanm 0:9b334a45a8ff 548 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
bogdanm 0:9b334a45a8ff 549 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
bogdanm 0:9b334a45a8ff 550 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
bogdanm 0:9b334a45a8ff 551 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
bogdanm 0:9b334a45a8ff 552 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
bogdanm 0:9b334a45a8ff 553 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
bogdanm 0:9b334a45a8ff 554 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 555 } SYSCFG_TypeDef;
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /**
bogdanm 0:9b334a45a8ff 558 * @brief Inter-integrated Circuit Interface
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 typedef struct
bogdanm 0:9b334a45a8ff 562 {
bogdanm 0:9b334a45a8ff 563 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 564 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 565 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 566 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 567 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 568 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 569 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 570 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 571 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 572 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 573 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 574 }I2C_TypeDef;
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /**
bogdanm 0:9b334a45a8ff 577 * @brief Independent WATCHDOG
bogdanm 0:9b334a45a8ff 578 */
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 typedef struct
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 583 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 584 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 585 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 586 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 587 } IWDG_TypeDef;
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /**
bogdanm 0:9b334a45a8ff 590 * @brief Power Control
bogdanm 0:9b334a45a8ff 591 */
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 typedef struct
bogdanm 0:9b334a45a8ff 594 {
bogdanm 0:9b334a45a8ff 595 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 596 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 597 } PWR_TypeDef;
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /**
bogdanm 0:9b334a45a8ff 600 * @brief Reset and Clock Control
bogdanm 0:9b334a45a8ff 601 */
bogdanm 0:9b334a45a8ff 602 typedef struct
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 605 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 606 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 607 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 608 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 609 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 610 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 611 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 612 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 613 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 614 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 615 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 616 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 617 } RCC_TypeDef;
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /**
bogdanm 0:9b334a45a8ff 620 * @brief Real-Time Clock
bogdanm 0:9b334a45a8ff 621 */
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 typedef struct
bogdanm 0:9b334a45a8ff 624 {
bogdanm 0:9b334a45a8ff 625 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 626 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 627 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 628 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 629 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 630 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 631 uint32_t RESERVED0; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 632 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 633 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 634 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 635 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 636 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 637 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 638 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 639 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 640 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 641 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 642 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 643 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 644 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 0:9b334a45a8ff 645 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 646 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 647 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 648 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 649 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 650 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 651 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 652 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 653 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 0:9b334a45a8ff 654 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 0:9b334a45a8ff 655 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 0:9b334a45a8ff 656 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 0:9b334a45a8ff 657 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 658 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 659 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 0:9b334a45a8ff 660 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 661 } RTC_TypeDef;
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /**
bogdanm 0:9b334a45a8ff 665 * @brief Serial Peripheral Interface
bogdanm 0:9b334a45a8ff 666 */
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 typedef struct
bogdanm 0:9b334a45a8ff 669 {
bogdanm 0:9b334a45a8ff 670 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 671 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 672 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 673 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 674 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 675 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 676 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 677 } SPI_TypeDef;
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 /**
bogdanm 0:9b334a45a8ff 680 * @brief TIM
bogdanm 0:9b334a45a8ff 681 */
bogdanm 0:9b334a45a8ff 682 typedef struct
bogdanm 0:9b334a45a8ff 683 {
bogdanm 0:9b334a45a8ff 684 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 685 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 686 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 687 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 688 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 689 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 690 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 691 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 692 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 693 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 694 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 695 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 696 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 697 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 698 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 699 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 700 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 701 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 702 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 703 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 704 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 705 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 706 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 707 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 708 } TIM_TypeDef;
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 /**
bogdanm 0:9b334a45a8ff 711 * @brief Touch Sensing Controller (TSC)
bogdanm 0:9b334a45a8ff 712 */
bogdanm 0:9b334a45a8ff 713 typedef struct
bogdanm 0:9b334a45a8ff 714 {
bogdanm 0:9b334a45a8ff 715 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 716 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 717 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 718 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 719 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 720 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 721 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 722 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 723 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 724 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 725 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 726 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 727 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 728 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 0:9b334a45a8ff 729 } TSC_TypeDef;
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /**
bogdanm 0:9b334a45a8ff 732 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 0:9b334a45a8ff 733 */
bogdanm 0:9b334a45a8ff 734
bogdanm 0:9b334a45a8ff 735 typedef struct
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 738 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 739 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 740 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 741 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 742 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 743 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 744 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 745 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 746 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 747 uint16_t RESERVED1; /*!< Reserved, 0x26 */
bogdanm 0:9b334a45a8ff 748 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 749 uint16_t RESERVED2; /*!< Reserved, 0x2A */
bogdanm 0:9b334a45a8ff 750 } USART_TypeDef;
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /**
bogdanm 0:9b334a45a8ff 753 * @brief Window WATCHDOG
bogdanm 0:9b334a45a8ff 754 */
bogdanm 0:9b334a45a8ff 755 typedef struct
bogdanm 0:9b334a45a8ff 756 {
bogdanm 0:9b334a45a8ff 757 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 758 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 759 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 760 } WWDG_TypeDef;
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 /** @addtogroup Peripheral_memory_map
bogdanm 0:9b334a45a8ff 763 * @{
bogdanm 0:9b334a45a8ff 764 */
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 767 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 768 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 769 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 772 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 773 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775
bogdanm 0:9b334a45a8ff 776 /*!< Peripheral memory map */
bogdanm 0:9b334a45a8ff 777 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 0:9b334a45a8ff 778 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 0:9b334a45a8ff 779 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 0:9b334a45a8ff 780 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm 0:9b334a45a8ff 781 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /*!< APB1 peripherals */
bogdanm 0:9b334a45a8ff 784 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 785 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 786 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 787 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
bogdanm 0:9b334a45a8ff 788 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
bogdanm 0:9b334a45a8ff 789 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
bogdanm 0:9b334a45a8ff 790 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 791 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
bogdanm 0:9b334a45a8ff 792 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
bogdanm 0:9b334a45a8ff 793 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
bogdanm 0:9b334a45a8ff 794 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
bogdanm 0:9b334a45a8ff 795 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
bogdanm 0:9b334a45a8ff 796 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
bogdanm 0:9b334a45a8ff 797 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
bogdanm 0:9b334a45a8ff 798 #define DAC_BASE DAC1_BASE
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /*!< APB2 peripherals */
bogdanm 0:9b334a45a8ff 801 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 802 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
bogdanm 0:9b334a45a8ff 803 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
bogdanm 0:9b334a45a8ff 804 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
bogdanm 0:9b334a45a8ff 805 #define COMP_BASE COMP2_BASE
bogdanm 0:9b334a45a8ff 806 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
bogdanm 0:9b334a45a8ff 807 #define OPAMP_BASE OPAMP2_BASE
bogdanm 0:9b334a45a8ff 808 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 809 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
bogdanm 0:9b334a45a8ff 810 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 811 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
bogdanm 0:9b334a45a8ff 812 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
bogdanm 0:9b334a45a8ff 813 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
bogdanm 0:9b334a45a8ff 814 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
bogdanm 0:9b334a45a8ff 815 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
bogdanm 0:9b334a45a8ff 816 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
bogdanm 0:9b334a45a8ff 817 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
bogdanm 0:9b334a45a8ff 818 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
bogdanm 0:9b334a45a8ff 819 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
bogdanm 0:9b334a45a8ff 820 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
bogdanm 0:9b334a45a8ff 821 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /*!< AHB1 peripherals */
bogdanm 0:9b334a45a8ff 824 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 825 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
bogdanm 0:9b334a45a8ff 826 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
bogdanm 0:9b334a45a8ff 827 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
bogdanm 0:9b334a45a8ff 828 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
bogdanm 0:9b334a45a8ff 829 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
bogdanm 0:9b334a45a8ff 830 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
bogdanm 0:9b334a45a8ff 831 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
bogdanm 0:9b334a45a8ff 832 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 833 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
bogdanm 0:9b334a45a8ff 834 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
bogdanm 0:9b334a45a8ff 835 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 836 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /*!< AHB2 peripherals */
bogdanm 0:9b334a45a8ff 839 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 840 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 841 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
bogdanm 0:9b334a45a8ff 842 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
bogdanm 0:9b334a45a8ff 843 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 /*!< AHB3 peripherals */
bogdanm 0:9b334a45a8ff 846 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 847 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
bogdanm 0:9b334a45a8ff 848 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
bogdanm 0:9b334a45a8ff 851 /**
bogdanm 0:9b334a45a8ff 852 * @}
bogdanm 0:9b334a45a8ff 853 */
bogdanm 0:9b334a45a8ff 854
bogdanm 0:9b334a45a8ff 855 /** @addtogroup Peripheral_declaration
bogdanm 0:9b334a45a8ff 856 * @{
bogdanm 0:9b334a45a8ff 857 */
bogdanm 0:9b334a45a8ff 858 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
bogdanm 0:9b334a45a8ff 859 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
bogdanm 0:9b334a45a8ff 860 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
bogdanm 0:9b334a45a8ff 861 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
bogdanm 0:9b334a45a8ff 862 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
bogdanm 0:9b334a45a8ff 863 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
bogdanm 0:9b334a45a8ff 864 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
bogdanm 0:9b334a45a8ff 865 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 0:9b334a45a8ff 866 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 0:9b334a45a8ff 867 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 0:9b334a45a8ff 868 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 0:9b334a45a8ff 869 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 0:9b334a45a8ff 870 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 0:9b334a45a8ff 871 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 0:9b334a45a8ff 872 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 0:9b334a45a8ff 873 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 0:9b334a45a8ff 874 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 0:9b334a45a8ff 875 #define CAN ((CAN_TypeDef *) CAN_BASE)
bogdanm 0:9b334a45a8ff 876 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 0:9b334a45a8ff 877 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
bogdanm 0:9b334a45a8ff 878 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
bogdanm 0:9b334a45a8ff 879 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 0:9b334a45a8ff 880 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 0:9b334a45a8ff 881 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm 0:9b334a45a8ff 882 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
bogdanm 0:9b334a45a8ff 883 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
bogdanm 0:9b334a45a8ff 884 #define COMP ((COMP_TypeDef *) COMP_BASE)
bogdanm 0:9b334a45a8ff 885 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
bogdanm 0:9b334a45a8ff 886 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
bogdanm 0:9b334a45a8ff 887 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 0:9b334a45a8ff 888 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 0:9b334a45a8ff 889 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 0:9b334a45a8ff 890 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 0:9b334a45a8ff 891 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm 0:9b334a45a8ff 892 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm 0:9b334a45a8ff 893 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm 0:9b334a45a8ff 894 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 0:9b334a45a8ff 895 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 0:9b334a45a8ff 896 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 0:9b334a45a8ff 897 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 0:9b334a45a8ff 898 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 0:9b334a45a8ff 899 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 0:9b334a45a8ff 900 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 0:9b334a45a8ff 901 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 0:9b334a45a8ff 902 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 0:9b334a45a8ff 903 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 0:9b334a45a8ff 904 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 0:9b334a45a8ff 905 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 0:9b334a45a8ff 906 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 0:9b334a45a8ff 907 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 0:9b334a45a8ff 908 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 0:9b334a45a8ff 909 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 0:9b334a45a8ff 910 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 0:9b334a45a8ff 911 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 0:9b334a45a8ff 912 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 0:9b334a45a8ff 913 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 0:9b334a45a8ff 914 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 0:9b334a45a8ff 915 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
bogdanm 0:9b334a45a8ff 916 /**
bogdanm 0:9b334a45a8ff 917 * @}
bogdanm 0:9b334a45a8ff 918 */
bogdanm 0:9b334a45a8ff 919
bogdanm 0:9b334a45a8ff 920 /** @addtogroup Exported_constants
bogdanm 0:9b334a45a8ff 921 * @{
bogdanm 0:9b334a45a8ff 922 */
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 0:9b334a45a8ff 925 * @{
bogdanm 0:9b334a45a8ff 926 */
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /******************************************************************************/
bogdanm 0:9b334a45a8ff 929 /* Peripheral Registers_Bits_Definition */
bogdanm 0:9b334a45a8ff 930 /******************************************************************************/
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /******************************************************************************/
bogdanm 0:9b334a45a8ff 933 /* */
bogdanm 0:9b334a45a8ff 934 /* Analog to Digital Converter SAR (ADC) */
bogdanm 0:9b334a45a8ff 935 /* */
bogdanm 0:9b334a45a8ff 936 /******************************************************************************/
bogdanm 0:9b334a45a8ff 937 /******************** Bit definition for ADC_ISR register ********************/
bogdanm 0:9b334a45a8ff 938 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
bogdanm 0:9b334a45a8ff 939 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
bogdanm 0:9b334a45a8ff 940 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
bogdanm 0:9b334a45a8ff 941 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
bogdanm 0:9b334a45a8ff 942 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
bogdanm 0:9b334a45a8ff 943 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
bogdanm 0:9b334a45a8ff 944 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
bogdanm 0:9b334a45a8ff 945 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
bogdanm 0:9b334a45a8ff 946 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
bogdanm 0:9b334a45a8ff 947 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
bogdanm 0:9b334a45a8ff 948 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
bogdanm 0:9b334a45a8ff 949
bogdanm 0:9b334a45a8ff 950 /******************** Bit definition for ADC_IER register ********************/
bogdanm 0:9b334a45a8ff 951 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
bogdanm 0:9b334a45a8ff 952 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
bogdanm 0:9b334a45a8ff 953 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
bogdanm 0:9b334a45a8ff 954 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
bogdanm 0:9b334a45a8ff 955 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
bogdanm 0:9b334a45a8ff 956 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
bogdanm 0:9b334a45a8ff 957 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
bogdanm 0:9b334a45a8ff 958 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
bogdanm 0:9b334a45a8ff 959 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
bogdanm 0:9b334a45a8ff 960 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
bogdanm 0:9b334a45a8ff 961 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
bogdanm 0:9b334a45a8ff 962
bogdanm 0:9b334a45a8ff 963 /******************** Bit definition for ADC_CR register ********************/
bogdanm 0:9b334a45a8ff 964 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
bogdanm 0:9b334a45a8ff 965 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
bogdanm 0:9b334a45a8ff 966 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
bogdanm 0:9b334a45a8ff 967 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
bogdanm 0:9b334a45a8ff 968 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
bogdanm 0:9b334a45a8ff 969 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
bogdanm 0:9b334a45a8ff 970 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
bogdanm 0:9b334a45a8ff 971 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
bogdanm 0:9b334a45a8ff 972 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
bogdanm 0:9b334a45a8ff 973 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
bogdanm 0:9b334a45a8ff 974 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 /******************** Bit definition for ADC_CFGR register ********************/
bogdanm 0:9b334a45a8ff 977 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
bogdanm 0:9b334a45a8ff 978 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
bogdanm 0:9b334a45a8ff 979
bogdanm 0:9b334a45a8ff 980 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
bogdanm 0:9b334a45a8ff 981 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
bogdanm 0:9b334a45a8ff 982 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
bogdanm 0:9b334a45a8ff 985
bogdanm 0:9b334a45a8ff 986 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
bogdanm 0:9b334a45a8ff 987 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
bogdanm 0:9b334a45a8ff 988 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
bogdanm 0:9b334a45a8ff 989 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
bogdanm 0:9b334a45a8ff 990 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
bogdanm 0:9b334a45a8ff 991
bogdanm 0:9b334a45a8ff 992 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
bogdanm 0:9b334a45a8ff 993 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
bogdanm 0:9b334a45a8ff 994 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
bogdanm 0:9b334a45a8ff 995
bogdanm 0:9b334a45a8ff 996 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
bogdanm 0:9b334a45a8ff 997 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
bogdanm 0:9b334a45a8ff 998 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
bogdanm 0:9b334a45a8ff 999 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
bogdanm 0:9b334a45a8ff 1000 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
bogdanm 0:9b334a45a8ff 1003 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
bogdanm 0:9b334a45a8ff 1004 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
bogdanm 0:9b334a45a8ff 1005 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
bogdanm 0:9b334a45a8ff 1006
bogdanm 0:9b334a45a8ff 1007 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
bogdanm 0:9b334a45a8ff 1008 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
bogdanm 0:9b334a45a8ff 1009 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
bogdanm 0:9b334a45a8ff 1010 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
bogdanm 0:9b334a45a8ff 1011 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
bogdanm 0:9b334a45a8ff 1012 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
bogdanm 0:9b334a45a8ff 1013
bogdanm 0:9b334a45a8ff 1014 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
bogdanm 0:9b334a45a8ff 1015 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
bogdanm 0:9b334a45a8ff 1016 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
bogdanm 0:9b334a45a8ff 1017 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
bogdanm 0:9b334a45a8ff 1018 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
bogdanm 0:9b334a45a8ff 1019 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /******************** Bit definition for ADC_SMPR1 register ********************/
bogdanm 0:9b334a45a8ff 1022 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
bogdanm 0:9b334a45a8ff 1023 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
bogdanm 0:9b334a45a8ff 1024 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
bogdanm 0:9b334a45a8ff 1025 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
bogdanm 0:9b334a45a8ff 1028 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
bogdanm 0:9b334a45a8ff 1029 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
bogdanm 0:9b334a45a8ff 1030 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
bogdanm 0:9b334a45a8ff 1033 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
bogdanm 0:9b334a45a8ff 1034 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
bogdanm 0:9b334a45a8ff 1035 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
bogdanm 0:9b334a45a8ff 1038 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
bogdanm 0:9b334a45a8ff 1039 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
bogdanm 0:9b334a45a8ff 1040 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
bogdanm 0:9b334a45a8ff 1043 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
bogdanm 0:9b334a45a8ff 1044 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
bogdanm 0:9b334a45a8ff 1045 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
bogdanm 0:9b334a45a8ff 1048 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
bogdanm 0:9b334a45a8ff 1049 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
bogdanm 0:9b334a45a8ff 1050 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
bogdanm 0:9b334a45a8ff 1053 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
bogdanm 0:9b334a45a8ff 1054 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
bogdanm 0:9b334a45a8ff 1055 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
bogdanm 0:9b334a45a8ff 1058 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
bogdanm 0:9b334a45a8ff 1059 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
bogdanm 0:9b334a45a8ff 1060 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
bogdanm 0:9b334a45a8ff 1061
bogdanm 0:9b334a45a8ff 1062 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
bogdanm 0:9b334a45a8ff 1063 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
bogdanm 0:9b334a45a8ff 1064 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
bogdanm 0:9b334a45a8ff 1065 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
bogdanm 0:9b334a45a8ff 1066
bogdanm 0:9b334a45a8ff 1067 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
bogdanm 0:9b334a45a8ff 1068 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
bogdanm 0:9b334a45a8ff 1069 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
bogdanm 0:9b334a45a8ff 1070 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
bogdanm 0:9b334a45a8ff 1071
bogdanm 0:9b334a45a8ff 1072 /******************** Bit definition for ADC_SMPR2 register ********************/
bogdanm 0:9b334a45a8ff 1073 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
bogdanm 0:9b334a45a8ff 1074 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
bogdanm 0:9b334a45a8ff 1075 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
bogdanm 0:9b334a45a8ff 1076 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
bogdanm 0:9b334a45a8ff 1079 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
bogdanm 0:9b334a45a8ff 1080 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
bogdanm 0:9b334a45a8ff 1081 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
bogdanm 0:9b334a45a8ff 1084 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
bogdanm 0:9b334a45a8ff 1085 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
bogdanm 0:9b334a45a8ff 1086 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
bogdanm 0:9b334a45a8ff 1089 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
bogdanm 0:9b334a45a8ff 1090 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
bogdanm 0:9b334a45a8ff 1091 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
bogdanm 0:9b334a45a8ff 1092
bogdanm 0:9b334a45a8ff 1093 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
bogdanm 0:9b334a45a8ff 1094 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
bogdanm 0:9b334a45a8ff 1095 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
bogdanm 0:9b334a45a8ff 1096 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
bogdanm 0:9b334a45a8ff 1097
bogdanm 0:9b334a45a8ff 1098 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
bogdanm 0:9b334a45a8ff 1099 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
bogdanm 0:9b334a45a8ff 1100 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
bogdanm 0:9b334a45a8ff 1101 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
bogdanm 0:9b334a45a8ff 1104 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
bogdanm 0:9b334a45a8ff 1105 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
bogdanm 0:9b334a45a8ff 1106 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
bogdanm 0:9b334a45a8ff 1107
bogdanm 0:9b334a45a8ff 1108 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
bogdanm 0:9b334a45a8ff 1109 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
bogdanm 0:9b334a45a8ff 1110 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
bogdanm 0:9b334a45a8ff 1111 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
bogdanm 0:9b334a45a8ff 1112
bogdanm 0:9b334a45a8ff 1113 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
bogdanm 0:9b334a45a8ff 1114 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
bogdanm 0:9b334a45a8ff 1115 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
bogdanm 0:9b334a45a8ff 1116 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 /******************** Bit definition for ADC_TR1 register ********************/
bogdanm 0:9b334a45a8ff 1119 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
bogdanm 0:9b334a45a8ff 1120 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
bogdanm 0:9b334a45a8ff 1121 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
bogdanm 0:9b334a45a8ff 1122 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
bogdanm 0:9b334a45a8ff 1123 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
bogdanm 0:9b334a45a8ff 1124 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
bogdanm 0:9b334a45a8ff 1125 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
bogdanm 0:9b334a45a8ff 1126 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
bogdanm 0:9b334a45a8ff 1127 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
bogdanm 0:9b334a45a8ff 1128 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
bogdanm 0:9b334a45a8ff 1129 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
bogdanm 0:9b334a45a8ff 1130 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
bogdanm 0:9b334a45a8ff 1131 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
bogdanm 0:9b334a45a8ff 1134 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
bogdanm 0:9b334a45a8ff 1135 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
bogdanm 0:9b334a45a8ff 1136 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
bogdanm 0:9b334a45a8ff 1137 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
bogdanm 0:9b334a45a8ff 1138 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
bogdanm 0:9b334a45a8ff 1139 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
bogdanm 0:9b334a45a8ff 1140 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
bogdanm 0:9b334a45a8ff 1141 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
bogdanm 0:9b334a45a8ff 1142 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
bogdanm 0:9b334a45a8ff 1143 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
bogdanm 0:9b334a45a8ff 1144 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
bogdanm 0:9b334a45a8ff 1145 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
bogdanm 0:9b334a45a8ff 1146
bogdanm 0:9b334a45a8ff 1147 /******************** Bit definition for ADC_TR2 register ********************/
bogdanm 0:9b334a45a8ff 1148 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
bogdanm 0:9b334a45a8ff 1149 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
bogdanm 0:9b334a45a8ff 1150 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
bogdanm 0:9b334a45a8ff 1151 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
bogdanm 0:9b334a45a8ff 1152 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
bogdanm 0:9b334a45a8ff 1153 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
bogdanm 0:9b334a45a8ff 1154 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
bogdanm 0:9b334a45a8ff 1155 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
bogdanm 0:9b334a45a8ff 1156 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
bogdanm 0:9b334a45a8ff 1157
bogdanm 0:9b334a45a8ff 1158 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
bogdanm 0:9b334a45a8ff 1159 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
bogdanm 0:9b334a45a8ff 1160 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
bogdanm 0:9b334a45a8ff 1161 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
bogdanm 0:9b334a45a8ff 1162 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
bogdanm 0:9b334a45a8ff 1163 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
bogdanm 0:9b334a45a8ff 1164 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
bogdanm 0:9b334a45a8ff 1165 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
bogdanm 0:9b334a45a8ff 1166 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 /******************** Bit definition for ADC_TR3 register ********************/
bogdanm 0:9b334a45a8ff 1169 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
bogdanm 0:9b334a45a8ff 1170 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
bogdanm 0:9b334a45a8ff 1171 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
bogdanm 0:9b334a45a8ff 1172 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
bogdanm 0:9b334a45a8ff 1173 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
bogdanm 0:9b334a45a8ff 1174 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
bogdanm 0:9b334a45a8ff 1175 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
bogdanm 0:9b334a45a8ff 1176 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
bogdanm 0:9b334a45a8ff 1177 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
bogdanm 0:9b334a45a8ff 1178
bogdanm 0:9b334a45a8ff 1179 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
bogdanm 0:9b334a45a8ff 1180 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
bogdanm 0:9b334a45a8ff 1181 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
bogdanm 0:9b334a45a8ff 1182 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
bogdanm 0:9b334a45a8ff 1183 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
bogdanm 0:9b334a45a8ff 1184 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
bogdanm 0:9b334a45a8ff 1185 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
bogdanm 0:9b334a45a8ff 1186 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
bogdanm 0:9b334a45a8ff 1187 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
bogdanm 0:9b334a45a8ff 1188
bogdanm 0:9b334a45a8ff 1189 /******************** Bit definition for ADC_SQR1 register ********************/
bogdanm 0:9b334a45a8ff 1190 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
bogdanm 0:9b334a45a8ff 1191 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
bogdanm 0:9b334a45a8ff 1192 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
bogdanm 0:9b334a45a8ff 1193 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
bogdanm 0:9b334a45a8ff 1194 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
bogdanm 0:9b334a45a8ff 1195
bogdanm 0:9b334a45a8ff 1196 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1197 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
bogdanm 0:9b334a45a8ff 1198 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
bogdanm 0:9b334a45a8ff 1199 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
bogdanm 0:9b334a45a8ff 1200 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
bogdanm 0:9b334a45a8ff 1201 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1204 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
bogdanm 0:9b334a45a8ff 1205 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
bogdanm 0:9b334a45a8ff 1206 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
bogdanm 0:9b334a45a8ff 1207 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
bogdanm 0:9b334a45a8ff 1208 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
bogdanm 0:9b334a45a8ff 1209
bogdanm 0:9b334a45a8ff 1210 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1211 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
bogdanm 0:9b334a45a8ff 1212 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
bogdanm 0:9b334a45a8ff 1213 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
bogdanm 0:9b334a45a8ff 1214 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
bogdanm 0:9b334a45a8ff 1215 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1218 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
bogdanm 0:9b334a45a8ff 1219 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
bogdanm 0:9b334a45a8ff 1220 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
bogdanm 0:9b334a45a8ff 1221 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
bogdanm 0:9b334a45a8ff 1222 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
bogdanm 0:9b334a45a8ff 1223
bogdanm 0:9b334a45a8ff 1224 /******************** Bit definition for ADC_SQR2 register ********************/
bogdanm 0:9b334a45a8ff 1225 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1226 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
bogdanm 0:9b334a45a8ff 1227 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
bogdanm 0:9b334a45a8ff 1228 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
bogdanm 0:9b334a45a8ff 1229 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
bogdanm 0:9b334a45a8ff 1230 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
bogdanm 0:9b334a45a8ff 1231
bogdanm 0:9b334a45a8ff 1232 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1233 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
bogdanm 0:9b334a45a8ff 1234 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
bogdanm 0:9b334a45a8ff 1235 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
bogdanm 0:9b334a45a8ff 1236 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
bogdanm 0:9b334a45a8ff 1237 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
bogdanm 0:9b334a45a8ff 1238
bogdanm 0:9b334a45a8ff 1239 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1240 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
bogdanm 0:9b334a45a8ff 1241 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
bogdanm 0:9b334a45a8ff 1242 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
bogdanm 0:9b334a45a8ff 1243 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
bogdanm 0:9b334a45a8ff 1244 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
bogdanm 0:9b334a45a8ff 1245
bogdanm 0:9b334a45a8ff 1246 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1247 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
bogdanm 0:9b334a45a8ff 1248 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
bogdanm 0:9b334a45a8ff 1249 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
bogdanm 0:9b334a45a8ff 1250 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
bogdanm 0:9b334a45a8ff 1251 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
bogdanm 0:9b334a45a8ff 1252
bogdanm 0:9b334a45a8ff 1253 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1254 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
bogdanm 0:9b334a45a8ff 1255 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
bogdanm 0:9b334a45a8ff 1256 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
bogdanm 0:9b334a45a8ff 1257 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
bogdanm 0:9b334a45a8ff 1258 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
bogdanm 0:9b334a45a8ff 1259
bogdanm 0:9b334a45a8ff 1260 /******************** Bit definition for ADC_SQR3 register ********************/
bogdanm 0:9b334a45a8ff 1261 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1262 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
bogdanm 0:9b334a45a8ff 1263 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
bogdanm 0:9b334a45a8ff 1264 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
bogdanm 0:9b334a45a8ff 1265 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
bogdanm 0:9b334a45a8ff 1266 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
bogdanm 0:9b334a45a8ff 1267
bogdanm 0:9b334a45a8ff 1268 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1269 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
bogdanm 0:9b334a45a8ff 1270 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
bogdanm 0:9b334a45a8ff 1271 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
bogdanm 0:9b334a45a8ff 1272 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
bogdanm 0:9b334a45a8ff 1273 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1276 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
bogdanm 0:9b334a45a8ff 1277 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
bogdanm 0:9b334a45a8ff 1278 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
bogdanm 0:9b334a45a8ff 1279 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
bogdanm 0:9b334a45a8ff 1280 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
bogdanm 0:9b334a45a8ff 1281
bogdanm 0:9b334a45a8ff 1282 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1283 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
bogdanm 0:9b334a45a8ff 1284 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
bogdanm 0:9b334a45a8ff 1285 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
bogdanm 0:9b334a45a8ff 1286 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
bogdanm 0:9b334a45a8ff 1287 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1290 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
bogdanm 0:9b334a45a8ff 1291 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
bogdanm 0:9b334a45a8ff 1292 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
bogdanm 0:9b334a45a8ff 1293 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
bogdanm 0:9b334a45a8ff 1294 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
bogdanm 0:9b334a45a8ff 1295
bogdanm 0:9b334a45a8ff 1296 /******************** Bit definition for ADC_SQR4 register ********************/
bogdanm 0:9b334a45a8ff 1297 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1298 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
bogdanm 0:9b334a45a8ff 1299 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
bogdanm 0:9b334a45a8ff 1300 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
bogdanm 0:9b334a45a8ff 1301 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
bogdanm 0:9b334a45a8ff 1302 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
bogdanm 0:9b334a45a8ff 1303
bogdanm 0:9b334a45a8ff 1304 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
bogdanm 0:9b334a45a8ff 1305 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
bogdanm 0:9b334a45a8ff 1306 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
bogdanm 0:9b334a45a8ff 1307 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
bogdanm 0:9b334a45a8ff 1308 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
bogdanm 0:9b334a45a8ff 1309 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
bogdanm 0:9b334a45a8ff 1310 /******************** Bit definition for ADC_DR register ********************/
bogdanm 0:9b334a45a8ff 1311 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
bogdanm 0:9b334a45a8ff 1312 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
bogdanm 0:9b334a45a8ff 1313 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
bogdanm 0:9b334a45a8ff 1314 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
bogdanm 0:9b334a45a8ff 1315 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
bogdanm 0:9b334a45a8ff 1316 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
bogdanm 0:9b334a45a8ff 1317 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
bogdanm 0:9b334a45a8ff 1318 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
bogdanm 0:9b334a45a8ff 1319 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
bogdanm 0:9b334a45a8ff 1320 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
bogdanm 0:9b334a45a8ff 1321 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
bogdanm 0:9b334a45a8ff 1322 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
bogdanm 0:9b334a45a8ff 1323 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
bogdanm 0:9b334a45a8ff 1324 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
bogdanm 0:9b334a45a8ff 1325 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
bogdanm 0:9b334a45a8ff 1326 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
bogdanm 0:9b334a45a8ff 1327 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
bogdanm 0:9b334a45a8ff 1328
bogdanm 0:9b334a45a8ff 1329 /******************** Bit definition for ADC_JSQR register ********************/
bogdanm 0:9b334a45a8ff 1330 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
bogdanm 0:9b334a45a8ff 1331 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
bogdanm 0:9b334a45a8ff 1332 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
bogdanm 0:9b334a45a8ff 1333
bogdanm 0:9b334a45a8ff 1334 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
bogdanm 0:9b334a45a8ff 1335 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
bogdanm 0:9b334a45a8ff 1336 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
bogdanm 0:9b334a45a8ff 1337 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
bogdanm 0:9b334a45a8ff 1338 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
bogdanm 0:9b334a45a8ff 1339
bogdanm 0:9b334a45a8ff 1340 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
bogdanm 0:9b334a45a8ff 1341 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
bogdanm 0:9b334a45a8ff 1342 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
bogdanm 0:9b334a45a8ff 1343
bogdanm 0:9b334a45a8ff 1344 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
bogdanm 0:9b334a45a8ff 1345 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
bogdanm 0:9b334a45a8ff 1346 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
bogdanm 0:9b334a45a8ff 1347 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
bogdanm 0:9b334a45a8ff 1348 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
bogdanm 0:9b334a45a8ff 1349 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
bogdanm 0:9b334a45a8ff 1350
bogdanm 0:9b334a45a8ff 1351 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
bogdanm 0:9b334a45a8ff 1352 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
bogdanm 0:9b334a45a8ff 1353 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
bogdanm 0:9b334a45a8ff 1354 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
bogdanm 0:9b334a45a8ff 1355 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
bogdanm 0:9b334a45a8ff 1356 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
bogdanm 0:9b334a45a8ff 1357
bogdanm 0:9b334a45a8ff 1358 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
bogdanm 0:9b334a45a8ff 1359 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
bogdanm 0:9b334a45a8ff 1360 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
bogdanm 0:9b334a45a8ff 1361 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
bogdanm 0:9b334a45a8ff 1362 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
bogdanm 0:9b334a45a8ff 1363 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
bogdanm 0:9b334a45a8ff 1366 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
bogdanm 0:9b334a45a8ff 1367 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
bogdanm 0:9b334a45a8ff 1368 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
bogdanm 0:9b334a45a8ff 1369 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
bogdanm 0:9b334a45a8ff 1370 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 /******************** Bit definition for ADC_OFR1 register ********************/
bogdanm 0:9b334a45a8ff 1373 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
bogdanm 0:9b334a45a8ff 1374 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
bogdanm 0:9b334a45a8ff 1375 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
bogdanm 0:9b334a45a8ff 1376 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
bogdanm 0:9b334a45a8ff 1377 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
bogdanm 0:9b334a45a8ff 1378 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
bogdanm 0:9b334a45a8ff 1379 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
bogdanm 0:9b334a45a8ff 1380 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
bogdanm 0:9b334a45a8ff 1381 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
bogdanm 0:9b334a45a8ff 1382 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
bogdanm 0:9b334a45a8ff 1383 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
bogdanm 0:9b334a45a8ff 1384 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
bogdanm 0:9b334a45a8ff 1385 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
bogdanm 0:9b334a45a8ff 1386
bogdanm 0:9b334a45a8ff 1387 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
bogdanm 0:9b334a45a8ff 1388 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
bogdanm 0:9b334a45a8ff 1389 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
bogdanm 0:9b334a45a8ff 1390 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
bogdanm 0:9b334a45a8ff 1391 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
bogdanm 0:9b334a45a8ff 1392 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
bogdanm 0:9b334a45a8ff 1393
bogdanm 0:9b334a45a8ff 1394 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
bogdanm 0:9b334a45a8ff 1395
bogdanm 0:9b334a45a8ff 1396 /******************** Bit definition for ADC_OFR2 register ********************/
bogdanm 0:9b334a45a8ff 1397 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
bogdanm 0:9b334a45a8ff 1398 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
bogdanm 0:9b334a45a8ff 1399 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
bogdanm 0:9b334a45a8ff 1400 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
bogdanm 0:9b334a45a8ff 1401 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
bogdanm 0:9b334a45a8ff 1402 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
bogdanm 0:9b334a45a8ff 1403 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
bogdanm 0:9b334a45a8ff 1404 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
bogdanm 0:9b334a45a8ff 1405 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
bogdanm 0:9b334a45a8ff 1406 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
bogdanm 0:9b334a45a8ff 1407 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
bogdanm 0:9b334a45a8ff 1408 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
bogdanm 0:9b334a45a8ff 1409 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
bogdanm 0:9b334a45a8ff 1410
bogdanm 0:9b334a45a8ff 1411 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
bogdanm 0:9b334a45a8ff 1412 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
bogdanm 0:9b334a45a8ff 1413 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
bogdanm 0:9b334a45a8ff 1414 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
bogdanm 0:9b334a45a8ff 1415 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
bogdanm 0:9b334a45a8ff 1416 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
bogdanm 0:9b334a45a8ff 1417
bogdanm 0:9b334a45a8ff 1418 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
bogdanm 0:9b334a45a8ff 1419
bogdanm 0:9b334a45a8ff 1420 /******************** Bit definition for ADC_OFR3 register ********************/
bogdanm 0:9b334a45a8ff 1421 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
bogdanm 0:9b334a45a8ff 1422 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
bogdanm 0:9b334a45a8ff 1423 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
bogdanm 0:9b334a45a8ff 1424 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
bogdanm 0:9b334a45a8ff 1425 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
bogdanm 0:9b334a45a8ff 1426 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
bogdanm 0:9b334a45a8ff 1427 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
bogdanm 0:9b334a45a8ff 1428 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
bogdanm 0:9b334a45a8ff 1429 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
bogdanm 0:9b334a45a8ff 1430 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
bogdanm 0:9b334a45a8ff 1431 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
bogdanm 0:9b334a45a8ff 1432 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
bogdanm 0:9b334a45a8ff 1433 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
bogdanm 0:9b334a45a8ff 1434
bogdanm 0:9b334a45a8ff 1435 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
bogdanm 0:9b334a45a8ff 1436 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
bogdanm 0:9b334a45a8ff 1437 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
bogdanm 0:9b334a45a8ff 1438 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
bogdanm 0:9b334a45a8ff 1439 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
bogdanm 0:9b334a45a8ff 1440 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
bogdanm 0:9b334a45a8ff 1441
bogdanm 0:9b334a45a8ff 1442 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
bogdanm 0:9b334a45a8ff 1443
bogdanm 0:9b334a45a8ff 1444 /******************** Bit definition for ADC_OFR4 register ********************/
bogdanm 0:9b334a45a8ff 1445 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
bogdanm 0:9b334a45a8ff 1446 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
bogdanm 0:9b334a45a8ff 1447 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
bogdanm 0:9b334a45a8ff 1448 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
bogdanm 0:9b334a45a8ff 1449 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
bogdanm 0:9b334a45a8ff 1450 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
bogdanm 0:9b334a45a8ff 1451 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
bogdanm 0:9b334a45a8ff 1452 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
bogdanm 0:9b334a45a8ff 1453 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
bogdanm 0:9b334a45a8ff 1454 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
bogdanm 0:9b334a45a8ff 1455 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
bogdanm 0:9b334a45a8ff 1456 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
bogdanm 0:9b334a45a8ff 1457 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
bogdanm 0:9b334a45a8ff 1458
bogdanm 0:9b334a45a8ff 1459 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
bogdanm 0:9b334a45a8ff 1460 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
bogdanm 0:9b334a45a8ff 1461 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
bogdanm 0:9b334a45a8ff 1462 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
bogdanm 0:9b334a45a8ff 1463 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
bogdanm 0:9b334a45a8ff 1464 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
bogdanm 0:9b334a45a8ff 1465
bogdanm 0:9b334a45a8ff 1466 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
bogdanm 0:9b334a45a8ff 1467
bogdanm 0:9b334a45a8ff 1468 /******************** Bit definition for ADC_JDR1 register ********************/
bogdanm 0:9b334a45a8ff 1469 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 0:9b334a45a8ff 1470 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 0:9b334a45a8ff 1471 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 0:9b334a45a8ff 1472 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 0:9b334a45a8ff 1473 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 0:9b334a45a8ff 1474 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 0:9b334a45a8ff 1475 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 0:9b334a45a8ff 1476 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 0:9b334a45a8ff 1477 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 0:9b334a45a8ff 1478 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 0:9b334a45a8ff 1479 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 0:9b334a45a8ff 1480 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 0:9b334a45a8ff 1481 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 0:9b334a45a8ff 1482 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 0:9b334a45a8ff 1483 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 0:9b334a45a8ff 1484 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 0:9b334a45a8ff 1485 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 0:9b334a45a8ff 1486
bogdanm 0:9b334a45a8ff 1487 /******************** Bit definition for ADC_JDR2 register ********************/
bogdanm 0:9b334a45a8ff 1488 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 0:9b334a45a8ff 1489 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 0:9b334a45a8ff 1490 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 0:9b334a45a8ff 1491 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 0:9b334a45a8ff 1492 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 0:9b334a45a8ff 1493 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 0:9b334a45a8ff 1494 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 0:9b334a45a8ff 1495 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 0:9b334a45a8ff 1496 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 0:9b334a45a8ff 1497 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 0:9b334a45a8ff 1498 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 0:9b334a45a8ff 1499 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 0:9b334a45a8ff 1500 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 0:9b334a45a8ff 1501 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 0:9b334a45a8ff 1502 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 0:9b334a45a8ff 1503 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 0:9b334a45a8ff 1504 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /******************** Bit definition for ADC_JDR3 register ********************/
bogdanm 0:9b334a45a8ff 1507 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 0:9b334a45a8ff 1508 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 0:9b334a45a8ff 1509 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 0:9b334a45a8ff 1510 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 0:9b334a45a8ff 1511 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 0:9b334a45a8ff 1512 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 0:9b334a45a8ff 1513 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 0:9b334a45a8ff 1514 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 0:9b334a45a8ff 1515 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 0:9b334a45a8ff 1516 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 0:9b334a45a8ff 1517 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 0:9b334a45a8ff 1518 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 0:9b334a45a8ff 1519 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 0:9b334a45a8ff 1520 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 0:9b334a45a8ff 1521 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 0:9b334a45a8ff 1522 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 0:9b334a45a8ff 1523 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 0:9b334a45a8ff 1524
bogdanm 0:9b334a45a8ff 1525 /******************** Bit definition for ADC_JDR4 register ********************/
bogdanm 0:9b334a45a8ff 1526 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
bogdanm 0:9b334a45a8ff 1527 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
bogdanm 0:9b334a45a8ff 1528 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
bogdanm 0:9b334a45a8ff 1529 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
bogdanm 0:9b334a45a8ff 1530 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
bogdanm 0:9b334a45a8ff 1531 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
bogdanm 0:9b334a45a8ff 1532 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
bogdanm 0:9b334a45a8ff 1533 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
bogdanm 0:9b334a45a8ff 1534 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
bogdanm 0:9b334a45a8ff 1535 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
bogdanm 0:9b334a45a8ff 1536 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
bogdanm 0:9b334a45a8ff 1537 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
bogdanm 0:9b334a45a8ff 1538 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
bogdanm 0:9b334a45a8ff 1539 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
bogdanm 0:9b334a45a8ff 1540 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
bogdanm 0:9b334a45a8ff 1541 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
bogdanm 0:9b334a45a8ff 1542 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
bogdanm 0:9b334a45a8ff 1543
bogdanm 0:9b334a45a8ff 1544 /******************** Bit definition for ADC_AWD2CR register ********************/
bogdanm 0:9b334a45a8ff 1545 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
bogdanm 0:9b334a45a8ff 1546 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
bogdanm 0:9b334a45a8ff 1547 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
bogdanm 0:9b334a45a8ff 1548 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
bogdanm 0:9b334a45a8ff 1549 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
bogdanm 0:9b334a45a8ff 1550 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
bogdanm 0:9b334a45a8ff 1551 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
bogdanm 0:9b334a45a8ff 1552 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
bogdanm 0:9b334a45a8ff 1553 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
bogdanm 0:9b334a45a8ff 1554 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
bogdanm 0:9b334a45a8ff 1555 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
bogdanm 0:9b334a45a8ff 1556 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
bogdanm 0:9b334a45a8ff 1557 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
bogdanm 0:9b334a45a8ff 1558 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
bogdanm 0:9b334a45a8ff 1559 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
bogdanm 0:9b334a45a8ff 1560 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
bogdanm 0:9b334a45a8ff 1561 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
bogdanm 0:9b334a45a8ff 1562 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
bogdanm 0:9b334a45a8ff 1563 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
bogdanm 0:9b334a45a8ff 1564
bogdanm 0:9b334a45a8ff 1565 /******************** Bit definition for ADC_AWD3CR register ********************/
bogdanm 0:9b334a45a8ff 1566 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
bogdanm 0:9b334a45a8ff 1567 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
bogdanm 0:9b334a45a8ff 1568 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
bogdanm 0:9b334a45a8ff 1569 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
bogdanm 0:9b334a45a8ff 1570 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
bogdanm 0:9b334a45a8ff 1571 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
bogdanm 0:9b334a45a8ff 1572 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
bogdanm 0:9b334a45a8ff 1573 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
bogdanm 0:9b334a45a8ff 1574 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
bogdanm 0:9b334a45a8ff 1575 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
bogdanm 0:9b334a45a8ff 1576 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
bogdanm 0:9b334a45a8ff 1577 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
bogdanm 0:9b334a45a8ff 1578 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
bogdanm 0:9b334a45a8ff 1579 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
bogdanm 0:9b334a45a8ff 1580 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
bogdanm 0:9b334a45a8ff 1581 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
bogdanm 0:9b334a45a8ff 1582 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
bogdanm 0:9b334a45a8ff 1583 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
bogdanm 0:9b334a45a8ff 1584 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
bogdanm 0:9b334a45a8ff 1585
bogdanm 0:9b334a45a8ff 1586 /******************** Bit definition for ADC_DIFSEL register ********************/
bogdanm 0:9b334a45a8ff 1587 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
bogdanm 0:9b334a45a8ff 1588 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
bogdanm 0:9b334a45a8ff 1589 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
bogdanm 0:9b334a45a8ff 1590 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
bogdanm 0:9b334a45a8ff 1591 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
bogdanm 0:9b334a45a8ff 1592 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
bogdanm 0:9b334a45a8ff 1593 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
bogdanm 0:9b334a45a8ff 1594 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
bogdanm 0:9b334a45a8ff 1595 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
bogdanm 0:9b334a45a8ff 1596 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
bogdanm 0:9b334a45a8ff 1597 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
bogdanm 0:9b334a45a8ff 1598 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
bogdanm 0:9b334a45a8ff 1599 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
bogdanm 0:9b334a45a8ff 1600 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
bogdanm 0:9b334a45a8ff 1601 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
bogdanm 0:9b334a45a8ff 1602 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
bogdanm 0:9b334a45a8ff 1603 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
bogdanm 0:9b334a45a8ff 1604 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
bogdanm 0:9b334a45a8ff 1605 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
bogdanm 0:9b334a45a8ff 1606
bogdanm 0:9b334a45a8ff 1607 /******************** Bit definition for ADC_CALFACT register ********************/
bogdanm 0:9b334a45a8ff 1608 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
bogdanm 0:9b334a45a8ff 1609 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
bogdanm 0:9b334a45a8ff 1610 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
bogdanm 0:9b334a45a8ff 1611 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
bogdanm 0:9b334a45a8ff 1612 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
bogdanm 0:9b334a45a8ff 1613 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
bogdanm 0:9b334a45a8ff 1614 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
bogdanm 0:9b334a45a8ff 1615 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
bogdanm 0:9b334a45a8ff 1616 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
bogdanm 0:9b334a45a8ff 1617 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
bogdanm 0:9b334a45a8ff 1618 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
bogdanm 0:9b334a45a8ff 1619 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
bogdanm 0:9b334a45a8ff 1620 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
bogdanm 0:9b334a45a8ff 1621 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
bogdanm 0:9b334a45a8ff 1622 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
bogdanm 0:9b334a45a8ff 1623 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
bogdanm 0:9b334a45a8ff 1624
bogdanm 0:9b334a45a8ff 1625 /************************* ADC Common registers *****************************/
bogdanm 0:9b334a45a8ff 1626 /******************** Bit definition for ADC12_CSR register ********************/
bogdanm 0:9b334a45a8ff 1627 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
bogdanm 0:9b334a45a8ff 1628 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
bogdanm 0:9b334a45a8ff 1629 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
bogdanm 0:9b334a45a8ff 1630 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
bogdanm 0:9b334a45a8ff 1631 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
bogdanm 0:9b334a45a8ff 1632 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
bogdanm 0:9b334a45a8ff 1633 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
bogdanm 0:9b334a45a8ff 1634 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1635 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1636 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1637 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
bogdanm 0:9b334a45a8ff 1638 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
bogdanm 0:9b334a45a8ff 1639 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1640 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
bogdanm 0:9b334a45a8ff 1641 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1642 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1643 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
bogdanm 0:9b334a45a8ff 1644 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1645 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1646 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1647 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1648 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1649
bogdanm 0:9b334a45a8ff 1650 /******************** Bit definition for ADC34_CSR register ********************/
bogdanm 0:9b334a45a8ff 1651 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
bogdanm 0:9b334a45a8ff 1652 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
bogdanm 0:9b334a45a8ff 1653 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
bogdanm 0:9b334a45a8ff 1654 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
bogdanm 0:9b334a45a8ff 1655 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
bogdanm 0:9b334a45a8ff 1656 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
bogdanm 0:9b334a45a8ff 1657 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
bogdanm 0:9b334a45a8ff 1658 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1659 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1660 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
bogdanm 0:9b334a45a8ff 1661 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
bogdanm 0:9b334a45a8ff 1662 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
bogdanm 0:9b334a45a8ff 1663 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1664 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
bogdanm 0:9b334a45a8ff 1665 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1666 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1667 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
bogdanm 0:9b334a45a8ff 1668 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1669 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1670 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1671 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1672 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
bogdanm 0:9b334a45a8ff 1673
bogdanm 0:9b334a45a8ff 1674 /******************** Bit definition for ADC_CCR register ********************/
bogdanm 0:9b334a45a8ff 1675 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
bogdanm 0:9b334a45a8ff 1676 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
bogdanm 0:9b334a45a8ff 1677 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
bogdanm 0:9b334a45a8ff 1678 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
bogdanm 0:9b334a45a8ff 1679 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
bogdanm 0:9b334a45a8ff 1680 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
bogdanm 0:9b334a45a8ff 1681 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
bogdanm 0:9b334a45a8ff 1682 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
bogdanm 0:9b334a45a8ff 1683 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
bogdanm 0:9b334a45a8ff 1684 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
bogdanm 0:9b334a45a8ff 1685 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
bogdanm 0:9b334a45a8ff 1686 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
bogdanm 0:9b334a45a8ff 1687 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
bogdanm 0:9b334a45a8ff 1688 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
bogdanm 0:9b334a45a8ff 1689 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
bogdanm 0:9b334a45a8ff 1690 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
bogdanm 0:9b334a45a8ff 1691 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
bogdanm 0:9b334a45a8ff 1692 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
bogdanm 0:9b334a45a8ff 1693 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
bogdanm 0:9b334a45a8ff 1694 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
bogdanm 0:9b334a45a8ff 1695 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
bogdanm 0:9b334a45a8ff 1696
bogdanm 0:9b334a45a8ff 1697 /******************** Bit definition for ADC_CDR register ********************/
bogdanm 0:9b334a45a8ff 1698 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
bogdanm 0:9b334a45a8ff 1699 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
bogdanm 0:9b334a45a8ff 1700 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
bogdanm 0:9b334a45a8ff 1701 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
bogdanm 0:9b334a45a8ff 1702 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
bogdanm 0:9b334a45a8ff 1703 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
bogdanm 0:9b334a45a8ff 1704 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
bogdanm 0:9b334a45a8ff 1705 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
bogdanm 0:9b334a45a8ff 1706 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
bogdanm 0:9b334a45a8ff 1707 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
bogdanm 0:9b334a45a8ff 1708 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
bogdanm 0:9b334a45a8ff 1709 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
bogdanm 0:9b334a45a8ff 1710 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
bogdanm 0:9b334a45a8ff 1711 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
bogdanm 0:9b334a45a8ff 1712 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
bogdanm 0:9b334a45a8ff 1713 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
bogdanm 0:9b334a45a8ff 1714 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
bogdanm 0:9b334a45a8ff 1715
bogdanm 0:9b334a45a8ff 1716 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
bogdanm 0:9b334a45a8ff 1717 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
bogdanm 0:9b334a45a8ff 1718 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
bogdanm 0:9b334a45a8ff 1719 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
bogdanm 0:9b334a45a8ff 1720 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
bogdanm 0:9b334a45a8ff 1721 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
bogdanm 0:9b334a45a8ff 1722 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
bogdanm 0:9b334a45a8ff 1723 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
bogdanm 0:9b334a45a8ff 1724 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
bogdanm 0:9b334a45a8ff 1725 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
bogdanm 0:9b334a45a8ff 1726 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
bogdanm 0:9b334a45a8ff 1727 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
bogdanm 0:9b334a45a8ff 1728 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
bogdanm 0:9b334a45a8ff 1729 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
bogdanm 0:9b334a45a8ff 1730 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
bogdanm 0:9b334a45a8ff 1731 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
bogdanm 0:9b334a45a8ff 1732 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
bogdanm 0:9b334a45a8ff 1733
bogdanm 0:9b334a45a8ff 1734 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1735 /* */
bogdanm 0:9b334a45a8ff 1736 /* Analog Comparators (COMP) */
bogdanm 0:9b334a45a8ff 1737 /* */
bogdanm 0:9b334a45a8ff 1738 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1739 /********************** Bit definition for COMP2_CSR register ***************/
bogdanm 0:9b334a45a8ff 1740 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
bogdanm 0:9b334a45a8ff 1741 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
bogdanm 0:9b334a45a8ff 1742 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 1743 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 1744 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 1745 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
bogdanm 0:9b334a45a8ff 1746 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
bogdanm 0:9b334a45a8ff 1747 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
bogdanm 0:9b334a45a8ff 1748 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
bogdanm 0:9b334a45a8ff 1749 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
bogdanm 0:9b334a45a8ff 1750 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
bogdanm 0:9b334a45a8ff 1751 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
bogdanm 0:9b334a45a8ff 1752 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
bogdanm 0:9b334a45a8ff 1753 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
bogdanm 0:9b334a45a8ff 1754 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
bogdanm 0:9b334a45a8ff 1755 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
bogdanm 0:9b334a45a8ff 1756 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
bogdanm 0:9b334a45a8ff 1757 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
bogdanm 0:9b334a45a8ff 1758
bogdanm 0:9b334a45a8ff 1759 /********************** Bit definition for COMP4_CSR register ***************/
bogdanm 0:9b334a45a8ff 1760 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
bogdanm 0:9b334a45a8ff 1761 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
bogdanm 0:9b334a45a8ff 1762 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 1763 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 1764 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 1765 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
bogdanm 0:9b334a45a8ff 1766 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
bogdanm 0:9b334a45a8ff 1767 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
bogdanm 0:9b334a45a8ff 1768 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
bogdanm 0:9b334a45a8ff 1769 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
bogdanm 0:9b334a45a8ff 1770 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
bogdanm 0:9b334a45a8ff 1771 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
bogdanm 0:9b334a45a8ff 1772 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
bogdanm 0:9b334a45a8ff 1773 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
bogdanm 0:9b334a45a8ff 1774 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
bogdanm 0:9b334a45a8ff 1775 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
bogdanm 0:9b334a45a8ff 1776 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
bogdanm 0:9b334a45a8ff 1777 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /********************** Bit definition for COMP6_CSR register ***************/
bogdanm 0:9b334a45a8ff 1780 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
bogdanm 0:9b334a45a8ff 1781 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
bogdanm 0:9b334a45a8ff 1782 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 1783 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 1784 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 1785 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
bogdanm 0:9b334a45a8ff 1786 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
bogdanm 0:9b334a45a8ff 1787 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
bogdanm 0:9b334a45a8ff 1788 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
bogdanm 0:9b334a45a8ff 1789 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
bogdanm 0:9b334a45a8ff 1790 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
bogdanm 0:9b334a45a8ff 1791 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
bogdanm 0:9b334a45a8ff 1792 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
bogdanm 0:9b334a45a8ff 1793 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
bogdanm 0:9b334a45a8ff 1794 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
bogdanm 0:9b334a45a8ff 1795 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
bogdanm 0:9b334a45a8ff 1796 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
bogdanm 0:9b334a45a8ff 1797 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
bogdanm 0:9b334a45a8ff 1798
bogdanm 0:9b334a45a8ff 1799 /********************** Bit definition for COMP_CSR register ****************/
bogdanm 0:9b334a45a8ff 1800 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
bogdanm 0:9b334a45a8ff 1801 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
bogdanm 0:9b334a45a8ff 1802 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 1803 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 1804 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 1805 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
bogdanm 0:9b334a45a8ff 1806 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
bogdanm 0:9b334a45a8ff 1807 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
bogdanm 0:9b334a45a8ff 1808 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
bogdanm 0:9b334a45a8ff 1809 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
bogdanm 0:9b334a45a8ff 1810 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
bogdanm 0:9b334a45a8ff 1811 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
bogdanm 0:9b334a45a8ff 1812 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
bogdanm 0:9b334a45a8ff 1813 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
bogdanm 0:9b334a45a8ff 1814 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
bogdanm 0:9b334a45a8ff 1815 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
bogdanm 0:9b334a45a8ff 1816 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
bogdanm 0:9b334a45a8ff 1817 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
bogdanm 0:9b334a45a8ff 1818
bogdanm 0:9b334a45a8ff 1819 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1820 /* */
bogdanm 0:9b334a45a8ff 1821 /* Operational Amplifier (OPAMP) */
bogdanm 0:9b334a45a8ff 1822 /* */
bogdanm 0:9b334a45a8ff 1823 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1824 /********************* Bit definition for OPAMP2_CSR register ***************/
bogdanm 0:9b334a45a8ff 1825 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
bogdanm 0:9b334a45a8ff 1826 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 0:9b334a45a8ff 1827 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 0:9b334a45a8ff 1828 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1829 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1830 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 0:9b334a45a8ff 1831 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1832 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1833 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 0:9b334a45a8ff 1834 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 0:9b334a45a8ff 1835 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 0:9b334a45a8ff 1836 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1837 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1838 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 0:9b334a45a8ff 1839 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 0:9b334a45a8ff 1840 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1841 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1842 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 0:9b334a45a8ff 1843 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1844 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1845 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 1846 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 1847 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 0:9b334a45a8ff 1848 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 0:9b334a45a8ff 1849 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 0:9b334a45a8ff 1850 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 0:9b334a45a8ff 1851 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
bogdanm 0:9b334a45a8ff 1852 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 0:9b334a45a8ff 1853
bogdanm 0:9b334a45a8ff 1854 /********************* Bit definition for OPAMPx_CSR register ***************/
bogdanm 0:9b334a45a8ff 1855 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
bogdanm 0:9b334a45a8ff 1856 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
bogdanm 0:9b334a45a8ff 1857 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
bogdanm 0:9b334a45a8ff 1858 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1859 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1860 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
bogdanm 0:9b334a45a8ff 1861 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1862 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1863 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
bogdanm 0:9b334a45a8ff 1864 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
bogdanm 0:9b334a45a8ff 1865 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
bogdanm 0:9b334a45a8ff 1866 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1867 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1868 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
bogdanm 0:9b334a45a8ff 1869 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
bogdanm 0:9b334a45a8ff 1870 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1871 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1872 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
bogdanm 0:9b334a45a8ff 1873 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 1874 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 1875 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 1876 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 1877 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
bogdanm 0:9b334a45a8ff 1878 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
bogdanm 0:9b334a45a8ff 1879 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
bogdanm 0:9b334a45a8ff 1880 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
bogdanm 0:9b334a45a8ff 1881 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
bogdanm 0:9b334a45a8ff 1882 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
bogdanm 0:9b334a45a8ff 1883
bogdanm 0:9b334a45a8ff 1884 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1885 /* */
bogdanm 0:9b334a45a8ff 1886 /* Controller Area Network (CAN ) */
bogdanm 0:9b334a45a8ff 1887 /* */
bogdanm 0:9b334a45a8ff 1888 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1889 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 0:9b334a45a8ff 1890 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
bogdanm 0:9b334a45a8ff 1891 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
bogdanm 0:9b334a45a8ff 1892 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
bogdanm 0:9b334a45a8ff 1893 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
bogdanm 0:9b334a45a8ff 1894 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
bogdanm 0:9b334a45a8ff 1895 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
bogdanm 0:9b334a45a8ff 1896 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
bogdanm 0:9b334a45a8ff 1897 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
bogdanm 0:9b334a45a8ff 1898 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
bogdanm 0:9b334a45a8ff 1899
bogdanm 0:9b334a45a8ff 1900 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 0:9b334a45a8ff 1901 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
bogdanm 0:9b334a45a8ff 1902 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
bogdanm 0:9b334a45a8ff 1903 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
bogdanm 0:9b334a45a8ff 1904 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 1905 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
bogdanm 0:9b334a45a8ff 1906 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
bogdanm 0:9b334a45a8ff 1907 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
bogdanm 0:9b334a45a8ff 1908 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
bogdanm 0:9b334a45a8ff 1909 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
bogdanm 0:9b334a45a8ff 1910
bogdanm 0:9b334a45a8ff 1911 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 0:9b334a45a8ff 1912 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 0:9b334a45a8ff 1913 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 0:9b334a45a8ff 1914 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 0:9b334a45a8ff 1915 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 0:9b334a45a8ff 1916 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 0:9b334a45a8ff 1917 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 0:9b334a45a8ff 1918 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 0:9b334a45a8ff 1919 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 0:9b334a45a8ff 1920 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 0:9b334a45a8ff 1921 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 0:9b334a45a8ff 1922 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 0:9b334a45a8ff 1923 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 0:9b334a45a8ff 1924 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 0:9b334a45a8ff 1925 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 0:9b334a45a8ff 1926 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 0:9b334a45a8ff 1927 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 0:9b334a45a8ff 1928
bogdanm 0:9b334a45a8ff 1929 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 0:9b334a45a8ff 1930 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 0:9b334a45a8ff 1931 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 0:9b334a45a8ff 1932 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 0:9b334a45a8ff 1933
bogdanm 0:9b334a45a8ff 1934 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 0:9b334a45a8ff 1935 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 0:9b334a45a8ff 1936 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 0:9b334a45a8ff 1937 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 0:9b334a45a8ff 1938
bogdanm 0:9b334a45a8ff 1939 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 0:9b334a45a8ff 1940 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
bogdanm 0:9b334a45a8ff 1941 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
bogdanm 0:9b334a45a8ff 1942 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
bogdanm 0:9b334a45a8ff 1943 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
bogdanm 0:9b334a45a8ff 1944
bogdanm 0:9b334a45a8ff 1945 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 0:9b334a45a8ff 1946 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
bogdanm 0:9b334a45a8ff 1947 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
bogdanm 0:9b334a45a8ff 1948 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
bogdanm 0:9b334a45a8ff 1949 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
bogdanm 0:9b334a45a8ff 1950
bogdanm 0:9b334a45a8ff 1951 /******************** Bit definition for CAN_IER register *******************/
bogdanm 0:9b334a45a8ff 1952 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 1953 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 1954 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 1955 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 1956 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 1957 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 1958 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 1959 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 0:9b334a45a8ff 1960 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 0:9b334a45a8ff 1961 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 0:9b334a45a8ff 1962 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 0:9b334a45a8ff 1963 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 1964 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 0:9b334a45a8ff 1965 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 0:9b334a45a8ff 1966
bogdanm 0:9b334a45a8ff 1967 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 0:9b334a45a8ff 1968 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 0:9b334a45a8ff 1969 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 0:9b334a45a8ff 1970 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 0:9b334a45a8ff 1971
bogdanm 0:9b334a45a8ff 1972 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 0:9b334a45a8ff 1973 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1974 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1975 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1976
bogdanm 0:9b334a45a8ff 1977 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 0:9b334a45a8ff 1978 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 0:9b334a45a8ff 1979
bogdanm 0:9b334a45a8ff 1980 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 0:9b334a45a8ff 1981 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 0:9b334a45a8ff 1982 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 0:9b334a45a8ff 1983 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
bogdanm 0:9b334a45a8ff 1984 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
bogdanm 0:9b334a45a8ff 1985 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
bogdanm 0:9b334a45a8ff 1986 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
bogdanm 0:9b334a45a8ff 1987 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 0:9b334a45a8ff 1988 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
bogdanm 0:9b334a45a8ff 1989 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
bogdanm 0:9b334a45a8ff 1990 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
bogdanm 0:9b334a45a8ff 1991 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 0:9b334a45a8ff 1992 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
bogdanm 0:9b334a45a8ff 1993 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
bogdanm 0:9b334a45a8ff 1994 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 0:9b334a45a8ff 1995 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 0:9b334a45a8ff 1996
bogdanm 0:9b334a45a8ff 1997 /*!<Mailbox registers */
bogdanm 0:9b334a45a8ff 1998 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 0:9b334a45a8ff 1999 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 2000 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 2001 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 2002 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 2003 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 2004
bogdanm 0:9b334a45a8ff 2005 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 0:9b334a45a8ff 2006 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 2007 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 2008 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 2009
bogdanm 0:9b334a45a8ff 2010 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 0:9b334a45a8ff 2011 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 2012 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 2013 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 2014 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 2015
bogdanm 0:9b334a45a8ff 2016 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 0:9b334a45a8ff 2017 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 2018 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 2019 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 2020 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 2021
bogdanm 0:9b334a45a8ff 2022 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 0:9b334a45a8ff 2023 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 2024 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 2025 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 2026 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 2027 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 2028
bogdanm 0:9b334a45a8ff 2029 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 0:9b334a45a8ff 2030 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 2031 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 2032 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 2033
bogdanm 0:9b334a45a8ff 2034 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 0:9b334a45a8ff 2035 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 2036 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 2037 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 2038 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 2039
bogdanm 0:9b334a45a8ff 2040 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 0:9b334a45a8ff 2041 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 2042 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 2043 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 2044 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 2045
bogdanm 0:9b334a45a8ff 2046 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 0:9b334a45a8ff 2047 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 2048 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 2049 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 2050 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 2051 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 2052
bogdanm 0:9b334a45a8ff 2053 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 0:9b334a45a8ff 2054 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 2055 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 2056 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 2057
bogdanm 0:9b334a45a8ff 2058 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 0:9b334a45a8ff 2059 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 2060 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 2061 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 2062 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 2063
bogdanm 0:9b334a45a8ff 2064 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 0:9b334a45a8ff 2065 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 2066 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 2067 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 2068 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 2069
bogdanm 0:9b334a45a8ff 2070 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 0:9b334a45a8ff 2071 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 2072 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 2073 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 2074 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 2075
bogdanm 0:9b334a45a8ff 2076 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 0:9b334a45a8ff 2077 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 2078 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 2079 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 2080
bogdanm 0:9b334a45a8ff 2081 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 0:9b334a45a8ff 2082 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 2083 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 2084 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 2085 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 2086
bogdanm 0:9b334a45a8ff 2087 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 0:9b334a45a8ff 2088 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 2089 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 2090 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 2091 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 2092
bogdanm 0:9b334a45a8ff 2093 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 0:9b334a45a8ff 2094 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 2095 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 2096 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 2097 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 2098
bogdanm 0:9b334a45a8ff 2099 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 0:9b334a45a8ff 2100 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 2101 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 2102 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 2103
bogdanm 0:9b334a45a8ff 2104 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 0:9b334a45a8ff 2105 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 2106 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 2107 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 2108 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 2109
bogdanm 0:9b334a45a8ff 2110 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 0:9b334a45a8ff 2111 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 2112 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 2113 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 2114 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 2115
bogdanm 0:9b334a45a8ff 2116 /*!<CAN filter registers */
bogdanm 0:9b334a45a8ff 2117 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 0:9b334a45a8ff 2118 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
bogdanm 0:9b334a45a8ff 2119
bogdanm 0:9b334a45a8ff 2120 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 0:9b334a45a8ff 2121 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
bogdanm 0:9b334a45a8ff 2122 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
bogdanm 0:9b334a45a8ff 2123 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
bogdanm 0:9b334a45a8ff 2124 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
bogdanm 0:9b334a45a8ff 2125 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
bogdanm 0:9b334a45a8ff 2126 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
bogdanm 0:9b334a45a8ff 2127 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
bogdanm 0:9b334a45a8ff 2128 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
bogdanm 0:9b334a45a8ff 2129 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
bogdanm 0:9b334a45a8ff 2130 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
bogdanm 0:9b334a45a8ff 2131 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
bogdanm 0:9b334a45a8ff 2132 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
bogdanm 0:9b334a45a8ff 2133 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
bogdanm 0:9b334a45a8ff 2134 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
bogdanm 0:9b334a45a8ff 2135 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
bogdanm 0:9b334a45a8ff 2136
bogdanm 0:9b334a45a8ff 2137 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 0:9b334a45a8ff 2138 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
bogdanm 0:9b334a45a8ff 2139 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
bogdanm 0:9b334a45a8ff 2140 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
bogdanm 0:9b334a45a8ff 2141 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
bogdanm 0:9b334a45a8ff 2142 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
bogdanm 0:9b334a45a8ff 2143 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
bogdanm 0:9b334a45a8ff 2144 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
bogdanm 0:9b334a45a8ff 2145 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
bogdanm 0:9b334a45a8ff 2146 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
bogdanm 0:9b334a45a8ff 2147 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
bogdanm 0:9b334a45a8ff 2148 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
bogdanm 0:9b334a45a8ff 2149 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
bogdanm 0:9b334a45a8ff 2150 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
bogdanm 0:9b334a45a8ff 2151 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
bogdanm 0:9b334a45a8ff 2152 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
bogdanm 0:9b334a45a8ff 2153
bogdanm 0:9b334a45a8ff 2154 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 0:9b334a45a8ff 2155 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
bogdanm 0:9b334a45a8ff 2156 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
bogdanm 0:9b334a45a8ff 2157 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
bogdanm 0:9b334a45a8ff 2158 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
bogdanm 0:9b334a45a8ff 2159 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
bogdanm 0:9b334a45a8ff 2160 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
bogdanm 0:9b334a45a8ff 2161 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
bogdanm 0:9b334a45a8ff 2162 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
bogdanm 0:9b334a45a8ff 2163 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
bogdanm 0:9b334a45a8ff 2164 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
bogdanm 0:9b334a45a8ff 2165 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
bogdanm 0:9b334a45a8ff 2166 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
bogdanm 0:9b334a45a8ff 2167 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
bogdanm 0:9b334a45a8ff 2168 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
bogdanm 0:9b334a45a8ff 2169 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 0:9b334a45a8ff 2170
bogdanm 0:9b334a45a8ff 2171 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 0:9b334a45a8ff 2172 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
bogdanm 0:9b334a45a8ff 2173 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
bogdanm 0:9b334a45a8ff 2174 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
bogdanm 0:9b334a45a8ff 2175 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
bogdanm 0:9b334a45a8ff 2176 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
bogdanm 0:9b334a45a8ff 2177 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
bogdanm 0:9b334a45a8ff 2178 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
bogdanm 0:9b334a45a8ff 2179 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
bogdanm 0:9b334a45a8ff 2180 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
bogdanm 0:9b334a45a8ff 2181 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
bogdanm 0:9b334a45a8ff 2182 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
bogdanm 0:9b334a45a8ff 2183 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
bogdanm 0:9b334a45a8ff 2184 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
bogdanm 0:9b334a45a8ff 2185 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
bogdanm 0:9b334a45a8ff 2186 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
bogdanm 0:9b334a45a8ff 2187
bogdanm 0:9b334a45a8ff 2188 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 0:9b334a45a8ff 2189 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2190 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2191 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2192 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2193 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2194 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2195 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2196 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2197 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2198 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2199 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2200 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2201 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2202 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2203 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2204 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2205 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2206 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2207 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2208 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2209 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2210 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2211 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2212 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2213 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2214 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2215 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2216 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2217 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2218 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2219 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2220 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2221
bogdanm 0:9b334a45a8ff 2222 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 0:9b334a45a8ff 2223 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2224 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2225 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2226 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2227 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2228 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2229 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2230 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2231 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2232 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2233 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2234 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2235 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2236 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2237 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2238 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2239 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2240 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2241 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2242 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2243 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2244 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2245 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2246 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2247 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2248 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2249 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2250 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2251 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2252 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2253 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2254 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2255
bogdanm 0:9b334a45a8ff 2256 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 0:9b334a45a8ff 2257 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2258 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2259 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2260 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2261 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2262 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2263 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2264 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2265 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2266 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2267 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2268 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2269 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2270 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2271 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2272 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2273 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2274 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2275 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2276 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2277 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2278 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2279 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2280 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2281 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2282 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2283 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2284 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2285 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2286 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2287 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2288 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2289
bogdanm 0:9b334a45a8ff 2290 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 0:9b334a45a8ff 2291 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2292 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2293 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2294 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2295 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2296 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2297 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2298 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2299 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2300 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2301 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2302 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2303 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2304 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2305 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2306 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2307 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2308 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2309 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2310 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2311 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2312 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2313 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2314 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2315 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2316 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2317 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2318 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2319 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2320 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2321 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2322 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2323
bogdanm 0:9b334a45a8ff 2324 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 0:9b334a45a8ff 2325 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2326 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2327 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2328 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2329 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2330 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2331 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2332 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2333 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2334 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2335 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2336 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2337 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2338 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2339 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2340 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2341 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2342 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2343 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2344 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2345 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2346 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2347 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2348 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2349 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2350 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2351 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2352 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2353 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2354 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2355 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2356 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2357
bogdanm 0:9b334a45a8ff 2358 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 0:9b334a45a8ff 2359 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2360 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2361 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2362 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2363 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2364 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2365 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2366 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2367 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2368 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2369 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2370 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2371 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2372 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2373 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2374 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2375 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2376 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2377 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2378 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2379 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2380 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2381 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2382 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2383 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2384 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2385 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2386 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2387 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2388 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2389 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2390 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2391
bogdanm 0:9b334a45a8ff 2392 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 0:9b334a45a8ff 2393 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2394 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2395 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2396 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2397 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2398 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2399 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2400 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2401 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2402 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2403 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2404 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2405 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2406 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2407 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2408 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2409 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2410 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2411 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2412 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2413 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2414 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2415 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2416 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2417 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2418 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2419 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2420 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2421 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2422 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2423 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2424 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2425
bogdanm 0:9b334a45a8ff 2426 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 0:9b334a45a8ff 2427 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2428 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2429 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2430 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2431 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2432 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2433 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2434 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2435 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2436 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2437 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2438 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2439 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2440 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2441 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2442 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2443 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2444 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2445 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2446 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2447 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2448 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2449 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2450 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2451 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2452 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2453 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2454 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2455 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2456 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2457 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2458 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2459
bogdanm 0:9b334a45a8ff 2460 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 0:9b334a45a8ff 2461 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2462 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2463 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2464 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2465 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2466 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2467 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2468 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2469 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2470 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2471 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2472 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2473 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2474 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2475 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2476 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2477 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2478 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2479 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2480 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2481 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2482 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2483 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2484 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2485 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2486 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2487 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2488 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2489 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2490 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2491 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2492 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2493
bogdanm 0:9b334a45a8ff 2494 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 0:9b334a45a8ff 2495 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2496 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2497 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2498 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2499 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2500 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2501 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2502 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2503 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2504 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2505 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2506 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2507 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2508 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2509 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2510 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2511 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2512 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2513 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2514 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2515 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2516 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2517 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2518 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2519 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2520 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2521 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2522 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2523 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2524 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2525 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2526 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2527
bogdanm 0:9b334a45a8ff 2528 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 0:9b334a45a8ff 2529 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2530 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2531 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2532 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2533 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2534 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2535 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2536 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2537 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2538 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2539 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2540 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2541 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2542 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2543 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2544 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2545 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2546 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2547 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2548 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2549 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2550 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2551 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2552 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2553 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2554 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2555 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2556 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2557 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2558 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2559 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2560 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2561
bogdanm 0:9b334a45a8ff 2562 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 0:9b334a45a8ff 2563 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2564 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2565 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2566 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2567 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2568 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2569 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2570 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2571 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2572 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2573 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2574 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2575 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2576 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2577 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2578 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2579 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2580 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2581 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2582 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2583 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2584 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2585 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2586 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2587 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2588 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2589 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2590 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2591 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2592 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2593 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2594 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2595
bogdanm 0:9b334a45a8ff 2596 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 0:9b334a45a8ff 2597 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2598 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2599 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2600 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2601 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2602 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2603 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2604 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2605 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2606 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2607 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2608 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2609 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2610 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2611 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2612 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2613 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2614 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2615 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2616 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2617 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2618 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2619 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2620 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2621 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2622 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2623 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2624 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2625 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2626 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2627 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2628 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2629
bogdanm 0:9b334a45a8ff 2630 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 0:9b334a45a8ff 2631 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2632 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2633 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2634 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2635 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2636 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2637 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2638 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2639 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2640 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2641 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2642 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2643 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2644 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2645 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2646 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2647 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2648 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2649 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2650 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2651 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2652 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2653 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2654 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2655 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2656 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2657 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2658 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2659 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2660 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2661 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2662 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2663
bogdanm 0:9b334a45a8ff 2664 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 0:9b334a45a8ff 2665 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2666 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2667 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2668 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2669 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2670 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2671 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2672 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2673 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2674 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2675 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2676 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2677 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2678 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2679 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2680 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2681 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2682 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2683 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2684 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2685 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2686 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2687 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2688 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2689 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2690 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2691 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2692 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2693 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2694 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2695 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2696 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2697
bogdanm 0:9b334a45a8ff 2698 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 0:9b334a45a8ff 2699 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2700 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2701 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2702 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2703 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2704 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2705 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2706 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2707 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2708 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2709 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2710 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2711 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2712 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2713 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2714 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2715 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2716 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2717 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2718 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2719 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2720 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2721 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2722 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2723 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2724 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2725 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2726 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2727 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2728 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2729 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2730 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2731
bogdanm 0:9b334a45a8ff 2732 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 0:9b334a45a8ff 2733 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2734 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2735 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2736 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2737 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2738 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2739 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2740 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2741 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2742 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2743 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2744 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2745 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2746 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2747 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2748 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2749 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2750 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2751 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2752 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2753 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2754 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2755 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2756 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2757 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2758 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2759 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2760 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2761 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2762 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2763 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2764 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2765
bogdanm 0:9b334a45a8ff 2766 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 0:9b334a45a8ff 2767 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2768 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2769 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2770 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2771 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2772 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2773 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2774 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2775 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2776 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2777 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2778 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2779 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2780 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2781 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2782 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2783 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2784 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2785 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2786 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2787 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2788 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2789 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2790 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2791 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2792 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2793 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2794 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2795 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2796 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2797 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2798 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2799
bogdanm 0:9b334a45a8ff 2800 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 0:9b334a45a8ff 2801 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2802 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2803 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2804 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2805 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2806 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2807 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2808 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2809 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2810 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2811 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2812 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2813 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2814 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2815 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2816 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2817 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2818 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2819 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2820 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2821 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2822 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2823 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2824 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2825 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2826 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2827 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2828 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2829 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2830 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2831 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2832 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2833
bogdanm 0:9b334a45a8ff 2834 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 0:9b334a45a8ff 2835 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2836 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2837 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2838 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2839 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2840 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2841 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2842 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2843 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2844 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2845 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2846 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2847 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2848 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2849 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2850 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2851 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2852 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2853 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2854 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2855 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2856 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2857 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2858 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2859 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2860 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2861 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2862 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2863 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2864 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2865 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2866 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2867
bogdanm 0:9b334a45a8ff 2868 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 0:9b334a45a8ff 2869 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2870 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2871 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2872 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2873 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2874 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2875 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2876 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2877 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2878 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2879 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2880 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2881 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2882 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2883 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2884 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2885 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2886 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2887 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2888 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2889 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2890 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2891 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2892 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2893 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2894 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2895 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2896 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2897 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2898 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2899 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2900 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2901
bogdanm 0:9b334a45a8ff 2902 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 0:9b334a45a8ff 2903 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2904 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2905 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2906 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2907 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2908 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2909 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2910 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2911 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2912 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2913 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2914 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2915 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2916 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2917 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2918 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2919 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2920 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2921 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2922 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2923 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2924 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2925 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2926 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2927 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2928 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2929 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2930 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2931 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2932 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2933 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2934 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2935
bogdanm 0:9b334a45a8ff 2936 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 0:9b334a45a8ff 2937 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2938 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2939 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2940 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2941 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2942 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2943 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2944 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2945 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2946 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2947 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2948 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2949 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2950 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2951 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2952 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2953 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2954 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2955 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2956 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2957 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2958 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2959 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2960 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2961 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2962 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2963 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2964 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2965 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2966 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2967 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2968 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2969
bogdanm 0:9b334a45a8ff 2970 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 0:9b334a45a8ff 2971 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2972 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2973 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2974 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2975 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2976 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2977 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2978 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2979 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2980 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2981 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2982 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2983 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2984 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2985 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2986 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2987 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2988 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2989 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2990 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2991 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2992 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2993 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2994 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2995 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2996 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2997 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2998 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2999 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 3000 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 3001 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 3002 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 3003
bogdanm 0:9b334a45a8ff 3004 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 0:9b334a45a8ff 3005 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 3006 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 3007 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 3008 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 3009 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 3010 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 3011 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 3012 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 3013 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 3014 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 3015 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 3016 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 3017 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 3018 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 3019 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 3020 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 3021 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 3022 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 3023 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 3024 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 3025 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 3026 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 3027 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 3028 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 3029 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 3030 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 3031 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 3032 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 3033 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 3034 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 3035 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 3036 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 3037
bogdanm 0:9b334a45a8ff 3038 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 0:9b334a45a8ff 3039 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 3040 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 3041 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 3042 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 3043 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 3044 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 3045 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 3046 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 3047 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 3048 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 3049 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 3050 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 3051 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 3052 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 3053 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 3054 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 3055 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 3056 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 3057 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 3058 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 3059 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 3060 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 3061 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 3062 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 3063 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 3064 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 3065 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 3066 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 3067 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 3068 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 3069 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 3070 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 3071
bogdanm 0:9b334a45a8ff 3072 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 0:9b334a45a8ff 3073 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 3074 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 3075 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 3076 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 3077 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 3078 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 3079 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 3080 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 3081 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 3082 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 3083 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 3084 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 3085 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 3086 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 3087 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 3088 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 3089 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 3090 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 3091 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 3092 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 3093 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 3094 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 3095 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 3096 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 3097 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 3098 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 3099 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 3100 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 3101 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 3102 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 3103 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 3104 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 3105
bogdanm 0:9b334a45a8ff 3106 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 0:9b334a45a8ff 3107 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 3108 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 3109 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 3110 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 3111 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 3112 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 3113 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 3114 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 3115 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 3116 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 3117 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 3118 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 3119 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 3120 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 3121 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 3122 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 3123 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 3124 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 3125 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 3126 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 3127 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 3128 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 3129 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 3130 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 3131 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 3132 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 3133 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 3134 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 3135 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 3136 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 3137 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 3138 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 3139
bogdanm 0:9b334a45a8ff 3140 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3141 /* */
bogdanm 0:9b334a45a8ff 3142 /* CRC calculation unit (CRC) */
bogdanm 0:9b334a45a8ff 3143 /* */
bogdanm 0:9b334a45a8ff 3144 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3145 /******************* Bit definition for CRC_DR register *********************/
bogdanm 0:9b334a45a8ff 3146 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 0:9b334a45a8ff 3147
bogdanm 0:9b334a45a8ff 3148 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 0:9b334a45a8ff 3149 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 0:9b334a45a8ff 3150
bogdanm 0:9b334a45a8ff 3151 /******************** Bit definition for CRC_CR register ********************/
bogdanm 0:9b334a45a8ff 3152 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
bogdanm 0:9b334a45a8ff 3153 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
bogdanm 0:9b334a45a8ff 3154 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
bogdanm 0:9b334a45a8ff 3155 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
bogdanm 0:9b334a45a8ff 3156 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
bogdanm 0:9b334a45a8ff 3157 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3158 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3159 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
bogdanm 0:9b334a45a8ff 3160
bogdanm 0:9b334a45a8ff 3161 /******************* Bit definition for CRC_INIT register *******************/
bogdanm 0:9b334a45a8ff 3162 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
bogdanm 0:9b334a45a8ff 3163
bogdanm 0:9b334a45a8ff 3164 /******************* Bit definition for CRC_POL register ********************/
bogdanm 0:9b334a45a8ff 3165 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
bogdanm 0:9b334a45a8ff 3166
bogdanm 0:9b334a45a8ff 3167 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3168 /* */
bogdanm 0:9b334a45a8ff 3169 /* Digital to Analog Converter (DAC) */
bogdanm 0:9b334a45a8ff 3170 /* */
bogdanm 0:9b334a45a8ff 3171 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3172 /******************** Bit definition for DAC_CR register ********************/
bogdanm 0:9b334a45a8ff 3173 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
bogdanm 0:9b334a45a8ff 3174 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
bogdanm 0:9b334a45a8ff 3175 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
bogdanm 0:9b334a45a8ff 3176
bogdanm 0:9b334a45a8ff 3177 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 0:9b334a45a8ff 3178 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3179 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3180 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3181
bogdanm 0:9b334a45a8ff 3182 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 3183 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3184 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3185
bogdanm 0:9b334a45a8ff 3186 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 3187 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3188 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3189 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3190 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3191
bogdanm 0:9b334a45a8ff 3192 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
bogdanm 0:9b334a45a8ff 3193 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
bogdanm 0:9b334a45a8ff 3194 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
bogdanm 0:9b334a45a8ff 3195 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
bogdanm 0:9b334a45a8ff 3196 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
bogdanm 0:9b334a45a8ff 3197
bogdanm 0:9b334a45a8ff 3198 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 0:9b334a45a8ff 3199 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3200 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3201 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3202
bogdanm 0:9b334a45a8ff 3203 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 3204 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3205 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3206
bogdanm 0:9b334a45a8ff 3207 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 3208 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3209 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3210 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3211 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3212
bogdanm 0:9b334a45a8ff 3213 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
bogdanm 0:9b334a45a8ff 3214 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
bogdanm 0:9b334a45a8ff 3215
bogdanm 0:9b334a45a8ff 3216 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 0:9b334a45a8ff 3217 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
bogdanm 0:9b334a45a8ff 3218 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
bogdanm 0:9b334a45a8ff 3219
bogdanm 0:9b334a45a8ff 3220 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 0:9b334a45a8ff 3221 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3222
bogdanm 0:9b334a45a8ff 3223 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 0:9b334a45a8ff 3224 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3225
bogdanm 0:9b334a45a8ff 3226 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 0:9b334a45a8ff 3227 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3228
bogdanm 0:9b334a45a8ff 3229 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 0:9b334a45a8ff 3230 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3231
bogdanm 0:9b334a45a8ff 3232 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 0:9b334a45a8ff 3233 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3234
bogdanm 0:9b334a45a8ff 3235 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 0:9b334a45a8ff 3236 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3237
bogdanm 0:9b334a45a8ff 3238 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 0:9b334a45a8ff 3239 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3240 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3241
bogdanm 0:9b334a45a8ff 3242 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 0:9b334a45a8ff 3243 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3244 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3245
bogdanm 0:9b334a45a8ff 3246 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 0:9b334a45a8ff 3247 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3248 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3249
bogdanm 0:9b334a45a8ff 3250 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 0:9b334a45a8ff 3251 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
bogdanm 0:9b334a45a8ff 3252
bogdanm 0:9b334a45a8ff 3253 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 0:9b334a45a8ff 3254 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
bogdanm 0:9b334a45a8ff 3255
bogdanm 0:9b334a45a8ff 3256 /******************** Bit definition for DAC_SR register ********************/
bogdanm 0:9b334a45a8ff 3257 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
bogdanm 0:9b334a45a8ff 3258 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
bogdanm 0:9b334a45a8ff 3259
bogdanm 0:9b334a45a8ff 3260 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3261 /* */
bogdanm 0:9b334a45a8ff 3262 /* Debug MCU (DBGMCU) */
bogdanm 0:9b334a45a8ff 3263 /* */
bogdanm 0:9b334a45a8ff 3264 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3265 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 0:9b334a45a8ff 3266 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 0:9b334a45a8ff 3267 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 0:9b334a45a8ff 3268
bogdanm 0:9b334a45a8ff 3269 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 0:9b334a45a8ff 3270 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3271 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3272 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3273 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3274
bogdanm 0:9b334a45a8ff 3275 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3276 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3277 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3278
bogdanm 0:9b334a45a8ff 3279 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 0:9b334a45a8ff 3280 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3281 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3282 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3283 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3284 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3285 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3286 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3287 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3288 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3289
bogdanm 0:9b334a45a8ff 3290 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 0:9b334a45a8ff 3291 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3292 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3293 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3294 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3295 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3296
bogdanm 0:9b334a45a8ff 3297 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3298 /* */
bogdanm 0:9b334a45a8ff 3299 /* DMA Controller (DMA) */
bogdanm 0:9b334a45a8ff 3300 /* */
bogdanm 0:9b334a45a8ff 3301 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3302 /******************* Bit definition for DMA_ISR register ********************/
bogdanm 0:9b334a45a8ff 3303 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3304 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3305 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3306 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3307 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3308 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3309 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3310 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3311 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3312 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3313 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3314 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3315 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3316 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3317 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3318 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3319 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3320 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3321 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3322 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3323 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3324 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3325 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3326 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3327 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
bogdanm 0:9b334a45a8ff 3328 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 3329 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
bogdanm 0:9b334a45a8ff 3330 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
bogdanm 0:9b334a45a8ff 3331
bogdanm 0:9b334a45a8ff 3332 /******************* Bit definition for DMA_IFCR register *******************/
bogdanm 0:9b334a45a8ff 3333 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3334 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3335 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3336 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3337 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3338 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3339 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3340 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3341 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3342 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3343 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3344 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3345 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3346 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3347 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3348 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3349 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3350 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3351 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3352 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3353 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3354 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3355 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3356 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3357 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
bogdanm 0:9b334a45a8ff 3358 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 3359 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
bogdanm 0:9b334a45a8ff 3360 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
bogdanm 0:9b334a45a8ff 3361
bogdanm 0:9b334a45a8ff 3362 /******************* Bit definition for DMA_CCR register ********************/
bogdanm 0:9b334a45a8ff 3363 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
bogdanm 0:9b334a45a8ff 3364 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
bogdanm 0:9b334a45a8ff 3365 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
bogdanm 0:9b334a45a8ff 3366 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
bogdanm 0:9b334a45a8ff 3367 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
bogdanm 0:9b334a45a8ff 3368 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
bogdanm 0:9b334a45a8ff 3369 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
bogdanm 0:9b334a45a8ff 3370 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
bogdanm 0:9b334a45a8ff 3371
bogdanm 0:9b334a45a8ff 3372 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 0:9b334a45a8ff 3373 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3374 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3375
bogdanm 0:9b334a45a8ff 3376 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 0:9b334a45a8ff 3377 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3378 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3379
bogdanm 0:9b334a45a8ff 3380 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
bogdanm 0:9b334a45a8ff 3381 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3382 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3383
bogdanm 0:9b334a45a8ff 3384 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
bogdanm 0:9b334a45a8ff 3385
bogdanm 0:9b334a45a8ff 3386 /****************** Bit definition for DMA_CNDTR register *******************/
bogdanm 0:9b334a45a8ff 3387 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
bogdanm 0:9b334a45a8ff 3388
bogdanm 0:9b334a45a8ff 3389 /****************** Bit definition for DMA_CPAR register ********************/
bogdanm 0:9b334a45a8ff 3390 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 0:9b334a45a8ff 3391
bogdanm 0:9b334a45a8ff 3392 /****************** Bit definition for DMA_CMAR register ********************/
bogdanm 0:9b334a45a8ff 3393 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 0:9b334a45a8ff 3394
bogdanm 0:9b334a45a8ff 3395 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3396 /* */
bogdanm 0:9b334a45a8ff 3397 /* External Interrupt/Event Controller (EXTI) */
bogdanm 0:9b334a45a8ff 3398 /* */
bogdanm 0:9b334a45a8ff 3399 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3400 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
bogdanm 0:9b334a45a8ff 3401 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 0:9b334a45a8ff 3402 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 0:9b334a45a8ff 3403 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 0:9b334a45a8ff 3404 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 0:9b334a45a8ff 3405 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 0:9b334a45a8ff 3406 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 0:9b334a45a8ff 3407 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 0:9b334a45a8ff 3408 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 0:9b334a45a8ff 3409 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 0:9b334a45a8ff 3410 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 0:9b334a45a8ff 3411 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 0:9b334a45a8ff 3412 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 0:9b334a45a8ff 3413 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 0:9b334a45a8ff 3414 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 0:9b334a45a8ff 3415 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 0:9b334a45a8ff 3416 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 0:9b334a45a8ff 3417 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 0:9b334a45a8ff 3418 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 0:9b334a45a8ff 3419 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 0:9b334a45a8ff 3420 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 0:9b334a45a8ff 3421 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
bogdanm 0:9b334a45a8ff 3422 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
bogdanm 0:9b334a45a8ff 3423 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
bogdanm 0:9b334a45a8ff 3424 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
bogdanm 0:9b334a45a8ff 3425 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
bogdanm 0:9b334a45a8ff 3426 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
bogdanm 0:9b334a45a8ff 3427 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
bogdanm 0:9b334a45a8ff 3428 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
bogdanm 0:9b334a45a8ff 3429 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
bogdanm 0:9b334a45a8ff 3430
bogdanm 0:9b334a45a8ff 3431 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
bogdanm 0:9b334a45a8ff 3432 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 0:9b334a45a8ff 3433 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 0:9b334a45a8ff 3434 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 0:9b334a45a8ff 3435 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 0:9b334a45a8ff 3436 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 0:9b334a45a8ff 3437 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 0:9b334a45a8ff 3438 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 0:9b334a45a8ff 3439 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 0:9b334a45a8ff 3440 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 0:9b334a45a8ff 3441 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 0:9b334a45a8ff 3442 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 0:9b334a45a8ff 3443 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 0:9b334a45a8ff 3444 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 0:9b334a45a8ff 3445 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 0:9b334a45a8ff 3446 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 0:9b334a45a8ff 3447 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 0:9b334a45a8ff 3448 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 0:9b334a45a8ff 3449 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 0:9b334a45a8ff 3450 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 0:9b334a45a8ff 3451 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 0:9b334a45a8ff 3452 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
bogdanm 0:9b334a45a8ff 3453 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
bogdanm 0:9b334a45a8ff 3454 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
bogdanm 0:9b334a45a8ff 3455 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
bogdanm 0:9b334a45a8ff 3456 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
bogdanm 0:9b334a45a8ff 3457 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
bogdanm 0:9b334a45a8ff 3458 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
bogdanm 0:9b334a45a8ff 3459 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
bogdanm 0:9b334a45a8ff 3460 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
bogdanm 0:9b334a45a8ff 3461
bogdanm 0:9b334a45a8ff 3462 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
bogdanm 0:9b334a45a8ff 3463 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 3464 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 3465 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 3466 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 3467 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 3468 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 3469 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 3470 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 3471 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 3472 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 3473 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 3474 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 3475 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 3476 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 3477 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 3478 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 3479 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 3480 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 3481 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 0:9b334a45a8ff 3482 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 3483 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
bogdanm 0:9b334a45a8ff 3484 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
bogdanm 0:9b334a45a8ff 3485 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
bogdanm 0:9b334a45a8ff 3486 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
bogdanm 0:9b334a45a8ff 3487 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
bogdanm 0:9b334a45a8ff 3488 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
bogdanm 0:9b334a45a8ff 3489 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
bogdanm 0:9b334a45a8ff 3490 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
bogdanm 0:9b334a45a8ff 3491 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
bogdanm 0:9b334a45a8ff 3492
bogdanm 0:9b334a45a8ff 3493 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
bogdanm 0:9b334a45a8ff 3494 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 3495 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 3496 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 3497 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 3498 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 3499 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 3500 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 3501 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 3502 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 3503 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 3504 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 3505 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 3506 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 3507 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 3508 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 3509 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 3510 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 3511 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 3512 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 0:9b334a45a8ff 3513 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 3514 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
bogdanm 0:9b334a45a8ff 3515 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
bogdanm 0:9b334a45a8ff 3516 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
bogdanm 0:9b334a45a8ff 3517 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
bogdanm 0:9b334a45a8ff 3518 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
bogdanm 0:9b334a45a8ff 3519 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
bogdanm 0:9b334a45a8ff 3520 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
bogdanm 0:9b334a45a8ff 3521 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
bogdanm 0:9b334a45a8ff 3522 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
bogdanm 0:9b334a45a8ff 3523
bogdanm 0:9b334a45a8ff 3524 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
bogdanm 0:9b334a45a8ff 3525 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 0:9b334a45a8ff 3526 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 0:9b334a45a8ff 3527 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 0:9b334a45a8ff 3528 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 0:9b334a45a8ff 3529 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 0:9b334a45a8ff 3530 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 0:9b334a45a8ff 3531 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 0:9b334a45a8ff 3532 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 0:9b334a45a8ff 3533 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 0:9b334a45a8ff 3534 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 0:9b334a45a8ff 3535 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 0:9b334a45a8ff 3536 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 0:9b334a45a8ff 3537 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 0:9b334a45a8ff 3538 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 0:9b334a45a8ff 3539 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 0:9b334a45a8ff 3540 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 0:9b334a45a8ff 3541 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 0:9b334a45a8ff 3542 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 0:9b334a45a8ff 3543 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 0:9b334a45a8ff 3544 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 0:9b334a45a8ff 3545 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
bogdanm 0:9b334a45a8ff 3546 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
bogdanm 0:9b334a45a8ff 3547 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
bogdanm 0:9b334a45a8ff 3548 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
bogdanm 0:9b334a45a8ff 3549 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
bogdanm 0:9b334a45a8ff 3550 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
bogdanm 0:9b334a45a8ff 3551 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
bogdanm 0:9b334a45a8ff 3552 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
bogdanm 0:9b334a45a8ff 3553 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
bogdanm 0:9b334a45a8ff 3554
bogdanm 0:9b334a45a8ff 3555 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
bogdanm 0:9b334a45a8ff 3556 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 0:9b334a45a8ff 3557 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 0:9b334a45a8ff 3558 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 0:9b334a45a8ff 3559 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 0:9b334a45a8ff 3560 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 0:9b334a45a8ff 3561 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 0:9b334a45a8ff 3562 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 0:9b334a45a8ff 3563 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 0:9b334a45a8ff 3564 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 0:9b334a45a8ff 3565 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 0:9b334a45a8ff 3566 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 0:9b334a45a8ff 3567 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 0:9b334a45a8ff 3568 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 0:9b334a45a8ff 3569 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 0:9b334a45a8ff 3570 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 0:9b334a45a8ff 3571 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 0:9b334a45a8ff 3572 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 0:9b334a45a8ff 3573 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 0:9b334a45a8ff 3574 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 0:9b334a45a8ff 3575 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 0:9b334a45a8ff 3576 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
bogdanm 0:9b334a45a8ff 3577 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
bogdanm 0:9b334a45a8ff 3578 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
bogdanm 0:9b334a45a8ff 3579 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
bogdanm 0:9b334a45a8ff 3580 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
bogdanm 0:9b334a45a8ff 3581 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
bogdanm 0:9b334a45a8ff 3582 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
bogdanm 0:9b334a45a8ff 3583 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
bogdanm 0:9b334a45a8ff 3584 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
bogdanm 0:9b334a45a8ff 3585
bogdanm 0:9b334a45a8ff 3586 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3587 /* */
bogdanm 0:9b334a45a8ff 3588 /* FLASH */
bogdanm 0:9b334a45a8ff 3589 /* */
bogdanm 0:9b334a45a8ff 3590 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3591 /******************* Bit definition for FLASH_ACR register ******************/
bogdanm 0:9b334a45a8ff 3592 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
bogdanm 0:9b334a45a8ff 3593 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3594 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3595 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3596
bogdanm 0:9b334a45a8ff 3597 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
bogdanm 0:9b334a45a8ff 3598 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
bogdanm 0:9b334a45a8ff 3599 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
bogdanm 0:9b334a45a8ff 3600
bogdanm 0:9b334a45a8ff 3601 /****************** Bit definition for FLASH_KEYR register ******************/
bogdanm 0:9b334a45a8ff 3602 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
bogdanm 0:9b334a45a8ff 3603
bogdanm 0:9b334a45a8ff 3604 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
bogdanm 0:9b334a45a8ff 3605 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
bogdanm 0:9b334a45a8ff 3606 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
bogdanm 0:9b334a45a8ff 3607
bogdanm 0:9b334a45a8ff 3608 /***************** Bit definition for FLASH_OPTKEYR register ****************/
bogdanm 0:9b334a45a8ff 3609 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
bogdanm 0:9b334a45a8ff 3610
bogdanm 0:9b334a45a8ff 3611 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
bogdanm 0:9b334a45a8ff 3612 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
bogdanm 0:9b334a45a8ff 3613
bogdanm 0:9b334a45a8ff 3614 /****************** Bit definition for FLASH_SR register *******************/
bogdanm 0:9b334a45a8ff 3615 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
bogdanm 0:9b334a45a8ff 3616 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
bogdanm 0:9b334a45a8ff 3617 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
bogdanm 0:9b334a45a8ff 3618 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
bogdanm 0:9b334a45a8ff 3619
bogdanm 0:9b334a45a8ff 3620 /******************* Bit definition for FLASH_CR register *******************/
bogdanm 0:9b334a45a8ff 3621 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
bogdanm 0:9b334a45a8ff 3622 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
bogdanm 0:9b334a45a8ff 3623 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
bogdanm 0:9b334a45a8ff 3624 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
bogdanm 0:9b334a45a8ff 3625 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
bogdanm 0:9b334a45a8ff 3626 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
bogdanm 0:9b334a45a8ff 3627 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
bogdanm 0:9b334a45a8ff 3628 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
bogdanm 0:9b334a45a8ff 3629 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 3630 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
bogdanm 0:9b334a45a8ff 3631 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
bogdanm 0:9b334a45a8ff 3632
bogdanm 0:9b334a45a8ff 3633 /******************* Bit definition for FLASH_AR register *******************/
bogdanm 0:9b334a45a8ff 3634 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
bogdanm 0:9b334a45a8ff 3635
bogdanm 0:9b334a45a8ff 3636 /****************** Bit definition for FLASH_OBR register *******************/
bogdanm 0:9b334a45a8ff 3637 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
bogdanm 0:9b334a45a8ff 3638 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
bogdanm 0:9b334a45a8ff 3639 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
bogdanm 0:9b334a45a8ff 3640 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
bogdanm 0:9b334a45a8ff 3641
bogdanm 0:9b334a45a8ff 3642 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
bogdanm 0:9b334a45a8ff 3643 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
bogdanm 0:9b334a45a8ff 3644 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
bogdanm 0:9b334a45a8ff 3645 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
bogdanm 0:9b334a45a8ff 3646 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
bogdanm 0:9b334a45a8ff 3647 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
bogdanm 0:9b334a45a8ff 3648 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
bogdanm 0:9b334a45a8ff 3649
bogdanm 0:9b334a45a8ff 3650 /****************** Bit definition for FLASH_WRPR register ******************/
bogdanm 0:9b334a45a8ff 3651 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
bogdanm 0:9b334a45a8ff 3652
bogdanm 0:9b334a45a8ff 3653 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 3654
bogdanm 0:9b334a45a8ff 3655 /****************** Bit definition for OB_RDP register **********************/
bogdanm 0:9b334a45a8ff 3656 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
bogdanm 0:9b334a45a8ff 3657 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
bogdanm 0:9b334a45a8ff 3658
bogdanm 0:9b334a45a8ff 3659 /****************** Bit definition for OB_USER register *********************/
bogdanm 0:9b334a45a8ff 3660 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
bogdanm 0:9b334a45a8ff 3661 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
bogdanm 0:9b334a45a8ff 3662
bogdanm 0:9b334a45a8ff 3663 /****************** Bit definition for FLASH_WRP0 register ******************/
bogdanm 0:9b334a45a8ff 3664 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 3665 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 3666
bogdanm 0:9b334a45a8ff 3667 /****************** Bit definition for FLASH_WRP1 register ******************/
bogdanm 0:9b334a45a8ff 3668 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 3669 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 3670
bogdanm 0:9b334a45a8ff 3671 /****************** Bit definition for FLASH_WRP2 register ******************/
bogdanm 0:9b334a45a8ff 3672 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 3673 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 3674
bogdanm 0:9b334a45a8ff 3675 /****************** Bit definition for FLASH_WRP3 register ******************/
bogdanm 0:9b334a45a8ff 3676 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 3677 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 3678 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3679 /* */
bogdanm 0:9b334a45a8ff 3680 /* General Purpose I/O (GPIO) */
bogdanm 0:9b334a45a8ff 3681 /* */
bogdanm 0:9b334a45a8ff 3682 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3683 /******************* Bit definition for GPIO_MODER register *****************/
bogdanm 0:9b334a45a8ff 3684 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3685 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3686 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3687 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3688 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3689 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3690 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3691 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3692 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3693 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3694 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3695 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3696 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3697 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3698 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3699 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 3700 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3701 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3702 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 3703 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3704 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3705 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 3706 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3707 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3708 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3709 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3710 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3711 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 3712 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3713 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3714 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3715 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3716 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3717 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 3718 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3719 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3720 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 3721 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3722 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3723 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 3724 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3725 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3726 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3727 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3728 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3729 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 3730 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3731 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3732
bogdanm 0:9b334a45a8ff 3733 /****************** Bit definition for GPIO_OTYPER register *****************/
bogdanm 0:9b334a45a8ff 3734 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3735 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3736 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3737 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3738 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3739 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3740 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3741 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3742 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3743 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3744 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3745 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3746 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3747 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3748 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3749 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3750
bogdanm 0:9b334a45a8ff 3751 /**************** Bit definition for GPIO_OSPEEDR register ******************/
bogdanm 0:9b334a45a8ff 3752 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3753 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3754 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3755 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3756 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3757 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3758 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3759 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3760 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3761 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3762 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3763 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3764 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3765 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3766 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3767 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 3768 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3769 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3770 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 3771 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3772 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3773 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 3774 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3775 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3776 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3777 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3778 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3779 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 3780 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3781 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3782 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3783 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3784 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3785 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 3786 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3787 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3788 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 3789 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3790 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3791 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 3792 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3793 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3794 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3795 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3796 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3797 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 3798 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3799 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3800
bogdanm 0:9b334a45a8ff 3801 /******************* Bit definition for GPIO_PUPDR register ******************/
bogdanm 0:9b334a45a8ff 3802 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3803 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3804 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3805 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3806 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3807 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3808 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3809 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3810 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3811 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3812 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3813 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3814 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3815 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3816 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3817 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 3818 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3819 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3820 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 3821 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3822 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3823 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 3824 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3825 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3826 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3827 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3828 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3829 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 3830 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3831 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3832 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3833 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3834 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3835 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 3836 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3837 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3838 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 3839 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3840 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3841 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 3842 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3843 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3844 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3845 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3846 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3847 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 3848 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3849 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3850
bogdanm 0:9b334a45a8ff 3851 /******************* Bit definition for GPIO_IDR register *******************/
bogdanm 0:9b334a45a8ff 3852 #define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3853 #define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3854 #define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3855 #define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3856 #define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3857 #define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3858 #define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3859 #define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3860 #define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3861 #define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3862 #define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3863 #define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3864 #define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3865 #define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3866 #define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3867 #define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3868
bogdanm 0:9b334a45a8ff 3869 /****************** Bit definition for GPIO_ODR register ********************/
bogdanm 0:9b334a45a8ff 3870 #define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3871 #define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3872 #define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3873 #define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3874 #define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3875 #define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3876 #define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3877 #define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3878 #define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3879 #define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3880 #define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3881 #define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3882 #define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3883 #define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3884 #define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3885 #define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3886
bogdanm 0:9b334a45a8ff 3887 /****************** Bit definition for GPIO_BSRR register ********************/
bogdanm 0:9b334a45a8ff 3888 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3889 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3890 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3891 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3892 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3893 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3894 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3895 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3896 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3897 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3898 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3899 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3900 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3901 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3902 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3903 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3904 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3905 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3906 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3907 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3908 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3909 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3910 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3911 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3912 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3913 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3914 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3915 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3916 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3917 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3918 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3919 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3920
bogdanm 0:9b334a45a8ff 3921 /****************** Bit definition for GPIO_LCKR register ********************/
bogdanm 0:9b334a45a8ff 3922 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3923 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3924 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3925 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3926 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3927 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3928 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3929 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3930 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3931 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3932 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3933 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3934 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3935 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3936 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3937 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3938 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3939
bogdanm 0:9b334a45a8ff 3940 /****************** Bit definition for GPIO_AFRL register ********************/
bogdanm 0:9b334a45a8ff 3941 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3942 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm 0:9b334a45a8ff 3943 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3944 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm 0:9b334a45a8ff 3945 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3946 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 3947 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 3948 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm 0:9b334a45a8ff 3949
bogdanm 0:9b334a45a8ff 3950 /****************** Bit definition for GPIO_AFRH register ********************/
bogdanm 0:9b334a45a8ff 3951 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3952 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm 0:9b334a45a8ff 3953 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3954 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm 0:9b334a45a8ff 3955 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3956 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 3957 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 3958 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm 0:9b334a45a8ff 3959
bogdanm 0:9b334a45a8ff 3960 /****************** Bit definition for GPIO_BRR register *********************/
bogdanm 0:9b334a45a8ff 3961 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3962 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3963 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3964 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3965 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3966 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3967 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3968 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3969 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3970 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3971 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3972 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3973 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3974 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3975 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3976 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3977
bogdanm 0:9b334a45a8ff 3978 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3979 /* */
bogdanm 0:9b334a45a8ff 3980 /* High Resolution Timer (HRTIM) */
bogdanm 0:9b334a45a8ff 3981 /* */
bogdanm 0:9b334a45a8ff 3982 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3983 /******************** Master Timer control register ***************************/
bogdanm 0:9b334a45a8ff 3984 #define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */
bogdanm 0:9b334a45a8ff 3985 #define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */
bogdanm 0:9b334a45a8ff 3986 #define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */
bogdanm 0:9b334a45a8ff 3987 #define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */
bogdanm 0:9b334a45a8ff 3988
bogdanm 0:9b334a45a8ff 3989 #define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */
bogdanm 0:9b334a45a8ff 3990 #define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */
bogdanm 0:9b334a45a8ff 3991 #define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */
bogdanm 0:9b334a45a8ff 3992
bogdanm 0:9b334a45a8ff 3993 #define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */
bogdanm 0:9b334a45a8ff 3994 #define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */
bogdanm 0:9b334a45a8ff 3995 #define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */
bogdanm 0:9b334a45a8ff 3996 #define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */
bogdanm 0:9b334a45a8ff 3997 #define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */
bogdanm 0:9b334a45a8ff 3998 #define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */
bogdanm 0:9b334a45a8ff 3999 #define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */
bogdanm 0:9b334a45a8ff 4000 #define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */
bogdanm 0:9b334a45a8ff 4001 #define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */
bogdanm 0:9b334a45a8ff 4002 #define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */
bogdanm 0:9b334a45a8ff 4003 #define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */
bogdanm 0:9b334a45a8ff 4004
bogdanm 0:9b334a45a8ff 4005 #define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */
bogdanm 0:9b334a45a8ff 4006 #define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */
bogdanm 0:9b334a45a8ff 4007 #define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */
bogdanm 0:9b334a45a8ff 4008 #define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */
bogdanm 0:9b334a45a8ff 4009 #define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */
bogdanm 0:9b334a45a8ff 4010 #define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */
bogdanm 0:9b334a45a8ff 4011
bogdanm 0:9b334a45a8ff 4012 #define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC sychronization mask */
bogdanm 0:9b334a45a8ff 4013 #define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC sychronization bit 0 */
bogdanm 0:9b334a45a8ff 4014 #define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC sychronization bit 1 */
bogdanm 0:9b334a45a8ff 4015
bogdanm 0:9b334a45a8ff 4016 #define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */
bogdanm 0:9b334a45a8ff 4017 #define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */
bogdanm 0:9b334a45a8ff 4018
bogdanm 0:9b334a45a8ff 4019 #define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */
bogdanm 0:9b334a45a8ff 4020 #define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/
bogdanm 0:9b334a45a8ff 4021 #define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */
bogdanm 0:9b334a45a8ff 4022
bogdanm 0:9b334a45a8ff 4023 /******************** Master Timer Interrupt status register ******************/
bogdanm 0:9b334a45a8ff 4024 #define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */
bogdanm 0:9b334a45a8ff 4025 #define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */
bogdanm 0:9b334a45a8ff 4026 #define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */
bogdanm 0:9b334a45a8ff 4027 #define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */
bogdanm 0:9b334a45a8ff 4028 #define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */
bogdanm 0:9b334a45a8ff 4029 #define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */
bogdanm 0:9b334a45a8ff 4030 #define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */
bogdanm 0:9b334a45a8ff 4031
bogdanm 0:9b334a45a8ff 4032 /******************** Master Timer Interrupt clear register *******************/
bogdanm 0:9b334a45a8ff 4033 #define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4034 #define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4035 #define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4036 #define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4037 #define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */
bogdanm 0:9b334a45a8ff 4038 #define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */
bogdanm 0:9b334a45a8ff 4039 #define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */
bogdanm 0:9b334a45a8ff 4040
bogdanm 0:9b334a45a8ff 4041 /******************** Master Timer DMA/Interrupt enable register **************/
bogdanm 0:9b334a45a8ff 4042 #define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */
bogdanm 0:9b334a45a8ff 4043 #define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */
bogdanm 0:9b334a45a8ff 4044 #define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */
bogdanm 0:9b334a45a8ff 4045 #define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */
bogdanm 0:9b334a45a8ff 4046 #define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */
bogdanm 0:9b334a45a8ff 4047 #define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */
bogdanm 0:9b334a45a8ff 4048 #define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */
bogdanm 0:9b334a45a8ff 4049
bogdanm 0:9b334a45a8ff 4050 #define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */
bogdanm 0:9b334a45a8ff 4051 #define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */
bogdanm 0:9b334a45a8ff 4052 #define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */
bogdanm 0:9b334a45a8ff 4053 #define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */
bogdanm 0:9b334a45a8ff 4054 #define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */
bogdanm 0:9b334a45a8ff 4055 #define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */
bogdanm 0:9b334a45a8ff 4056 #define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */
bogdanm 0:9b334a45a8ff 4057
bogdanm 0:9b334a45a8ff 4058 /******************* Bit definition for HRTIM_MCNTR register ****************/
bogdanm 0:9b334a45a8ff 4059 #define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
bogdanm 0:9b334a45a8ff 4060
bogdanm 0:9b334a45a8ff 4061 /******************* Bit definition for HRTIM_MPER register *****************/
bogdanm 0:9b334a45a8ff 4062 #define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
bogdanm 0:9b334a45a8ff 4063
bogdanm 0:9b334a45a8ff 4064 /******************* Bit definition for HRTIM_MREP register *****************/
bogdanm 0:9b334a45a8ff 4065 #define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */
bogdanm 0:9b334a45a8ff 4066
bogdanm 0:9b334a45a8ff 4067 /******************* Bit definition for HRTIM_MCMP1R register *****************/
bogdanm 0:9b334a45a8ff 4068 #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 0:9b334a45a8ff 4069
bogdanm 0:9b334a45a8ff 4070 /******************* Bit definition for HRTIM_MCMP2R register *****************/
bogdanm 0:9b334a45a8ff 4071 #define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 0:9b334a45a8ff 4072
bogdanm 0:9b334a45a8ff 4073 /******************* Bit definition for HRTIM_MCMP3R register *****************/
bogdanm 0:9b334a45a8ff 4074 #define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 0:9b334a45a8ff 4075
bogdanm 0:9b334a45a8ff 4076 /******************* Bit definition for HRTIM_MCMP4R register *****************/
bogdanm 0:9b334a45a8ff 4077 #define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
bogdanm 0:9b334a45a8ff 4078
bogdanm 0:9b334a45a8ff 4079 /******************** Slave control register **********************************/
bogdanm 0:9b334a45a8ff 4080 #define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
bogdanm 0:9b334a45a8ff 4081 #define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */
bogdanm 0:9b334a45a8ff 4082 #define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */
bogdanm 0:9b334a45a8ff 4083 #define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */
bogdanm 0:9b334a45a8ff 4084
bogdanm 0:9b334a45a8ff 4085 #define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */
bogdanm 0:9b334a45a8ff 4086 #define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */
bogdanm 0:9b334a45a8ff 4087 #define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */
bogdanm 0:9b334a45a8ff 4088 #define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */
bogdanm 0:9b334a45a8ff 4089
bogdanm 0:9b334a45a8ff 4090 #define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */
bogdanm 0:9b334a45a8ff 4091 #define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */
bogdanm 0:9b334a45a8ff 4092
bogdanm 0:9b334a45a8ff 4093 #define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed compartor 2 mode mask */
bogdanm 0:9b334a45a8ff 4094 #define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed compartor 2 bit 0 */
bogdanm 0:9b334a45a8ff 4095 #define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed compartor 2 bit 1 */
bogdanm 0:9b334a45a8ff 4096 #define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed compartor 4 mode mask */
bogdanm 0:9b334a45a8ff 4097 #define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed compartor 4 bit 0 */
bogdanm 0:9b334a45a8ff 4098 #define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed compartor 4 bit 1 */
bogdanm 0:9b334a45a8ff 4099
bogdanm 0:9b334a45a8ff 4100 #define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */
bogdanm 0:9b334a45a8ff 4101 #define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */
bogdanm 0:9b334a45a8ff 4102 #define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */
bogdanm 0:9b334a45a8ff 4103 #define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */
bogdanm 0:9b334a45a8ff 4104 #define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */
bogdanm 0:9b334a45a8ff 4105 #define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */
bogdanm 0:9b334a45a8ff 4106 #define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */
bogdanm 0:9b334a45a8ff 4107 #define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */
bogdanm 0:9b334a45a8ff 4108
bogdanm 0:9b334a45a8ff 4109 #define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC sychronization mask */
bogdanm 0:9b334a45a8ff 4110 #define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC sychronization bit 0 */
bogdanm 0:9b334a45a8ff 4111 #define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC sychronization bit 1 */
bogdanm 0:9b334a45a8ff 4112 #define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */
bogdanm 0:9b334a45a8ff 4113
bogdanm 0:9b334a45a8ff 4114 #define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */
bogdanm 0:9b334a45a8ff 4115 #define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */
bogdanm 0:9b334a45a8ff 4116 #define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */
bogdanm 0:9b334a45a8ff 4117 #define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */
bogdanm 0:9b334a45a8ff 4118 #define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */
bogdanm 0:9b334a45a8ff 4119
bogdanm 0:9b334a45a8ff 4120 /******************** Slave Interrupt status register **************************/
bogdanm 0:9b334a45a8ff 4121 #define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */
bogdanm 0:9b334a45a8ff 4122 #define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */
bogdanm 0:9b334a45a8ff 4123 #define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */
bogdanm 0:9b334a45a8ff 4124 #define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */
bogdanm 0:9b334a45a8ff 4125 #define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */
bogdanm 0:9b334a45a8ff 4126 #define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */
bogdanm 0:9b334a45a8ff 4127 #define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */
bogdanm 0:9b334a45a8ff 4128 #define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */
bogdanm 0:9b334a45a8ff 4129 #define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */
bogdanm 0:9b334a45a8ff 4130 #define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */
bogdanm 0:9b334a45a8ff 4131 #define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */
bogdanm 0:9b334a45a8ff 4132 #define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */
bogdanm 0:9b334a45a8ff 4133 #define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */
bogdanm 0:9b334a45a8ff 4134 #define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */
bogdanm 0:9b334a45a8ff 4135 #define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */
bogdanm 0:9b334a45a8ff 4136 #define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */
bogdanm 0:9b334a45a8ff 4137 #define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */
bogdanm 0:9b334a45a8ff 4138 #define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */
bogdanm 0:9b334a45a8ff 4139 #define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */
bogdanm 0:9b334a45a8ff 4140 #define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */
bogdanm 0:9b334a45a8ff 4141
bogdanm 0:9b334a45a8ff 4142 /******************** Slave Interrupt clear register **************************/
bogdanm 0:9b334a45a8ff 4143 #define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */
bogdanm 0:9b334a45a8ff 4144 #define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */
bogdanm 0:9b334a45a8ff 4145 #define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */
bogdanm 0:9b334a45a8ff 4146 #define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */
bogdanm 0:9b334a45a8ff 4147 #define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */
bogdanm 0:9b334a45a8ff 4148 #define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */
bogdanm 0:9b334a45a8ff 4149 #define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */
bogdanm 0:9b334a45a8ff 4150 #define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */
bogdanm 0:9b334a45a8ff 4151 #define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */
bogdanm 0:9b334a45a8ff 4152 #define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */
bogdanm 0:9b334a45a8ff 4153 #define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */
bogdanm 0:9b334a45a8ff 4154 #define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */
bogdanm 0:9b334a45a8ff 4155 #define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */
bogdanm 0:9b334a45a8ff 4156 #define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */
bogdanm 0:9b334a45a8ff 4157 #define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */
bogdanm 0:9b334a45a8ff 4158
bogdanm 0:9b334a45a8ff 4159 /******************** Slave DMA/Interrupt enable register *********************/
bogdanm 0:9b334a45a8ff 4160 #define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */
bogdanm 0:9b334a45a8ff 4161 #define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */
bogdanm 0:9b334a45a8ff 4162 #define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */
bogdanm 0:9b334a45a8ff 4163 #define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */
bogdanm 0:9b334a45a8ff 4164 #define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */
bogdanm 0:9b334a45a8ff 4165 #define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */
bogdanm 0:9b334a45a8ff 4166 #define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */
bogdanm 0:9b334a45a8ff 4167 #define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */
bogdanm 0:9b334a45a8ff 4168 #define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */
bogdanm 0:9b334a45a8ff 4169 #define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */
bogdanm 0:9b334a45a8ff 4170 #define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */
bogdanm 0:9b334a45a8ff 4171 #define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */
bogdanm 0:9b334a45a8ff 4172 #define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */
bogdanm 0:9b334a45a8ff 4173 #define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */
bogdanm 0:9b334a45a8ff 4174
bogdanm 0:9b334a45a8ff 4175 #define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */
bogdanm 0:9b334a45a8ff 4176 #define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */
bogdanm 0:9b334a45a8ff 4177 #define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */
bogdanm 0:9b334a45a8ff 4178 #define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */
bogdanm 0:9b334a45a8ff 4179 #define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */
bogdanm 0:9b334a45a8ff 4180 #define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */
bogdanm 0:9b334a45a8ff 4181 #define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */
bogdanm 0:9b334a45a8ff 4182 #define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */
bogdanm 0:9b334a45a8ff 4183 #define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */
bogdanm 0:9b334a45a8ff 4184 #define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */
bogdanm 0:9b334a45a8ff 4185 #define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */
bogdanm 0:9b334a45a8ff 4186 #define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */
bogdanm 0:9b334a45a8ff 4187 #define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */
bogdanm 0:9b334a45a8ff 4188 #define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slavedelay protection request enable */
bogdanm 0:9b334a45a8ff 4189
bogdanm 0:9b334a45a8ff 4190 /****************** Bit definition for HRTIM_CNTR register ****************/
bogdanm 0:9b334a45a8ff 4191 #define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */
bogdanm 0:9b334a45a8ff 4192
bogdanm 0:9b334a45a8ff 4193 /******************* Bit definition for HRTIM_PER register *****************/
bogdanm 0:9b334a45a8ff 4194 #define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
bogdanm 0:9b334a45a8ff 4195
bogdanm 0:9b334a45a8ff 4196 /******************* Bit definition for HRTIM_REP register *****************/
bogdanm 0:9b334a45a8ff 4197 #define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */
bogdanm 0:9b334a45a8ff 4198
bogdanm 0:9b334a45a8ff 4199 /******************* Bit definition for HRTIM_CMP1R register *****************/
bogdanm 0:9b334a45a8ff 4200 #define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 0:9b334a45a8ff 4201
bogdanm 0:9b334a45a8ff 4202 /******************* Bit definition for HRTIM_CMP1CR register *****************/
bogdanm 0:9b334a45a8ff 4203 #define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 0:9b334a45a8ff 4204
bogdanm 0:9b334a45a8ff 4205 /******************* Bit definition for HRTIM_CMP2R register *****************/
bogdanm 0:9b334a45a8ff 4206 #define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 0:9b334a45a8ff 4207
bogdanm 0:9b334a45a8ff 4208 /******************* Bit definition for HRTIM_CMP3R register *****************/
bogdanm 0:9b334a45a8ff 4209 #define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 0:9b334a45a8ff 4210
bogdanm 0:9b334a45a8ff 4211 /******************* Bit definition for HRTIM_CMP4R register *****************/
bogdanm 0:9b334a45a8ff 4212 #define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
bogdanm 0:9b334a45a8ff 4213
bogdanm 0:9b334a45a8ff 4214 /******************* Bit definition for HRTIM_CPT1R register ****************/
bogdanm 0:9b334a45a8ff 4215 #define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
bogdanm 0:9b334a45a8ff 4216
bogdanm 0:9b334a45a8ff 4217 /******************* Bit definition for HRTIM_CPT2R register ****************/
bogdanm 0:9b334a45a8ff 4218 #define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
bogdanm 0:9b334a45a8ff 4219
bogdanm 0:9b334a45a8ff 4220 /******************** Bit definition for Slave Deadtime register **************/
bogdanm 0:9b334a45a8ff 4221 #define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */
bogdanm 0:9b334a45a8ff 4222 #define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */
bogdanm 0:9b334a45a8ff 4223 #define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */
bogdanm 0:9b334a45a8ff 4224 #define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */
bogdanm 0:9b334a45a8ff 4225 #define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */
bogdanm 0:9b334a45a8ff 4226 #define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */
bogdanm 0:9b334a45a8ff 4227 #define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */
bogdanm 0:9b334a45a8ff 4228 #define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */
bogdanm 0:9b334a45a8ff 4229 #define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */
bogdanm 0:9b334a45a8ff 4230 #define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */
bogdanm 0:9b334a45a8ff 4231 #define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */
bogdanm 0:9b334a45a8ff 4232 #define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */
bogdanm 0:9b334a45a8ff 4233 #define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */
bogdanm 0:9b334a45a8ff 4234 #define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */
bogdanm 0:9b334a45a8ff 4235 #define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */
bogdanm 0:9b334a45a8ff 4236 #define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */
bogdanm 0:9b334a45a8ff 4237 #define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */
bogdanm 0:9b334a45a8ff 4238 #define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */
bogdanm 0:9b334a45a8ff 4239 #define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */
bogdanm 0:9b334a45a8ff 4240 #define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */
bogdanm 0:9b334a45a8ff 4241 #define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */
bogdanm 0:9b334a45a8ff 4242 #define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */
bogdanm 0:9b334a45a8ff 4243 #define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */
bogdanm 0:9b334a45a8ff 4244 #define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */
bogdanm 0:9b334a45a8ff 4245 #define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */
bogdanm 0:9b334a45a8ff 4246 #define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */
bogdanm 0:9b334a45a8ff 4247 #define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */
bogdanm 0:9b334a45a8ff 4248 #define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */
bogdanm 0:9b334a45a8ff 4249 #define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */
bogdanm 0:9b334a45a8ff 4250 #define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */
bogdanm 0:9b334a45a8ff 4251
bogdanm 0:9b334a45a8ff 4252 /**** Bit definition for Slave Output 1 set register **************************/
bogdanm 0:9b334a45a8ff 4253 #define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */
bogdanm 0:9b334a45a8ff 4254 #define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 0:9b334a45a8ff 4255 #define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 0:9b334a45a8ff 4256 #define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4257 #define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4258 #define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4259 #define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 0:9b334a45a8ff 4260
bogdanm 0:9b334a45a8ff 4261 #define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 0:9b334a45a8ff 4262 #define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 0:9b334a45a8ff 4263 #define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 0:9b334a45a8ff 4264 #define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 0:9b334a45a8ff 4265 #define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 0:9b334a45a8ff 4266
bogdanm 0:9b334a45a8ff 4267 #define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 0:9b334a45a8ff 4268 #define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 0:9b334a45a8ff 4269 #define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 0:9b334a45a8ff 4270 #define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 0:9b334a45a8ff 4271 #define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 0:9b334a45a8ff 4272 #define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 0:9b334a45a8ff 4273 #define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 0:9b334a45a8ff 4274 #define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 0:9b334a45a8ff 4275 #define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 0:9b334a45a8ff 4276
bogdanm 0:9b334a45a8ff 4277 #define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 0:9b334a45a8ff 4278 #define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 0:9b334a45a8ff 4279 #define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 0:9b334a45a8ff 4280 #define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 0:9b334a45a8ff 4281 #define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 0:9b334a45a8ff 4282 #define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 0:9b334a45a8ff 4283 #define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 0:9b334a45a8ff 4284 #define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 0:9b334a45a8ff 4285 #define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 0:9b334a45a8ff 4286 #define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 0:9b334a45a8ff 4287
bogdanm 0:9b334a45a8ff 4288 #define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 0:9b334a45a8ff 4289
bogdanm 0:9b334a45a8ff 4290 /**** Bit definition for Slave Output 1 reset register ************************/
bogdanm 0:9b334a45a8ff 4291 #define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
bogdanm 0:9b334a45a8ff 4292 #define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 0:9b334a45a8ff 4293 #define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 0:9b334a45a8ff 4294 #define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4295 #define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4296 #define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4297 #define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 0:9b334a45a8ff 4298
bogdanm 0:9b334a45a8ff 4299 #define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 0:9b334a45a8ff 4300 #define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 0:9b334a45a8ff 4301 #define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 0:9b334a45a8ff 4302 #define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 0:9b334a45a8ff 4303 #define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 0:9b334a45a8ff 4304
bogdanm 0:9b334a45a8ff 4305 #define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 0:9b334a45a8ff 4306 #define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 0:9b334a45a8ff 4307 #define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 0:9b334a45a8ff 4308 #define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 0:9b334a45a8ff 4309 #define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 0:9b334a45a8ff 4310 #define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 0:9b334a45a8ff 4311 #define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 0:9b334a45a8ff 4312 #define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 0:9b334a45a8ff 4313 #define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 0:9b334a45a8ff 4314
bogdanm 0:9b334a45a8ff 4315 #define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 0:9b334a45a8ff 4316 #define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 0:9b334a45a8ff 4317 #define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 0:9b334a45a8ff 4318 #define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 0:9b334a45a8ff 4319 #define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 0:9b334a45a8ff 4320 #define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 0:9b334a45a8ff 4321 #define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 0:9b334a45a8ff 4322 #define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 0:9b334a45a8ff 4323 #define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 0:9b334a45a8ff 4324 #define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 0:9b334a45a8ff 4325
bogdanm 0:9b334a45a8ff 4326 #define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 0:9b334a45a8ff 4327
bogdanm 0:9b334a45a8ff 4328
bogdanm 0:9b334a45a8ff 4329 /**** Bit definition for Slave Output 2 set register **************************/
bogdanm 0:9b334a45a8ff 4330 #define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */
bogdanm 0:9b334a45a8ff 4331 #define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 0:9b334a45a8ff 4332 #define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 0:9b334a45a8ff 4333 #define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4334 #define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4335 #define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4336 #define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 0:9b334a45a8ff 4337
bogdanm 0:9b334a45a8ff 4338 #define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 0:9b334a45a8ff 4339 #define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 0:9b334a45a8ff 4340 #define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 0:9b334a45a8ff 4341 #define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 0:9b334a45a8ff 4342 #define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 0:9b334a45a8ff 4343
bogdanm 0:9b334a45a8ff 4344 #define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 0:9b334a45a8ff 4345 #define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 0:9b334a45a8ff 4346 #define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 0:9b334a45a8ff 4347 #define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 0:9b334a45a8ff 4348 #define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 0:9b334a45a8ff 4349 #define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 0:9b334a45a8ff 4350 #define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 0:9b334a45a8ff 4351 #define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 0:9b334a45a8ff 4352 #define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 0:9b334a45a8ff 4353
bogdanm 0:9b334a45a8ff 4354 #define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 0:9b334a45a8ff 4355 #define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 0:9b334a45a8ff 4356 #define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 0:9b334a45a8ff 4357 #define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 0:9b334a45a8ff 4358 #define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 0:9b334a45a8ff 4359 #define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 0:9b334a45a8ff 4360 #define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 0:9b334a45a8ff 4361 #define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 0:9b334a45a8ff 4362 #define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 0:9b334a45a8ff 4363 #define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 0:9b334a45a8ff 4364
bogdanm 0:9b334a45a8ff 4365 #define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 0:9b334a45a8ff 4366
bogdanm 0:9b334a45a8ff 4367 /**** Bit definition for Slave Output 2 reset register ************************/
bogdanm 0:9b334a45a8ff 4368 #define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
bogdanm 0:9b334a45a8ff 4369 #define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
bogdanm 0:9b334a45a8ff 4370 #define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
bogdanm 0:9b334a45a8ff 4371 #define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4372 #define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4373 #define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4374 #define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
bogdanm 0:9b334a45a8ff 4375
bogdanm 0:9b334a45a8ff 4376 #define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
bogdanm 0:9b334a45a8ff 4377 #define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
bogdanm 0:9b334a45a8ff 4378 #define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
bogdanm 0:9b334a45a8ff 4379 #define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
bogdanm 0:9b334a45a8ff 4380 #define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
bogdanm 0:9b334a45a8ff 4381
bogdanm 0:9b334a45a8ff 4382 #define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
bogdanm 0:9b334a45a8ff 4383 #define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
bogdanm 0:9b334a45a8ff 4384 #define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
bogdanm 0:9b334a45a8ff 4385 #define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
bogdanm 0:9b334a45a8ff 4386 #define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
bogdanm 0:9b334a45a8ff 4387 #define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
bogdanm 0:9b334a45a8ff 4388 #define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
bogdanm 0:9b334a45a8ff 4389 #define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
bogdanm 0:9b334a45a8ff 4390 #define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
bogdanm 0:9b334a45a8ff 4391
bogdanm 0:9b334a45a8ff 4392 #define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
bogdanm 0:9b334a45a8ff 4393 #define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
bogdanm 0:9b334a45a8ff 4394 #define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
bogdanm 0:9b334a45a8ff 4395 #define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
bogdanm 0:9b334a45a8ff 4396 #define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
bogdanm 0:9b334a45a8ff 4397 #define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
bogdanm 0:9b334a45a8ff 4398 #define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
bogdanm 0:9b334a45a8ff 4399 #define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
bogdanm 0:9b334a45a8ff 4400 #define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
bogdanm 0:9b334a45a8ff 4401 #define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
bogdanm 0:9b334a45a8ff 4402
bogdanm 0:9b334a45a8ff 4403 #define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
bogdanm 0:9b334a45a8ff 4404
bogdanm 0:9b334a45a8ff 4405 /**** Bit definition for Slave external event filtering register 1 ***********/
bogdanm 0:9b334a45a8ff 4406 #define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */
bogdanm 0:9b334a45a8ff 4407 #define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */
bogdanm 0:9b334a45a8ff 4408 #define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */
bogdanm 0:9b334a45a8ff 4409 #define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/
bogdanm 0:9b334a45a8ff 4410 #define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */
bogdanm 0:9b334a45a8ff 4411 #define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */
bogdanm 0:9b334a45a8ff 4412
bogdanm 0:9b334a45a8ff 4413 #define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */
bogdanm 0:9b334a45a8ff 4414 #define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */
bogdanm 0:9b334a45a8ff 4415 #define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */
bogdanm 0:9b334a45a8ff 4416 #define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/
bogdanm 0:9b334a45a8ff 4417 #define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */
bogdanm 0:9b334a45a8ff 4418 #define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */
bogdanm 0:9b334a45a8ff 4419
bogdanm 0:9b334a45a8ff 4420 #define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */
bogdanm 0:9b334a45a8ff 4421 #define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */
bogdanm 0:9b334a45a8ff 4422 #define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */
bogdanm 0:9b334a45a8ff 4423 #define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/
bogdanm 0:9b334a45a8ff 4424 #define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */
bogdanm 0:9b334a45a8ff 4425 #define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */
bogdanm 0:9b334a45a8ff 4426
bogdanm 0:9b334a45a8ff 4427 #define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */
bogdanm 0:9b334a45a8ff 4428 #define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */
bogdanm 0:9b334a45a8ff 4429 #define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */
bogdanm 0:9b334a45a8ff 4430 #define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/
bogdanm 0:9b334a45a8ff 4431 #define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */
bogdanm 0:9b334a45a8ff 4432 #define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */
bogdanm 0:9b334a45a8ff 4433
bogdanm 0:9b334a45a8ff 4434 #define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */
bogdanm 0:9b334a45a8ff 4435 #define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */
bogdanm 0:9b334a45a8ff 4436 #define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */
bogdanm 0:9b334a45a8ff 4437 #define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/
bogdanm 0:9b334a45a8ff 4438 #define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */
bogdanm 0:9b334a45a8ff 4439 #define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */
bogdanm 0:9b334a45a8ff 4440
bogdanm 0:9b334a45a8ff 4441 /**** Bit definition for Slave external event filtering register 2 ***********/
bogdanm 0:9b334a45a8ff 4442 #define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */
bogdanm 0:9b334a45a8ff 4443 #define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */
bogdanm 0:9b334a45a8ff 4444 #define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */
bogdanm 0:9b334a45a8ff 4445 #define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/
bogdanm 0:9b334a45a8ff 4446 #define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */
bogdanm 0:9b334a45a8ff 4447 #define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */
bogdanm 0:9b334a45a8ff 4448
bogdanm 0:9b334a45a8ff 4449 #define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */
bogdanm 0:9b334a45a8ff 4450 #define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */
bogdanm 0:9b334a45a8ff 4451 #define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */
bogdanm 0:9b334a45a8ff 4452 #define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/
bogdanm 0:9b334a45a8ff 4453 #define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */
bogdanm 0:9b334a45a8ff 4454 #define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */
bogdanm 0:9b334a45a8ff 4455
bogdanm 0:9b334a45a8ff 4456 #define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */
bogdanm 0:9b334a45a8ff 4457 #define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */
bogdanm 0:9b334a45a8ff 4458 #define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */
bogdanm 0:9b334a45a8ff 4459 #define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/
bogdanm 0:9b334a45a8ff 4460 #define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */
bogdanm 0:9b334a45a8ff 4461 #define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */
bogdanm 0:9b334a45a8ff 4462
bogdanm 0:9b334a45a8ff 4463 #define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */
bogdanm 0:9b334a45a8ff 4464 #define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */
bogdanm 0:9b334a45a8ff 4465 #define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */
bogdanm 0:9b334a45a8ff 4466 #define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/
bogdanm 0:9b334a45a8ff 4467 #define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */
bogdanm 0:9b334a45a8ff 4468 #define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */
bogdanm 0:9b334a45a8ff 4469
bogdanm 0:9b334a45a8ff 4470 #define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */
bogdanm 0:9b334a45a8ff 4471 #define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */
bogdanm 0:9b334a45a8ff 4472 #define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */
bogdanm 0:9b334a45a8ff 4473 #define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/
bogdanm 0:9b334a45a8ff 4474 #define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */
bogdanm 0:9b334a45a8ff 4475 #define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */
bogdanm 0:9b334a45a8ff 4476
bogdanm 0:9b334a45a8ff 4477 /**** Bit definition for Slave Timer reset register ***************************/
bogdanm 0:9b334a45a8ff 4478 #define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */
bogdanm 0:9b334a45a8ff 4479 #define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */
bogdanm 0:9b334a45a8ff 4480 #define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */
bogdanm 0:9b334a45a8ff 4481
bogdanm 0:9b334a45a8ff 4482 #define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */
bogdanm 0:9b334a45a8ff 4483 #define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */
bogdanm 0:9b334a45a8ff 4484 #define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */
bogdanm 0:9b334a45a8ff 4485 #define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */
bogdanm 0:9b334a45a8ff 4486 #define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */
bogdanm 0:9b334a45a8ff 4487
bogdanm 0:9b334a45a8ff 4488 #define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */
bogdanm 0:9b334a45a8ff 4489 #define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */
bogdanm 0:9b334a45a8ff 4490 #define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */
bogdanm 0:9b334a45a8ff 4491 #define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */
bogdanm 0:9b334a45a8ff 4492 #define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */
bogdanm 0:9b334a45a8ff 4493 #define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */
bogdanm 0:9b334a45a8ff 4494 #define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */
bogdanm 0:9b334a45a8ff 4495 #define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */
bogdanm 0:9b334a45a8ff 4496 #define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */
bogdanm 0:9b334a45a8ff 4497 #define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */
bogdanm 0:9b334a45a8ff 4498
bogdanm 0:9b334a45a8ff 4499 #define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */
bogdanm 0:9b334a45a8ff 4500 #define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4501 #define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */
bogdanm 0:9b334a45a8ff 4502
bogdanm 0:9b334a45a8ff 4503 #define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 0:9b334a45a8ff 4504 #define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4505 #define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */
bogdanm 0:9b334a45a8ff 4506
bogdanm 0:9b334a45a8ff 4507 #define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */
bogdanm 0:9b334a45a8ff 4508 #define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4509 #define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */
bogdanm 0:9b334a45a8ff 4510
bogdanm 0:9b334a45a8ff 4511 #define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */
bogdanm 0:9b334a45a8ff 4512 #define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4513 #define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */
bogdanm 0:9b334a45a8ff 4514
bogdanm 0:9b334a45a8ff 4515 /**** Bit definition for Slave Timer Chopper register *************************/
bogdanm 0:9b334a45a8ff 4516 #define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */
bogdanm 0:9b334a45a8ff 4517 #define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */
bogdanm 0:9b334a45a8ff 4518 #define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */
bogdanm 0:9b334a45a8ff 4519 #define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */
bogdanm 0:9b334a45a8ff 4520 #define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */
bogdanm 0:9b334a45a8ff 4521
bogdanm 0:9b334a45a8ff 4522 #define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */
bogdanm 0:9b334a45a8ff 4523 #define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */
bogdanm 0:9b334a45a8ff 4524 #define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */
bogdanm 0:9b334a45a8ff 4525 #define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */
bogdanm 0:9b334a45a8ff 4526
bogdanm 0:9b334a45a8ff 4527 #define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */
bogdanm 0:9b334a45a8ff 4528 #define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */
bogdanm 0:9b334a45a8ff 4529 #define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */
bogdanm 0:9b334a45a8ff 4530 #define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */
bogdanm 0:9b334a45a8ff 4531 #define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */
bogdanm 0:9b334a45a8ff 4532
bogdanm 0:9b334a45a8ff 4533 /**** Bit definition for Slave Timer Capture 1 control register ***************/
bogdanm 0:9b334a45a8ff 4534 #define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
bogdanm 0:9b334a45a8ff 4535 #define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
bogdanm 0:9b334a45a8ff 4536 #define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
bogdanm 0:9b334a45a8ff 4537 #define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
bogdanm 0:9b334a45a8ff 4538 #define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
bogdanm 0:9b334a45a8ff 4539 #define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
bogdanm 0:9b334a45a8ff 4540 #define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
bogdanm 0:9b334a45a8ff 4541 #define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
bogdanm 0:9b334a45a8ff 4542 #define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
bogdanm 0:9b334a45a8ff 4543 #define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
bogdanm 0:9b334a45a8ff 4544 #define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
bogdanm 0:9b334a45a8ff 4545 #define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
bogdanm 0:9b334a45a8ff 4546
bogdanm 0:9b334a45a8ff 4547 #define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
bogdanm 0:9b334a45a8ff 4548 #define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
bogdanm 0:9b334a45a8ff 4549 #define HRTIM_CPT1CR_TIMACMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4550 #define HRTIM_CPT1CR_TIMACMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4551
bogdanm 0:9b334a45a8ff 4552 #define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
bogdanm 0:9b334a45a8ff 4553 #define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
bogdanm 0:9b334a45a8ff 4554 #define HRTIM_CPT1CR_TIMBCMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
bogdanm 0:9b334a45a8ff 4555 #define HRTIM_CPT1CR_TIMBCMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4556
bogdanm 0:9b334a45a8ff 4557 #define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
bogdanm 0:9b334a45a8ff 4558 #define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
bogdanm 0:9b334a45a8ff 4559 #define HRTIM_CPT1CR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 0:9b334a45a8ff 4560 #define HRTIM_CPT1CR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4561
bogdanm 0:9b334a45a8ff 4562 #define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
bogdanm 0:9b334a45a8ff 4563 #define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
bogdanm 0:9b334a45a8ff 4564 #define HRTIM_CPT1CR_TIMDCMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
bogdanm 0:9b334a45a8ff 4565 #define HRTIM_CPT1CR_TIMDCMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4566
bogdanm 0:9b334a45a8ff 4567 #define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
bogdanm 0:9b334a45a8ff 4568 #define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
bogdanm 0:9b334a45a8ff 4569 #define HRTIM_CPT1CR_TIMECMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
bogdanm 0:9b334a45a8ff 4570 #define HRTIM_CPT1CR_TIMECMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4571
bogdanm 0:9b334a45a8ff 4572 /**** Bit definition for Slave Timer Capture 2 control register ***************/
bogdanm 0:9b334a45a8ff 4573 #define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
bogdanm 0:9b334a45a8ff 4574 #define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
bogdanm 0:9b334a45a8ff 4575 #define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
bogdanm 0:9b334a45a8ff 4576 #define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
bogdanm 0:9b334a45a8ff 4577 #define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
bogdanm 0:9b334a45a8ff 4578 #define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
bogdanm 0:9b334a45a8ff 4579 #define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
bogdanm 0:9b334a45a8ff 4580 #define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
bogdanm 0:9b334a45a8ff 4581 #define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
bogdanm 0:9b334a45a8ff 4582 #define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
bogdanm 0:9b334a45a8ff 4583 #define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
bogdanm 0:9b334a45a8ff 4584 #define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
bogdanm 0:9b334a45a8ff 4585
bogdanm 0:9b334a45a8ff 4586 #define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
bogdanm 0:9b334a45a8ff 4587 #define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
bogdanm 0:9b334a45a8ff 4588 #define HRTIM_CPT2CR_TIMACMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4589 #define HRTIM_CPT2CR_TIMACMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4590
bogdanm 0:9b334a45a8ff 4591 #define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
bogdanm 0:9b334a45a8ff 4592 #define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
bogdanm 0:9b334a45a8ff 4593 #define HRTIM_CPT2CR_TIMBCMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
bogdanm 0:9b334a45a8ff 4594 #define HRTIM_CPT2CR_TIMBCMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4595
bogdanm 0:9b334a45a8ff 4596 #define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
bogdanm 0:9b334a45a8ff 4597 #define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
bogdanm 0:9b334a45a8ff 4598 #define HRTIM_CPT2CR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
bogdanm 0:9b334a45a8ff 4599 #define HRTIM_CPT2CR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4600
bogdanm 0:9b334a45a8ff 4601 #define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
bogdanm 0:9b334a45a8ff 4602 #define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
bogdanm 0:9b334a45a8ff 4603 #define HRTIM_CPT2CR_TIMDCMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
bogdanm 0:9b334a45a8ff 4604 #define HRTIM_CPT2CR_TIMDCMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4605
bogdanm 0:9b334a45a8ff 4606 #define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
bogdanm 0:9b334a45a8ff 4607 #define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
bogdanm 0:9b334a45a8ff 4608 #define HRTIM_CPT2CR_TIMECMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
bogdanm 0:9b334a45a8ff 4609 #define HRTIM_CPT2CR_TIMECMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4610
bogdanm 0:9b334a45a8ff 4611 /**** Bit definition for Slave Timer Output register **************************/
bogdanm 0:9b334a45a8ff 4612 #define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */
bogdanm 0:9b334a45a8ff 4613 #define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */
bogdanm 0:9b334a45a8ff 4614 #define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */
bogdanm 0:9b334a45a8ff 4615 #define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */
bogdanm 0:9b334a45a8ff 4616 #define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */
bogdanm 0:9b334a45a8ff 4617 #define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */
bogdanm 0:9b334a45a8ff 4618 #define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */
bogdanm 0:9b334a45a8ff 4619 #define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */
bogdanm 0:9b334a45a8ff 4620
bogdanm 0:9b334a45a8ff 4621 #define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */
bogdanm 0:9b334a45a8ff 4622 #define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */
bogdanm 0:9b334a45a8ff 4623 #define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */
bogdanm 0:9b334a45a8ff 4624 #define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */
bogdanm 0:9b334a45a8ff 4625 #define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */
bogdanm 0:9b334a45a8ff 4626 #define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */
bogdanm 0:9b334a45a8ff 4627
bogdanm 0:9b334a45a8ff 4628 #define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */
bogdanm 0:9b334a45a8ff 4629 #define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */
bogdanm 0:9b334a45a8ff 4630 #define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */
bogdanm 0:9b334a45a8ff 4631 #define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */
bogdanm 0:9b334a45a8ff 4632 #define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */
bogdanm 0:9b334a45a8ff 4633 #define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */
bogdanm 0:9b334a45a8ff 4634 #define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */
bogdanm 0:9b334a45a8ff 4635 #define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */
bogdanm 0:9b334a45a8ff 4636
bogdanm 0:9b334a45a8ff 4637 /**** Bit definition for Slave Timer Fault register ***************************/
bogdanm 0:9b334a45a8ff 4638 #define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */
bogdanm 0:9b334a45a8ff 4639 #define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */
bogdanm 0:9b334a45a8ff 4640 #define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */
bogdanm 0:9b334a45a8ff 4641 #define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */
bogdanm 0:9b334a45a8ff 4642 #define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */
bogdanm 0:9b334a45a8ff 4643 #define HRTIM_FLTR_FLTLCK ((uint32_t)0x80000000) /*!< Fault sources lock */
bogdanm 0:9b334a45a8ff 4644
bogdanm 0:9b334a45a8ff 4645 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
bogdanm 0:9b334a45a8ff 4646 #define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/
bogdanm 0:9b334a45a8ff 4647 #define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/
bogdanm 0:9b334a45a8ff 4648 #define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/
bogdanm 0:9b334a45a8ff 4649 #define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/
bogdanm 0:9b334a45a8ff 4650 #define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/
bogdanm 0:9b334a45a8ff 4651 #define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/
bogdanm 0:9b334a45a8ff 4652 #define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */
bogdanm 0:9b334a45a8ff 4653 #define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */
bogdanm 0:9b334a45a8ff 4654 #define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */
bogdanm 0:9b334a45a8ff 4655 #define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */
bogdanm 0:9b334a45a8ff 4656 #define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */
bogdanm 0:9b334a45a8ff 4657 #define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */
bogdanm 0:9b334a45a8ff 4658 #define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */
bogdanm 0:9b334a45a8ff 4659 #define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */
bogdanm 0:9b334a45a8ff 4660 #define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */
bogdanm 0:9b334a45a8ff 4661 #define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */
bogdanm 0:9b334a45a8ff 4662 #define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */
bogdanm 0:9b334a45a8ff 4663 #define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */
bogdanm 0:9b334a45a8ff 4664 #define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */
bogdanm 0:9b334a45a8ff 4665 #define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */
bogdanm 0:9b334a45a8ff 4666 #define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */
bogdanm 0:9b334a45a8ff 4667 #define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */
bogdanm 0:9b334a45a8ff 4668
bogdanm 0:9b334a45a8ff 4669 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
bogdanm 0:9b334a45a8ff 4670 #define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */
bogdanm 0:9b334a45a8ff 4671 #define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */
bogdanm 0:9b334a45a8ff 4672 #define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */
bogdanm 0:9b334a45a8ff 4673 #define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */
bogdanm 0:9b334a45a8ff 4674 #define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */
bogdanm 0:9b334a45a8ff 4675 #define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */
bogdanm 0:9b334a45a8ff 4676 #define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */
bogdanm 0:9b334a45a8ff 4677 #define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */
bogdanm 0:9b334a45a8ff 4678 #define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */
bogdanm 0:9b334a45a8ff 4679 #define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */
bogdanm 0:9b334a45a8ff 4680 #define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */
bogdanm 0:9b334a45a8ff 4681 #define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */
bogdanm 0:9b334a45a8ff 4682
bogdanm 0:9b334a45a8ff 4683 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
bogdanm 0:9b334a45a8ff 4684 #define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */
bogdanm 0:9b334a45a8ff 4685 #define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */
bogdanm 0:9b334a45a8ff 4686 #define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */
bogdanm 0:9b334a45a8ff 4687 #define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */
bogdanm 0:9b334a45a8ff 4688 #define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */
bogdanm 0:9b334a45a8ff 4689 #define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */
bogdanm 0:9b334a45a8ff 4690 #define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */
bogdanm 0:9b334a45a8ff 4691 #define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */
bogdanm 0:9b334a45a8ff 4692
bogdanm 0:9b334a45a8ff 4693 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
bogdanm 0:9b334a45a8ff 4694 #define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4695 #define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4696 #define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4697 #define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4698 #define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */
bogdanm 0:9b334a45a8ff 4699 #define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */
bogdanm 0:9b334a45a8ff 4700 #define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */
bogdanm 0:9b334a45a8ff 4701 #define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */
bogdanm 0:9b334a45a8ff 4702
bogdanm 0:9b334a45a8ff 4703 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
bogdanm 0:9b334a45a8ff 4704 #define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */
bogdanm 0:9b334a45a8ff 4705 #define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */
bogdanm 0:9b334a45a8ff 4706 #define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */
bogdanm 0:9b334a45a8ff 4707 #define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */
bogdanm 0:9b334a45a8ff 4708 #define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */
bogdanm 0:9b334a45a8ff 4709 #define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */
bogdanm 0:9b334a45a8ff 4710 #define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */
bogdanm 0:9b334a45a8ff 4711 #define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */
bogdanm 0:9b334a45a8ff 4712
bogdanm 0:9b334a45a8ff 4713 /**** Bit definition for Common HRTIM Timer output enable register ************/
bogdanm 0:9b334a45a8ff 4714 #define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */
bogdanm 0:9b334a45a8ff 4715 #define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */
bogdanm 0:9b334a45a8ff 4716 #define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */
bogdanm 0:9b334a45a8ff 4717 #define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */
bogdanm 0:9b334a45a8ff 4718 #define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */
bogdanm 0:9b334a45a8ff 4719 #define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */
bogdanm 0:9b334a45a8ff 4720 #define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */
bogdanm 0:9b334a45a8ff 4721 #define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */
bogdanm 0:9b334a45a8ff 4722 #define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */
bogdanm 0:9b334a45a8ff 4723 #define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */
bogdanm 0:9b334a45a8ff 4724
bogdanm 0:9b334a45a8ff 4725 /**** Bit definition for Common HRTIM Timer output disable register ***********/
bogdanm 0:9b334a45a8ff 4726 #define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */
bogdanm 0:9b334a45a8ff 4727 #define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */
bogdanm 0:9b334a45a8ff 4728 #define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */
bogdanm 0:9b334a45a8ff 4729 #define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */
bogdanm 0:9b334a45a8ff 4730 #define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */
bogdanm 0:9b334a45a8ff 4731 #define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */
bogdanm 0:9b334a45a8ff 4732 #define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */
bogdanm 0:9b334a45a8ff 4733 #define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */
bogdanm 0:9b334a45a8ff 4734 #define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */
bogdanm 0:9b334a45a8ff 4735 #define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */
bogdanm 0:9b334a45a8ff 4736
bogdanm 0:9b334a45a8ff 4737 /**** Bit definition for Common HRTIM Timer output disable status register *****/
bogdanm 0:9b334a45a8ff 4738 #define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */
bogdanm 0:9b334a45a8ff 4739 #define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */
bogdanm 0:9b334a45a8ff 4740 #define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */
bogdanm 0:9b334a45a8ff 4741 #define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */
bogdanm 0:9b334a45a8ff 4742 #define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */
bogdanm 0:9b334a45a8ff 4743 #define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */
bogdanm 0:9b334a45a8ff 4744 #define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */
bogdanm 0:9b334a45a8ff 4745 #define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */
bogdanm 0:9b334a45a8ff 4746 #define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */
bogdanm 0:9b334a45a8ff 4747 #define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */
bogdanm 0:9b334a45a8ff 4748
bogdanm 0:9b334a45a8ff 4749 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
bogdanm 0:9b334a45a8ff 4750 #define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enbale */
bogdanm 0:9b334a45a8ff 4751 #define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */
bogdanm 0:9b334a45a8ff 4752 #define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */
bogdanm 0:9b334a45a8ff 4753 #define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */
bogdanm 0:9b334a45a8ff 4754 #define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */
bogdanm 0:9b334a45a8ff 4755 #define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */
bogdanm 0:9b334a45a8ff 4756 #define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */
bogdanm 0:9b334a45a8ff 4757 #define HRTIM_BMCR_BMPRSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */
bogdanm 0:9b334a45a8ff 4758 #define HRTIM_BMCR_BMPRSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */
bogdanm 0:9b334a45a8ff 4759 #define HRTIM_BMCR_BMPRSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */
bogdanm 0:9b334a45a8ff 4760 #define HRTIM_BMCR_BMPRSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */
bogdanm 0:9b334a45a8ff 4761 #define HRTIM_BMCR_BMPRSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */
bogdanm 0:9b334a45a8ff 4762 #define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */
bogdanm 0:9b334a45a8ff 4763 #define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */
bogdanm 0:9b334a45a8ff 4764 #define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */
bogdanm 0:9b334a45a8ff 4765 #define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */
bogdanm 0:9b334a45a8ff 4766 #define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */
bogdanm 0:9b334a45a8ff 4767 #define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */
bogdanm 0:9b334a45a8ff 4768 #define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */
bogdanm 0:9b334a45a8ff 4769 #define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */
bogdanm 0:9b334a45a8ff 4770
bogdanm 0:9b334a45a8ff 4771 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
bogdanm 0:9b334a45a8ff 4772 #define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */
bogdanm 0:9b334a45a8ff 4773 #define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */
bogdanm 0:9b334a45a8ff 4774 #define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */
bogdanm 0:9b334a45a8ff 4775 #define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */
bogdanm 0:9b334a45a8ff 4776 #define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */
bogdanm 0:9b334a45a8ff 4777 #define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */
bogdanm 0:9b334a45a8ff 4778 #define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */
bogdanm 0:9b334a45a8ff 4779 #define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */
bogdanm 0:9b334a45a8ff 4780 #define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */
bogdanm 0:9b334a45a8ff 4781 #define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */
bogdanm 0:9b334a45a8ff 4782 #define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4783 #define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */
bogdanm 0:9b334a45a8ff 4784 #define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */
bogdanm 0:9b334a45a8ff 4785 #define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */
bogdanm 0:9b334a45a8ff 4786 #define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4787 #define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */
bogdanm 0:9b334a45a8ff 4788 #define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */
bogdanm 0:9b334a45a8ff 4789 #define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */
bogdanm 0:9b334a45a8ff 4790 #define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4791 #define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */
bogdanm 0:9b334a45a8ff 4792 #define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */
bogdanm 0:9b334a45a8ff 4793 #define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */
bogdanm 0:9b334a45a8ff 4794 #define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4795 #define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */
bogdanm 0:9b334a45a8ff 4796 #define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */
bogdanm 0:9b334a45a8ff 4797 #define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */
bogdanm 0:9b334a45a8ff 4798 #define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4799 #define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */
bogdanm 0:9b334a45a8ff 4800 #define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */
bogdanm 0:9b334a45a8ff 4801 #define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */
bogdanm 0:9b334a45a8ff 4802 #define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */
bogdanm 0:9b334a45a8ff 4803 #define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */
bogdanm 0:9b334a45a8ff 4804
bogdanm 0:9b334a45a8ff 4805 /******************* Bit definition for HRTIM_BMCMPR register ***************/
bogdanm 0:9b334a45a8ff 4806 #define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */
bogdanm 0:9b334a45a8ff 4807
bogdanm 0:9b334a45a8ff 4808 /******************* Bit definition for HRTIM_BMPER register ****************/
bogdanm 0:9b334a45a8ff 4809 #define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */
bogdanm 0:9b334a45a8ff 4810
bogdanm 0:9b334a45a8ff 4811 /******************* Bit definition for HRTIM_EECR1 register ****************/
bogdanm 0:9b334a45a8ff 4812 #define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */
bogdanm 0:9b334a45a8ff 4813 #define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */
bogdanm 0:9b334a45a8ff 4814 #define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */
bogdanm 0:9b334a45a8ff 4815 #define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */
bogdanm 0:9b334a45a8ff 4816 #define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */
bogdanm 0:9b334a45a8ff 4817 #define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4818 #define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4819 #define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */
bogdanm 0:9b334a45a8ff 4820
bogdanm 0:9b334a45a8ff 4821 #define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */
bogdanm 0:9b334a45a8ff 4822 #define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */
bogdanm 0:9b334a45a8ff 4823 #define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */
bogdanm 0:9b334a45a8ff 4824 #define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */
bogdanm 0:9b334a45a8ff 4825 #define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */
bogdanm 0:9b334a45a8ff 4826 #define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4827 #define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4828 #define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */
bogdanm 0:9b334a45a8ff 4829
bogdanm 0:9b334a45a8ff 4830 #define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */
bogdanm 0:9b334a45a8ff 4831 #define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */
bogdanm 0:9b334a45a8ff 4832 #define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */
bogdanm 0:9b334a45a8ff 4833 #define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */
bogdanm 0:9b334a45a8ff 4834 #define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */
bogdanm 0:9b334a45a8ff 4835 #define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4836 #define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4837 #define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */
bogdanm 0:9b334a45a8ff 4838
bogdanm 0:9b334a45a8ff 4839 #define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */
bogdanm 0:9b334a45a8ff 4840 #define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */
bogdanm 0:9b334a45a8ff 4841 #define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */
bogdanm 0:9b334a45a8ff 4842 #define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */
bogdanm 0:9b334a45a8ff 4843 #define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */
bogdanm 0:9b334a45a8ff 4844 #define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4845 #define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4846 #define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */
bogdanm 0:9b334a45a8ff 4847
bogdanm 0:9b334a45a8ff 4848 #define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */
bogdanm 0:9b334a45a8ff 4849 #define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */
bogdanm 0:9b334a45a8ff 4850 #define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */
bogdanm 0:9b334a45a8ff 4851 #define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */
bogdanm 0:9b334a45a8ff 4852 #define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */
bogdanm 0:9b334a45a8ff 4853 #define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4854 #define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4855 #define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */
bogdanm 0:9b334a45a8ff 4856
bogdanm 0:9b334a45a8ff 4857 /******************* Bit definition for HRTIM_EECR2 register ****************/
bogdanm 0:9b334a45a8ff 4858 #define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */
bogdanm 0:9b334a45a8ff 4859 #define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */
bogdanm 0:9b334a45a8ff 4860 #define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */
bogdanm 0:9b334a45a8ff 4861 #define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */
bogdanm 0:9b334a45a8ff 4862 #define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */
bogdanm 0:9b334a45a8ff 4863 #define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4864 #define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4865
bogdanm 0:9b334a45a8ff 4866 #define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */
bogdanm 0:9b334a45a8ff 4867 #define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */
bogdanm 0:9b334a45a8ff 4868 #define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */
bogdanm 0:9b334a45a8ff 4869 #define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */
bogdanm 0:9b334a45a8ff 4870 #define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */
bogdanm 0:9b334a45a8ff 4871 #define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4872 #define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4873
bogdanm 0:9b334a45a8ff 4874 #define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */
bogdanm 0:9b334a45a8ff 4875 #define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */
bogdanm 0:9b334a45a8ff 4876 #define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */
bogdanm 0:9b334a45a8ff 4877 #define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */
bogdanm 0:9b334a45a8ff 4878 #define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */
bogdanm 0:9b334a45a8ff 4879 #define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4880 #define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4881
bogdanm 0:9b334a45a8ff 4882 #define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */
bogdanm 0:9b334a45a8ff 4883 #define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */
bogdanm 0:9b334a45a8ff 4884 #define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */
bogdanm 0:9b334a45a8ff 4885 #define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */
bogdanm 0:9b334a45a8ff 4886 #define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */
bogdanm 0:9b334a45a8ff 4887 #define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4888 #define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4889
bogdanm 0:9b334a45a8ff 4890 #define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */
bogdanm 0:9b334a45a8ff 4891 #define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */
bogdanm 0:9b334a45a8ff 4892 #define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */
bogdanm 0:9b334a45a8ff 4893 #define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */
bogdanm 0:9b334a45a8ff 4894 #define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */
bogdanm 0:9b334a45a8ff 4895 #define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */
bogdanm 0:9b334a45a8ff 4896 #define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */
bogdanm 0:9b334a45a8ff 4897
bogdanm 0:9b334a45a8ff 4898 /******************* Bit definition for HRTIM_EECR3 register ****************/
bogdanm 0:9b334a45a8ff 4899 #define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */
bogdanm 0:9b334a45a8ff 4900 #define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */
bogdanm 0:9b334a45a8ff 4901 #define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */
bogdanm 0:9b334a45a8ff 4902 #define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */
bogdanm 0:9b334a45a8ff 4903 #define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */
bogdanm 0:9b334a45a8ff 4904 #define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */
bogdanm 0:9b334a45a8ff 4905 #define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */
bogdanm 0:9b334a45a8ff 4906 #define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */
bogdanm 0:9b334a45a8ff 4907 #define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */
bogdanm 0:9b334a45a8ff 4908 #define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */
bogdanm 0:9b334a45a8ff 4909 #define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */
bogdanm 0:9b334a45a8ff 4910 #define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */
bogdanm 0:9b334a45a8ff 4911 #define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */
bogdanm 0:9b334a45a8ff 4912 #define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */
bogdanm 0:9b334a45a8ff 4913 #define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */
bogdanm 0:9b334a45a8ff 4914 #define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */
bogdanm 0:9b334a45a8ff 4915 #define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */
bogdanm 0:9b334a45a8ff 4916 #define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */
bogdanm 0:9b334a45a8ff 4917 #define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */
bogdanm 0:9b334a45a8ff 4918 #define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */
bogdanm 0:9b334a45a8ff 4919 #define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */
bogdanm 0:9b334a45a8ff 4920 #define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */
bogdanm 0:9b334a45a8ff 4921 #define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */
bogdanm 0:9b334a45a8ff 4922 #define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */
bogdanm 0:9b334a45a8ff 4923 #define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */
bogdanm 0:9b334a45a8ff 4924 #define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */
bogdanm 0:9b334a45a8ff 4925 #define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */
bogdanm 0:9b334a45a8ff 4926 #define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */
bogdanm 0:9b334a45a8ff 4927
bogdanm 0:9b334a45a8ff 4928 /******************* Bit definition for HRTIM_ADC1R register ****************/
bogdanm 0:9b334a45a8ff 4929 #define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */
bogdanm 0:9b334a45a8ff 4930 #define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */
bogdanm 0:9b334a45a8ff 4931 #define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */
bogdanm 0:9b334a45a8ff 4932 #define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */
bogdanm 0:9b334a45a8ff 4933 #define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */
bogdanm 0:9b334a45a8ff 4934 #define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */
bogdanm 0:9b334a45a8ff 4935 #define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */
bogdanm 0:9b334a45a8ff 4936 #define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */
bogdanm 0:9b334a45a8ff 4937 #define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */
bogdanm 0:9b334a45a8ff 4938 #define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */
bogdanm 0:9b334a45a8ff 4939 #define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4940 #define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4941 #define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */
bogdanm 0:9b334a45a8ff 4942 #define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */
bogdanm 0:9b334a45a8ff 4943 #define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */
bogdanm 0:9b334a45a8ff 4944 #define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4945 #define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */
bogdanm 0:9b334a45a8ff 4946 #define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */
bogdanm 0:9b334a45a8ff 4947 #define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */
bogdanm 0:9b334a45a8ff 4948 #define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */
bogdanm 0:9b334a45a8ff 4949 #define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4950 #define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */
bogdanm 0:9b334a45a8ff 4951 #define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */
bogdanm 0:9b334a45a8ff 4952 #define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */
bogdanm 0:9b334a45a8ff 4953 #define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4954 #define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */
bogdanm 0:9b334a45a8ff 4955 #define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */
bogdanm 0:9b334a45a8ff 4956 #define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */
bogdanm 0:9b334a45a8ff 4957 #define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4958 #define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */
bogdanm 0:9b334a45a8ff 4959 #define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */
bogdanm 0:9b334a45a8ff 4960 #define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */
bogdanm 0:9b334a45a8ff 4961
bogdanm 0:9b334a45a8ff 4962 /******************* Bit definition for HRTIM_ADC2R register ****************/
bogdanm 0:9b334a45a8ff 4963 #define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */
bogdanm 0:9b334a45a8ff 4964 #define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */
bogdanm 0:9b334a45a8ff 4965 #define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */
bogdanm 0:9b334a45a8ff 4966 #define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */
bogdanm 0:9b334a45a8ff 4967 #define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */
bogdanm 0:9b334a45a8ff 4968 #define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */
bogdanm 0:9b334a45a8ff 4969 #define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */
bogdanm 0:9b334a45a8ff 4970 #define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */
bogdanm 0:9b334a45a8ff 4971 #define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */
bogdanm 0:9b334a45a8ff 4972 #define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */
bogdanm 0:9b334a45a8ff 4973 #define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */
bogdanm 0:9b334a45a8ff 4974 #define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */
bogdanm 0:9b334a45a8ff 4975 #define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/
bogdanm 0:9b334a45a8ff 4976 #define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */
bogdanm 0:9b334a45a8ff 4977 #define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */
bogdanm 0:9b334a45a8ff 4978 #define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */
bogdanm 0:9b334a45a8ff 4979 #define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */
bogdanm 0:9b334a45a8ff 4980 #define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */
bogdanm 0:9b334a45a8ff 4981 #define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */
bogdanm 0:9b334a45a8ff 4982 #define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */
bogdanm 0:9b334a45a8ff 4983 #define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */
bogdanm 0:9b334a45a8ff 4984 #define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */
bogdanm 0:9b334a45a8ff 4985 #define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */
bogdanm 0:9b334a45a8ff 4986 #define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */
bogdanm 0:9b334a45a8ff 4987 #define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */
bogdanm 0:9b334a45a8ff 4988 #define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/
bogdanm 0:9b334a45a8ff 4989 #define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */
bogdanm 0:9b334a45a8ff 4990 #define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */
bogdanm 0:9b334a45a8ff 4991 #define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */
bogdanm 0:9b334a45a8ff 4992 #define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */
bogdanm 0:9b334a45a8ff 4993 #define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */
bogdanm 0:9b334a45a8ff 4994 #define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */
bogdanm 0:9b334a45a8ff 4995
bogdanm 0:9b334a45a8ff 4996 /******************* Bit definition for HRTIM_ADC3R register ****************/
bogdanm 0:9b334a45a8ff 4997 #define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */
bogdanm 0:9b334a45a8ff 4998 #define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */
bogdanm 0:9b334a45a8ff 4999 #define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */
bogdanm 0:9b334a45a8ff 5000 #define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */
bogdanm 0:9b334a45a8ff 5001 #define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */
bogdanm 0:9b334a45a8ff 5002 #define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */
bogdanm 0:9b334a45a8ff 5003 #define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */
bogdanm 0:9b334a45a8ff 5004 #define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */
bogdanm 0:9b334a45a8ff 5005 #define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */
bogdanm 0:9b334a45a8ff 5006 #define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */
bogdanm 0:9b334a45a8ff 5007 #define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */
bogdanm 0:9b334a45a8ff 5008 #define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */
bogdanm 0:9b334a45a8ff 5009 #define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */
bogdanm 0:9b334a45a8ff 5010 #define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */
bogdanm 0:9b334a45a8ff 5011 #define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */
bogdanm 0:9b334a45a8ff 5012 #define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */
bogdanm 0:9b334a45a8ff 5013 #define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */
bogdanm 0:9b334a45a8ff 5014 #define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */
bogdanm 0:9b334a45a8ff 5015 #define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */
bogdanm 0:9b334a45a8ff 5016 #define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */
bogdanm 0:9b334a45a8ff 5017 #define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */
bogdanm 0:9b334a45a8ff 5018 #define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */
bogdanm 0:9b334a45a8ff 5019 #define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */
bogdanm 0:9b334a45a8ff 5020 #define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */
bogdanm 0:9b334a45a8ff 5021 #define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */
bogdanm 0:9b334a45a8ff 5022 #define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */
bogdanm 0:9b334a45a8ff 5023 #define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */
bogdanm 0:9b334a45a8ff 5024 #define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */
bogdanm 0:9b334a45a8ff 5025 #define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */
bogdanm 0:9b334a45a8ff 5026 #define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */
bogdanm 0:9b334a45a8ff 5027 #define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */
bogdanm 0:9b334a45a8ff 5028 #define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */
bogdanm 0:9b334a45a8ff 5029
bogdanm 0:9b334a45a8ff 5030 /******************* Bit definition for HRTIM_ADC4R register ****************/
bogdanm 0:9b334a45a8ff 5031 #define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */
bogdanm 0:9b334a45a8ff 5032 #define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */
bogdanm 0:9b334a45a8ff 5033 #define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */
bogdanm 0:9b334a45a8ff 5034 #define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */
bogdanm 0:9b334a45a8ff 5035 #define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */
bogdanm 0:9b334a45a8ff 5036 #define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */
bogdanm 0:9b334a45a8ff 5037 #define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */
bogdanm 0:9b334a45a8ff 5038 #define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */
bogdanm 0:9b334a45a8ff 5039 #define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */
bogdanm 0:9b334a45a8ff 5040 #define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */
bogdanm 0:9b334a45a8ff 5041 #define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */
bogdanm 0:9b334a45a8ff 5042 #define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */
bogdanm 0:9b334a45a8ff 5043 #define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/
bogdanm 0:9b334a45a8ff 5044 #define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */
bogdanm 0:9b334a45a8ff 5045 #define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */
bogdanm 0:9b334a45a8ff 5046 #define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */
bogdanm 0:9b334a45a8ff 5047 #define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */
bogdanm 0:9b334a45a8ff 5048 #define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */
bogdanm 0:9b334a45a8ff 5049 #define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */
bogdanm 0:9b334a45a8ff 5050 #define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */
bogdanm 0:9b334a45a8ff 5051 #define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */
bogdanm 0:9b334a45a8ff 5052 #define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */
bogdanm 0:9b334a45a8ff 5053 #define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */
bogdanm 0:9b334a45a8ff 5054 #define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */
bogdanm 0:9b334a45a8ff 5055 #define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */
bogdanm 0:9b334a45a8ff 5056 #define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/
bogdanm 0:9b334a45a8ff 5057 #define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */
bogdanm 0:9b334a45a8ff 5058 #define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */
bogdanm 0:9b334a45a8ff 5059 #define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */
bogdanm 0:9b334a45a8ff 5060 #define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */
bogdanm 0:9b334a45a8ff 5061 #define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */
bogdanm 0:9b334a45a8ff 5062 #define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */
bogdanm 0:9b334a45a8ff 5063
bogdanm 0:9b334a45a8ff 5064 /******************* Bit definition for HRTIM_DLLCR register ****************/
bogdanm 0:9b334a45a8ff 5065 #define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */
bogdanm 0:9b334a45a8ff 5066 #define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */
bogdanm 0:9b334a45a8ff 5067 #define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */
bogdanm 0:9b334a45a8ff 5068 #define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */
bogdanm 0:9b334a45a8ff 5069 #define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */
bogdanm 0:9b334a45a8ff 5070
bogdanm 0:9b334a45a8ff 5071 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
bogdanm 0:9b334a45a8ff 5072 #define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */
bogdanm 0:9b334a45a8ff 5073 #define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */
bogdanm 0:9b334a45a8ff 5074 #define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */
bogdanm 0:9b334a45a8ff 5075 #define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */
bogdanm 0:9b334a45a8ff 5076 #define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */
bogdanm 0:9b334a45a8ff 5077 #define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */
bogdanm 0:9b334a45a8ff 5078 #define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */
bogdanm 0:9b334a45a8ff 5079 #define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */
bogdanm 0:9b334a45a8ff 5080 #define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */
bogdanm 0:9b334a45a8ff 5081
bogdanm 0:9b334a45a8ff 5082 #define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */
bogdanm 0:9b334a45a8ff 5083 #define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */
bogdanm 0:9b334a45a8ff 5084 #define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */
bogdanm 0:9b334a45a8ff 5085 #define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */
bogdanm 0:9b334a45a8ff 5086 #define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */
bogdanm 0:9b334a45a8ff 5087 #define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */
bogdanm 0:9b334a45a8ff 5088 #define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */
bogdanm 0:9b334a45a8ff 5089 #define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */
bogdanm 0:9b334a45a8ff 5090 #define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */
bogdanm 0:9b334a45a8ff 5091
bogdanm 0:9b334a45a8ff 5092 #define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */
bogdanm 0:9b334a45a8ff 5093 #define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */
bogdanm 0:9b334a45a8ff 5094 #define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */
bogdanm 0:9b334a45a8ff 5095 #define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */
bogdanm 0:9b334a45a8ff 5096 #define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */
bogdanm 0:9b334a45a8ff 5097 #define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */
bogdanm 0:9b334a45a8ff 5098 #define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */
bogdanm 0:9b334a45a8ff 5099 #define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */
bogdanm 0:9b334a45a8ff 5100 #define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */
bogdanm 0:9b334a45a8ff 5101
bogdanm 0:9b334a45a8ff 5102 #define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */
bogdanm 0:9b334a45a8ff 5103 #define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */
bogdanm 0:9b334a45a8ff 5104 #define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */
bogdanm 0:9b334a45a8ff 5105 #define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */
bogdanm 0:9b334a45a8ff 5106 #define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */
bogdanm 0:9b334a45a8ff 5107 #define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */
bogdanm 0:9b334a45a8ff 5108 #define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */
bogdanm 0:9b334a45a8ff 5109 #define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */
bogdanm 0:9b334a45a8ff 5110 #define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */
bogdanm 0:9b334a45a8ff 5111
bogdanm 0:9b334a45a8ff 5112 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
bogdanm 0:9b334a45a8ff 5113 #define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */
bogdanm 0:9b334a45a8ff 5114 #define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */
bogdanm 0:9b334a45a8ff 5115 #define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */
bogdanm 0:9b334a45a8ff 5116 #define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */
bogdanm 0:9b334a45a8ff 5117 #define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */
bogdanm 0:9b334a45a8ff 5118 #define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */
bogdanm 0:9b334a45a8ff 5119 #define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */
bogdanm 0:9b334a45a8ff 5120 #define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */
bogdanm 0:9b334a45a8ff 5121 #define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */
bogdanm 0:9b334a45a8ff 5122 #define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */
bogdanm 0:9b334a45a8ff 5123 #define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */
bogdanm 0:9b334a45a8ff 5124 #define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */
bogdanm 0:9b334a45a8ff 5125
bogdanm 0:9b334a45a8ff 5126 /******************* Bit definition for HRTIM_BDMUPR register ***************/
bogdanm 0:9b334a45a8ff 5127 #define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */
bogdanm 0:9b334a45a8ff 5128 #define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */
bogdanm 0:9b334a45a8ff 5129 #define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */
bogdanm 0:9b334a45a8ff 5130 #define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */
bogdanm 0:9b334a45a8ff 5131 #define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */
bogdanm 0:9b334a45a8ff 5132 #define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */
bogdanm 0:9b334a45a8ff 5133 #define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */
bogdanm 0:9b334a45a8ff 5134 #define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */
bogdanm 0:9b334a45a8ff 5135 #define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */
bogdanm 0:9b334a45a8ff 5136 #define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */
bogdanm 0:9b334a45a8ff 5137
bogdanm 0:9b334a45a8ff 5138 /******************* Bit definition for HRTIM_BDTUPR register ***************/
bogdanm 0:9b334a45a8ff 5139 #define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */
bogdanm 0:9b334a45a8ff 5140 #define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */
bogdanm 0:9b334a45a8ff 5141 #define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */
bogdanm 0:9b334a45a8ff 5142 #define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */
bogdanm 0:9b334a45a8ff 5143 #define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */
bogdanm 0:9b334a45a8ff 5144 #define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */
bogdanm 0:9b334a45a8ff 5145 #define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */
bogdanm 0:9b334a45a8ff 5146 #define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */
bogdanm 0:9b334a45a8ff 5147 #define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */
bogdanm 0:9b334a45a8ff 5148 #define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */
bogdanm 0:9b334a45a8ff 5149 #define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */
bogdanm 0:9b334a45a8ff 5150 #define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */
bogdanm 0:9b334a45a8ff 5151 #define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */
bogdanm 0:9b334a45a8ff 5152 #define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */
bogdanm 0:9b334a45a8ff 5153 #define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */
bogdanm 0:9b334a45a8ff 5154 #define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */
bogdanm 0:9b334a45a8ff 5155 #define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */
bogdanm 0:9b334a45a8ff 5156 #define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */
bogdanm 0:9b334a45a8ff 5157 #define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */
bogdanm 0:9b334a45a8ff 5158 #define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */
bogdanm 0:9b334a45a8ff 5159 #define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */
bogdanm 0:9b334a45a8ff 5160
bogdanm 0:9b334a45a8ff 5161 /******************* Bit definition for HRTIM_BDMADR register ***************/
bogdanm 0:9b334a45a8ff 5162 #define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */
bogdanm 0:9b334a45a8ff 5163
bogdanm 0:9b334a45a8ff 5164 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5165 /* */
bogdanm 0:9b334a45a8ff 5166 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 0:9b334a45a8ff 5167 /* */
bogdanm 0:9b334a45a8ff 5168 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5169 /******************* Bit definition for I2C_CR1 register *******************/
bogdanm 0:9b334a45a8ff 5170 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
bogdanm 0:9b334a45a8ff 5171 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
bogdanm 0:9b334a45a8ff 5172 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
bogdanm 0:9b334a45a8ff 5173 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
bogdanm 0:9b334a45a8ff 5174 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
bogdanm 0:9b334a45a8ff 5175 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
bogdanm 0:9b334a45a8ff 5176 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
bogdanm 0:9b334a45a8ff 5177 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
bogdanm 0:9b334a45a8ff 5178 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
bogdanm 0:9b334a45a8ff 5179 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
bogdanm 0:9b334a45a8ff 5180 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
bogdanm 0:9b334a45a8ff 5181 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
bogdanm 0:9b334a45a8ff 5182 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
bogdanm 0:9b334a45a8ff 5183 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
bogdanm 0:9b334a45a8ff 5184 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
bogdanm 0:9b334a45a8ff 5185 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
bogdanm 0:9b334a45a8ff 5186 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
bogdanm 0:9b334a45a8ff 5187 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
bogdanm 0:9b334a45a8ff 5188 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
bogdanm 0:9b334a45a8ff 5189 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
bogdanm 0:9b334a45a8ff 5190 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
bogdanm 0:9b334a45a8ff 5191
bogdanm 0:9b334a45a8ff 5192 /****************** Bit definition for I2C_CR2 register ********************/
bogdanm 0:9b334a45a8ff 5193 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
bogdanm 0:9b334a45a8ff 5194 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
bogdanm 0:9b334a45a8ff 5195 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
bogdanm 0:9b334a45a8ff 5196 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
bogdanm 0:9b334a45a8ff 5197 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
bogdanm 0:9b334a45a8ff 5198 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
bogdanm 0:9b334a45a8ff 5199 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
bogdanm 0:9b334a45a8ff 5200 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
bogdanm 0:9b334a45a8ff 5201 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
bogdanm 0:9b334a45a8ff 5202 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
bogdanm 0:9b334a45a8ff 5203 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
bogdanm 0:9b334a45a8ff 5204
bogdanm 0:9b334a45a8ff 5205 /******************* Bit definition for I2C_OAR1 register ******************/
bogdanm 0:9b334a45a8ff 5206 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
bogdanm 0:9b334a45a8ff 5207 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
bogdanm 0:9b334a45a8ff 5208 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
bogdanm 0:9b334a45a8ff 5209
bogdanm 0:9b334a45a8ff 5210 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 0:9b334a45a8ff 5211 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
bogdanm 0:9b334a45a8ff 5212 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
bogdanm 0:9b334a45a8ff 5213 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
bogdanm 0:9b334a45a8ff 5214
bogdanm 0:9b334a45a8ff 5215 /******************* Bit definition for I2C_TIMINGR register *****************/
bogdanm 0:9b334a45a8ff 5216 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
bogdanm 0:9b334a45a8ff 5217 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
bogdanm 0:9b334a45a8ff 5218 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
bogdanm 0:9b334a45a8ff 5219 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
bogdanm 0:9b334a45a8ff 5220 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
bogdanm 0:9b334a45a8ff 5221
bogdanm 0:9b334a45a8ff 5222 /******************* Bit definition for I2C_TIMEOUTR register *****************/
bogdanm 0:9b334a45a8ff 5223 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
bogdanm 0:9b334a45a8ff 5224 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
bogdanm 0:9b334a45a8ff 5225 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
bogdanm 0:9b334a45a8ff 5226 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
bogdanm 0:9b334a45a8ff 5227 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
bogdanm 0:9b334a45a8ff 5228
bogdanm 0:9b334a45a8ff 5229 /****************** Bit definition for I2C_ISR register *********************/
bogdanm 0:9b334a45a8ff 5230 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
bogdanm 0:9b334a45a8ff 5231 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
bogdanm 0:9b334a45a8ff 5232 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
bogdanm 0:9b334a45a8ff 5233 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
bogdanm 0:9b334a45a8ff 5234 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
bogdanm 0:9b334a45a8ff 5235 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
bogdanm 0:9b334a45a8ff 5236 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
bogdanm 0:9b334a45a8ff 5237 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
bogdanm 0:9b334a45a8ff 5238 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
bogdanm 0:9b334a45a8ff 5239 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
bogdanm 0:9b334a45a8ff 5240 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
bogdanm 0:9b334a45a8ff 5241 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
bogdanm 0:9b334a45a8ff 5242 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
bogdanm 0:9b334a45a8ff 5243 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
bogdanm 0:9b334a45a8ff 5244 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
bogdanm 0:9b334a45a8ff 5245 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
bogdanm 0:9b334a45a8ff 5246 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
bogdanm 0:9b334a45a8ff 5247
bogdanm 0:9b334a45a8ff 5248 /****************** Bit definition for I2C_ICR register *********************/
bogdanm 0:9b334a45a8ff 5249 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
bogdanm 0:9b334a45a8ff 5250 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
bogdanm 0:9b334a45a8ff 5251 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
bogdanm 0:9b334a45a8ff 5252 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
bogdanm 0:9b334a45a8ff 5253 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
bogdanm 0:9b334a45a8ff 5254 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
bogdanm 0:9b334a45a8ff 5255 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
bogdanm 0:9b334a45a8ff 5256 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
bogdanm 0:9b334a45a8ff 5257 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
bogdanm 0:9b334a45a8ff 5258
bogdanm 0:9b334a45a8ff 5259 /****************** Bit definition for I2C_PECR register ********************/
bogdanm 0:9b334a45a8ff 5260 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
bogdanm 0:9b334a45a8ff 5261
bogdanm 0:9b334a45a8ff 5262 /****************** Bit definition for I2C_RXDR register *********************/
bogdanm 0:9b334a45a8ff 5263 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
bogdanm 0:9b334a45a8ff 5264
bogdanm 0:9b334a45a8ff 5265 /****************** Bit definition for I2C_TXDR register *********************/
bogdanm 0:9b334a45a8ff 5266 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
bogdanm 0:9b334a45a8ff 5267
bogdanm 0:9b334a45a8ff 5268
bogdanm 0:9b334a45a8ff 5269 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5270 /* */
bogdanm 0:9b334a45a8ff 5271 /* Independent WATCHDOG (IWDG) */
bogdanm 0:9b334a45a8ff 5272 /* */
bogdanm 0:9b334a45a8ff 5273 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5274 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 0:9b334a45a8ff 5275 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
bogdanm 0:9b334a45a8ff 5276
bogdanm 0:9b334a45a8ff 5277 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 0:9b334a45a8ff 5278 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
bogdanm 0:9b334a45a8ff 5279 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5280 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5281 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5282
bogdanm 0:9b334a45a8ff 5283 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 0:9b334a45a8ff 5284 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
bogdanm 0:9b334a45a8ff 5285
bogdanm 0:9b334a45a8ff 5286 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 0:9b334a45a8ff 5287 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
bogdanm 0:9b334a45a8ff 5288 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
bogdanm 0:9b334a45a8ff 5289 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
bogdanm 0:9b334a45a8ff 5290
bogdanm 0:9b334a45a8ff 5291 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 0:9b334a45a8ff 5292 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
bogdanm 0:9b334a45a8ff 5293
bogdanm 0:9b334a45a8ff 5294 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5295 /* */
bogdanm 0:9b334a45a8ff 5296 /* Power Control */
bogdanm 0:9b334a45a8ff 5297 /* */
bogdanm 0:9b334a45a8ff 5298 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5299 /******************** Bit definition for PWR_CR register ********************/
bogdanm 0:9b334a45a8ff 5300 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
bogdanm 0:9b334a45a8ff 5301 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 0:9b334a45a8ff 5302 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 0:9b334a45a8ff 5303 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 0:9b334a45a8ff 5304 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 0:9b334a45a8ff 5305
bogdanm 0:9b334a45a8ff 5306 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 0:9b334a45a8ff 5307 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5308 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5309 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5310
bogdanm 0:9b334a45a8ff 5311 /*!< PVD level configuration */
bogdanm 0:9b334a45a8ff 5312 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 0:9b334a45a8ff 5313 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 0:9b334a45a8ff 5314 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 0:9b334a45a8ff 5315 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 0:9b334a45a8ff 5316 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 0:9b334a45a8ff 5317 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 0:9b334a45a8ff 5318 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 0:9b334a45a8ff 5319 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 0:9b334a45a8ff 5320
bogdanm 0:9b334a45a8ff 5321 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 0:9b334a45a8ff 5322
bogdanm 0:9b334a45a8ff 5323 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 0:9b334a45a8ff 5324 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 0:9b334a45a8ff 5325 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 0:9b334a45a8ff 5326 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 0:9b334a45a8ff 5327
bogdanm 0:9b334a45a8ff 5328 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
bogdanm 0:9b334a45a8ff 5329 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
bogdanm 0:9b334a45a8ff 5330 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
bogdanm 0:9b334a45a8ff 5331
bogdanm 0:9b334a45a8ff 5332 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5333 /* */
bogdanm 0:9b334a45a8ff 5334 /* Reset and Clock Control */
bogdanm 0:9b334a45a8ff 5335 /* */
bogdanm 0:9b334a45a8ff 5336 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5337 /******************** Bit definition for RCC_CR register ********************/
bogdanm 0:9b334a45a8ff 5338 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5339 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5340
bogdanm 0:9b334a45a8ff 5341 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 0:9b334a45a8ff 5342 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5343 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5344 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5345 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 0:9b334a45a8ff 5346 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 0:9b334a45a8ff 5347
bogdanm 0:9b334a45a8ff 5348 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 0:9b334a45a8ff 5349 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5350 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5351 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5352 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 0:9b334a45a8ff 5353 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 0:9b334a45a8ff 5354 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 0:9b334a45a8ff 5355 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 0:9b334a45a8ff 5356 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 0:9b334a45a8ff 5357
bogdanm 0:9b334a45a8ff 5358 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5359 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5360 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5361 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5362 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5363 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5364
bogdanm 0:9b334a45a8ff 5365 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 0:9b334a45a8ff 5366 /*!< SW configuration */
bogdanm 0:9b334a45a8ff 5367 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 0:9b334a45a8ff 5368 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5369 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5370
bogdanm 0:9b334a45a8ff 5371 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 0:9b334a45a8ff 5372 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 0:9b334a45a8ff 5373 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 0:9b334a45a8ff 5374
bogdanm 0:9b334a45a8ff 5375 /*!< SWS configuration */
bogdanm 0:9b334a45a8ff 5376 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 0:9b334a45a8ff 5377 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5378 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5379
bogdanm 0:9b334a45a8ff 5380 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 0:9b334a45a8ff 5381 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 0:9b334a45a8ff 5382 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 5383
bogdanm 0:9b334a45a8ff 5384 /*!< HPRE configuration */
bogdanm 0:9b334a45a8ff 5385 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 0:9b334a45a8ff 5386 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5387 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5388 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5389 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 5390
bogdanm 0:9b334a45a8ff 5391 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 0:9b334a45a8ff 5392 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 0:9b334a45a8ff 5393 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 0:9b334a45a8ff 5394 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 0:9b334a45a8ff 5395 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 0:9b334a45a8ff 5396 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 0:9b334a45a8ff 5397 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 0:9b334a45a8ff 5398 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 0:9b334a45a8ff 5399 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 0:9b334a45a8ff 5400
bogdanm 0:9b334a45a8ff 5401 /*!< PPRE1 configuration */
bogdanm 0:9b334a45a8ff 5402 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 0:9b334a45a8ff 5403 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5404 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5405 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5406
bogdanm 0:9b334a45a8ff 5407 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 0:9b334a45a8ff 5408 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
bogdanm 0:9b334a45a8ff 5409 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
bogdanm 0:9b334a45a8ff 5410 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
bogdanm 0:9b334a45a8ff 5411 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 5412
bogdanm 0:9b334a45a8ff 5413 /*!< PPRE2 configuration */
bogdanm 0:9b334a45a8ff 5414 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 0:9b334a45a8ff 5415 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5416 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5417 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5418
bogdanm 0:9b334a45a8ff 5419 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 0:9b334a45a8ff 5420 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
bogdanm 0:9b334a45a8ff 5421 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
bogdanm 0:9b334a45a8ff 5422 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
bogdanm 0:9b334a45a8ff 5423 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 5424
bogdanm 0:9b334a45a8ff 5425 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
bogdanm 0:9b334a45a8ff 5426 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 5427 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 5428
bogdanm 0:9b334a45a8ff 5429 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
bogdanm 0:9b334a45a8ff 5430 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
bogdanm 0:9b334a45a8ff 5431 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
bogdanm 0:9b334a45a8ff 5432
bogdanm 0:9b334a45a8ff 5433 /*!< PLLMUL configuration */
bogdanm 0:9b334a45a8ff 5434 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
bogdanm 0:9b334a45a8ff 5435 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5436 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5437 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5438 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 5439
bogdanm 0:9b334a45a8ff 5440 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
bogdanm 0:9b334a45a8ff 5441 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
bogdanm 0:9b334a45a8ff 5442 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
bogdanm 0:9b334a45a8ff 5443 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
bogdanm 0:9b334a45a8ff 5444 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
bogdanm 0:9b334a45a8ff 5445 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
bogdanm 0:9b334a45a8ff 5446 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
bogdanm 0:9b334a45a8ff 5447 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
bogdanm 0:9b334a45a8ff 5448 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
bogdanm 0:9b334a45a8ff 5449 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
bogdanm 0:9b334a45a8ff 5450 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
bogdanm 0:9b334a45a8ff 5451 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
bogdanm 0:9b334a45a8ff 5452 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
bogdanm 0:9b334a45a8ff 5453 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
bogdanm 0:9b334a45a8ff 5454 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
bogdanm 0:9b334a45a8ff 5455
bogdanm 0:9b334a45a8ff 5456 /*!< MCO configuration */
bogdanm 0:9b334a45a8ff 5457 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
bogdanm 0:9b334a45a8ff 5458 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5459 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5460 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5461
bogdanm 0:9b334a45a8ff 5462 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 0:9b334a45a8ff 5463 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
bogdanm 0:9b334a45a8ff 5464 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
bogdanm 0:9b334a45a8ff 5465 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 0:9b334a45a8ff 5466 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 0:9b334a45a8ff 5467 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 0:9b334a45a8ff 5468 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 0:9b334a45a8ff 5469
bogdanm 0:9b334a45a8ff 5470 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
bogdanm 0:9b334a45a8ff 5471 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
bogdanm 0:9b334a45a8ff 5472 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
bogdanm 0:9b334a45a8ff 5473 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
bogdanm 0:9b334a45a8ff 5474 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
bogdanm 0:9b334a45a8ff 5475 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
bogdanm 0:9b334a45a8ff 5476 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
bogdanm 0:9b334a45a8ff 5477 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
bogdanm 0:9b334a45a8ff 5478 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
bogdanm 0:9b334a45a8ff 5479
bogdanm 0:9b334a45a8ff 5480 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
bogdanm 0:9b334a45a8ff 5481
bogdanm 0:9b334a45a8ff 5482 /********************* Bit definition for RCC_CIR register ********************/
bogdanm 0:9b334a45a8ff 5483 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 5484 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 5485 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 5486 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 5487 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 5488 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
bogdanm 0:9b334a45a8ff 5489 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 5490 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 5491 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 5492 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 5493 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 5494 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 5495 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 5496 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 5497 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 5498 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 5499 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
bogdanm 0:9b334a45a8ff 5500
bogdanm 0:9b334a45a8ff 5501 /****************** Bit definition for RCC_APB2RSTR register *****************/
bogdanm 0:9b334a45a8ff 5502 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
bogdanm 0:9b334a45a8ff 5503 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
bogdanm 0:9b334a45a8ff 5504 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
bogdanm 0:9b334a45a8ff 5505 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
bogdanm 0:9b334a45a8ff 5506 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
bogdanm 0:9b334a45a8ff 5507 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
bogdanm 0:9b334a45a8ff 5508 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
bogdanm 0:9b334a45a8ff 5509 #define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< TIM17 reset */
bogdanm 0:9b334a45a8ff 5510
bogdanm 0:9b334a45a8ff 5511 /****************** Bit definition for RCC_APB1RSTR register ******************/
bogdanm 0:9b334a45a8ff 5512 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
bogdanm 0:9b334a45a8ff 5513 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
bogdanm 0:9b334a45a8ff 5514 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
bogdanm 0:9b334a45a8ff 5515 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
bogdanm 0:9b334a45a8ff 5516 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
bogdanm 0:9b334a45a8ff 5517 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
bogdanm 0:9b334a45a8ff 5518 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
bogdanm 0:9b334a45a8ff 5519 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
bogdanm 0:9b334a45a8ff 5520 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
bogdanm 0:9b334a45a8ff 5521 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
bogdanm 0:9b334a45a8ff 5522 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
bogdanm 0:9b334a45a8ff 5523 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
bogdanm 0:9b334a45a8ff 5524
bogdanm 0:9b334a45a8ff 5525 /****************** Bit definition for RCC_AHBENR register ******************/
bogdanm 0:9b334a45a8ff 5526 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
bogdanm 0:9b334a45a8ff 5527 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
bogdanm 0:9b334a45a8ff 5528 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
bogdanm 0:9b334a45a8ff 5529 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
bogdanm 0:9b334a45a8ff 5530 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
bogdanm 0:9b334a45a8ff 5531 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
bogdanm 0:9b334a45a8ff 5532 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
bogdanm 0:9b334a45a8ff 5533 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
bogdanm 0:9b334a45a8ff 5534 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
bogdanm 0:9b334a45a8ff 5535 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
bogdanm 0:9b334a45a8ff 5536 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
bogdanm 0:9b334a45a8ff 5537
bogdanm 0:9b334a45a8ff 5538 /***************** Bit definition for RCC_APB2ENR register ******************/
bogdanm 0:9b334a45a8ff 5539 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
bogdanm 0:9b334a45a8ff 5540 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
bogdanm 0:9b334a45a8ff 5541 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
bogdanm 0:9b334a45a8ff 5542 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
bogdanm 0:9b334a45a8ff 5543 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
bogdanm 0:9b334a45a8ff 5544 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
bogdanm 0:9b334a45a8ff 5545 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
bogdanm 0:9b334a45a8ff 5546 #define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< TIM17 reset */
bogdanm 0:9b334a45a8ff 5547
bogdanm 0:9b334a45a8ff 5548 /****************** Bit definition for RCC_APB1ENR register ******************/
bogdanm 0:9b334a45a8ff 5549 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
bogdanm 0:9b334a45a8ff 5550 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
bogdanm 0:9b334a45a8ff 5551 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 0:9b334a45a8ff 5552 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
bogdanm 0:9b334a45a8ff 5553 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
bogdanm 0:9b334a45a8ff 5554 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
bogdanm 0:9b334a45a8ff 5555 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
bogdanm 0:9b334a45a8ff 5556 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
bogdanm 0:9b334a45a8ff 5557 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
bogdanm 0:9b334a45a8ff 5558 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
bogdanm 0:9b334a45a8ff 5559 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
bogdanm 0:9b334a45a8ff 5560 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
bogdanm 0:9b334a45a8ff 5561
bogdanm 0:9b334a45a8ff 5562 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 0:9b334a45a8ff 5563 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
bogdanm 0:9b334a45a8ff 5564 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
bogdanm 0:9b334a45a8ff 5565 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
bogdanm 0:9b334a45a8ff 5566 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
bogdanm 0:9b334a45a8ff 5567
bogdanm 0:9b334a45a8ff 5568 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
bogdanm 0:9b334a45a8ff 5569 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5570 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5571
bogdanm 0:9b334a45a8ff 5572 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
bogdanm 0:9b334a45a8ff 5573 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5574 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5575
bogdanm 0:9b334a45a8ff 5576 /*!< RTC configuration */
bogdanm 0:9b334a45a8ff 5577 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 0:9b334a45a8ff 5578 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
bogdanm 0:9b334a45a8ff 5579 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
bogdanm 0:9b334a45a8ff 5580 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
bogdanm 0:9b334a45a8ff 5581
bogdanm 0:9b334a45a8ff 5582 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
bogdanm 0:9b334a45a8ff 5583 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
bogdanm 0:9b334a45a8ff 5584
bogdanm 0:9b334a45a8ff 5585 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 0:9b334a45a8ff 5586 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
bogdanm 0:9b334a45a8ff 5587 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
bogdanm 0:9b334a45a8ff 5588 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
bogdanm 0:9b334a45a8ff 5589 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
bogdanm 0:9b334a45a8ff 5590 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
bogdanm 0:9b334a45a8ff 5591 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
bogdanm 0:9b334a45a8ff 5592 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
bogdanm 0:9b334a45a8ff 5593 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
bogdanm 0:9b334a45a8ff 5594 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
bogdanm 0:9b334a45a8ff 5595 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
bogdanm 0:9b334a45a8ff 5596
bogdanm 0:9b334a45a8ff 5597 /******************* Bit definition for RCC_AHBRSTR register ****************/
bogdanm 0:9b334a45a8ff 5598 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
bogdanm 0:9b334a45a8ff 5599 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
bogdanm 0:9b334a45a8ff 5600 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
bogdanm 0:9b334a45a8ff 5601 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
bogdanm 0:9b334a45a8ff 5602 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
bogdanm 0:9b334a45a8ff 5603 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
bogdanm 0:9b334a45a8ff 5604 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
bogdanm 0:9b334a45a8ff 5605
bogdanm 0:9b334a45a8ff 5606 /******************* Bit definition for RCC_CFGR2 register ******************/
bogdanm 0:9b334a45a8ff 5607 /*!< PREDIV configuration */
bogdanm 0:9b334a45a8ff 5608 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
bogdanm 0:9b334a45a8ff 5609 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5610 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5611 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5612 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 5613
bogdanm 0:9b334a45a8ff 5614 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
bogdanm 0:9b334a45a8ff 5615 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
bogdanm 0:9b334a45a8ff 5616 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
bogdanm 0:9b334a45a8ff 5617 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
bogdanm 0:9b334a45a8ff 5618 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
bogdanm 0:9b334a45a8ff 5619 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
bogdanm 0:9b334a45a8ff 5620 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
bogdanm 0:9b334a45a8ff 5621 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
bogdanm 0:9b334a45a8ff 5622 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
bogdanm 0:9b334a45a8ff 5623 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
bogdanm 0:9b334a45a8ff 5624 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
bogdanm 0:9b334a45a8ff 5625 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
bogdanm 0:9b334a45a8ff 5626 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
bogdanm 0:9b334a45a8ff 5627 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
bogdanm 0:9b334a45a8ff 5628 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
bogdanm 0:9b334a45a8ff 5629 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
bogdanm 0:9b334a45a8ff 5630
bogdanm 0:9b334a45a8ff 5631 /*!< ADCPRE12 configuration */
bogdanm 0:9b334a45a8ff 5632 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
bogdanm 0:9b334a45a8ff 5633 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5634 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5635 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5636 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 5637 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 5638
bogdanm 0:9b334a45a8ff 5639 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
bogdanm 0:9b334a45a8ff 5640 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
bogdanm 0:9b334a45a8ff 5641 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
bogdanm 0:9b334a45a8ff 5642 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
bogdanm 0:9b334a45a8ff 5643 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
bogdanm 0:9b334a45a8ff 5644 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
bogdanm 0:9b334a45a8ff 5645 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
bogdanm 0:9b334a45a8ff 5646 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
bogdanm 0:9b334a45a8ff 5647 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
bogdanm 0:9b334a45a8ff 5648 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
bogdanm 0:9b334a45a8ff 5649 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
bogdanm 0:9b334a45a8ff 5650 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
bogdanm 0:9b334a45a8ff 5651 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
bogdanm 0:9b334a45a8ff 5652
bogdanm 0:9b334a45a8ff 5653 /******************* Bit definition for RCC_CFGR3 register ******************/
bogdanm 0:9b334a45a8ff 5654 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
bogdanm 0:9b334a45a8ff 5655 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5656 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5657
bogdanm 0:9b334a45a8ff 5658 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 5659 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
bogdanm 0:9b334a45a8ff 5660 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 5661 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 5662
bogdanm 0:9b334a45a8ff 5663 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
bogdanm 0:9b334a45a8ff 5664 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
bogdanm 0:9b334a45a8ff 5665
bogdanm 0:9b334a45a8ff 5666 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
bogdanm 0:9b334a45a8ff 5667 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
bogdanm 0:9b334a45a8ff 5668
bogdanm 0:9b334a45a8ff 5669 #define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
bogdanm 0:9b334a45a8ff 5670 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
bogdanm 0:9b334a45a8ff 5671
bogdanm 0:9b334a45a8ff 5672 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
bogdanm 0:9b334a45a8ff 5673 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
bogdanm 0:9b334a45a8ff 5674
bogdanm 0:9b334a45a8ff 5675 #define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< TIMSW bits */
bogdanm 0:9b334a45a8ff 5676 #define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< TIM1SW bits */
bogdanm 0:9b334a45a8ff 5677
bogdanm 0:9b334a45a8ff 5678 #define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
bogdanm 0:9b334a45a8ff 5679 #define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as TIM1 clock source */
bogdanm 0:9b334a45a8ff 5680
bogdanm 0:9b334a45a8ff 5681 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
bogdanm 0:9b334a45a8ff 5682 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5683 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5684
bogdanm 0:9b334a45a8ff 5685 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 5686 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
bogdanm 0:9b334a45a8ff 5687 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 5688 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 5689
bogdanm 0:9b334a45a8ff 5690 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
bogdanm 0:9b334a45a8ff 5691 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5692 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5693
bogdanm 0:9b334a45a8ff 5694 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
bogdanm 0:9b334a45a8ff 5695 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
bogdanm 0:9b334a45a8ff 5696 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
bogdanm 0:9b334a45a8ff 5697 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
bogdanm 0:9b334a45a8ff 5698
bogdanm 0:9b334a45a8ff 5699 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5700 /* */
bogdanm 0:9b334a45a8ff 5701 /* Real-Time Clock (RTC) */
bogdanm 0:9b334a45a8ff 5702 /* */
bogdanm 0:9b334a45a8ff 5703 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5704 /******************** Bits definition for RTC_TR register *******************/
bogdanm 0:9b334a45a8ff 5705 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5706 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5707 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5708 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5709 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5710 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5711 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5712 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5713 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5714 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5715 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5716 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5717 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5718 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5719 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5720 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5721 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5722 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5723 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5724 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5725 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5726 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5727 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5728 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5729 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5730 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5731 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5732
bogdanm 0:9b334a45a8ff 5733 /******************** Bits definition for RTC_DR register *******************/
bogdanm 0:9b334a45a8ff 5734 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 5735 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5736 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5737 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5738 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5739 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5740 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5741 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5742 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5743 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5744 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 5745 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5746 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5747 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5748 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5749 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5750 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5751 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5752 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5753 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5754 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 5755 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5756 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5757 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5758 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5759 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5760 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5761 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5762
bogdanm 0:9b334a45a8ff 5763 /******************** Bits definition for RTC_CR register *******************/
bogdanm 0:9b334a45a8ff 5764 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5765 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 0:9b334a45a8ff 5766 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5767 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5768 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5769 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5770 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5771 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5772 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5773 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5774 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5775 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5776 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5777 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5778 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5779 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5780 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5781 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5782 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5783 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5784 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5785 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 0:9b334a45a8ff 5786 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5787 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5788 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5789
bogdanm 0:9b334a45a8ff 5790 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 0:9b334a45a8ff 5791 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5792 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5793 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5794 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5795 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5796 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5797 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5798 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5799 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5800 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5801 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5802 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5803 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5804 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5805 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5806 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5807 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5808
bogdanm 0:9b334a45a8ff 5809 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 0:9b334a45a8ff 5810 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 0:9b334a45a8ff 5811 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 5812
bogdanm 0:9b334a45a8ff 5813 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 0:9b334a45a8ff 5814 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5815
bogdanm 0:9b334a45a8ff 5816 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 0:9b334a45a8ff 5817 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5818 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5819 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 5820 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5821 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5822 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5823 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5824 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5825 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5826 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5827 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5828 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5829 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5830 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5831 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5832 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5833 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5834 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5835 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5836 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5837 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5838 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5839 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5840 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5841 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5842 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5843 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5844 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5845 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5846 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5847 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5848 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5849 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5850 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5851 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5852 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5853 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5854 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5855 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5856 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5857
bogdanm 0:9b334a45a8ff 5858 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 0:9b334a45a8ff 5859 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5860 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5861 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 5862 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5863 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5864 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5865 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5866 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5867 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5868 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5869 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5870 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5871 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5872 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5873 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5874 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5875 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5876 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5877 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5878 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5879 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5880 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5881 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5882 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5883 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5884 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5885 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5886 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5887 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5888 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5889 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5890 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5891 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5892 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5893 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5894 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5895 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5896 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5897 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5898 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5899
bogdanm 0:9b334a45a8ff 5900 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 0:9b334a45a8ff 5901 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 0:9b334a45a8ff 5902
bogdanm 0:9b334a45a8ff 5903 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 0:9b334a45a8ff 5904 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5905
bogdanm 0:9b334a45a8ff 5906 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 0:9b334a45a8ff 5907 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 5908 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5909
bogdanm 0:9b334a45a8ff 5910 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 0:9b334a45a8ff 5911 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5912 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5913 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5914 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5915 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5916 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5917 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5918 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5919 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5920 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5921 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5922 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5923 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5924 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5925 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5926 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5927 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5928 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5929 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5930 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5931 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5932 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5933 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5934 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5935 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5936 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5937 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5938
bogdanm 0:9b334a45a8ff 5939 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 0:9b334a45a8ff 5940 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 5941 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5942 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5943 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5944 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5945 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5946 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5947 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5948 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5949 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5950 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 5951 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5952 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5953 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5954 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5955 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5956 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5957 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5958
bogdanm 0:9b334a45a8ff 5959 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 0:9b334a45a8ff 5960 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5961
bogdanm 0:9b334a45a8ff 5962 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 0:9b334a45a8ff 5963 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5964 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5965 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5966 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 0:9b334a45a8ff 5967 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5968 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5969 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5970 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5971 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5972 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5973 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5974 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5975 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5976
bogdanm 0:9b334a45a8ff 5977 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 0:9b334a45a8ff 5978 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5979 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5980 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 0:9b334a45a8ff 5981 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5982 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5983 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 0:9b334a45a8ff 5984 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5985 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5986 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 0:9b334a45a8ff 5987 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5988 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5989 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5990 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5991 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5992 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5993 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5994 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5995 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5996 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5997 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5998
bogdanm 0:9b334a45a8ff 5999 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 0:9b334a45a8ff 6000 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 6001 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 6002 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 6003 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 6004 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 6005 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 6006
bogdanm 0:9b334a45a8ff 6007 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 0:9b334a45a8ff 6008 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 6009 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 6010 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 6011 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 6012 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 6013 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 6014
bogdanm 0:9b334a45a8ff 6015 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 0:9b334a45a8ff 6016 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6017
bogdanm 0:9b334a45a8ff 6018 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 0:9b334a45a8ff 6019 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6020
bogdanm 0:9b334a45a8ff 6021 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 0:9b334a45a8ff 6022 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6023
bogdanm 0:9b334a45a8ff 6024 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 0:9b334a45a8ff 6025 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6026
bogdanm 0:9b334a45a8ff 6027 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 0:9b334a45a8ff 6028 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6029
bogdanm 0:9b334a45a8ff 6030 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 0:9b334a45a8ff 6031 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6032
bogdanm 0:9b334a45a8ff 6033 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 0:9b334a45a8ff 6034 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6035
bogdanm 0:9b334a45a8ff 6036 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 0:9b334a45a8ff 6037 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6038
bogdanm 0:9b334a45a8ff 6039 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 0:9b334a45a8ff 6040 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6041
bogdanm 0:9b334a45a8ff 6042 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 0:9b334a45a8ff 6043 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6044
bogdanm 0:9b334a45a8ff 6045 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 0:9b334a45a8ff 6046 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6047
bogdanm 0:9b334a45a8ff 6048 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 0:9b334a45a8ff 6049 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6050
bogdanm 0:9b334a45a8ff 6051 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 0:9b334a45a8ff 6052 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6053
bogdanm 0:9b334a45a8ff 6054 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 0:9b334a45a8ff 6055 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6056
bogdanm 0:9b334a45a8ff 6057 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 0:9b334a45a8ff 6058 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6059
bogdanm 0:9b334a45a8ff 6060 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 0:9b334a45a8ff 6061 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 6062
bogdanm 0:9b334a45a8ff 6063 /******************** Number of backup registers ******************************/
bogdanm 0:9b334a45a8ff 6064 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 6065
bogdanm 0:9b334a45a8ff 6066 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6067 /* */
bogdanm 0:9b334a45a8ff 6068 /* Serial Peripheral Interface (SPI) */
bogdanm 0:9b334a45a8ff 6069 /* */
bogdanm 0:9b334a45a8ff 6070 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6071 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 0:9b334a45a8ff 6072 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
bogdanm 0:9b334a45a8ff 6073 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
bogdanm 0:9b334a45a8ff 6074 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
bogdanm 0:9b334a45a8ff 6075 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
bogdanm 0:9b334a45a8ff 6076 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6077 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6078 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 6079 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
bogdanm 0:9b334a45a8ff 6080 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
bogdanm 0:9b334a45a8ff 6081 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
bogdanm 0:9b334a45a8ff 6082 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
bogdanm 0:9b334a45a8ff 6083 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
bogdanm 0:9b334a45a8ff 6084 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
bogdanm 0:9b334a45a8ff 6085 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
bogdanm 0:9b334a45a8ff 6086 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
bogdanm 0:9b334a45a8ff 6087 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
bogdanm 0:9b334a45a8ff 6088 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
bogdanm 0:9b334a45a8ff 6089
bogdanm 0:9b334a45a8ff 6090 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 0:9b334a45a8ff 6091 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 6092 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 6093 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
bogdanm 0:9b334a45a8ff 6094 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
bogdanm 0:9b334a45a8ff 6095 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
bogdanm 0:9b334a45a8ff 6096 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 6097 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 6098 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 6099 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
bogdanm 0:9b334a45a8ff 6100 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6101 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6102 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 6103 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 6104 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
bogdanm 0:9b334a45a8ff 6105 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
bogdanm 0:9b334a45a8ff 6106 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
bogdanm 0:9b334a45a8ff 6107
bogdanm 0:9b334a45a8ff 6108 /******************** Bit definition for SPI_SR register ********************/
bogdanm 0:9b334a45a8ff 6109 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
bogdanm 0:9b334a45a8ff 6110 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
bogdanm 0:9b334a45a8ff 6111 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
bogdanm 0:9b334a45a8ff 6112 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
bogdanm 0:9b334a45a8ff 6113 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
bogdanm 0:9b334a45a8ff 6114 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
bogdanm 0:9b334a45a8ff 6115 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
bogdanm 0:9b334a45a8ff 6116 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
bogdanm 0:9b334a45a8ff 6117 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
bogdanm 0:9b334a45a8ff 6118 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
bogdanm 0:9b334a45a8ff 6119 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6120 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6121 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
bogdanm 0:9b334a45a8ff 6122 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6123 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6124
bogdanm 0:9b334a45a8ff 6125 /******************** Bit definition for SPI_DR register ********************/
bogdanm 0:9b334a45a8ff 6126 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
bogdanm 0:9b334a45a8ff 6127
bogdanm 0:9b334a45a8ff 6128 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 0:9b334a45a8ff 6129 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
bogdanm 0:9b334a45a8ff 6130
bogdanm 0:9b334a45a8ff 6131 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 0:9b334a45a8ff 6132 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
bogdanm 0:9b334a45a8ff 6133
bogdanm 0:9b334a45a8ff 6134 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 0:9b334a45a8ff 6135 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
bogdanm 0:9b334a45a8ff 6136
bogdanm 0:9b334a45a8ff 6137 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6138 /* */
bogdanm 0:9b334a45a8ff 6139 /* System Configuration(SYSCFG) */
bogdanm 0:9b334a45a8ff 6140 /* */
bogdanm 0:9b334a45a8ff 6141 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6142 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
bogdanm 0:9b334a45a8ff 6143 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
bogdanm 0:9b334a45a8ff 6144 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6145 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6146 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
bogdanm 0:9b334a45a8ff 6147 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
bogdanm 0:9b334a45a8ff 6148 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
bogdanm 0:9b334a45a8ff 6149 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
bogdanm 0:9b334a45a8ff 6150 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
bogdanm 0:9b334a45a8ff 6151 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
bogdanm 0:9b334a45a8ff 6152 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
bogdanm 0:9b334a45a8ff 6153 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
bogdanm 0:9b334a45a8ff 6154 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
bogdanm 0:9b334a45a8ff 6155 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
bogdanm 0:9b334a45a8ff 6156 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
bogdanm 0:9b334a45a8ff 6157 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
bogdanm 0:9b334a45a8ff 6158 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
bogdanm 0:9b334a45a8ff 6159 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
bogdanm 0:9b334a45a8ff 6160 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
bogdanm 0:9b334a45a8ff 6161 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
bogdanm 0:9b334a45a8ff 6162 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
bogdanm 0:9b334a45a8ff 6163 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
bogdanm 0:9b334a45a8ff 6164 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
bogdanm 0:9b334a45a8ff 6165 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
bogdanm 0:9b334a45a8ff 6166 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
bogdanm 0:9b334a45a8ff 6167 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
bogdanm 0:9b334a45a8ff 6168 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
bogdanm 0:9b334a45a8ff 6169
bogdanm 0:9b334a45a8ff 6170 /***************** Bit definition for SYSCFG_RCR register *******************/
bogdanm 0:9b334a45a8ff 6171 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
bogdanm 0:9b334a45a8ff 6172 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
bogdanm 0:9b334a45a8ff 6173 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
bogdanm 0:9b334a45a8ff 6174 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
bogdanm 0:9b334a45a8ff 6175
bogdanm 0:9b334a45a8ff 6176 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 0:9b334a45a8ff 6177 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
bogdanm 0:9b334a45a8ff 6178 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
bogdanm 0:9b334a45a8ff 6179 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
bogdanm 0:9b334a45a8ff 6180 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
bogdanm 0:9b334a45a8ff 6181
bogdanm 0:9b334a45a8ff 6182 /*!<*
bogdanm 0:9b334a45a8ff 6183 * @brief EXTI0 configuration
bogdanm 0:9b334a45a8ff 6184 */
bogdanm 0:9b334a45a8ff 6185 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
bogdanm 0:9b334a45a8ff 6186 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
bogdanm 0:9b334a45a8ff 6187 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
bogdanm 0:9b334a45a8ff 6188 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
bogdanm 0:9b334a45a8ff 6189 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
bogdanm 0:9b334a45a8ff 6190 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
bogdanm 0:9b334a45a8ff 6191
bogdanm 0:9b334a45a8ff 6192 /*!<*
bogdanm 0:9b334a45a8ff 6193 * @brief EXTI1 configuration
bogdanm 0:9b334a45a8ff 6194 */
bogdanm 0:9b334a45a8ff 6195 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
bogdanm 0:9b334a45a8ff 6196 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
bogdanm 0:9b334a45a8ff 6197 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
bogdanm 0:9b334a45a8ff 6198 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
bogdanm 0:9b334a45a8ff 6199 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
bogdanm 0:9b334a45a8ff 6200 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
bogdanm 0:9b334a45a8ff 6201
bogdanm 0:9b334a45a8ff 6202 /*!<*
bogdanm 0:9b334a45a8ff 6203 * @brief EXTI2 configuration
bogdanm 0:9b334a45a8ff 6204 */
bogdanm 0:9b334a45a8ff 6205 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
bogdanm 0:9b334a45a8ff 6206 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
bogdanm 0:9b334a45a8ff 6207 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
bogdanm 0:9b334a45a8ff 6208 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
bogdanm 0:9b334a45a8ff 6209 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
bogdanm 0:9b334a45a8ff 6210 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
bogdanm 0:9b334a45a8ff 6211
bogdanm 0:9b334a45a8ff 6212 /*!<*
bogdanm 0:9b334a45a8ff 6213 * @brief EXTI3 configuration
bogdanm 0:9b334a45a8ff 6214 */
bogdanm 0:9b334a45a8ff 6215 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
bogdanm 0:9b334a45a8ff 6216 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
bogdanm 0:9b334a45a8ff 6217 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
bogdanm 0:9b334a45a8ff 6218 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
bogdanm 0:9b334a45a8ff 6219 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
bogdanm 0:9b334a45a8ff 6220
bogdanm 0:9b334a45a8ff 6221 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 0:9b334a45a8ff 6222 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
bogdanm 0:9b334a45a8ff 6223 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
bogdanm 0:9b334a45a8ff 6224 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
bogdanm 0:9b334a45a8ff 6225 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
bogdanm 0:9b334a45a8ff 6226
bogdanm 0:9b334a45a8ff 6227 /*!<*
bogdanm 0:9b334a45a8ff 6228 * @brief EXTI4 configuration
bogdanm 0:9b334a45a8ff 6229 */
bogdanm 0:9b334a45a8ff 6230 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
bogdanm 0:9b334a45a8ff 6231 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
bogdanm 0:9b334a45a8ff 6232 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
bogdanm 0:9b334a45a8ff 6233 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
bogdanm 0:9b334a45a8ff 6234 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
bogdanm 0:9b334a45a8ff 6235 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
bogdanm 0:9b334a45a8ff 6236
bogdanm 0:9b334a45a8ff 6237 /*!<*
bogdanm 0:9b334a45a8ff 6238 * @brief EXTI5 configuration
bogdanm 0:9b334a45a8ff 6239 */
bogdanm 0:9b334a45a8ff 6240 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
bogdanm 0:9b334a45a8ff 6241 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
bogdanm 0:9b334a45a8ff 6242 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
bogdanm 0:9b334a45a8ff 6243 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
bogdanm 0:9b334a45a8ff 6244 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
bogdanm 0:9b334a45a8ff 6245 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
bogdanm 0:9b334a45a8ff 6246
bogdanm 0:9b334a45a8ff 6247 /*!<*
bogdanm 0:9b334a45a8ff 6248 * @brief EXTI6 configuration
bogdanm 0:9b334a45a8ff 6249 */
bogdanm 0:9b334a45a8ff 6250 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
bogdanm 0:9b334a45a8ff 6251 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
bogdanm 0:9b334a45a8ff 6252 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
bogdanm 0:9b334a45a8ff 6253 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
bogdanm 0:9b334a45a8ff 6254 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
bogdanm 0:9b334a45a8ff 6255 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
bogdanm 0:9b334a45a8ff 6256
bogdanm 0:9b334a45a8ff 6257 /*!<*
bogdanm 0:9b334a45a8ff 6258 * @brief EXTI7 configuration
bogdanm 0:9b334a45a8ff 6259 */
bogdanm 0:9b334a45a8ff 6260 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
bogdanm 0:9b334a45a8ff 6261 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
bogdanm 0:9b334a45a8ff 6262 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
bogdanm 0:9b334a45a8ff 6263 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
bogdanm 0:9b334a45a8ff 6264 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
bogdanm 0:9b334a45a8ff 6265
bogdanm 0:9b334a45a8ff 6266 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 0:9b334a45a8ff 6267 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
bogdanm 0:9b334a45a8ff 6268 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
bogdanm 0:9b334a45a8ff 6269 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
bogdanm 0:9b334a45a8ff 6270 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
bogdanm 0:9b334a45a8ff 6271
bogdanm 0:9b334a45a8ff 6272 /*!<*
bogdanm 0:9b334a45a8ff 6273 * @brief EXTI8 configuration
bogdanm 0:9b334a45a8ff 6274 */
bogdanm 0:9b334a45a8ff 6275 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
bogdanm 0:9b334a45a8ff 6276 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
bogdanm 0:9b334a45a8ff 6277 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
bogdanm 0:9b334a45a8ff 6278 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
bogdanm 0:9b334a45a8ff 6279 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
bogdanm 0:9b334a45a8ff 6280
bogdanm 0:9b334a45a8ff 6281 /*!<*
bogdanm 0:9b334a45a8ff 6282 * @brief EXTI9 configuration
bogdanm 0:9b334a45a8ff 6283 */
bogdanm 0:9b334a45a8ff 6284 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
bogdanm 0:9b334a45a8ff 6285 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
bogdanm 0:9b334a45a8ff 6286 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
bogdanm 0:9b334a45a8ff 6287 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
bogdanm 0:9b334a45a8ff 6288 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
bogdanm 0:9b334a45a8ff 6289 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
bogdanm 0:9b334a45a8ff 6290
bogdanm 0:9b334a45a8ff 6291 /*!<*
bogdanm 0:9b334a45a8ff 6292 * @brief EXTI10 configuration
bogdanm 0:9b334a45a8ff 6293 */
bogdanm 0:9b334a45a8ff 6294 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
bogdanm 0:9b334a45a8ff 6295 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
bogdanm 0:9b334a45a8ff 6296 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
bogdanm 0:9b334a45a8ff 6297 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
bogdanm 0:9b334a45a8ff 6298 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
bogdanm 0:9b334a45a8ff 6299 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
bogdanm 0:9b334a45a8ff 6300
bogdanm 0:9b334a45a8ff 6301 /*!<*
bogdanm 0:9b334a45a8ff 6302 * @brief EXTI11 configuration
bogdanm 0:9b334a45a8ff 6303 */
bogdanm 0:9b334a45a8ff 6304 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
bogdanm 0:9b334a45a8ff 6305 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
bogdanm 0:9b334a45a8ff 6306 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
bogdanm 0:9b334a45a8ff 6307 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
bogdanm 0:9b334a45a8ff 6308 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
bogdanm 0:9b334a45a8ff 6309
bogdanm 0:9b334a45a8ff 6310 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
bogdanm 0:9b334a45a8ff 6311 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
bogdanm 0:9b334a45a8ff 6312 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
bogdanm 0:9b334a45a8ff 6313 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
bogdanm 0:9b334a45a8ff 6314 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
bogdanm 0:9b334a45a8ff 6315
bogdanm 0:9b334a45a8ff 6316 /*!<*
bogdanm 0:9b334a45a8ff 6317 * @brief EXTI12 configuration
bogdanm 0:9b334a45a8ff 6318 */
bogdanm 0:9b334a45a8ff 6319 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
bogdanm 0:9b334a45a8ff 6320 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
bogdanm 0:9b334a45a8ff 6321 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
bogdanm 0:9b334a45a8ff 6322 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
bogdanm 0:9b334a45a8ff 6323 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
bogdanm 0:9b334a45a8ff 6324
bogdanm 0:9b334a45a8ff 6325 /*!<*
bogdanm 0:9b334a45a8ff 6326 * @brief EXTI13 configuration
bogdanm 0:9b334a45a8ff 6327 */
bogdanm 0:9b334a45a8ff 6328 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
bogdanm 0:9b334a45a8ff 6329 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
bogdanm 0:9b334a45a8ff 6330 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
bogdanm 0:9b334a45a8ff 6331 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
bogdanm 0:9b334a45a8ff 6332 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
bogdanm 0:9b334a45a8ff 6333
bogdanm 0:9b334a45a8ff 6334 /*!<*
bogdanm 0:9b334a45a8ff 6335 * @brief EXTI14 configuration
bogdanm 0:9b334a45a8ff 6336 */
bogdanm 0:9b334a45a8ff 6337 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
bogdanm 0:9b334a45a8ff 6338 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
bogdanm 0:9b334a45a8ff 6339 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
bogdanm 0:9b334a45a8ff 6340 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
bogdanm 0:9b334a45a8ff 6341 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
bogdanm 0:9b334a45a8ff 6342
bogdanm 0:9b334a45a8ff 6343 /*!<*
bogdanm 0:9b334a45a8ff 6344 * @brief EXTI15 configuration
bogdanm 0:9b334a45a8ff 6345 */
bogdanm 0:9b334a45a8ff 6346 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
bogdanm 0:9b334a45a8ff 6347 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
bogdanm 0:9b334a45a8ff 6348 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
bogdanm 0:9b334a45a8ff 6349 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
bogdanm 0:9b334a45a8ff 6350 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
bogdanm 0:9b334a45a8ff 6351
bogdanm 0:9b334a45a8ff 6352 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
bogdanm 0:9b334a45a8ff 6353 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
bogdanm 0:9b334a45a8ff 6354 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
bogdanm 0:9b334a45a8ff 6355 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
bogdanm 0:9b334a45a8ff 6356 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
bogdanm 0:9b334a45a8ff 6357 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
bogdanm 0:9b334a45a8ff 6358
bogdanm 0:9b334a45a8ff 6359 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
bogdanm 0:9b334a45a8ff 6360 #define SYSCFG_CFGR3_DMA_RMP ((uint32_t)0x000003FF) /*!< DMA remap mask */
bogdanm 0:9b334a45a8ff 6361 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
bogdanm 0:9b334a45a8ff 6362 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
bogdanm 0:9b334a45a8ff 6363 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
bogdanm 0:9b334a45a8ff 6364 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
bogdanm 0:9b334a45a8ff 6365 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
bogdanm 0:9b334a45a8ff 6366 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
bogdanm 0:9b334a45a8ff 6367 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
bogdanm 0:9b334a45a8ff 6368 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
bogdanm 0:9b334a45a8ff 6369 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
bogdanm 0:9b334a45a8ff 6370 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
bogdanm 0:9b334a45a8ff 6371 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
bogdanm 0:9b334a45a8ff 6372 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
bogdanm 0:9b334a45a8ff 6373 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
bogdanm 0:9b334a45a8ff 6374 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
bogdanm 0:9b334a45a8ff 6375 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
bogdanm 0:9b334a45a8ff 6376 #define SYSCFG_CFGR3_TRIGGER_RMP ((uint32_t)0x00030000) /*!< Trigger remap mask */
bogdanm 0:9b334a45a8ff 6377 #define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */
bogdanm 0:9b334a45a8ff 6378 #define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */
bogdanm 0:9b334a45a8ff 6379
bogdanm 0:9b334a45a8ff 6380 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6381 /* */
bogdanm 0:9b334a45a8ff 6382 /* TIM */
bogdanm 0:9b334a45a8ff 6383 /* */
bogdanm 0:9b334a45a8ff 6384 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6385 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 0:9b334a45a8ff 6386 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
bogdanm 0:9b334a45a8ff 6387 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
bogdanm 0:9b334a45a8ff 6388 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
bogdanm 0:9b334a45a8ff 6389 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
bogdanm 0:9b334a45a8ff 6390 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
bogdanm 0:9b334a45a8ff 6391
bogdanm 0:9b334a45a8ff 6392 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 0:9b334a45a8ff 6393 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6394 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6395
bogdanm 0:9b334a45a8ff 6396 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
bogdanm 0:9b334a45a8ff 6397
bogdanm 0:9b334a45a8ff 6398 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
bogdanm 0:9b334a45a8ff 6399 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6400 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6401
bogdanm 0:9b334a45a8ff 6402 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
bogdanm 0:9b334a45a8ff 6403
bogdanm 0:9b334a45a8ff 6404 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 0:9b334a45a8ff 6405 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
bogdanm 0:9b334a45a8ff 6406 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
bogdanm 0:9b334a45a8ff 6407 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
bogdanm 0:9b334a45a8ff 6408
bogdanm 0:9b334a45a8ff 6409 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 0:9b334a45a8ff 6410 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6411 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6412 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6413
bogdanm 0:9b334a45a8ff 6414 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
bogdanm 0:9b334a45a8ff 6415 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 0:9b334a45a8ff 6416 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 0:9b334a45a8ff 6417 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 0:9b334a45a8ff 6418 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 0:9b334a45a8ff 6419 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 0:9b334a45a8ff 6420 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 0:9b334a45a8ff 6421 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 0:9b334a45a8ff 6422 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 0:9b334a45a8ff 6423 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 0:9b334a45a8ff 6424
bogdanm 0:9b334a45a8ff 6425 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 0:9b334a45a8ff 6426 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6427 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6428 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6429 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6430
bogdanm 0:9b334a45a8ff 6431 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 0:9b334a45a8ff 6432 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 0:9b334a45a8ff 6433 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6434 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6435 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6436 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6437
bogdanm 0:9b334a45a8ff 6438 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
bogdanm 0:9b334a45a8ff 6439
bogdanm 0:9b334a45a8ff 6440 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 0:9b334a45a8ff 6441 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6442 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6443 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6444
bogdanm 0:9b334a45a8ff 6445 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
bogdanm 0:9b334a45a8ff 6446
bogdanm 0:9b334a45a8ff 6447 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 0:9b334a45a8ff 6448 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6449 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6450 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6451 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6452
bogdanm 0:9b334a45a8ff 6453 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 0:9b334a45a8ff 6454 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6455 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6456
bogdanm 0:9b334a45a8ff 6457 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
bogdanm 0:9b334a45a8ff 6458 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
bogdanm 0:9b334a45a8ff 6459
bogdanm 0:9b334a45a8ff 6460 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 0:9b334a45a8ff 6461 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
bogdanm 0:9b334a45a8ff 6462 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 0:9b334a45a8ff 6463 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 0:9b334a45a8ff 6464 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 0:9b334a45a8ff 6465 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 0:9b334a45a8ff 6466 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
bogdanm 0:9b334a45a8ff 6467 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
bogdanm 0:9b334a45a8ff 6468 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
bogdanm 0:9b334a45a8ff 6469 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
bogdanm 0:9b334a45a8ff 6470 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 0:9b334a45a8ff 6471 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 0:9b334a45a8ff 6472 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 0:9b334a45a8ff 6473 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 0:9b334a45a8ff 6474 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
bogdanm 0:9b334a45a8ff 6475 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
bogdanm 0:9b334a45a8ff 6476
bogdanm 0:9b334a45a8ff 6477 /******************** Bit definition for TIM_SR register ********************/
bogdanm 0:9b334a45a8ff 6478 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
bogdanm 0:9b334a45a8ff 6479 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 0:9b334a45a8ff 6480 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 0:9b334a45a8ff 6481 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 0:9b334a45a8ff 6482 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 0:9b334a45a8ff 6483 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
bogdanm 0:9b334a45a8ff 6484 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
bogdanm 0:9b334a45a8ff 6485 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
bogdanm 0:9b334a45a8ff 6486 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
bogdanm 0:9b334a45a8ff 6487 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6488 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6489 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6490 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6491 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
bogdanm 0:9b334a45a8ff 6492 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
bogdanm 0:9b334a45a8ff 6493
bogdanm 0:9b334a45a8ff 6494 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 0:9b334a45a8ff 6495 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
bogdanm 0:9b334a45a8ff 6496 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
bogdanm 0:9b334a45a8ff 6497 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
bogdanm 0:9b334a45a8ff 6498 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
bogdanm 0:9b334a45a8ff 6499 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
bogdanm 0:9b334a45a8ff 6500 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
bogdanm 0:9b334a45a8ff 6501 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
bogdanm 0:9b334a45a8ff 6502 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
bogdanm 0:9b334a45a8ff 6503 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
bogdanm 0:9b334a45a8ff 6504
bogdanm 0:9b334a45a8ff 6505 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 0:9b334a45a8ff 6506 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 0:9b334a45a8ff 6507 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6508 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6509
bogdanm 0:9b334a45a8ff 6510 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
bogdanm 0:9b334a45a8ff 6511 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
bogdanm 0:9b334a45a8ff 6512
bogdanm 0:9b334a45a8ff 6513 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 0:9b334a45a8ff 6514 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6515 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6516 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6517 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6518
bogdanm 0:9b334a45a8ff 6519 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
bogdanm 0:9b334a45a8ff 6520
bogdanm 0:9b334a45a8ff 6521 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 0:9b334a45a8ff 6522 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6523 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6524
bogdanm 0:9b334a45a8ff 6525 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
bogdanm 0:9b334a45a8ff 6526 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
bogdanm 0:9b334a45a8ff 6527
bogdanm 0:9b334a45a8ff 6528 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 0:9b334a45a8ff 6529 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6530 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6531 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6532 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6533
bogdanm 0:9b334a45a8ff 6534 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
bogdanm 0:9b334a45a8ff 6535
bogdanm 0:9b334a45a8ff 6536 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 6537
bogdanm 0:9b334a45a8ff 6538 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 0:9b334a45a8ff 6539 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6540 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6541
bogdanm 0:9b334a45a8ff 6542 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 0:9b334a45a8ff 6543 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6544 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6545 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6546 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6547
bogdanm 0:9b334a45a8ff 6548 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 0:9b334a45a8ff 6549 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6550 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6551
bogdanm 0:9b334a45a8ff 6552 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 0:9b334a45a8ff 6553 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6554 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6555 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6556 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6557
bogdanm 0:9b334a45a8ff 6558 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 0:9b334a45a8ff 6559 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 0:9b334a45a8ff 6560 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6561 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6562
bogdanm 0:9b334a45a8ff 6563 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
bogdanm 0:9b334a45a8ff 6564 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
bogdanm 0:9b334a45a8ff 6565
bogdanm 0:9b334a45a8ff 6566 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 0:9b334a45a8ff 6567 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6568 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6569 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6570 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6571
bogdanm 0:9b334a45a8ff 6572 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
bogdanm 0:9b334a45a8ff 6573
bogdanm 0:9b334a45a8ff 6574 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 0:9b334a45a8ff 6575 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6576 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6577
bogdanm 0:9b334a45a8ff 6578 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
bogdanm 0:9b334a45a8ff 6579 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
bogdanm 0:9b334a45a8ff 6580
bogdanm 0:9b334a45a8ff 6581 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 0:9b334a45a8ff 6582 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6583 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6584 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6585 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6586
bogdanm 0:9b334a45a8ff 6587 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
bogdanm 0:9b334a45a8ff 6588
bogdanm 0:9b334a45a8ff 6589 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 6590
bogdanm 0:9b334a45a8ff 6591 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 0:9b334a45a8ff 6592 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6593 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6594
bogdanm 0:9b334a45a8ff 6595 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 0:9b334a45a8ff 6596 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6597 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6598 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6599 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6600
bogdanm 0:9b334a45a8ff 6601 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 0:9b334a45a8ff 6602 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6603 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6604
bogdanm 0:9b334a45a8ff 6605 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 0:9b334a45a8ff 6606 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6607 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6608 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6609 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6610
bogdanm 0:9b334a45a8ff 6611 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 0:9b334a45a8ff 6612 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
bogdanm 0:9b334a45a8ff 6613 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
bogdanm 0:9b334a45a8ff 6614 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 0:9b334a45a8ff 6615 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6616 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
bogdanm 0:9b334a45a8ff 6617 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
bogdanm 0:9b334a45a8ff 6618 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 0:9b334a45a8ff 6619 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6620 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
bogdanm 0:9b334a45a8ff 6621 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
bogdanm 0:9b334a45a8ff 6622 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 0:9b334a45a8ff 6623 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6624 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
bogdanm 0:9b334a45a8ff 6625 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
bogdanm 0:9b334a45a8ff 6626 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6627 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
bogdanm 0:9b334a45a8ff 6628 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
bogdanm 0:9b334a45a8ff 6629 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
bogdanm 0:9b334a45a8ff 6630 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
bogdanm 0:9b334a45a8ff 6631
bogdanm 0:9b334a45a8ff 6632 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 0:9b334a45a8ff 6633 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
bogdanm 0:9b334a45a8ff 6634 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
bogdanm 0:9b334a45a8ff 6635
bogdanm 0:9b334a45a8ff 6636 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 0:9b334a45a8ff 6637 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
bogdanm 0:9b334a45a8ff 6638
bogdanm 0:9b334a45a8ff 6639 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 0:9b334a45a8ff 6640 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
bogdanm 0:9b334a45a8ff 6641
bogdanm 0:9b334a45a8ff 6642 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 0:9b334a45a8ff 6643 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
bogdanm 0:9b334a45a8ff 6644
bogdanm 0:9b334a45a8ff 6645 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 0:9b334a45a8ff 6646 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
bogdanm 0:9b334a45a8ff 6647
bogdanm 0:9b334a45a8ff 6648 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 0:9b334a45a8ff 6649 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
bogdanm 0:9b334a45a8ff 6650
bogdanm 0:9b334a45a8ff 6651 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 0:9b334a45a8ff 6652 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
bogdanm 0:9b334a45a8ff 6653
bogdanm 0:9b334a45a8ff 6654 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 0:9b334a45a8ff 6655 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
bogdanm 0:9b334a45a8ff 6656
bogdanm 0:9b334a45a8ff 6657 /******************* Bit definition for TIM_CCR5 register *******************/
bogdanm 0:9b334a45a8ff 6658 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
bogdanm 0:9b334a45a8ff 6659 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
bogdanm 0:9b334a45a8ff 6660 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
bogdanm 0:9b334a45a8ff 6661 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
bogdanm 0:9b334a45a8ff 6662
bogdanm 0:9b334a45a8ff 6663 /******************* Bit definition for TIM_CCR6 register *******************/
bogdanm 0:9b334a45a8ff 6664 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
bogdanm 0:9b334a45a8ff 6665
bogdanm 0:9b334a45a8ff 6666 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 0:9b334a45a8ff 6667 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 0:9b334a45a8ff 6668 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6669 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6670 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6671 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6672 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6673 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6674 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6675 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 6676
bogdanm 0:9b334a45a8ff 6677 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 0:9b334a45a8ff 6678 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6679 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6680
bogdanm 0:9b334a45a8ff 6681 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
bogdanm 0:9b334a45a8ff 6682 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
bogdanm 0:9b334a45a8ff 6683 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
bogdanm 0:9b334a45a8ff 6684 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
bogdanm 0:9b334a45a8ff 6685 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
bogdanm 0:9b334a45a8ff 6686 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
bogdanm 0:9b334a45a8ff 6687
bogdanm 0:9b334a45a8ff 6688 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
bogdanm 0:9b334a45a8ff 6689 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
bogdanm 0:9b334a45a8ff 6690
bogdanm 0:9b334a45a8ff 6691 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
bogdanm 0:9b334a45a8ff 6692 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
bogdanm 0:9b334a45a8ff 6693
bogdanm 0:9b334a45a8ff 6694 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 0:9b334a45a8ff 6695 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 0:9b334a45a8ff 6696 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6697 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6698 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6699 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6700 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6701
bogdanm 0:9b334a45a8ff 6702 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 0:9b334a45a8ff 6703 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6704 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6705 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6706 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6707 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6708
bogdanm 0:9b334a45a8ff 6709 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 0:9b334a45a8ff 6710 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
bogdanm 0:9b334a45a8ff 6711
bogdanm 0:9b334a45a8ff 6712 /******************* Bit definition for TIM16_OR register *********************/
bogdanm 0:9b334a45a8ff 6713 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
bogdanm 0:9b334a45a8ff 6714 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6715 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6716
bogdanm 0:9b334a45a8ff 6717 /******************* Bit definition for TIM1_OR register *********************/
bogdanm 0:9b334a45a8ff 6718 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
bogdanm 0:9b334a45a8ff 6719 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6720 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6721 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6722 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6723
bogdanm 0:9b334a45a8ff 6724 /****************** Bit definition for TIM_CCMR3 register *******************/
bogdanm 0:9b334a45a8ff 6725 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
bogdanm 0:9b334a45a8ff 6726 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
bogdanm 0:9b334a45a8ff 6727
bogdanm 0:9b334a45a8ff 6728 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
bogdanm 0:9b334a45a8ff 6729 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6730 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6731 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6732 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6733
bogdanm 0:9b334a45a8ff 6734 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
bogdanm 0:9b334a45a8ff 6735
bogdanm 0:9b334a45a8ff 6736 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
bogdanm 0:9b334a45a8ff 6737 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
bogdanm 0:9b334a45a8ff 6738
bogdanm 0:9b334a45a8ff 6739 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
bogdanm 0:9b334a45a8ff 6740 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6741 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6742 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6743 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6744
bogdanm 0:9b334a45a8ff 6745 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
bogdanm 0:9b334a45a8ff 6746
bogdanm 0:9b334a45a8ff 6747 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6748 /* */
bogdanm 0:9b334a45a8ff 6749 /* Touch Sensing Controller (TSC) */
bogdanm 0:9b334a45a8ff 6750 /* */
bogdanm 0:9b334a45a8ff 6751 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6752 /******************* Bit definition for TSC_CR register *********************/
bogdanm 0:9b334a45a8ff 6753 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
bogdanm 0:9b334a45a8ff 6754 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
bogdanm 0:9b334a45a8ff 6755 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
bogdanm 0:9b334a45a8ff 6756 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
bogdanm 0:9b334a45a8ff 6757 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
bogdanm 0:9b334a45a8ff 6758
bogdanm 0:9b334a45a8ff 6759 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
bogdanm 0:9b334a45a8ff 6760 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6761 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6762 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6763
bogdanm 0:9b334a45a8ff 6764 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
bogdanm 0:9b334a45a8ff 6765 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6766 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6767 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6768
bogdanm 0:9b334a45a8ff 6769 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
bogdanm 0:9b334a45a8ff 6770 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
bogdanm 0:9b334a45a8ff 6771
bogdanm 0:9b334a45a8ff 6772 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
bogdanm 0:9b334a45a8ff 6773 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6774 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6775 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6776 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6777 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6778 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6779 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6780
bogdanm 0:9b334a45a8ff 6781 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
bogdanm 0:9b334a45a8ff 6782 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6783 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6784 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6785 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6786
bogdanm 0:9b334a45a8ff 6787 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
bogdanm 0:9b334a45a8ff 6788 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6789 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6790 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6791 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6792
bogdanm 0:9b334a45a8ff 6793 /******************* Bit definition for TSC_IER register ********************/
bogdanm 0:9b334a45a8ff 6794 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
bogdanm 0:9b334a45a8ff 6795 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
bogdanm 0:9b334a45a8ff 6796
bogdanm 0:9b334a45a8ff 6797 /******************* Bit definition for TSC_ICR register ********************/
bogdanm 0:9b334a45a8ff 6798 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
bogdanm 0:9b334a45a8ff 6799 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
bogdanm 0:9b334a45a8ff 6800
bogdanm 0:9b334a45a8ff 6801 /******************* Bit definition for TSC_ISR register ********************/
bogdanm 0:9b334a45a8ff 6802 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
bogdanm 0:9b334a45a8ff 6803 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
bogdanm 0:9b334a45a8ff 6804
bogdanm 0:9b334a45a8ff 6805 /******************* Bit definition for TSC_IOHCR register ******************/
bogdanm 0:9b334a45a8ff 6806 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6807 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6808 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6809 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6810 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6811 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6812 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6813 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6814 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6815 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6816 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6817 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6818 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6819 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6820 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6821 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6822 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6823 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6824 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6825 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6826 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6827 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6828 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6829 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6830 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6831 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6832 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6833 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6834 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6835 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6836 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6837 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 6838
bogdanm 0:9b334a45a8ff 6839 /******************* Bit definition for TSC_IOASCR register *****************/
bogdanm 0:9b334a45a8ff 6840 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6841 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6842 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6843 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6844 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6845 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6846 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6847 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6848 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6849 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6850 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6851 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6852 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6853 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6854 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6855 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6856 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6857 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6858 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6859 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6860 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6861 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6862 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6863 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6864 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6865 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6866 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6867 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6868 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 6869 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 6870 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 6871 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 6872
bogdanm 0:9b334a45a8ff 6873 /******************* Bit definition for TSC_IOSCR register ******************/
bogdanm 0:9b334a45a8ff 6874 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6875 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6876 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6877 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6878 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6879 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6880 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6881 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6882 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6883 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6884 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6885 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6886 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6887 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6888 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6889 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6890 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6891 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6892 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6893 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6894 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6895 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6896 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6897 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6898 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6899 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6900 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6901 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6902 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 6903 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 6904 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 6905 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 6906
bogdanm 0:9b334a45a8ff 6907 /******************* Bit definition for TSC_IOCCR register ******************/
bogdanm 0:9b334a45a8ff 6908 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6909 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6910 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6911 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6912 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6913 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6914 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6915 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6916 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6917 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6918 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6919 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6920 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6921 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6922 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6923 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6924 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6925 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6926 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6927 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6928 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6929 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6930 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6931 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6932 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6933 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6934 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6935 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6936 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
bogdanm 0:9b334a45a8ff 6937 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
bogdanm 0:9b334a45a8ff 6938 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
bogdanm 0:9b334a45a8ff 6939 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
bogdanm 0:9b334a45a8ff 6940
bogdanm 0:9b334a45a8ff 6941 /******************* Bit definition for TSC_IOGCSR register *****************/
bogdanm 0:9b334a45a8ff 6942 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
bogdanm 0:9b334a45a8ff 6943 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
bogdanm 0:9b334a45a8ff 6944 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
bogdanm 0:9b334a45a8ff 6945 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
bogdanm 0:9b334a45a8ff 6946 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
bogdanm 0:9b334a45a8ff 6947 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
bogdanm 0:9b334a45a8ff 6948 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
bogdanm 0:9b334a45a8ff 6949 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
bogdanm 0:9b334a45a8ff 6950 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
bogdanm 0:9b334a45a8ff 6951 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
bogdanm 0:9b334a45a8ff 6952 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
bogdanm 0:9b334a45a8ff 6953 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
bogdanm 0:9b334a45a8ff 6954 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
bogdanm 0:9b334a45a8ff 6955 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
bogdanm 0:9b334a45a8ff 6956 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
bogdanm 0:9b334a45a8ff 6957 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
bogdanm 0:9b334a45a8ff 6958
bogdanm 0:9b334a45a8ff 6959 /******************* Bit definition for TSC_IOGXCR register *****************/
bogdanm 0:9b334a45a8ff 6960 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
bogdanm 0:9b334a45a8ff 6961
bogdanm 0:9b334a45a8ff 6962 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6963 /* */
bogdanm 0:9b334a45a8ff 6964 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 0:9b334a45a8ff 6965 /* */
bogdanm 0:9b334a45a8ff 6966 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6967 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 0:9b334a45a8ff 6968 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
bogdanm 0:9b334a45a8ff 6969 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
bogdanm 0:9b334a45a8ff 6970 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
bogdanm 0:9b334a45a8ff 6971 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
bogdanm 0:9b334a45a8ff 6972 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6973 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6974 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 6975 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6976 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6977 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
bogdanm 0:9b334a45a8ff 6978 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
bogdanm 0:9b334a45a8ff 6979 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
bogdanm 0:9b334a45a8ff 6980 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
bogdanm 0:9b334a45a8ff 6981 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
bogdanm 0:9b334a45a8ff 6982 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
bogdanm 0:9b334a45a8ff 6983 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
bogdanm 0:9b334a45a8ff 6984 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
bogdanm 0:9b334a45a8ff 6985 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6986 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6987 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 6988 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 6989 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 6990 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
bogdanm 0:9b334a45a8ff 6991 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 6992 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 6993 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 6994 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 6995 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 6996 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
bogdanm 0:9b334a45a8ff 6997 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
bogdanm 0:9b334a45a8ff 6998 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
bogdanm 0:9b334a45a8ff 6999 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
bogdanm 0:9b334a45a8ff 7000
bogdanm 0:9b334a45a8ff 7001 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 0:9b334a45a8ff 7002 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
bogdanm 0:9b334a45a8ff 7003 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
bogdanm 0:9b334a45a8ff 7004 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
bogdanm 0:9b334a45a8ff 7005 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
bogdanm 0:9b334a45a8ff 7006 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
bogdanm 0:9b334a45a8ff 7007 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
bogdanm 0:9b334a45a8ff 7008 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
bogdanm 0:9b334a45a8ff 7009 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
bogdanm 0:9b334a45a8ff 7010 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 7011 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 7012 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
bogdanm 0:9b334a45a8ff 7013 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
bogdanm 0:9b334a45a8ff 7014 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
bogdanm 0:9b334a45a8ff 7015 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
bogdanm 0:9b334a45a8ff 7016 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
bogdanm 0:9b334a45a8ff 7017 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
bogdanm 0:9b334a45a8ff 7018 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
bogdanm 0:9b334a45a8ff 7019 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
bogdanm 0:9b334a45a8ff 7020 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 7021 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 7022 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
bogdanm 0:9b334a45a8ff 7023 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
bogdanm 0:9b334a45a8ff 7024
bogdanm 0:9b334a45a8ff 7025 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 0:9b334a45a8ff 7026 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 7027 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
bogdanm 0:9b334a45a8ff 7028 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
bogdanm 0:9b334a45a8ff 7029 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
bogdanm 0:9b334a45a8ff 7030 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
bogdanm 0:9b334a45a8ff 7031 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
bogdanm 0:9b334a45a8ff 7032 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
bogdanm 0:9b334a45a8ff 7033 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
bogdanm 0:9b334a45a8ff 7034 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
bogdanm 0:9b334a45a8ff 7035 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
bogdanm 0:9b334a45a8ff 7036 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
bogdanm 0:9b334a45a8ff 7037 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
bogdanm 0:9b334a45a8ff 7038 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
bogdanm 0:9b334a45a8ff 7039 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
bogdanm 0:9b334a45a8ff 7040 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
bogdanm 0:9b334a45a8ff 7041 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
bogdanm 0:9b334a45a8ff 7042 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
bogdanm 0:9b334a45a8ff 7043 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 7044 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 7045 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 7046 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
bogdanm 0:9b334a45a8ff 7047 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 7048 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 7049 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
bogdanm 0:9b334a45a8ff 7050
bogdanm 0:9b334a45a8ff 7051 /****************** Bit definition for USART_BRR register *******************/
bogdanm 0:9b334a45a8ff 7052 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
bogdanm 0:9b334a45a8ff 7053 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
bogdanm 0:9b334a45a8ff 7054
bogdanm 0:9b334a45a8ff 7055 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 0:9b334a45a8ff 7056 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
bogdanm 0:9b334a45a8ff 7057 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
bogdanm 0:9b334a45a8ff 7058
bogdanm 0:9b334a45a8ff 7059
bogdanm 0:9b334a45a8ff 7060 /******************* Bit definition for USART_RTOR register *****************/
bogdanm 0:9b334a45a8ff 7061 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
bogdanm 0:9b334a45a8ff 7062 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
bogdanm 0:9b334a45a8ff 7063
bogdanm 0:9b334a45a8ff 7064 /******************* Bit definition for USART_RQR register ******************/
bogdanm 0:9b334a45a8ff 7065 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
bogdanm 0:9b334a45a8ff 7066 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
bogdanm 0:9b334a45a8ff 7067 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
bogdanm 0:9b334a45a8ff 7068 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
bogdanm 0:9b334a45a8ff 7069 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
bogdanm 0:9b334a45a8ff 7070
bogdanm 0:9b334a45a8ff 7071 /******************* Bit definition for USART_ISR register ******************/
bogdanm 0:9b334a45a8ff 7072 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
bogdanm 0:9b334a45a8ff 7073 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
bogdanm 0:9b334a45a8ff 7074 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
bogdanm 0:9b334a45a8ff 7075 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
bogdanm 0:9b334a45a8ff 7076 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
bogdanm 0:9b334a45a8ff 7077 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
bogdanm 0:9b334a45a8ff 7078 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
bogdanm 0:9b334a45a8ff 7079 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
bogdanm 0:9b334a45a8ff 7080 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
bogdanm 0:9b334a45a8ff 7081 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
bogdanm 0:9b334a45a8ff 7082 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
bogdanm 0:9b334a45a8ff 7083 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
bogdanm 0:9b334a45a8ff 7084 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
bogdanm 0:9b334a45a8ff 7085 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
bogdanm 0:9b334a45a8ff 7086 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
bogdanm 0:9b334a45a8ff 7087 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
bogdanm 0:9b334a45a8ff 7088 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
bogdanm 0:9b334a45a8ff 7089 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
bogdanm 0:9b334a45a8ff 7090 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
bogdanm 0:9b334a45a8ff 7091 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
bogdanm 0:9b334a45a8ff 7092 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
bogdanm 0:9b334a45a8ff 7093 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
bogdanm 0:9b334a45a8ff 7094
bogdanm 0:9b334a45a8ff 7095 /******************* Bit definition for USART_ICR register ******************/
bogdanm 0:9b334a45a8ff 7096 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
bogdanm 0:9b334a45a8ff 7097 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
bogdanm 0:9b334a45a8ff 7098 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
bogdanm 0:9b334a45a8ff 7099 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
bogdanm 0:9b334a45a8ff 7100 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
bogdanm 0:9b334a45a8ff 7101 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
bogdanm 0:9b334a45a8ff 7102 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
bogdanm 0:9b334a45a8ff 7103 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
bogdanm 0:9b334a45a8ff 7104 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
bogdanm 0:9b334a45a8ff 7105 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
bogdanm 0:9b334a45a8ff 7106 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
bogdanm 0:9b334a45a8ff 7107 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
bogdanm 0:9b334a45a8ff 7108
bogdanm 0:9b334a45a8ff 7109 /******************* Bit definition for USART_RDR register ******************/
bogdanm 0:9b334a45a8ff 7110 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 0:9b334a45a8ff 7111
bogdanm 0:9b334a45a8ff 7112 /******************* Bit definition for USART_TDR register ******************/
bogdanm 0:9b334a45a8ff 7113 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 0:9b334a45a8ff 7114
bogdanm 0:9b334a45a8ff 7115 /******************************************************************************/
bogdanm 0:9b334a45a8ff 7116 /* */
bogdanm 0:9b334a45a8ff 7117 /* Window WATCHDOG */
bogdanm 0:9b334a45a8ff 7118 /* */
bogdanm 0:9b334a45a8ff 7119 /******************************************************************************/
bogdanm 0:9b334a45a8ff 7120 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 0:9b334a45a8ff 7121 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 0:9b334a45a8ff 7122 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 7123 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 7124 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 7125 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 7126 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 7127 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 7128 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 7129
bogdanm 0:9b334a45a8ff 7130 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
bogdanm 0:9b334a45a8ff 7131
bogdanm 0:9b334a45a8ff 7132 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 0:9b334a45a8ff 7133 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 0:9b334a45a8ff 7134 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 7135 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 7136 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 7137 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 7138 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 7139 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 7140 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 7141
bogdanm 0:9b334a45a8ff 7142 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 0:9b334a45a8ff 7143 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 7144 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 7145
bogdanm 0:9b334a45a8ff 7146 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 7147
bogdanm 0:9b334a45a8ff 7148 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 0:9b334a45a8ff 7149 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
bogdanm 0:9b334a45a8ff 7150
bogdanm 0:9b334a45a8ff 7151 /**
bogdanm 0:9b334a45a8ff 7152 * @}
bogdanm 0:9b334a45a8ff 7153 */
bogdanm 0:9b334a45a8ff 7154
bogdanm 0:9b334a45a8ff 7155 /**
bogdanm 0:9b334a45a8ff 7156 * @}
bogdanm 0:9b334a45a8ff 7157 */
bogdanm 0:9b334a45a8ff 7158
bogdanm 0:9b334a45a8ff 7159 /** @addtogroup Exported_macros
bogdanm 0:9b334a45a8ff 7160 * @{
bogdanm 0:9b334a45a8ff 7161 */
bogdanm 0:9b334a45a8ff 7162
bogdanm 0:9b334a45a8ff 7163 /****************************** ADC Instances *********************************/
bogdanm 0:9b334a45a8ff 7164 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
bogdanm 0:9b334a45a8ff 7165 ((INSTANCE) == ADC2))
bogdanm 0:9b334a45a8ff 7166
bogdanm 0:9b334a45a8ff 7167 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
bogdanm 0:9b334a45a8ff 7168
bogdanm 0:9b334a45a8ff 7169 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
bogdanm 0:9b334a45a8ff 7170
bogdanm 0:9b334a45a8ff 7171 /****************************** CAN Instances *********************************/
bogdanm 0:9b334a45a8ff 7172 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
bogdanm 0:9b334a45a8ff 7173
bogdanm 0:9b334a45a8ff 7174 /****************************** COMP Instances ********************************/
bogdanm 0:9b334a45a8ff 7175 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
bogdanm 0:9b334a45a8ff 7176 ((INSTANCE) == COMP4) || \
bogdanm 0:9b334a45a8ff 7177 ((INSTANCE) == COMP6))
bogdanm 0:9b334a45a8ff 7178
bogdanm 0:9b334a45a8ff 7179 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
bogdanm 0:9b334a45a8ff 7180 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0)
bogdanm 0:9b334a45a8ff 7181
bogdanm 0:9b334a45a8ff 7182 /******************** COMP Instances with window mode capability **************/
bogdanm 0:9b334a45a8ff 7183 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0)
bogdanm 0:9b334a45a8ff 7184
bogdanm 0:9b334a45a8ff 7185 /****************************** CRC Instances *********************************/
bogdanm 0:9b334a45a8ff 7186 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 0:9b334a45a8ff 7187
bogdanm 0:9b334a45a8ff 7188 /****************************** DAC Instances *********************************/
bogdanm 0:9b334a45a8ff 7189 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
bogdanm 0:9b334a45a8ff 7190 ((INSTANCE) == DAC2))
bogdanm 0:9b334a45a8ff 7191
bogdanm 0:9b334a45a8ff 7192 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 7193 ((((INSTANCE) == DAC1) && \
bogdanm 0:9b334a45a8ff 7194 (((CHANNEL) == DAC_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7195 ((CHANNEL) == DAC_CHANNEL_2))) \
bogdanm 0:9b334a45a8ff 7196 || \
bogdanm 0:9b334a45a8ff 7197 (((INSTANCE) == DAC2) && \
bogdanm 0:9b334a45a8ff 7198 (((CHANNEL) == DAC_CHANNEL_1))))
bogdanm 0:9b334a45a8ff 7199
bogdanm 0:9b334a45a8ff 7200 /****************************** DMA Instances *********************************/
bogdanm 0:9b334a45a8ff 7201 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
bogdanm 0:9b334a45a8ff 7202 ((INSTANCE) == DMA1_Channel2) || \
bogdanm 0:9b334a45a8ff 7203 ((INSTANCE) == DMA1_Channel3) || \
bogdanm 0:9b334a45a8ff 7204 ((INSTANCE) == DMA1_Channel4) || \
bogdanm 0:9b334a45a8ff 7205 ((INSTANCE) == DMA1_Channel5) || \
bogdanm 0:9b334a45a8ff 7206 ((INSTANCE) == DMA1_Channel6) || \
bogdanm 0:9b334a45a8ff 7207 ((INSTANCE) == DMA1_Channel7))
bogdanm 0:9b334a45a8ff 7208
bogdanm 0:9b334a45a8ff 7209 /****************************** GPIO Instances ********************************/
bogdanm 0:9b334a45a8ff 7210 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 0:9b334a45a8ff 7211 ((INSTANCE) == GPIOB) || \
bogdanm 0:9b334a45a8ff 7212 ((INSTANCE) == GPIOC) || \
bogdanm 0:9b334a45a8ff 7213 ((INSTANCE) == GPIOD) || \
bogdanm 0:9b334a45a8ff 7214 ((INSTANCE) == GPIOF))
bogdanm 0:9b334a45a8ff 7215
bogdanm 0:9b334a45a8ff 7216 /****************************** HRTIM Instances *********************************/
bogdanm 0:9b334a45a8ff 7217 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
bogdanm 0:9b334a45a8ff 7218
bogdanm 0:9b334a45a8ff 7219 /****************************** I2C Instances *********************************/
bogdanm 0:9b334a45a8ff 7220 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
bogdanm 0:9b334a45a8ff 7221
bogdanm 0:9b334a45a8ff 7222 /****************************** IWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 7223 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 0:9b334a45a8ff 7224
bogdanm 0:9b334a45a8ff 7225 /****************************** OPAMP Instances *******************************/
bogdanm 0:9b334a45a8ff 7226 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
bogdanm 0:9b334a45a8ff 7227
bogdanm 0:9b334a45a8ff 7228 /****************************** RTC Instances *********************************/
bogdanm 0:9b334a45a8ff 7229 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 0:9b334a45a8ff 7230
bogdanm 0:9b334a45a8ff 7231 /****************************** SMBUS Instances *******************************/
bogdanm 0:9b334a45a8ff 7232 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
bogdanm 0:9b334a45a8ff 7233
bogdanm 0:9b334a45a8ff 7234 /****************************** SPI Instances *********************************/
bogdanm 0:9b334a45a8ff 7235 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
bogdanm 0:9b334a45a8ff 7236
bogdanm 0:9b334a45a8ff 7237 /******************* TIM Instances : All supported instances ******************/
bogdanm 0:9b334a45a8ff 7238 #define IS_TIM_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7239 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7240 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7241 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7242 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 7243 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 7244 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7245 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7246 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7247
bogdanm 0:9b334a45a8ff 7248 /******************* TIM Instances : at least 1 capture/compare channel *******/
bogdanm 0:9b334a45a8ff 7249 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7250 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7251 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7252 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7253 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7254 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7255 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7256
bogdanm 0:9b334a45a8ff 7257 /****************** TIM Instances : at least 2 capture/compare channels *******/
bogdanm 0:9b334a45a8ff 7258 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7259 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7260 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7261 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7262 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7263
bogdanm 0:9b334a45a8ff 7264 /****************** TIM Instances : at least 3 capture/compare channels *******/
bogdanm 0:9b334a45a8ff 7265 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7266 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7267 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7268 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7269
bogdanm 0:9b334a45a8ff 7270 /****************** TIM Instances : at least 4 capture/compare channels *******/
bogdanm 0:9b334a45a8ff 7271 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7272 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7273 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7274 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7275
bogdanm 0:9b334a45a8ff 7276 /****************** TIM Instances : at least 5 capture/compare channels *******/
bogdanm 0:9b334a45a8ff 7277 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7278 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7279
bogdanm 0:9b334a45a8ff 7280 /****************** TIM Instances : at least 6 capture/compare channels *******/
bogdanm 0:9b334a45a8ff 7281 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7282 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7283
bogdanm 0:9b334a45a8ff 7284 /************************** TIM Instances : Advanced-control timers ***********/
bogdanm 0:9b334a45a8ff 7285
bogdanm 0:9b334a45a8ff 7286 /****************** TIM Instances : supporting clock selection ****************/
bogdanm 0:9b334a45a8ff 7287 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7288 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7289 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7290 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7291 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7292
bogdanm 0:9b334a45a8ff 7293 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
bogdanm 0:9b334a45a8ff 7294 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7295 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7296 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7297 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7298
bogdanm 0:9b334a45a8ff 7299 /****************** TIM Instances : supporting external clock mode 2 **********/
bogdanm 0:9b334a45a8ff 7300 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7301 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7302 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7303 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7304
bogdanm 0:9b334a45a8ff 7305 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
bogdanm 0:9b334a45a8ff 7306 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7307 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7308 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7309 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7310 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7311
bogdanm 0:9b334a45a8ff 7312 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
bogdanm 0:9b334a45a8ff 7313 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7314 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7315 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7316 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7317 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7318
bogdanm 0:9b334a45a8ff 7319 /****************** TIM Instances : supporting OCxREF clear *******************/
bogdanm 0:9b334a45a8ff 7320 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7321 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7322 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7323 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7324
bogdanm 0:9b334a45a8ff 7325 /****************** TIM Instances : supporting encoder interface **************/
bogdanm 0:9b334a45a8ff 7326 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7327 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7328 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7329 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7330
bogdanm 0:9b334a45a8ff 7331 /****************** TIM Instances : supporting Hall interface *****************/
bogdanm 0:9b334a45a8ff 7332 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7333 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7334
bogdanm 0:9b334a45a8ff 7335 /****************** TIM Instances : supporting input XOR function *************/
bogdanm 0:9b334a45a8ff 7336 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7337 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7338 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7339 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7340 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7341
bogdanm 0:9b334a45a8ff 7342 /****************** TIM Instances : supporting master mode ********************/
bogdanm 0:9b334a45a8ff 7343 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7344 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7345 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7346 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7347 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 7348 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 7349 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7350
bogdanm 0:9b334a45a8ff 7351 /****************** TIM Instances : supporting slave mode *********************/
bogdanm 0:9b334a45a8ff 7352 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7353 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7354 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7355 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7356 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7357
bogdanm 0:9b334a45a8ff 7358 /****************** TIM Instances : supporting synchronization ****************/
bogdanm 0:9b334a45a8ff 7359 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7360 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7361 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7362 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7363 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 7364 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 7365 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 7366
bogdanm 0:9b334a45a8ff 7367 /****************** TIM Instances : supporting 32 bits counter ****************/
bogdanm 0:9b334a45a8ff 7368 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7369 ((INSTANCE) == TIM2)
bogdanm 0:9b334a45a8ff 7370
bogdanm 0:9b334a45a8ff 7371 /****************** TIM Instances : supporting DMA burst **********************/
bogdanm 0:9b334a45a8ff 7372 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7373 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7374 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7375 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7376 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7377 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7378 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7379
bogdanm 0:9b334a45a8ff 7380 /****************** TIM Instances : supporting the break function *************/
bogdanm 0:9b334a45a8ff 7381 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7382 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7383 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7384 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7385 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7386
bogdanm 0:9b334a45a8ff 7387 /****************** TIM Instances : supporting input/output channel(s) ********/
bogdanm 0:9b334a45a8ff 7388 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 7389 ((((INSTANCE) == TIM1) && \
bogdanm 0:9b334a45a8ff 7390 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7391 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 7392 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 7393 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 0:9b334a45a8ff 7394 ((CHANNEL) == TIM_CHANNEL_5) || \
bogdanm 0:9b334a45a8ff 7395 ((CHANNEL) == TIM_CHANNEL_6))) \
bogdanm 0:9b334a45a8ff 7396 || \
bogdanm 0:9b334a45a8ff 7397 (((INSTANCE) == TIM2) && \
bogdanm 0:9b334a45a8ff 7398 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7399 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 7400 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 7401 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 7402 || \
bogdanm 0:9b334a45a8ff 7403 (((INSTANCE) == TIM3) && \
bogdanm 0:9b334a45a8ff 7404 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7405 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 7406 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 7407 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 7408 || \
bogdanm 0:9b334a45a8ff 7409 (((INSTANCE) == TIM15) && \
bogdanm 0:9b334a45a8ff 7410 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7411 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 0:9b334a45a8ff 7412 || \
bogdanm 0:9b334a45a8ff 7413 (((INSTANCE) == TIM16) && \
bogdanm 0:9b334a45a8ff 7414 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 0:9b334a45a8ff 7415 || \
bogdanm 0:9b334a45a8ff 7416 (((INSTANCE) == TIM17) && \
bogdanm 0:9b334a45a8ff 7417 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 0:9b334a45a8ff 7418
bogdanm 0:9b334a45a8ff 7419 /****************** TIM Instances : supporting complementary output(s) ********/
bogdanm 0:9b334a45a8ff 7420 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 7421 ((((INSTANCE) == TIM1) && \
bogdanm 0:9b334a45a8ff 7422 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 7423 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 7424 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 0:9b334a45a8ff 7425 || \
bogdanm 0:9b334a45a8ff 7426 (((INSTANCE) == TIM15) && \
bogdanm 0:9b334a45a8ff 7427 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 0:9b334a45a8ff 7428 || \
bogdanm 0:9b334a45a8ff 7429 (((INSTANCE) == TIM16) && \
bogdanm 0:9b334a45a8ff 7430 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 0:9b334a45a8ff 7431 || \
bogdanm 0:9b334a45a8ff 7432 (((INSTANCE) == TIM17) && \
bogdanm 0:9b334a45a8ff 7433 ((CHANNEL) == TIM_CHANNEL_1)))
bogdanm 0:9b334a45a8ff 7434
bogdanm 0:9b334a45a8ff 7435 /****************** TIM Instances : supporting counting mode selection ********/
bogdanm 0:9b334a45a8ff 7436 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7437 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7438 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7439 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 7440
bogdanm 0:9b334a45a8ff 7441 /****************** TIM Instances : supporting repetition counter *************/
bogdanm 0:9b334a45a8ff 7442 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7443 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7444 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7445 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7446 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7447
bogdanm 0:9b334a45a8ff 7448 /****************** TIM Instances : supporting clock division *****************/
bogdanm 0:9b334a45a8ff 7449 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7450 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7451 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7452 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7453 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7454 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7455 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7456
bogdanm 0:9b334a45a8ff 7457 /****************** TIM Instances : supporting 2 break inputs *****************/
bogdanm 0:9b334a45a8ff 7458 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7459 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7460
bogdanm 0:9b334a45a8ff 7461 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
bogdanm 0:9b334a45a8ff 7462 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7463 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7464
bogdanm 0:9b334a45a8ff 7465 /****************** TIM Instances : supporting DMA generation on Update events*/
bogdanm 0:9b334a45a8ff 7466 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7467 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7468 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7469 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7470 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 7471 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 7472 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7473 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7474 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7475
bogdanm 0:9b334a45a8ff 7476 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
bogdanm 0:9b334a45a8ff 7477 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7478 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7479 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 7480 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 7481 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7482 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7483 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7484
bogdanm 0:9b334a45a8ff 7485 /****************** TIM Instances : supporting commutation event generation ***/
bogdanm 0:9b334a45a8ff 7486 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7487 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7488 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 7489 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 7490 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 7491
bogdanm 0:9b334a45a8ff 7492 /****************** TIM Instances : supporting remapping capability ***********/
bogdanm 0:9b334a45a8ff 7493 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 7494 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 7495 ((INSTANCE) == TIM16))
bogdanm 0:9b334a45a8ff 7496
bogdanm 0:9b334a45a8ff 7497 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
bogdanm 0:9b334a45a8ff 7498 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
bogdanm 0:9b334a45a8ff 7499 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 7500
bogdanm 0:9b334a45a8ff 7501 /****************************** TSC Instances *********************************/
bogdanm 0:9b334a45a8ff 7502 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
bogdanm 0:9b334a45a8ff 7503
bogdanm 0:9b334a45a8ff 7504 /******************** USART Instances : Synchronous mode **********************/
bogdanm 0:9b334a45a8ff 7505 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 7506 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 7507 ((INSTANCE) == USART3))
bogdanm 0:9b334a45a8ff 7508
bogdanm 0:9b334a45a8ff 7509 /****************** USART Instances : Auto Baud Rate detection ****************/
bogdanm 0:9b334a45a8ff 7510 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7511
bogdanm 0:9b334a45a8ff 7512 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 0:9b334a45a8ff 7513 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 7514 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 7515 ((INSTANCE) == USART3))
bogdanm 0:9b334a45a8ff 7516
bogdanm 0:9b334a45a8ff 7517 /******************** UART Instances : Half-Duplex mode **********************/
bogdanm 0:9b334a45a8ff 7518 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 7519 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 7520 ((INSTANCE) == USART3))
bogdanm 0:9b334a45a8ff 7521
bogdanm 0:9b334a45a8ff 7522 /******************** UART Instances : LIN mode **********************/
bogdanm 0:9b334a45a8ff 7523 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7524
bogdanm 0:9b334a45a8ff 7525 /******************** UART Instances : Wake-up from Stop mode **********************/
bogdanm 0:9b334a45a8ff 7526 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7527
bogdanm 0:9b334a45a8ff 7528 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 0:9b334a45a8ff 7529 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 7530 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 7531 ((INSTANCE) == USART3))
bogdanm 0:9b334a45a8ff 7532
bogdanm 0:9b334a45a8ff 7533 /****************** UART Instances : Auto Baud Rate detection *****************/
bogdanm 0:9b334a45a8ff 7534 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7535
bogdanm 0:9b334a45a8ff 7536 /****************** UART Instances : Driver Enable ****************************/
bogdanm 0:9b334a45a8ff 7537 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 7538 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 7539 ((INSTANCE) == USART3))
bogdanm 0:9b334a45a8ff 7540
bogdanm 0:9b334a45a8ff 7541 /********************* UART Instances : Smard card mode ***********************/
bogdanm 0:9b334a45a8ff 7542 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7543
bogdanm 0:9b334a45a8ff 7544 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 0:9b334a45a8ff 7545 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
bogdanm 0:9b334a45a8ff 7546
bogdanm 0:9b334a45a8ff 7547 /****************************** WWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 7548 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 0:9b334a45a8ff 7549
bogdanm 0:9b334a45a8ff 7550 /**
bogdanm 0:9b334a45a8ff 7551 * @}
bogdanm 0:9b334a45a8ff 7552 */
bogdanm 0:9b334a45a8ff 7553
bogdanm 0:9b334a45a8ff 7554
bogdanm 0:9b334a45a8ff 7555 /******************************************************************************/
bogdanm 0:9b334a45a8ff 7556 /* For a painless codes migration between the STM32F3xx device product */
bogdanm 0:9b334a45a8ff 7557 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 0:9b334a45a8ff 7558 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 0:9b334a45a8ff 7559 /* No need to update developed interrupt code when moving across */
bogdanm 0:9b334a45a8ff 7560 /* product lines within the same STM32F3 Family */
bogdanm 0:9b334a45a8ff 7561 /******************************************************************************/
bogdanm 0:9b334a45a8ff 7562
bogdanm 0:9b334a45a8ff 7563 /* Aliases for __IRQn */
bogdanm 0:9b334a45a8ff 7564
bogdanm 0:9b334a45a8ff 7565 #define ADC1_IRQn ADC1_2_IRQn
bogdanm 0:9b334a45a8ff 7566 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
bogdanm 0:9b334a45a8ff 7567 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
bogdanm 0:9b334a45a8ff 7568 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
bogdanm 0:9b334a45a8ff 7569 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
bogdanm 0:9b334a45a8ff 7570 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
bogdanm 0:9b334a45a8ff 7571 #define COMP_IRQn COMP2_IRQn
bogdanm 0:9b334a45a8ff 7572 #define COMP1_2_3_IRQn COMP2_IRQn
bogdanm 0:9b334a45a8ff 7573 #define COMP1_2_IRQn COMP2_IRQn
bogdanm 0:9b334a45a8ff 7574 #define COMP4_5_6_IRQn COMP4_6_IRQn
bogdanm 0:9b334a45a8ff 7575 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn
bogdanm 0:9b334a45a8ff 7576
bogdanm 0:9b334a45a8ff 7577 /* Aliases for __IRQHandler */
bogdanm 0:9b334a45a8ff 7578 #define ADC1_IRQHandler ADC1_2_IRQHandler
bogdanm 0:9b334a45a8ff 7579 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
bogdanm 0:9b334a45a8ff 7580 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
bogdanm 0:9b334a45a8ff 7581 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
bogdanm 0:9b334a45a8ff 7582 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
bogdanm 0:9b334a45a8ff 7583 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
bogdanm 0:9b334a45a8ff 7584 #define COMP_IRQHandler COMP2_IRQHandler
bogdanm 0:9b334a45a8ff 7585 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
bogdanm 0:9b334a45a8ff 7586 #define COMP1_2_IRQHandler COMP2_IRQHandler
bogdanm 0:9b334a45a8ff 7587 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
bogdanm 0:9b334a45a8ff 7588 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
bogdanm 0:9b334a45a8ff 7589
bogdanm 0:9b334a45a8ff 7590 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 7591 }
bogdanm 0:9b334a45a8ff 7592 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 7593
bogdanm 0:9b334a45a8ff 7594 #endif /* __STM32F334x8_H */
bogdanm 0:9b334a45a8ff 7595
bogdanm 0:9b334a45a8ff 7596 /**
bogdanm 0:9b334a45a8ff 7597 * @}
bogdanm 0:9b334a45a8ff 7598 */
bogdanm 0:9b334a45a8ff 7599
bogdanm 0:9b334a45a8ff 7600 /**
bogdanm 0:9b334a45a8ff 7601 * @}
bogdanm 0:9b334a45a8ff 7602 */
bogdanm 0:9b334a45a8ff 7603
bogdanm 0:9b334a45a8ff 7604 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/